1 /* 2 * pata_artop.c - ARTOP ATA controller driver 3 * 4 * (C) 2006 Red Hat 5 * (C) 2007 Bartlomiej Zolnierkiewicz 6 * 7 * Based in part on drivers/ide/pci/aec62xx.c 8 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org> 9 * 865/865R fixes for Macintosh card version from a patch to the old 10 * driver by Thibaut VARENE <varenet@parisc-linux.org> 11 * When setting the PCI latency we must set 0x80 or higher for burst 12 * performance Alessandro Zummo <alessandro.zummo@towertech.it> 13 * 14 * TODO 15 * Investigate no_dsc on 850R 16 * Clock detect 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/init.h> 23 #include <linux/blkdev.h> 24 #include <linux/delay.h> 25 #include <linux/device.h> 26 #include <scsi/scsi_host.h> 27 #include <linux/libata.h> 28 #include <linux/ata.h> 29 30 #define DRV_NAME "pata_artop" 31 #define DRV_VERSION "0.4.5" 32 33 /* 34 * The ARTOP has 33 Mhz and "over clocked" timing tables. Until we 35 * get PCI bus speed functionality we leave this as 0. Its a variable 36 * for when we get the functionality and also for folks wanting to 37 * test stuff. 38 */ 39 40 static int clock = 0; 41 42 static int artop6210_pre_reset(struct ata_link *link, unsigned long deadline) 43 { 44 struct ata_port *ap = link->ap; 45 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 46 const struct pci_bits artop_enable_bits[] = { 47 { 0x4AU, 1U, 0x02UL, 0x02UL }, /* port 0 */ 48 { 0x4AU, 1U, 0x04UL, 0x04UL }, /* port 1 */ 49 }; 50 51 if (!pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no])) 52 return -ENOENT; 53 54 return ata_sff_prereset(link, deadline); 55 } 56 57 /** 58 * artop6260_pre_reset - check for 40/80 pin 59 * @link: link 60 * @deadline: deadline jiffies for the operation 61 * 62 * The ARTOP hardware reports the cable detect bits in register 0x49. 63 * Nothing complicated needed here. 64 */ 65 66 static int artop6260_pre_reset(struct ata_link *link, unsigned long deadline) 67 { 68 static const struct pci_bits artop_enable_bits[] = { 69 { 0x4AU, 1U, 0x02UL, 0x02UL }, /* port 0 */ 70 { 0x4AU, 1U, 0x04UL, 0x04UL }, /* port 1 */ 71 }; 72 73 struct ata_port *ap = link->ap; 74 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 75 76 /* Odd numbered device ids are the units with enable bits (the -R cards) */ 77 if (pdev->device % 1 && !pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no])) 78 return -ENOENT; 79 80 return ata_sff_prereset(link, deadline); 81 } 82 83 /** 84 * artop6260_cable_detect - identify cable type 85 * @ap: Port 86 * 87 * Identify the cable type for the ARTOP interface in question 88 */ 89 90 static int artop6260_cable_detect(struct ata_port *ap) 91 { 92 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 93 u8 tmp; 94 pci_read_config_byte(pdev, 0x49, &tmp); 95 if (tmp & (1 << ap->port_no)) 96 return ATA_CBL_PATA40; 97 return ATA_CBL_PATA80; 98 } 99 100 /** 101 * artop6210_load_piomode - Load a set of PATA PIO timings 102 * @ap: Port whose timings we are configuring 103 * @adev: Device 104 * @pio: PIO mode 105 * 106 * Set PIO mode for device, in host controller PCI config space. This 107 * is used both to set PIO timings in PIO mode and also to set the 108 * matching PIO clocking for UDMA, as well as the MWDMA timings. 109 * 110 * LOCKING: 111 * None (inherited from caller). 112 */ 113 114 static void artop6210_load_piomode(struct ata_port *ap, struct ata_device *adev, unsigned int pio) 115 { 116 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 117 int dn = adev->devno + 2 * ap->port_no; 118 const u16 timing[2][5] = { 119 { 0x0000, 0x000A, 0x0008, 0x0303, 0x0301 }, 120 { 0x0700, 0x070A, 0x0708, 0x0403, 0x0401 } 121 122 }; 123 /* Load the PIO timing active/recovery bits */ 124 pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]); 125 } 126 127 /** 128 * artop6210_set_piomode - Initialize host controller PATA PIO timings 129 * @ap: Port whose timings we are configuring 130 * @adev: Device we are configuring 131 * 132 * Set PIO mode for device, in host controller PCI config space. For 133 * ARTOP we must also clear the UDMA bits if we are not doing UDMA. In 134 * the event UDMA is used the later call to set_dmamode will set the 135 * bits as required. 136 * 137 * LOCKING: 138 * None (inherited from caller). 139 */ 140 141 static void artop6210_set_piomode(struct ata_port *ap, struct ata_device *adev) 142 { 143 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 144 int dn = adev->devno + 2 * ap->port_no; 145 u8 ultra; 146 147 artop6210_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0); 148 149 /* Clear the UDMA mode bits (set_dmamode will redo this if needed) */ 150 pci_read_config_byte(pdev, 0x54, &ultra); 151 ultra &= ~(3 << (2 * dn)); 152 pci_write_config_byte(pdev, 0x54, ultra); 153 } 154 155 /** 156 * artop6260_load_piomode - Initialize host controller PATA PIO timings 157 * @ap: Port whose timings we are configuring 158 * @adev: Device we are configuring 159 * @pio: PIO mode 160 * 161 * Set PIO mode for device, in host controller PCI config space. The 162 * ARTOP6260 and relatives store the timing data differently. 163 * 164 * LOCKING: 165 * None (inherited from caller). 166 */ 167 168 static void artop6260_load_piomode (struct ata_port *ap, struct ata_device *adev, unsigned int pio) 169 { 170 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 171 int dn = adev->devno + 2 * ap->port_no; 172 const u8 timing[2][5] = { 173 { 0x00, 0x0A, 0x08, 0x33, 0x31 }, 174 { 0x70, 0x7A, 0x78, 0x43, 0x41 } 175 176 }; 177 /* Load the PIO timing active/recovery bits */ 178 pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]); 179 } 180 181 /** 182 * artop6260_set_piomode - Initialize host controller PATA PIO timings 183 * @ap: Port whose timings we are configuring 184 * @adev: Device we are configuring 185 * 186 * Set PIO mode for device, in host controller PCI config space. For 187 * ARTOP we must also clear the UDMA bits if we are not doing UDMA. In 188 * the event UDMA is used the later call to set_dmamode will set the 189 * bits as required. 190 * 191 * LOCKING: 192 * None (inherited from caller). 193 */ 194 195 static void artop6260_set_piomode(struct ata_port *ap, struct ata_device *adev) 196 { 197 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 198 u8 ultra; 199 200 artop6260_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0); 201 202 /* Clear the UDMA mode bits (set_dmamode will redo this if needed) */ 203 pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra); 204 ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */ 205 pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra); 206 } 207 208 /** 209 * artop6210_set_dmamode - Initialize host controller PATA PIO timings 210 * @ap: Port whose timings we are configuring 211 * @adev: Device whose timings we are configuring 212 * 213 * Set DMA mode for device, in host controller PCI config space. 214 * 215 * LOCKING: 216 * None (inherited from caller). 217 */ 218 219 static void artop6210_set_dmamode (struct ata_port *ap, struct ata_device *adev) 220 { 221 unsigned int pio; 222 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 223 int dn = adev->devno + 2 * ap->port_no; 224 u8 ultra; 225 226 if (adev->dma_mode == XFER_MW_DMA_0) 227 pio = 1; 228 else 229 pio = 4; 230 231 /* Load the PIO timing active/recovery bits */ 232 artop6210_load_piomode(ap, adev, pio); 233 234 pci_read_config_byte(pdev, 0x54, &ultra); 235 ultra &= ~(3 << (2 * dn)); 236 237 /* Add ultra DMA bits if in UDMA mode */ 238 if (adev->dma_mode >= XFER_UDMA_0) { 239 u8 mode = (adev->dma_mode - XFER_UDMA_0) + 1 - clock; 240 if (mode == 0) 241 mode = 1; 242 ultra |= (mode << (2 * dn)); 243 } 244 pci_write_config_byte(pdev, 0x54, ultra); 245 } 246 247 /** 248 * artop6260_set_dmamode - Initialize host controller PATA PIO timings 249 * @ap: Port whose timings we are configuring 250 * @adev: Device we are configuring 251 * 252 * Set DMA mode for device, in host controller PCI config space. The 253 * ARTOP6260 and relatives store the timing data differently. 254 * 255 * LOCKING: 256 * None (inherited from caller). 257 */ 258 259 static void artop6260_set_dmamode (struct ata_port *ap, struct ata_device *adev) 260 { 261 unsigned int pio = adev->pio_mode - XFER_PIO_0; 262 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 263 u8 ultra; 264 265 if (adev->dma_mode == XFER_MW_DMA_0) 266 pio = 1; 267 else 268 pio = 4; 269 270 /* Load the PIO timing active/recovery bits */ 271 artop6260_load_piomode(ap, adev, pio); 272 273 /* Add ultra DMA bits if in UDMA mode */ 274 pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra); 275 ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */ 276 if (adev->dma_mode >= XFER_UDMA_0) { 277 u8 mode = adev->dma_mode - XFER_UDMA_0 + 1 - clock; 278 if (mode == 0) 279 mode = 1; 280 ultra |= (mode << (4 * adev->devno)); 281 } 282 pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra); 283 } 284 285 /** 286 * artop_6210_qc_defer - implement serialization 287 * @qc: command 288 * 289 * Issue commands per host on this chip. 290 */ 291 292 static int artop6210_qc_defer(struct ata_queued_cmd *qc) 293 { 294 struct ata_host *host = qc->ap->host; 295 struct ata_port *alt = host->ports[1 ^ qc->ap->port_no]; 296 int rc; 297 298 /* First apply the usual rules */ 299 rc = ata_std_qc_defer(qc); 300 if (rc != 0) 301 return rc; 302 303 /* Now apply serialization rules. Only allow a command if the 304 other channel state machine is idle */ 305 if (alt && alt->qc_active) 306 return ATA_DEFER_PORT; 307 return 0; 308 } 309 310 static struct scsi_host_template artop_sht = { 311 ATA_BMDMA_SHT(DRV_NAME), 312 }; 313 314 static struct ata_port_operations artop6210_ops = { 315 .inherits = &ata_bmdma_port_ops, 316 .cable_detect = ata_cable_40wire, 317 .set_piomode = artop6210_set_piomode, 318 .set_dmamode = artop6210_set_dmamode, 319 .prereset = artop6210_pre_reset, 320 .qc_defer = artop6210_qc_defer, 321 }; 322 323 static struct ata_port_operations artop6260_ops = { 324 .inherits = &ata_bmdma_port_ops, 325 .cable_detect = artop6260_cable_detect, 326 .set_piomode = artop6260_set_piomode, 327 .set_dmamode = artop6260_set_dmamode, 328 .prereset = artop6260_pre_reset, 329 }; 330 331 332 /** 333 * artop_init_one - Register ARTOP ATA PCI device with kernel services 334 * @pdev: PCI device to register 335 * @ent: Entry in artop_pci_tbl matching with @pdev 336 * 337 * Called from kernel PCI layer. 338 * 339 * LOCKING: 340 * Inherited from PCI layer (may sleep). 341 * 342 * RETURNS: 343 * Zero on success, or -ERRNO value. 344 */ 345 346 static int artop_init_one (struct pci_dev *pdev, const struct pci_device_id *id) 347 { 348 static int printed_version; 349 static const struct ata_port_info info_6210 = { 350 .flags = ATA_FLAG_SLAVE_POSS, 351 .pio_mask = ATA_PIO4, 352 .mwdma_mask = ATA_MWDMA2, 353 .udma_mask = ATA_UDMA2, 354 .port_ops = &artop6210_ops, 355 }; 356 static const struct ata_port_info info_626x = { 357 .flags = ATA_FLAG_SLAVE_POSS, 358 .pio_mask = ATA_PIO4, 359 .mwdma_mask = ATA_MWDMA2, 360 .udma_mask = ATA_UDMA4, 361 .port_ops = &artop6260_ops, 362 }; 363 static const struct ata_port_info info_628x = { 364 .flags = ATA_FLAG_SLAVE_POSS, 365 .pio_mask = ATA_PIO4, 366 .mwdma_mask = ATA_MWDMA2, 367 .udma_mask = ATA_UDMA5, 368 .port_ops = &artop6260_ops, 369 }; 370 static const struct ata_port_info info_628x_fast = { 371 .flags = ATA_FLAG_SLAVE_POSS, 372 .pio_mask = ATA_PIO4, 373 .mwdma_mask = ATA_MWDMA2, 374 .udma_mask = ATA_UDMA6, 375 .port_ops = &artop6260_ops, 376 }; 377 const struct ata_port_info *ppi[] = { NULL, NULL }; 378 int rc; 379 380 if (!printed_version++) 381 dev_printk(KERN_DEBUG, &pdev->dev, 382 "version " DRV_VERSION "\n"); 383 384 rc = pcim_enable_device(pdev); 385 if (rc) 386 return rc; 387 388 if (id->driver_data == 0) { /* 6210 variant */ 389 ppi[0] = &info_6210; 390 /* BIOS may have left us in UDMA, clear it before libata probe */ 391 pci_write_config_byte(pdev, 0x54, 0); 392 } 393 else if (id->driver_data == 1) /* 6260 */ 394 ppi[0] = &info_626x; 395 else if (id->driver_data == 2) { /* 6280 or 6280 + fast */ 396 unsigned long io = pci_resource_start(pdev, 4); 397 u8 reg; 398 399 ppi[0] = &info_628x; 400 if (inb(io) & 0x10) 401 ppi[0] = &info_628x_fast; 402 /* Mac systems come up with some registers not set as we 403 will need them */ 404 405 /* Clear reset & test bits */ 406 pci_read_config_byte(pdev, 0x49, ®); 407 pci_write_config_byte(pdev, 0x49, reg & ~ 0x30); 408 409 /* PCI latency must be > 0x80 for burst mode, tweak it 410 * if required. 411 */ 412 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, ®); 413 if (reg <= 0x80) 414 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x90); 415 416 /* Enable IRQ output and burst mode */ 417 pci_read_config_byte(pdev, 0x4a, ®); 418 pci_write_config_byte(pdev, 0x4a, (reg & ~0x01) | 0x80); 419 420 } 421 422 BUG_ON(ppi[0] == NULL); 423 424 return ata_pci_sff_init_one(pdev, ppi, &artop_sht, NULL); 425 } 426 427 static const struct pci_device_id artop_pci_tbl[] = { 428 { PCI_VDEVICE(ARTOP, 0x0005), 0 }, 429 { PCI_VDEVICE(ARTOP, 0x0006), 1 }, 430 { PCI_VDEVICE(ARTOP, 0x0007), 1 }, 431 { PCI_VDEVICE(ARTOP, 0x0008), 2 }, 432 { PCI_VDEVICE(ARTOP, 0x0009), 2 }, 433 434 { } /* terminate list */ 435 }; 436 437 static struct pci_driver artop_pci_driver = { 438 .name = DRV_NAME, 439 .id_table = artop_pci_tbl, 440 .probe = artop_init_one, 441 .remove = ata_pci_remove_one, 442 }; 443 444 static int __init artop_init(void) 445 { 446 return pci_register_driver(&artop_pci_driver); 447 } 448 449 static void __exit artop_exit(void) 450 { 451 pci_unregister_driver(&artop_pci_driver); 452 } 453 454 module_init(artop_init); 455 module_exit(artop_exit); 456 457 MODULE_AUTHOR("Alan Cox"); 458 MODULE_DESCRIPTION("SCSI low-level driver for ARTOP PATA"); 459 MODULE_LICENSE("GPL"); 460 MODULE_DEVICE_TABLE(pci, artop_pci_tbl); 461 MODULE_VERSION(DRV_VERSION); 462 463