1 /* 2 * pata_amd.c - AMD PATA for new ATA layer 3 * (C) 2005-2006 Red Hat Inc 4 * 5 * Based on pata-sil680. Errata information is taken from data sheets 6 * and the amd74xx.c driver by Vojtech Pavlik. Nvidia SATA devices are 7 * claimed by sata-nv.c. 8 * 9 * TODO: 10 * Variable system clock when/if it makes sense 11 * Power management on ports 12 * 13 * 14 * Documentation publically available. 15 */ 16 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/pci.h> 20 #include <linux/init.h> 21 #include <linux/blkdev.h> 22 #include <linux/delay.h> 23 #include <scsi/scsi_host.h> 24 #include <linux/libata.h> 25 26 #define DRV_NAME "pata_amd" 27 #define DRV_VERSION "0.3.10" 28 29 /** 30 * timing_setup - shared timing computation and load 31 * @ap: ATA port being set up 32 * @adev: drive being configured 33 * @offset: port offset 34 * @speed: target speed 35 * @clock: clock multiplier (number of times 33MHz for this part) 36 * 37 * Perform the actual timing set up for Nvidia or AMD PATA devices. 38 * The actual devices vary so they all call into this helper function 39 * providing the clock multipler and offset (because AMD and Nvidia put 40 * the ports at different locations). 41 */ 42 43 static void timing_setup(struct ata_port *ap, struct ata_device *adev, int offset, int speed, int clock) 44 { 45 static const unsigned char amd_cyc2udma[] = { 46 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 47 }; 48 49 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 50 struct ata_device *peer = ata_dev_pair(adev); 51 int dn = ap->port_no * 2 + adev->devno; 52 struct ata_timing at, apeer; 53 int T, UT; 54 const int amd_clock = 33333; /* KHz. */ 55 u8 t; 56 57 T = 1000000000 / amd_clock; 58 UT = T; 59 if (clock >= 2) 60 UT = T / 2; 61 62 if (ata_timing_compute(adev, speed, &at, T, UT) < 0) { 63 dev_printk(KERN_ERR, &pdev->dev, "unknown mode %d.\n", speed); 64 return; 65 } 66 67 if (peer) { 68 /* This may be over conservative */ 69 if (peer->dma_mode) { 70 ata_timing_compute(peer, peer->dma_mode, &apeer, T, UT); 71 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT); 72 } 73 ata_timing_compute(peer, peer->pio_mode, &apeer, T, UT); 74 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT); 75 } 76 77 if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1; 78 if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15; 79 80 /* 81 * Now do the setup work 82 */ 83 84 /* Configure the address set up timing */ 85 pci_read_config_byte(pdev, offset + 0x0C, &t); 86 t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(at.setup, 1, 4) - 1) << ((3 - dn) << 1)); 87 pci_write_config_byte(pdev, offset + 0x0C , t); 88 89 /* Configure the 8bit I/O timing */ 90 pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)), 91 ((clamp_val(at.act8b, 1, 16) - 1) << 4) | (clamp_val(at.rec8b, 1, 16) - 1)); 92 93 /* Drive timing */ 94 pci_write_config_byte(pdev, offset + 0x08 + (3 - dn), 95 ((clamp_val(at.active, 1, 16) - 1) << 4) | (clamp_val(at.recover, 1, 16) - 1)); 96 97 switch (clock) { 98 case 1: 99 t = at.udma ? (0xc0 | (clamp_val(at.udma, 2, 5) - 2)) : 0x03; 100 break; 101 102 case 2: 103 t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 2, 10)]) : 0x03; 104 break; 105 106 case 3: 107 t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 10)]) : 0x03; 108 break; 109 110 case 4: 111 t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 15)]) : 0x03; 112 break; 113 114 default: 115 return; 116 } 117 118 /* UDMA timing */ 119 if (at.udma) 120 pci_write_config_byte(pdev, offset + 0x10 + (3 - dn), t); 121 } 122 123 /** 124 * amd_pre_reset - perform reset handling 125 * @link: ATA link 126 * @deadline: deadline jiffies for the operation 127 * 128 * Reset sequence checking enable bits to see which ports are 129 * active. 130 */ 131 132 static int amd_pre_reset(struct ata_link *link, unsigned long deadline) 133 { 134 static const struct pci_bits amd_enable_bits[] = { 135 { 0x40, 1, 0x02, 0x02 }, 136 { 0x40, 1, 0x01, 0x01 } 137 }; 138 139 struct ata_port *ap = link->ap; 140 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 141 142 if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no])) 143 return -ENOENT; 144 145 return ata_sff_prereset(link, deadline); 146 } 147 148 static int amd_cable_detect(struct ata_port *ap) 149 { 150 static const u32 bitmask[2] = {0x03, 0x0C}; 151 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 152 u8 ata66; 153 154 pci_read_config_byte(pdev, 0x42, &ata66); 155 if (ata66 & bitmask[ap->port_no]) 156 return ATA_CBL_PATA80; 157 return ATA_CBL_PATA40; 158 } 159 160 /** 161 * amd33_set_piomode - set initial PIO mode data 162 * @ap: ATA interface 163 * @adev: ATA device 164 * 165 * Program the AMD registers for PIO mode. 166 */ 167 168 static void amd33_set_piomode(struct ata_port *ap, struct ata_device *adev) 169 { 170 timing_setup(ap, adev, 0x40, adev->pio_mode, 1); 171 } 172 173 static void amd66_set_piomode(struct ata_port *ap, struct ata_device *adev) 174 { 175 timing_setup(ap, adev, 0x40, adev->pio_mode, 2); 176 } 177 178 static void amd100_set_piomode(struct ata_port *ap, struct ata_device *adev) 179 { 180 timing_setup(ap, adev, 0x40, adev->pio_mode, 3); 181 } 182 183 static void amd133_set_piomode(struct ata_port *ap, struct ata_device *adev) 184 { 185 timing_setup(ap, adev, 0x40, adev->pio_mode, 4); 186 } 187 188 /** 189 * amd33_set_dmamode - set initial DMA mode data 190 * @ap: ATA interface 191 * @adev: ATA device 192 * 193 * Program the MWDMA/UDMA modes for the AMD and Nvidia 194 * chipset. 195 */ 196 197 static void amd33_set_dmamode(struct ata_port *ap, struct ata_device *adev) 198 { 199 timing_setup(ap, adev, 0x40, adev->dma_mode, 1); 200 } 201 202 static void amd66_set_dmamode(struct ata_port *ap, struct ata_device *adev) 203 { 204 timing_setup(ap, adev, 0x40, adev->dma_mode, 2); 205 } 206 207 static void amd100_set_dmamode(struct ata_port *ap, struct ata_device *adev) 208 { 209 timing_setup(ap, adev, 0x40, adev->dma_mode, 3); 210 } 211 212 static void amd133_set_dmamode(struct ata_port *ap, struct ata_device *adev) 213 { 214 timing_setup(ap, adev, 0x40, adev->dma_mode, 4); 215 } 216 217 /* Both host-side and drive-side detection results are worthless on NV 218 * PATAs. Ignore them and just follow what BIOS configured. Both the 219 * current configuration in PCI config reg and ACPI GTM result are 220 * cached during driver attach and are consulted to select transfer 221 * mode. 222 */ 223 static unsigned long nv_mode_filter(struct ata_device *dev, 224 unsigned long xfer_mask) 225 { 226 static const unsigned int udma_mask_map[] = 227 { ATA_UDMA2, ATA_UDMA1, ATA_UDMA0, 0, 228 ATA_UDMA3, ATA_UDMA4, ATA_UDMA5, ATA_UDMA6 }; 229 struct ata_port *ap = dev->link->ap; 230 char acpi_str[32] = ""; 231 u32 saved_udma, udma; 232 const struct ata_acpi_gtm *gtm; 233 unsigned long bios_limit = 0, acpi_limit = 0, limit; 234 235 /* find out what BIOS configured */ 236 udma = saved_udma = (unsigned long)ap->host->private_data; 237 238 if (ap->port_no == 0) 239 udma >>= 16; 240 if (dev->devno == 0) 241 udma >>= 8; 242 243 if ((udma & 0xc0) == 0xc0) 244 bios_limit = ata_pack_xfermask(0, 0, udma_mask_map[udma & 0x7]); 245 246 /* consult ACPI GTM too */ 247 gtm = ata_acpi_init_gtm(ap); 248 if (gtm) { 249 acpi_limit = ata_acpi_gtm_xfermask(dev, gtm); 250 251 snprintf(acpi_str, sizeof(acpi_str), " (%u:%u:0x%x)", 252 gtm->drive[0].dma, gtm->drive[1].dma, gtm->flags); 253 } 254 255 /* be optimistic, EH can take care of things if something goes wrong */ 256 limit = bios_limit | acpi_limit; 257 258 /* If PIO or DMA isn't configured at all, don't limit. Let EH 259 * handle it. 260 */ 261 if (!(limit & ATA_MASK_PIO)) 262 limit |= ATA_MASK_PIO; 263 if (!(limit & (ATA_MASK_MWDMA | ATA_MASK_UDMA))) 264 limit |= ATA_MASK_MWDMA | ATA_MASK_UDMA; 265 266 ata_port_printk(ap, KERN_DEBUG, "nv_mode_filter: 0x%lx&0x%lx->0x%lx, " 267 "BIOS=0x%lx (0x%x) ACPI=0x%lx%s\n", 268 xfer_mask, limit, xfer_mask & limit, bios_limit, 269 saved_udma, acpi_limit, acpi_str); 270 271 return xfer_mask & limit; 272 } 273 274 /** 275 * nv_probe_init - cable detection 276 * @lin: ATA link 277 * 278 * Perform cable detection. The BIOS stores this in PCI config 279 * space for us. 280 */ 281 282 static int nv_pre_reset(struct ata_link *link, unsigned long deadline) 283 { 284 static const struct pci_bits nv_enable_bits[] = { 285 { 0x50, 1, 0x02, 0x02 }, 286 { 0x50, 1, 0x01, 0x01 } 287 }; 288 289 struct ata_port *ap = link->ap; 290 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 291 292 if (!pci_test_config_bits(pdev, &nv_enable_bits[ap->port_no])) 293 return -ENOENT; 294 295 return ata_sff_prereset(link, deadline); 296 } 297 298 /** 299 * nv100_set_piomode - set initial PIO mode data 300 * @ap: ATA interface 301 * @adev: ATA device 302 * 303 * Program the AMD registers for PIO mode. 304 */ 305 306 static void nv100_set_piomode(struct ata_port *ap, struct ata_device *adev) 307 { 308 timing_setup(ap, adev, 0x50, adev->pio_mode, 3); 309 } 310 311 static void nv133_set_piomode(struct ata_port *ap, struct ata_device *adev) 312 { 313 timing_setup(ap, adev, 0x50, adev->pio_mode, 4); 314 } 315 316 /** 317 * nv100_set_dmamode - set initial DMA mode data 318 * @ap: ATA interface 319 * @adev: ATA device 320 * 321 * Program the MWDMA/UDMA modes for the AMD and Nvidia 322 * chipset. 323 */ 324 325 static void nv100_set_dmamode(struct ata_port *ap, struct ata_device *adev) 326 { 327 timing_setup(ap, adev, 0x50, adev->dma_mode, 3); 328 } 329 330 static void nv133_set_dmamode(struct ata_port *ap, struct ata_device *adev) 331 { 332 timing_setup(ap, adev, 0x50, adev->dma_mode, 4); 333 } 334 335 static void nv_host_stop(struct ata_host *host) 336 { 337 u32 udma = (unsigned long)host->private_data; 338 339 /* restore PCI config register 0x60 */ 340 pci_write_config_dword(to_pci_dev(host->dev), 0x60, udma); 341 } 342 343 static struct scsi_host_template amd_sht = { 344 ATA_BMDMA_SHT(DRV_NAME), 345 }; 346 347 static const struct ata_port_operations amd_base_port_ops = { 348 .inherits = &ata_bmdma_port_ops, 349 .prereset = amd_pre_reset, 350 }; 351 352 static struct ata_port_operations amd33_port_ops = { 353 .inherits = &amd_base_port_ops, 354 .cable_detect = ata_cable_40wire, 355 .set_piomode = amd33_set_piomode, 356 .set_dmamode = amd33_set_dmamode, 357 }; 358 359 static struct ata_port_operations amd66_port_ops = { 360 .inherits = &amd_base_port_ops, 361 .cable_detect = ata_cable_unknown, 362 .set_piomode = amd66_set_piomode, 363 .set_dmamode = amd66_set_dmamode, 364 }; 365 366 static struct ata_port_operations amd100_port_ops = { 367 .inherits = &amd_base_port_ops, 368 .cable_detect = ata_cable_unknown, 369 .set_piomode = amd100_set_piomode, 370 .set_dmamode = amd100_set_dmamode, 371 }; 372 373 static struct ata_port_operations amd133_port_ops = { 374 .inherits = &amd_base_port_ops, 375 .cable_detect = amd_cable_detect, 376 .set_piomode = amd133_set_piomode, 377 .set_dmamode = amd133_set_dmamode, 378 }; 379 380 static const struct ata_port_operations nv_base_port_ops = { 381 .inherits = &ata_bmdma_port_ops, 382 .cable_detect = ata_cable_ignore, 383 .mode_filter = nv_mode_filter, 384 .prereset = nv_pre_reset, 385 .host_stop = nv_host_stop, 386 }; 387 388 static struct ata_port_operations nv100_port_ops = { 389 .inherits = &nv_base_port_ops, 390 .set_piomode = nv100_set_piomode, 391 .set_dmamode = nv100_set_dmamode, 392 }; 393 394 static struct ata_port_operations nv133_port_ops = { 395 .inherits = &nv_base_port_ops, 396 .set_piomode = nv133_set_piomode, 397 .set_dmamode = nv133_set_dmamode, 398 }; 399 400 static int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 401 { 402 static const struct ata_port_info info[10] = { 403 { /* 0: AMD 7401 */ 404 .flags = ATA_FLAG_SLAVE_POSS, 405 .pio_mask = 0x1f, 406 .mwdma_mask = 0x07, /* No SWDMA */ 407 .udma_mask = 0x07, /* UDMA 33 */ 408 .port_ops = &amd33_port_ops 409 }, 410 { /* 1: Early AMD7409 - no swdma */ 411 .flags = ATA_FLAG_SLAVE_POSS, 412 .pio_mask = 0x1f, 413 .mwdma_mask = 0x07, 414 .udma_mask = ATA_UDMA4, /* UDMA 66 */ 415 .port_ops = &amd66_port_ops 416 }, 417 { /* 2: AMD 7409, no swdma errata */ 418 .flags = ATA_FLAG_SLAVE_POSS, 419 .pio_mask = 0x1f, 420 .mwdma_mask = 0x07, 421 .udma_mask = ATA_UDMA4, /* UDMA 66 */ 422 .port_ops = &amd66_port_ops 423 }, 424 { /* 3: AMD 7411 */ 425 .flags = ATA_FLAG_SLAVE_POSS, 426 .pio_mask = 0x1f, 427 .mwdma_mask = 0x07, 428 .udma_mask = ATA_UDMA5, /* UDMA 100 */ 429 .port_ops = &amd100_port_ops 430 }, 431 { /* 4: AMD 7441 */ 432 .flags = ATA_FLAG_SLAVE_POSS, 433 .pio_mask = 0x1f, 434 .mwdma_mask = 0x07, 435 .udma_mask = ATA_UDMA5, /* UDMA 100 */ 436 .port_ops = &amd100_port_ops 437 }, 438 { /* 5: AMD 8111*/ 439 .flags = ATA_FLAG_SLAVE_POSS, 440 .pio_mask = 0x1f, 441 .mwdma_mask = 0x07, 442 .udma_mask = ATA_UDMA6, /* UDMA 133, no swdma */ 443 .port_ops = &amd133_port_ops 444 }, 445 { /* 6: AMD 8111 UDMA 100 (Serenade) */ 446 .flags = ATA_FLAG_SLAVE_POSS, 447 .pio_mask = 0x1f, 448 .mwdma_mask = 0x07, 449 .udma_mask = ATA_UDMA5, /* UDMA 100, no swdma */ 450 .port_ops = &amd133_port_ops 451 }, 452 { /* 7: Nvidia Nforce */ 453 .flags = ATA_FLAG_SLAVE_POSS, 454 .pio_mask = 0x1f, 455 .mwdma_mask = 0x07, 456 .udma_mask = ATA_UDMA5, /* UDMA 100 */ 457 .port_ops = &nv100_port_ops 458 }, 459 { /* 8: Nvidia Nforce2 and later */ 460 .flags = ATA_FLAG_SLAVE_POSS, 461 .pio_mask = 0x1f, 462 .mwdma_mask = 0x07, 463 .udma_mask = ATA_UDMA6, /* UDMA 133, no swdma */ 464 .port_ops = &nv133_port_ops 465 }, 466 { /* 9: AMD CS5536 (Geode companion) */ 467 .flags = ATA_FLAG_SLAVE_POSS, 468 .pio_mask = 0x1f, 469 .mwdma_mask = 0x07, 470 .udma_mask = ATA_UDMA5, /* UDMA 100 */ 471 .port_ops = &amd100_port_ops 472 } 473 }; 474 const struct ata_port_info *ppi[] = { NULL, NULL }; 475 static int printed_version; 476 int type = id->driver_data; 477 void *hpriv = NULL; 478 u8 fifo; 479 int rc; 480 481 if (!printed_version++) 482 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 483 484 rc = pcim_enable_device(pdev); 485 if (rc) 486 return rc; 487 488 pci_read_config_byte(pdev, 0x41, &fifo); 489 490 /* Check for AMD7409 without swdma errata and if found adjust type */ 491 if (type == 1 && pdev->revision > 0x7) 492 type = 2; 493 494 /* Serenade ? */ 495 if (type == 5 && pdev->subsystem_vendor == PCI_VENDOR_ID_AMD && 496 pdev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE) 497 type = 6; /* UDMA 100 only */ 498 499 /* 500 * Okay, type is determined now. Apply type-specific workarounds. 501 */ 502 ppi[0] = &info[type]; 503 504 if (type < 3) 505 ata_pci_bmdma_clear_simplex(pdev); 506 507 /* Check for AMD7411 */ 508 if (type == 3) 509 /* FIFO is broken */ 510 pci_write_config_byte(pdev, 0x41, fifo & 0x0F); 511 else 512 pci_write_config_byte(pdev, 0x41, fifo | 0xF0); 513 514 /* Cable detection on Nvidia chips doesn't work too well, 515 * cache BIOS programmed UDMA mode. 516 */ 517 if (type == 7 || type == 8) { 518 u32 udma; 519 520 pci_read_config_dword(pdev, 0x60, &udma); 521 hpriv = (void *)(unsigned long)udma; 522 } 523 524 /* And fire it up */ 525 return ata_pci_sff_init_one(pdev, ppi, &amd_sht, hpriv); 526 } 527 528 #ifdef CONFIG_PM 529 static int amd_reinit_one(struct pci_dev *pdev) 530 { 531 struct ata_host *host = dev_get_drvdata(&pdev->dev); 532 int rc; 533 534 rc = ata_pci_device_do_resume(pdev); 535 if (rc) 536 return rc; 537 538 if (pdev->vendor == PCI_VENDOR_ID_AMD) { 539 u8 fifo; 540 pci_read_config_byte(pdev, 0x41, &fifo); 541 if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7411) 542 /* FIFO is broken */ 543 pci_write_config_byte(pdev, 0x41, fifo & 0x0F); 544 else 545 pci_write_config_byte(pdev, 0x41, fifo | 0xF0); 546 if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7409 || 547 pdev->device == PCI_DEVICE_ID_AMD_COBRA_7401) 548 ata_pci_bmdma_clear_simplex(pdev); 549 } 550 551 ata_host_resume(host); 552 return 0; 553 } 554 #endif 555 556 static const struct pci_device_id amd[] = { 557 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 }, 558 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 }, 559 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 3 }, 560 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 4 }, 561 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 5 }, 562 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 7 }, 563 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 8 }, 564 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 8 }, 565 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 8 }, 566 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 8 }, 567 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 8 }, 568 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 8 }, 569 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 8 }, 570 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 8 }, 571 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 8 }, 572 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 8 }, 573 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 8 }, 574 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 8 }, 575 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 8 }, 576 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 9 }, 577 578 { }, 579 }; 580 581 static struct pci_driver amd_pci_driver = { 582 .name = DRV_NAME, 583 .id_table = amd, 584 .probe = amd_init_one, 585 .remove = ata_pci_remove_one, 586 #ifdef CONFIG_PM 587 .suspend = ata_pci_device_suspend, 588 .resume = amd_reinit_one, 589 #endif 590 }; 591 592 static int __init amd_init(void) 593 { 594 return pci_register_driver(&amd_pci_driver); 595 } 596 597 static void __exit amd_exit(void) 598 { 599 pci_unregister_driver(&amd_pci_driver); 600 } 601 602 MODULE_AUTHOR("Alan Cox"); 603 MODULE_DESCRIPTION("low-level driver for AMD and Nvidia PATA IDE"); 604 MODULE_LICENSE("GPL"); 605 MODULE_DEVICE_TABLE(pci, amd); 606 MODULE_VERSION(DRV_VERSION); 607 608 module_init(amd_init); 609 module_exit(amd_exit); 610