1 /* 2 * libata-sff.c - helper library for PCI IDE BMDMA 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2003-2006 Red Hat, Inc. All rights reserved. 9 * Copyright 2003-2006 Jeff Garzik 10 * 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2, or (at your option) 15 * any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; see the file COPYING. If not, write to 24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 26 * 27 * libata documentation is available via 'make {ps|pdf}docs', 28 * as Documentation/DocBook/libata.* 29 * 30 * Hardware documentation available from http://www.t13.org/ and 31 * http://www.sata-io.org/ 32 * 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/pci.h> 37 #include <linux/libata.h> 38 #include <linux/highmem.h> 39 40 #include "libata.h" 41 42 const struct ata_port_operations ata_sff_port_ops = { 43 .inherits = &ata_base_port_ops, 44 45 .qc_prep = ata_sff_qc_prep, 46 .qc_issue = ata_sff_qc_issue, 47 .qc_fill_rtf = ata_sff_qc_fill_rtf, 48 49 .freeze = ata_sff_freeze, 50 .thaw = ata_sff_thaw, 51 .prereset = ata_sff_prereset, 52 .softreset = ata_sff_softreset, 53 .hardreset = sata_sff_hardreset, 54 .postreset = ata_sff_postreset, 55 .error_handler = ata_sff_error_handler, 56 .post_internal_cmd = ata_sff_post_internal_cmd, 57 58 .sff_dev_select = ata_sff_dev_select, 59 .sff_check_status = ata_sff_check_status, 60 .sff_tf_load = ata_sff_tf_load, 61 .sff_tf_read = ata_sff_tf_read, 62 .sff_exec_command = ata_sff_exec_command, 63 .sff_data_xfer = ata_sff_data_xfer, 64 .sff_irq_on = ata_sff_irq_on, 65 .sff_irq_clear = ata_sff_irq_clear, 66 67 .port_start = ata_sff_port_start, 68 }; 69 70 const struct ata_port_operations ata_bmdma_port_ops = { 71 .inherits = &ata_sff_port_ops, 72 73 .mode_filter = ata_bmdma_mode_filter, 74 75 .bmdma_setup = ata_bmdma_setup, 76 .bmdma_start = ata_bmdma_start, 77 .bmdma_stop = ata_bmdma_stop, 78 .bmdma_status = ata_bmdma_status, 79 }; 80 81 /** 82 * ata_fill_sg - Fill PCI IDE PRD table 83 * @qc: Metadata associated with taskfile to be transferred 84 * 85 * Fill PCI IDE PRD (scatter-gather) table with segments 86 * associated with the current disk command. 87 * 88 * LOCKING: 89 * spin_lock_irqsave(host lock) 90 * 91 */ 92 static void ata_fill_sg(struct ata_queued_cmd *qc) 93 { 94 struct ata_port *ap = qc->ap; 95 struct scatterlist *sg; 96 unsigned int si, pi; 97 98 pi = 0; 99 for_each_sg(qc->sg, sg, qc->n_elem, si) { 100 u32 addr, offset; 101 u32 sg_len, len; 102 103 /* determine if physical DMA addr spans 64K boundary. 104 * Note h/w doesn't support 64-bit, so we unconditionally 105 * truncate dma_addr_t to u32. 106 */ 107 addr = (u32) sg_dma_address(sg); 108 sg_len = sg_dma_len(sg); 109 110 while (sg_len) { 111 offset = addr & 0xffff; 112 len = sg_len; 113 if ((offset + sg_len) > 0x10000) 114 len = 0x10000 - offset; 115 116 ap->prd[pi].addr = cpu_to_le32(addr); 117 ap->prd[pi].flags_len = cpu_to_le32(len & 0xffff); 118 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len); 119 120 pi++; 121 sg_len -= len; 122 addr += len; 123 } 124 } 125 126 ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); 127 } 128 129 /** 130 * ata_fill_sg_dumb - Fill PCI IDE PRD table 131 * @qc: Metadata associated with taskfile to be transferred 132 * 133 * Fill PCI IDE PRD (scatter-gather) table with segments 134 * associated with the current disk command. Perform the fill 135 * so that we avoid writing any length 64K records for 136 * controllers that don't follow the spec. 137 * 138 * LOCKING: 139 * spin_lock_irqsave(host lock) 140 * 141 */ 142 static void ata_fill_sg_dumb(struct ata_queued_cmd *qc) 143 { 144 struct ata_port *ap = qc->ap; 145 struct scatterlist *sg; 146 unsigned int si, pi; 147 148 pi = 0; 149 for_each_sg(qc->sg, sg, qc->n_elem, si) { 150 u32 addr, offset; 151 u32 sg_len, len, blen; 152 153 /* determine if physical DMA addr spans 64K boundary. 154 * Note h/w doesn't support 64-bit, so we unconditionally 155 * truncate dma_addr_t to u32. 156 */ 157 addr = (u32) sg_dma_address(sg); 158 sg_len = sg_dma_len(sg); 159 160 while (sg_len) { 161 offset = addr & 0xffff; 162 len = sg_len; 163 if ((offset + sg_len) > 0x10000) 164 len = 0x10000 - offset; 165 166 blen = len & 0xffff; 167 ap->prd[pi].addr = cpu_to_le32(addr); 168 if (blen == 0) { 169 /* Some PATA chipsets like the CS5530 can't 170 cope with 0x0000 meaning 64K as the spec says */ 171 ap->prd[pi].flags_len = cpu_to_le32(0x8000); 172 blen = 0x8000; 173 ap->prd[++pi].addr = cpu_to_le32(addr + 0x8000); 174 } 175 ap->prd[pi].flags_len = cpu_to_le32(blen); 176 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len); 177 178 pi++; 179 sg_len -= len; 180 addr += len; 181 } 182 } 183 184 ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); 185 } 186 187 /** 188 * ata_sff_qc_prep - Prepare taskfile for submission 189 * @qc: Metadata associated with taskfile to be prepared 190 * 191 * Prepare ATA taskfile for submission. 192 * 193 * LOCKING: 194 * spin_lock_irqsave(host lock) 195 */ 196 void ata_sff_qc_prep(struct ata_queued_cmd *qc) 197 { 198 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 199 return; 200 201 ata_fill_sg(qc); 202 } 203 204 /** 205 * ata_sff_dumb_qc_prep - Prepare taskfile for submission 206 * @qc: Metadata associated with taskfile to be prepared 207 * 208 * Prepare ATA taskfile for submission. 209 * 210 * LOCKING: 211 * spin_lock_irqsave(host lock) 212 */ 213 void ata_sff_dumb_qc_prep(struct ata_queued_cmd *qc) 214 { 215 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 216 return; 217 218 ata_fill_sg_dumb(qc); 219 } 220 221 /** 222 * ata_sff_check_status - Read device status reg & clear interrupt 223 * @ap: port where the device is 224 * 225 * Reads ATA taskfile status register for currently-selected device 226 * and return its value. This also clears pending interrupts 227 * from this device 228 * 229 * LOCKING: 230 * Inherited from caller. 231 */ 232 u8 ata_sff_check_status(struct ata_port *ap) 233 { 234 return ioread8(ap->ioaddr.status_addr); 235 } 236 237 /** 238 * ata_sff_altstatus - Read device alternate status reg 239 * @ap: port where the device is 240 * 241 * Reads ATA taskfile alternate status register for 242 * currently-selected device and return its value. 243 * 244 * Note: may NOT be used as the check_altstatus() entry in 245 * ata_port_operations. 246 * 247 * LOCKING: 248 * Inherited from caller. 249 */ 250 static u8 ata_sff_altstatus(struct ata_port *ap) 251 { 252 if (ap->ops->sff_check_altstatus) 253 return ap->ops->sff_check_altstatus(ap); 254 255 return ioread8(ap->ioaddr.altstatus_addr); 256 } 257 258 /** 259 * ata_sff_irq_status - Check if the device is busy 260 * @ap: port where the device is 261 * 262 * Determine if the port is currently busy. Uses altstatus 263 * if available in order to avoid clearing shared IRQ status 264 * when finding an IRQ source. Non ctl capable devices don't 265 * share interrupt lines fortunately for us. 266 * 267 * LOCKING: 268 * Inherited from caller. 269 */ 270 static u8 ata_sff_irq_status(struct ata_port *ap) 271 { 272 u8 status; 273 274 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) { 275 status = ata_sff_altstatus(ap); 276 /* Not us: We are busy */ 277 if (status & ATA_BUSY) 278 return status; 279 } 280 /* Clear INTRQ latch */ 281 status = ap->ops->sff_check_status(ap); 282 return status; 283 } 284 285 /** 286 * ata_sff_sync - Flush writes 287 * @ap: Port to wait for. 288 * 289 * CAUTION: 290 * If we have an mmio device with no ctl and no altstatus 291 * method this will fail. No such devices are known to exist. 292 * 293 * LOCKING: 294 * Inherited from caller. 295 */ 296 297 static void ata_sff_sync(struct ata_port *ap) 298 { 299 if (ap->ops->sff_check_altstatus) 300 ap->ops->sff_check_altstatus(ap); 301 else if (ap->ioaddr.altstatus_addr) 302 ioread8(ap->ioaddr.altstatus_addr); 303 } 304 305 /** 306 * ata_sff_pause - Flush writes and wait 400nS 307 * @ap: Port to pause for. 308 * 309 * CAUTION: 310 * If we have an mmio device with no ctl and no altstatus 311 * method this will fail. No such devices are known to exist. 312 * 313 * LOCKING: 314 * Inherited from caller. 315 */ 316 317 void ata_sff_pause(struct ata_port *ap) 318 { 319 ata_sff_sync(ap); 320 ndelay(400); 321 } 322 323 /** 324 * ata_sff_dma_pause - Pause before commencing DMA 325 * @ap: Port to pause for. 326 * 327 * Perform I/O fencing and ensure sufficient cycle delays occur 328 * for the HDMA1:0 transition 329 */ 330 331 void ata_sff_dma_pause(struct ata_port *ap) 332 { 333 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) { 334 /* An altstatus read will cause the needed delay without 335 messing up the IRQ status */ 336 ata_sff_altstatus(ap); 337 return; 338 } 339 /* There are no DMA controllers without ctl. BUG here to ensure 340 we never violate the HDMA1:0 transition timing and risk 341 corruption. */ 342 BUG(); 343 } 344 345 /** 346 * ata_sff_busy_sleep - sleep until BSY clears, or timeout 347 * @ap: port containing status register to be polled 348 * @tmout_pat: impatience timeout in msecs 349 * @tmout: overall timeout in msecs 350 * 351 * Sleep until ATA Status register bit BSY clears, 352 * or a timeout occurs. 353 * 354 * LOCKING: 355 * Kernel thread context (may sleep). 356 * 357 * RETURNS: 358 * 0 on success, -errno otherwise. 359 */ 360 int ata_sff_busy_sleep(struct ata_port *ap, 361 unsigned long tmout_pat, unsigned long tmout) 362 { 363 unsigned long timer_start, timeout; 364 u8 status; 365 366 status = ata_sff_busy_wait(ap, ATA_BUSY, 300); 367 timer_start = jiffies; 368 timeout = ata_deadline(timer_start, tmout_pat); 369 while (status != 0xff && (status & ATA_BUSY) && 370 time_before(jiffies, timeout)) { 371 msleep(50); 372 status = ata_sff_busy_wait(ap, ATA_BUSY, 3); 373 } 374 375 if (status != 0xff && (status & ATA_BUSY)) 376 ata_port_printk(ap, KERN_WARNING, 377 "port is slow to respond, please be patient " 378 "(Status 0x%x)\n", status); 379 380 timeout = ata_deadline(timer_start, tmout); 381 while (status != 0xff && (status & ATA_BUSY) && 382 time_before(jiffies, timeout)) { 383 msleep(50); 384 status = ap->ops->sff_check_status(ap); 385 } 386 387 if (status == 0xff) 388 return -ENODEV; 389 390 if (status & ATA_BUSY) { 391 ata_port_printk(ap, KERN_ERR, "port failed to respond " 392 "(%lu secs, Status 0x%x)\n", 393 DIV_ROUND_UP(tmout, 1000), status); 394 return -EBUSY; 395 } 396 397 return 0; 398 } 399 400 static int ata_sff_check_ready(struct ata_link *link) 401 { 402 u8 status = link->ap->ops->sff_check_status(link->ap); 403 404 return ata_check_ready(status); 405 } 406 407 /** 408 * ata_sff_wait_ready - sleep until BSY clears, or timeout 409 * @link: SFF link to wait ready status for 410 * @deadline: deadline jiffies for the operation 411 * 412 * Sleep until ATA Status register bit BSY clears, or timeout 413 * occurs. 414 * 415 * LOCKING: 416 * Kernel thread context (may sleep). 417 * 418 * RETURNS: 419 * 0 on success, -errno otherwise. 420 */ 421 int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline) 422 { 423 return ata_wait_ready(link, deadline, ata_sff_check_ready); 424 } 425 426 /** 427 * ata_sff_dev_select - Select device 0/1 on ATA bus 428 * @ap: ATA channel to manipulate 429 * @device: ATA device (numbered from zero) to select 430 * 431 * Use the method defined in the ATA specification to 432 * make either device 0, or device 1, active on the 433 * ATA channel. Works with both PIO and MMIO. 434 * 435 * May be used as the dev_select() entry in ata_port_operations. 436 * 437 * LOCKING: 438 * caller. 439 */ 440 void ata_sff_dev_select(struct ata_port *ap, unsigned int device) 441 { 442 u8 tmp; 443 444 if (device == 0) 445 tmp = ATA_DEVICE_OBS; 446 else 447 tmp = ATA_DEVICE_OBS | ATA_DEV1; 448 449 iowrite8(tmp, ap->ioaddr.device_addr); 450 ata_sff_pause(ap); /* needed; also flushes, for mmio */ 451 } 452 453 /** 454 * ata_dev_select - Select device 0/1 on ATA bus 455 * @ap: ATA channel to manipulate 456 * @device: ATA device (numbered from zero) to select 457 * @wait: non-zero to wait for Status register BSY bit to clear 458 * @can_sleep: non-zero if context allows sleeping 459 * 460 * Use the method defined in the ATA specification to 461 * make either device 0, or device 1, active on the 462 * ATA channel. 463 * 464 * This is a high-level version of ata_sff_dev_select(), which 465 * additionally provides the services of inserting the proper 466 * pauses and status polling, where needed. 467 * 468 * LOCKING: 469 * caller. 470 */ 471 void ata_dev_select(struct ata_port *ap, unsigned int device, 472 unsigned int wait, unsigned int can_sleep) 473 { 474 if (ata_msg_probe(ap)) 475 ata_port_printk(ap, KERN_INFO, "ata_dev_select: ENTER, " 476 "device %u, wait %u\n", device, wait); 477 478 if (wait) 479 ata_wait_idle(ap); 480 481 ap->ops->sff_dev_select(ap, device); 482 483 if (wait) { 484 if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI) 485 msleep(150); 486 ata_wait_idle(ap); 487 } 488 } 489 490 /** 491 * ata_sff_irq_on - Enable interrupts on a port. 492 * @ap: Port on which interrupts are enabled. 493 * 494 * Enable interrupts on a legacy IDE device using MMIO or PIO, 495 * wait for idle, clear any pending interrupts. 496 * 497 * LOCKING: 498 * Inherited from caller. 499 */ 500 u8 ata_sff_irq_on(struct ata_port *ap) 501 { 502 struct ata_ioports *ioaddr = &ap->ioaddr; 503 u8 tmp; 504 505 ap->ctl &= ~ATA_NIEN; 506 ap->last_ctl = ap->ctl; 507 508 if (ioaddr->ctl_addr) 509 iowrite8(ap->ctl, ioaddr->ctl_addr); 510 tmp = ata_wait_idle(ap); 511 512 ap->ops->sff_irq_clear(ap); 513 514 return tmp; 515 } 516 517 /** 518 * ata_sff_irq_clear - Clear PCI IDE BMDMA interrupt. 519 * @ap: Port associated with this ATA transaction. 520 * 521 * Clear interrupt and error flags in DMA status register. 522 * 523 * May be used as the irq_clear() entry in ata_port_operations. 524 * 525 * LOCKING: 526 * spin_lock_irqsave(host lock) 527 */ 528 void ata_sff_irq_clear(struct ata_port *ap) 529 { 530 void __iomem *mmio = ap->ioaddr.bmdma_addr; 531 532 if (!mmio) 533 return; 534 535 iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS); 536 } 537 538 /** 539 * ata_sff_tf_load - send taskfile registers to host controller 540 * @ap: Port to which output is sent 541 * @tf: ATA taskfile register set 542 * 543 * Outputs ATA taskfile to standard ATA host controller. 544 * 545 * LOCKING: 546 * Inherited from caller. 547 */ 548 void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) 549 { 550 struct ata_ioports *ioaddr = &ap->ioaddr; 551 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; 552 553 if (tf->ctl != ap->last_ctl) { 554 if (ioaddr->ctl_addr) 555 iowrite8(tf->ctl, ioaddr->ctl_addr); 556 ap->last_ctl = tf->ctl; 557 ata_wait_idle(ap); 558 } 559 560 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { 561 WARN_ON(!ioaddr->ctl_addr); 562 iowrite8(tf->hob_feature, ioaddr->feature_addr); 563 iowrite8(tf->hob_nsect, ioaddr->nsect_addr); 564 iowrite8(tf->hob_lbal, ioaddr->lbal_addr); 565 iowrite8(tf->hob_lbam, ioaddr->lbam_addr); 566 iowrite8(tf->hob_lbah, ioaddr->lbah_addr); 567 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", 568 tf->hob_feature, 569 tf->hob_nsect, 570 tf->hob_lbal, 571 tf->hob_lbam, 572 tf->hob_lbah); 573 } 574 575 if (is_addr) { 576 iowrite8(tf->feature, ioaddr->feature_addr); 577 iowrite8(tf->nsect, ioaddr->nsect_addr); 578 iowrite8(tf->lbal, ioaddr->lbal_addr); 579 iowrite8(tf->lbam, ioaddr->lbam_addr); 580 iowrite8(tf->lbah, ioaddr->lbah_addr); 581 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", 582 tf->feature, 583 tf->nsect, 584 tf->lbal, 585 tf->lbam, 586 tf->lbah); 587 } 588 589 if (tf->flags & ATA_TFLAG_DEVICE) { 590 iowrite8(tf->device, ioaddr->device_addr); 591 VPRINTK("device 0x%X\n", tf->device); 592 } 593 594 ata_wait_idle(ap); 595 } 596 597 /** 598 * ata_sff_tf_read - input device's ATA taskfile shadow registers 599 * @ap: Port from which input is read 600 * @tf: ATA taskfile register set for storing input 601 * 602 * Reads ATA taskfile registers for currently-selected device 603 * into @tf. Assumes the device has a fully SFF compliant task file 604 * layout and behaviour. If you device does not (eg has a different 605 * status method) then you will need to provide a replacement tf_read 606 * 607 * LOCKING: 608 * Inherited from caller. 609 */ 610 void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 611 { 612 struct ata_ioports *ioaddr = &ap->ioaddr; 613 614 tf->command = ata_sff_check_status(ap); 615 tf->feature = ioread8(ioaddr->error_addr); 616 tf->nsect = ioread8(ioaddr->nsect_addr); 617 tf->lbal = ioread8(ioaddr->lbal_addr); 618 tf->lbam = ioread8(ioaddr->lbam_addr); 619 tf->lbah = ioread8(ioaddr->lbah_addr); 620 tf->device = ioread8(ioaddr->device_addr); 621 622 if (tf->flags & ATA_TFLAG_LBA48) { 623 if (likely(ioaddr->ctl_addr)) { 624 iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr); 625 tf->hob_feature = ioread8(ioaddr->error_addr); 626 tf->hob_nsect = ioread8(ioaddr->nsect_addr); 627 tf->hob_lbal = ioread8(ioaddr->lbal_addr); 628 tf->hob_lbam = ioread8(ioaddr->lbam_addr); 629 tf->hob_lbah = ioread8(ioaddr->lbah_addr); 630 iowrite8(tf->ctl, ioaddr->ctl_addr); 631 ap->last_ctl = tf->ctl; 632 } else 633 WARN_ON(1); 634 } 635 } 636 637 /** 638 * ata_sff_exec_command - issue ATA command to host controller 639 * @ap: port to which command is being issued 640 * @tf: ATA taskfile register set 641 * 642 * Issues ATA command, with proper synchronization with interrupt 643 * handler / other threads. 644 * 645 * LOCKING: 646 * spin_lock_irqsave(host lock) 647 */ 648 void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf) 649 { 650 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); 651 652 iowrite8(tf->command, ap->ioaddr.command_addr); 653 ata_sff_pause(ap); 654 } 655 656 /** 657 * ata_tf_to_host - issue ATA taskfile to host controller 658 * @ap: port to which command is being issued 659 * @tf: ATA taskfile register set 660 * 661 * Issues ATA taskfile register set to ATA host controller, 662 * with proper synchronization with interrupt handler and 663 * other threads. 664 * 665 * LOCKING: 666 * spin_lock_irqsave(host lock) 667 */ 668 static inline void ata_tf_to_host(struct ata_port *ap, 669 const struct ata_taskfile *tf) 670 { 671 ap->ops->sff_tf_load(ap, tf); 672 ap->ops->sff_exec_command(ap, tf); 673 } 674 675 /** 676 * ata_sff_data_xfer - Transfer data by PIO 677 * @dev: device to target 678 * @buf: data buffer 679 * @buflen: buffer length 680 * @rw: read/write 681 * 682 * Transfer data from/to the device data register by PIO. 683 * 684 * LOCKING: 685 * Inherited from caller. 686 * 687 * RETURNS: 688 * Bytes consumed. 689 */ 690 unsigned int ata_sff_data_xfer(struct ata_device *dev, unsigned char *buf, 691 unsigned int buflen, int rw) 692 { 693 struct ata_port *ap = dev->link->ap; 694 void __iomem *data_addr = ap->ioaddr.data_addr; 695 unsigned int words = buflen >> 1; 696 697 /* Transfer multiple of 2 bytes */ 698 if (rw == READ) 699 ioread16_rep(data_addr, buf, words); 700 else 701 iowrite16_rep(data_addr, buf, words); 702 703 /* Transfer trailing 1 byte, if any. */ 704 if (unlikely(buflen & 0x01)) { 705 __le16 align_buf[1] = { 0 }; 706 unsigned char *trailing_buf = buf + buflen - 1; 707 708 if (rw == READ) { 709 align_buf[0] = cpu_to_le16(ioread16(data_addr)); 710 memcpy(trailing_buf, align_buf, 1); 711 } else { 712 memcpy(align_buf, trailing_buf, 1); 713 iowrite16(le16_to_cpu(align_buf[0]), data_addr); 714 } 715 words++; 716 } 717 718 return words << 1; 719 } 720 721 /** 722 * ata_sff_data_xfer_noirq - Transfer data by PIO 723 * @dev: device to target 724 * @buf: data buffer 725 * @buflen: buffer length 726 * @rw: read/write 727 * 728 * Transfer data from/to the device data register by PIO. Do the 729 * transfer with interrupts disabled. 730 * 731 * LOCKING: 732 * Inherited from caller. 733 * 734 * RETURNS: 735 * Bytes consumed. 736 */ 737 unsigned int ata_sff_data_xfer_noirq(struct ata_device *dev, unsigned char *buf, 738 unsigned int buflen, int rw) 739 { 740 unsigned long flags; 741 unsigned int consumed; 742 743 local_irq_save(flags); 744 consumed = ata_sff_data_xfer(dev, buf, buflen, rw); 745 local_irq_restore(flags); 746 747 return consumed; 748 } 749 750 /** 751 * ata_pio_sector - Transfer a sector of data. 752 * @qc: Command on going 753 * 754 * Transfer qc->sect_size bytes of data from/to the ATA device. 755 * 756 * LOCKING: 757 * Inherited from caller. 758 */ 759 static void ata_pio_sector(struct ata_queued_cmd *qc) 760 { 761 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE); 762 struct ata_port *ap = qc->ap; 763 struct page *page; 764 unsigned int offset; 765 unsigned char *buf; 766 767 if (qc->curbytes == qc->nbytes - qc->sect_size) 768 ap->hsm_task_state = HSM_ST_LAST; 769 770 page = sg_page(qc->cursg); 771 offset = qc->cursg->offset + qc->cursg_ofs; 772 773 /* get the current page and offset */ 774 page = nth_page(page, (offset >> PAGE_SHIFT)); 775 offset %= PAGE_SIZE; 776 777 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read"); 778 779 if (PageHighMem(page)) { 780 unsigned long flags; 781 782 /* FIXME: use a bounce buffer */ 783 local_irq_save(flags); 784 buf = kmap_atomic(page, KM_IRQ0); 785 786 /* do the actual data transfer */ 787 ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size, 788 do_write); 789 790 kunmap_atomic(buf, KM_IRQ0); 791 local_irq_restore(flags); 792 } else { 793 buf = page_address(page); 794 ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size, 795 do_write); 796 } 797 798 qc->curbytes += qc->sect_size; 799 qc->cursg_ofs += qc->sect_size; 800 801 if (qc->cursg_ofs == qc->cursg->length) { 802 qc->cursg = sg_next(qc->cursg); 803 qc->cursg_ofs = 0; 804 } 805 } 806 807 /** 808 * ata_pio_sectors - Transfer one or many sectors. 809 * @qc: Command on going 810 * 811 * Transfer one or many sectors of data from/to the 812 * ATA device for the DRQ request. 813 * 814 * LOCKING: 815 * Inherited from caller. 816 */ 817 static void ata_pio_sectors(struct ata_queued_cmd *qc) 818 { 819 if (is_multi_taskfile(&qc->tf)) { 820 /* READ/WRITE MULTIPLE */ 821 unsigned int nsect; 822 823 WARN_ON(qc->dev->multi_count == 0); 824 825 nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size, 826 qc->dev->multi_count); 827 while (nsect--) 828 ata_pio_sector(qc); 829 } else 830 ata_pio_sector(qc); 831 832 ata_sff_sync(qc->ap); /* flush */ 833 } 834 835 /** 836 * atapi_send_cdb - Write CDB bytes to hardware 837 * @ap: Port to which ATAPI device is attached. 838 * @qc: Taskfile currently active 839 * 840 * When device has indicated its readiness to accept 841 * a CDB, this function is called. Send the CDB. 842 * 843 * LOCKING: 844 * caller. 845 */ 846 static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc) 847 { 848 /* send SCSI cdb */ 849 DPRINTK("send cdb\n"); 850 WARN_ON(qc->dev->cdb_len < 12); 851 852 ap->ops->sff_data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1); 853 ata_sff_sync(ap); 854 /* FIXME: If the CDB is for DMA do we need to do the transition delay 855 or is bmdma_start guaranteed to do it ? */ 856 switch (qc->tf.protocol) { 857 case ATAPI_PROT_PIO: 858 ap->hsm_task_state = HSM_ST; 859 break; 860 case ATAPI_PROT_NODATA: 861 ap->hsm_task_state = HSM_ST_LAST; 862 break; 863 case ATAPI_PROT_DMA: 864 ap->hsm_task_state = HSM_ST_LAST; 865 /* initiate bmdma */ 866 ap->ops->bmdma_start(qc); 867 break; 868 } 869 } 870 871 /** 872 * __atapi_pio_bytes - Transfer data from/to the ATAPI device. 873 * @qc: Command on going 874 * @bytes: number of bytes 875 * 876 * Transfer Transfer data from/to the ATAPI device. 877 * 878 * LOCKING: 879 * Inherited from caller. 880 * 881 */ 882 static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes) 883 { 884 int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ; 885 struct ata_port *ap = qc->ap; 886 struct ata_device *dev = qc->dev; 887 struct ata_eh_info *ehi = &dev->link->eh_info; 888 struct scatterlist *sg; 889 struct page *page; 890 unsigned char *buf; 891 unsigned int offset, count, consumed; 892 893 next_sg: 894 sg = qc->cursg; 895 if (unlikely(!sg)) { 896 ata_ehi_push_desc(ehi, "unexpected or too much trailing data " 897 "buf=%u cur=%u bytes=%u", 898 qc->nbytes, qc->curbytes, bytes); 899 return -1; 900 } 901 902 page = sg_page(sg); 903 offset = sg->offset + qc->cursg_ofs; 904 905 /* get the current page and offset */ 906 page = nth_page(page, (offset >> PAGE_SHIFT)); 907 offset %= PAGE_SIZE; 908 909 /* don't overrun current sg */ 910 count = min(sg->length - qc->cursg_ofs, bytes); 911 912 /* don't cross page boundaries */ 913 count = min(count, (unsigned int)PAGE_SIZE - offset); 914 915 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read"); 916 917 if (PageHighMem(page)) { 918 unsigned long flags; 919 920 /* FIXME: use bounce buffer */ 921 local_irq_save(flags); 922 buf = kmap_atomic(page, KM_IRQ0); 923 924 /* do the actual data transfer */ 925 consumed = ap->ops->sff_data_xfer(dev, buf + offset, count, rw); 926 927 kunmap_atomic(buf, KM_IRQ0); 928 local_irq_restore(flags); 929 } else { 930 buf = page_address(page); 931 consumed = ap->ops->sff_data_xfer(dev, buf + offset, count, rw); 932 } 933 934 bytes -= min(bytes, consumed); 935 qc->curbytes += count; 936 qc->cursg_ofs += count; 937 938 if (qc->cursg_ofs == sg->length) { 939 qc->cursg = sg_next(qc->cursg); 940 qc->cursg_ofs = 0; 941 } 942 943 /* consumed can be larger than count only for the last transfer */ 944 WARN_ON(qc->cursg && count != consumed); 945 946 if (bytes) 947 goto next_sg; 948 return 0; 949 } 950 951 /** 952 * atapi_pio_bytes - Transfer data from/to the ATAPI device. 953 * @qc: Command on going 954 * 955 * Transfer Transfer data from/to the ATAPI device. 956 * 957 * LOCKING: 958 * Inherited from caller. 959 */ 960 static void atapi_pio_bytes(struct ata_queued_cmd *qc) 961 { 962 struct ata_port *ap = qc->ap; 963 struct ata_device *dev = qc->dev; 964 struct ata_eh_info *ehi = &dev->link->eh_info; 965 unsigned int ireason, bc_lo, bc_hi, bytes; 966 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0; 967 968 /* Abuse qc->result_tf for temp storage of intermediate TF 969 * here to save some kernel stack usage. 970 * For normal completion, qc->result_tf is not relevant. For 971 * error, qc->result_tf is later overwritten by ata_qc_complete(). 972 * So, the correctness of qc->result_tf is not affected. 973 */ 974 ap->ops->sff_tf_read(ap, &qc->result_tf); 975 ireason = qc->result_tf.nsect; 976 bc_lo = qc->result_tf.lbam; 977 bc_hi = qc->result_tf.lbah; 978 bytes = (bc_hi << 8) | bc_lo; 979 980 /* shall be cleared to zero, indicating xfer of data */ 981 if (unlikely(ireason & (1 << 0))) 982 goto atapi_check; 983 984 /* make sure transfer direction matches expected */ 985 i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0; 986 if (unlikely(do_write != i_write)) 987 goto atapi_check; 988 989 if (unlikely(!bytes)) 990 goto atapi_check; 991 992 VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes); 993 994 if (unlikely(__atapi_pio_bytes(qc, bytes))) 995 goto err_out; 996 ata_sff_sync(ap); /* flush */ 997 998 return; 999 1000 atapi_check: 1001 ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)", 1002 ireason, bytes); 1003 err_out: 1004 qc->err_mask |= AC_ERR_HSM; 1005 ap->hsm_task_state = HSM_ST_ERR; 1006 } 1007 1008 /** 1009 * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue. 1010 * @ap: the target ata_port 1011 * @qc: qc on going 1012 * 1013 * RETURNS: 1014 * 1 if ok in workqueue, 0 otherwise. 1015 */ 1016 static inline int ata_hsm_ok_in_wq(struct ata_port *ap, struct ata_queued_cmd *qc) 1017 { 1018 if (qc->tf.flags & ATA_TFLAG_POLLING) 1019 return 1; 1020 1021 if (ap->hsm_task_state == HSM_ST_FIRST) { 1022 if (qc->tf.protocol == ATA_PROT_PIO && 1023 (qc->tf.flags & ATA_TFLAG_WRITE)) 1024 return 1; 1025 1026 if (ata_is_atapi(qc->tf.protocol) && 1027 !(qc->dev->flags & ATA_DFLAG_CDB_INTR)) 1028 return 1; 1029 } 1030 1031 return 0; 1032 } 1033 1034 /** 1035 * ata_hsm_qc_complete - finish a qc running on standard HSM 1036 * @qc: Command to complete 1037 * @in_wq: 1 if called from workqueue, 0 otherwise 1038 * 1039 * Finish @qc which is running on standard HSM. 1040 * 1041 * LOCKING: 1042 * If @in_wq is zero, spin_lock_irqsave(host lock). 1043 * Otherwise, none on entry and grabs host lock. 1044 */ 1045 static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq) 1046 { 1047 struct ata_port *ap = qc->ap; 1048 unsigned long flags; 1049 1050 if (ap->ops->error_handler) { 1051 if (in_wq) { 1052 spin_lock_irqsave(ap->lock, flags); 1053 1054 /* EH might have kicked in while host lock is 1055 * released. 1056 */ 1057 qc = ata_qc_from_tag(ap, qc->tag); 1058 if (qc) { 1059 if (likely(!(qc->err_mask & AC_ERR_HSM))) { 1060 ap->ops->sff_irq_on(ap); 1061 ata_qc_complete(qc); 1062 } else 1063 ata_port_freeze(ap); 1064 } 1065 1066 spin_unlock_irqrestore(ap->lock, flags); 1067 } else { 1068 if (likely(!(qc->err_mask & AC_ERR_HSM))) 1069 ata_qc_complete(qc); 1070 else 1071 ata_port_freeze(ap); 1072 } 1073 } else { 1074 if (in_wq) { 1075 spin_lock_irqsave(ap->lock, flags); 1076 ap->ops->sff_irq_on(ap); 1077 ata_qc_complete(qc); 1078 spin_unlock_irqrestore(ap->lock, flags); 1079 } else 1080 ata_qc_complete(qc); 1081 } 1082 } 1083 1084 /** 1085 * ata_sff_hsm_move - move the HSM to the next state. 1086 * @ap: the target ata_port 1087 * @qc: qc on going 1088 * @status: current device status 1089 * @in_wq: 1 if called from workqueue, 0 otherwise 1090 * 1091 * RETURNS: 1092 * 1 when poll next status needed, 0 otherwise. 1093 */ 1094 int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc, 1095 u8 status, int in_wq) 1096 { 1097 struct ata_eh_info *ehi = &ap->link.eh_info; 1098 unsigned long flags = 0; 1099 int poll_next; 1100 1101 WARN_ON((qc->flags & ATA_QCFLAG_ACTIVE) == 0); 1102 1103 /* Make sure ata_sff_qc_issue() does not throw things 1104 * like DMA polling into the workqueue. Notice that 1105 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING). 1106 */ 1107 WARN_ON(in_wq != ata_hsm_ok_in_wq(ap, qc)); 1108 1109 fsm_start: 1110 DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n", 1111 ap->print_id, qc->tf.protocol, ap->hsm_task_state, status); 1112 1113 switch (ap->hsm_task_state) { 1114 case HSM_ST_FIRST: 1115 /* Send first data block or PACKET CDB */ 1116 1117 /* If polling, we will stay in the work queue after 1118 * sending the data. Otherwise, interrupt handler 1119 * takes over after sending the data. 1120 */ 1121 poll_next = (qc->tf.flags & ATA_TFLAG_POLLING); 1122 1123 /* check device status */ 1124 if (unlikely((status & ATA_DRQ) == 0)) { 1125 /* handle BSY=0, DRQ=0 as error */ 1126 if (likely(status & (ATA_ERR | ATA_DF))) 1127 /* device stops HSM for abort/error */ 1128 qc->err_mask |= AC_ERR_DEV; 1129 else { 1130 /* HSM violation. Let EH handle this */ 1131 ata_ehi_push_desc(ehi, 1132 "ST_FIRST: !(DRQ|ERR|DF)"); 1133 qc->err_mask |= AC_ERR_HSM; 1134 } 1135 1136 ap->hsm_task_state = HSM_ST_ERR; 1137 goto fsm_start; 1138 } 1139 1140 /* Device should not ask for data transfer (DRQ=1) 1141 * when it finds something wrong. 1142 * We ignore DRQ here and stop the HSM by 1143 * changing hsm_task_state to HSM_ST_ERR and 1144 * let the EH abort the command or reset the device. 1145 */ 1146 if (unlikely(status & (ATA_ERR | ATA_DF))) { 1147 /* Some ATAPI tape drives forget to clear the ERR bit 1148 * when doing the next command (mostly request sense). 1149 * We ignore ERR here to workaround and proceed sending 1150 * the CDB. 1151 */ 1152 if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) { 1153 ata_ehi_push_desc(ehi, "ST_FIRST: " 1154 "DRQ=1 with device error, " 1155 "dev_stat 0x%X", status); 1156 qc->err_mask |= AC_ERR_HSM; 1157 ap->hsm_task_state = HSM_ST_ERR; 1158 goto fsm_start; 1159 } 1160 } 1161 1162 /* Send the CDB (atapi) or the first data block (ata pio out). 1163 * During the state transition, interrupt handler shouldn't 1164 * be invoked before the data transfer is complete and 1165 * hsm_task_state is changed. Hence, the following locking. 1166 */ 1167 if (in_wq) 1168 spin_lock_irqsave(ap->lock, flags); 1169 1170 if (qc->tf.protocol == ATA_PROT_PIO) { 1171 /* PIO data out protocol. 1172 * send first data block. 1173 */ 1174 1175 /* ata_pio_sectors() might change the state 1176 * to HSM_ST_LAST. so, the state is changed here 1177 * before ata_pio_sectors(). 1178 */ 1179 ap->hsm_task_state = HSM_ST; 1180 ata_pio_sectors(qc); 1181 } else 1182 /* send CDB */ 1183 atapi_send_cdb(ap, qc); 1184 1185 if (in_wq) 1186 spin_unlock_irqrestore(ap->lock, flags); 1187 1188 /* if polling, ata_pio_task() handles the rest. 1189 * otherwise, interrupt handler takes over from here. 1190 */ 1191 break; 1192 1193 case HSM_ST: 1194 /* complete command or read/write the data register */ 1195 if (qc->tf.protocol == ATAPI_PROT_PIO) { 1196 /* ATAPI PIO protocol */ 1197 if ((status & ATA_DRQ) == 0) { 1198 /* No more data to transfer or device error. 1199 * Device error will be tagged in HSM_ST_LAST. 1200 */ 1201 ap->hsm_task_state = HSM_ST_LAST; 1202 goto fsm_start; 1203 } 1204 1205 /* Device should not ask for data transfer (DRQ=1) 1206 * when it finds something wrong. 1207 * We ignore DRQ here and stop the HSM by 1208 * changing hsm_task_state to HSM_ST_ERR and 1209 * let the EH abort the command or reset the device. 1210 */ 1211 if (unlikely(status & (ATA_ERR | ATA_DF))) { 1212 ata_ehi_push_desc(ehi, "ST-ATAPI: " 1213 "DRQ=1 with device error, " 1214 "dev_stat 0x%X", status); 1215 qc->err_mask |= AC_ERR_HSM; 1216 ap->hsm_task_state = HSM_ST_ERR; 1217 goto fsm_start; 1218 } 1219 1220 atapi_pio_bytes(qc); 1221 1222 if (unlikely(ap->hsm_task_state == HSM_ST_ERR)) 1223 /* bad ireason reported by device */ 1224 goto fsm_start; 1225 1226 } else { 1227 /* ATA PIO protocol */ 1228 if (unlikely((status & ATA_DRQ) == 0)) { 1229 /* handle BSY=0, DRQ=0 as error */ 1230 if (likely(status & (ATA_ERR | ATA_DF))) 1231 /* device stops HSM for abort/error */ 1232 qc->err_mask |= AC_ERR_DEV; 1233 else { 1234 /* HSM violation. Let EH handle this. 1235 * Phantom devices also trigger this 1236 * condition. Mark hint. 1237 */ 1238 ata_ehi_push_desc(ehi, "ST-ATA: " 1239 "DRQ=1 with device error, " 1240 "dev_stat 0x%X", status); 1241 qc->err_mask |= AC_ERR_HSM | 1242 AC_ERR_NODEV_HINT; 1243 } 1244 1245 ap->hsm_task_state = HSM_ST_ERR; 1246 goto fsm_start; 1247 } 1248 1249 /* For PIO reads, some devices may ask for 1250 * data transfer (DRQ=1) alone with ERR=1. 1251 * We respect DRQ here and transfer one 1252 * block of junk data before changing the 1253 * hsm_task_state to HSM_ST_ERR. 1254 * 1255 * For PIO writes, ERR=1 DRQ=1 doesn't make 1256 * sense since the data block has been 1257 * transferred to the device. 1258 */ 1259 if (unlikely(status & (ATA_ERR | ATA_DF))) { 1260 /* data might be corrputed */ 1261 qc->err_mask |= AC_ERR_DEV; 1262 1263 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) { 1264 ata_pio_sectors(qc); 1265 status = ata_wait_idle(ap); 1266 } 1267 1268 if (status & (ATA_BUSY | ATA_DRQ)) { 1269 ata_ehi_push_desc(ehi, "ST-ATA: " 1270 "BUSY|DRQ persists on ERR|DF, " 1271 "dev_stat 0x%X", status); 1272 qc->err_mask |= AC_ERR_HSM; 1273 } 1274 1275 /* ata_pio_sectors() might change the 1276 * state to HSM_ST_LAST. so, the state 1277 * is changed after ata_pio_sectors(). 1278 */ 1279 ap->hsm_task_state = HSM_ST_ERR; 1280 goto fsm_start; 1281 } 1282 1283 ata_pio_sectors(qc); 1284 1285 if (ap->hsm_task_state == HSM_ST_LAST && 1286 (!(qc->tf.flags & ATA_TFLAG_WRITE))) { 1287 /* all data read */ 1288 status = ata_wait_idle(ap); 1289 goto fsm_start; 1290 } 1291 } 1292 1293 poll_next = 1; 1294 break; 1295 1296 case HSM_ST_LAST: 1297 if (unlikely(!ata_ok(status))) { 1298 qc->err_mask |= __ac_err_mask(status); 1299 ap->hsm_task_state = HSM_ST_ERR; 1300 goto fsm_start; 1301 } 1302 1303 /* no more data to transfer */ 1304 DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n", 1305 ap->print_id, qc->dev->devno, status); 1306 1307 WARN_ON(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM)); 1308 1309 ap->hsm_task_state = HSM_ST_IDLE; 1310 1311 /* complete taskfile transaction */ 1312 ata_hsm_qc_complete(qc, in_wq); 1313 1314 poll_next = 0; 1315 break; 1316 1317 case HSM_ST_ERR: 1318 ap->hsm_task_state = HSM_ST_IDLE; 1319 1320 /* complete taskfile transaction */ 1321 ata_hsm_qc_complete(qc, in_wq); 1322 1323 poll_next = 0; 1324 break; 1325 default: 1326 poll_next = 0; 1327 BUG(); 1328 } 1329 1330 return poll_next; 1331 } 1332 1333 void ata_pio_task(struct work_struct *work) 1334 { 1335 struct ata_port *ap = 1336 container_of(work, struct ata_port, port_task.work); 1337 struct ata_queued_cmd *qc = ap->port_task_data; 1338 u8 status; 1339 int poll_next; 1340 1341 fsm_start: 1342 WARN_ON(ap->hsm_task_state == HSM_ST_IDLE); 1343 1344 /* 1345 * This is purely heuristic. This is a fast path. 1346 * Sometimes when we enter, BSY will be cleared in 1347 * a chk-status or two. If not, the drive is probably seeking 1348 * or something. Snooze for a couple msecs, then 1349 * chk-status again. If still busy, queue delayed work. 1350 */ 1351 status = ata_sff_busy_wait(ap, ATA_BUSY, 5); 1352 if (status & ATA_BUSY) { 1353 msleep(2); 1354 status = ata_sff_busy_wait(ap, ATA_BUSY, 10); 1355 if (status & ATA_BUSY) { 1356 ata_pio_queue_task(ap, qc, ATA_SHORT_PAUSE); 1357 return; 1358 } 1359 } 1360 1361 /* move the HSM */ 1362 poll_next = ata_sff_hsm_move(ap, qc, status, 1); 1363 1364 /* another command or interrupt handler 1365 * may be running at this point. 1366 */ 1367 if (poll_next) 1368 goto fsm_start; 1369 } 1370 1371 /** 1372 * ata_sff_qc_issue - issue taskfile to device in proto-dependent manner 1373 * @qc: command to issue to device 1374 * 1375 * Using various libata functions and hooks, this function 1376 * starts an ATA command. ATA commands are grouped into 1377 * classes called "protocols", and issuing each type of protocol 1378 * is slightly different. 1379 * 1380 * May be used as the qc_issue() entry in ata_port_operations. 1381 * 1382 * LOCKING: 1383 * spin_lock_irqsave(host lock) 1384 * 1385 * RETURNS: 1386 * Zero on success, AC_ERR_* mask on failure 1387 */ 1388 unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc) 1389 { 1390 struct ata_port *ap = qc->ap; 1391 1392 /* Use polling pio if the LLD doesn't handle 1393 * interrupt driven pio and atapi CDB interrupt. 1394 */ 1395 if (ap->flags & ATA_FLAG_PIO_POLLING) { 1396 switch (qc->tf.protocol) { 1397 case ATA_PROT_PIO: 1398 case ATA_PROT_NODATA: 1399 case ATAPI_PROT_PIO: 1400 case ATAPI_PROT_NODATA: 1401 qc->tf.flags |= ATA_TFLAG_POLLING; 1402 break; 1403 case ATAPI_PROT_DMA: 1404 if (qc->dev->flags & ATA_DFLAG_CDB_INTR) 1405 /* see ata_dma_blacklisted() */ 1406 BUG(); 1407 break; 1408 default: 1409 break; 1410 } 1411 } 1412 1413 /* select the device */ 1414 ata_dev_select(ap, qc->dev->devno, 1, 0); 1415 1416 /* start the command */ 1417 switch (qc->tf.protocol) { 1418 case ATA_PROT_NODATA: 1419 if (qc->tf.flags & ATA_TFLAG_POLLING) 1420 ata_qc_set_polling(qc); 1421 1422 ata_tf_to_host(ap, &qc->tf); 1423 ap->hsm_task_state = HSM_ST_LAST; 1424 1425 if (qc->tf.flags & ATA_TFLAG_POLLING) 1426 ata_pio_queue_task(ap, qc, 0); 1427 1428 break; 1429 1430 case ATA_PROT_DMA: 1431 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING); 1432 1433 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ 1434 ap->ops->bmdma_setup(qc); /* set up bmdma */ 1435 ap->ops->bmdma_start(qc); /* initiate bmdma */ 1436 ap->hsm_task_state = HSM_ST_LAST; 1437 break; 1438 1439 case ATA_PROT_PIO: 1440 if (qc->tf.flags & ATA_TFLAG_POLLING) 1441 ata_qc_set_polling(qc); 1442 1443 ata_tf_to_host(ap, &qc->tf); 1444 1445 if (qc->tf.flags & ATA_TFLAG_WRITE) { 1446 /* PIO data out protocol */ 1447 ap->hsm_task_state = HSM_ST_FIRST; 1448 ata_pio_queue_task(ap, qc, 0); 1449 1450 /* always send first data block using 1451 * the ata_pio_task() codepath. 1452 */ 1453 } else { 1454 /* PIO data in protocol */ 1455 ap->hsm_task_state = HSM_ST; 1456 1457 if (qc->tf.flags & ATA_TFLAG_POLLING) 1458 ata_pio_queue_task(ap, qc, 0); 1459 1460 /* if polling, ata_pio_task() handles the rest. 1461 * otherwise, interrupt handler takes over from here. 1462 */ 1463 } 1464 1465 break; 1466 1467 case ATAPI_PROT_PIO: 1468 case ATAPI_PROT_NODATA: 1469 if (qc->tf.flags & ATA_TFLAG_POLLING) 1470 ata_qc_set_polling(qc); 1471 1472 ata_tf_to_host(ap, &qc->tf); 1473 1474 ap->hsm_task_state = HSM_ST_FIRST; 1475 1476 /* send cdb by polling if no cdb interrupt */ 1477 if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) || 1478 (qc->tf.flags & ATA_TFLAG_POLLING)) 1479 ata_pio_queue_task(ap, qc, 0); 1480 break; 1481 1482 case ATAPI_PROT_DMA: 1483 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING); 1484 1485 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ 1486 ap->ops->bmdma_setup(qc); /* set up bmdma */ 1487 ap->hsm_task_state = HSM_ST_FIRST; 1488 1489 /* send cdb by polling if no cdb interrupt */ 1490 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) 1491 ata_pio_queue_task(ap, qc, 0); 1492 break; 1493 1494 default: 1495 WARN_ON(1); 1496 return AC_ERR_SYSTEM; 1497 } 1498 1499 return 0; 1500 } 1501 1502 /** 1503 * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read 1504 * @qc: qc to fill result TF for 1505 * 1506 * @qc is finished and result TF needs to be filled. Fill it 1507 * using ->sff_tf_read. 1508 * 1509 * LOCKING: 1510 * spin_lock_irqsave(host lock) 1511 * 1512 * RETURNS: 1513 * true indicating that result TF is successfully filled. 1514 */ 1515 bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc) 1516 { 1517 qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf); 1518 return true; 1519 } 1520 1521 /** 1522 * ata_sff_host_intr - Handle host interrupt for given (port, task) 1523 * @ap: Port on which interrupt arrived (possibly...) 1524 * @qc: Taskfile currently active in engine 1525 * 1526 * Handle host interrupt for given queued command. Currently, 1527 * only DMA interrupts are handled. All other commands are 1528 * handled via polling with interrupts disabled (nIEN bit). 1529 * 1530 * LOCKING: 1531 * spin_lock_irqsave(host lock) 1532 * 1533 * RETURNS: 1534 * One if interrupt was handled, zero if not (shared irq). 1535 */ 1536 inline unsigned int ata_sff_host_intr(struct ata_port *ap, 1537 struct ata_queued_cmd *qc) 1538 { 1539 struct ata_eh_info *ehi = &ap->link.eh_info; 1540 u8 status, host_stat = 0; 1541 1542 VPRINTK("ata%u: protocol %d task_state %d\n", 1543 ap->print_id, qc->tf.protocol, ap->hsm_task_state); 1544 1545 /* Check whether we are expecting interrupt in this state */ 1546 switch (ap->hsm_task_state) { 1547 case HSM_ST_FIRST: 1548 /* Some pre-ATAPI-4 devices assert INTRQ 1549 * at this state when ready to receive CDB. 1550 */ 1551 1552 /* Check the ATA_DFLAG_CDB_INTR flag is enough here. 1553 * The flag was turned on only for atapi devices. No 1554 * need to check ata_is_atapi(qc->tf.protocol) again. 1555 */ 1556 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) 1557 goto idle_irq; 1558 break; 1559 case HSM_ST_LAST: 1560 if (qc->tf.protocol == ATA_PROT_DMA || 1561 qc->tf.protocol == ATAPI_PROT_DMA) { 1562 /* check status of DMA engine */ 1563 host_stat = ap->ops->bmdma_status(ap); 1564 VPRINTK("ata%u: host_stat 0x%X\n", 1565 ap->print_id, host_stat); 1566 1567 /* if it's not our irq... */ 1568 if (!(host_stat & ATA_DMA_INTR)) 1569 goto idle_irq; 1570 1571 /* before we do anything else, clear DMA-Start bit */ 1572 ap->ops->bmdma_stop(qc); 1573 1574 if (unlikely(host_stat & ATA_DMA_ERR)) { 1575 /* error when transfering data to/from memory */ 1576 qc->err_mask |= AC_ERR_HOST_BUS; 1577 ap->hsm_task_state = HSM_ST_ERR; 1578 } 1579 } 1580 break; 1581 case HSM_ST: 1582 break; 1583 default: 1584 goto idle_irq; 1585 } 1586 1587 1588 /* check main status, clearing INTRQ if needed */ 1589 status = ata_sff_irq_status(ap); 1590 if (status & ATA_BUSY) 1591 goto idle_irq; 1592 1593 /* ack bmdma irq events */ 1594 ap->ops->sff_irq_clear(ap); 1595 1596 ata_sff_hsm_move(ap, qc, status, 0); 1597 1598 if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA || 1599 qc->tf.protocol == ATAPI_PROT_DMA)) 1600 ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat); 1601 1602 return 1; /* irq handled */ 1603 1604 idle_irq: 1605 ap->stats.idle_irq++; 1606 1607 #ifdef ATA_IRQ_TRAP 1608 if ((ap->stats.idle_irq % 1000) == 0) { 1609 ap->ops->sff_check_status(ap); 1610 ap->ops->sff_irq_clear(ap); 1611 ata_port_printk(ap, KERN_WARNING, "irq trap\n"); 1612 return 1; 1613 } 1614 #endif 1615 return 0; /* irq not handled */ 1616 } 1617 1618 /** 1619 * ata_sff_interrupt - Default ATA host interrupt handler 1620 * @irq: irq line (unused) 1621 * @dev_instance: pointer to our ata_host information structure 1622 * 1623 * Default interrupt handler for PCI IDE devices. Calls 1624 * ata_sff_host_intr() for each port that is not disabled. 1625 * 1626 * LOCKING: 1627 * Obtains host lock during operation. 1628 * 1629 * RETURNS: 1630 * IRQ_NONE or IRQ_HANDLED. 1631 */ 1632 irqreturn_t ata_sff_interrupt(int irq, void *dev_instance) 1633 { 1634 struct ata_host *host = dev_instance; 1635 unsigned int i; 1636 unsigned int handled = 0; 1637 unsigned long flags; 1638 1639 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */ 1640 spin_lock_irqsave(&host->lock, flags); 1641 1642 for (i = 0; i < host->n_ports; i++) { 1643 struct ata_port *ap; 1644 1645 ap = host->ports[i]; 1646 if (ap && 1647 !(ap->flags & ATA_FLAG_DISABLED)) { 1648 struct ata_queued_cmd *qc; 1649 1650 qc = ata_qc_from_tag(ap, ap->link.active_tag); 1651 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) && 1652 (qc->flags & ATA_QCFLAG_ACTIVE)) 1653 handled |= ata_sff_host_intr(ap, qc); 1654 } 1655 } 1656 1657 spin_unlock_irqrestore(&host->lock, flags); 1658 1659 return IRQ_RETVAL(handled); 1660 } 1661 1662 /** 1663 * ata_sff_freeze - Freeze SFF controller port 1664 * @ap: port to freeze 1665 * 1666 * Freeze BMDMA controller port. 1667 * 1668 * LOCKING: 1669 * Inherited from caller. 1670 */ 1671 void ata_sff_freeze(struct ata_port *ap) 1672 { 1673 struct ata_ioports *ioaddr = &ap->ioaddr; 1674 1675 ap->ctl |= ATA_NIEN; 1676 ap->last_ctl = ap->ctl; 1677 1678 if (ioaddr->ctl_addr) 1679 iowrite8(ap->ctl, ioaddr->ctl_addr); 1680 1681 /* Under certain circumstances, some controllers raise IRQ on 1682 * ATA_NIEN manipulation. Also, many controllers fail to mask 1683 * previously pending IRQ on ATA_NIEN assertion. Clear it. 1684 */ 1685 ap->ops->sff_check_status(ap); 1686 1687 ap->ops->sff_irq_clear(ap); 1688 } 1689 1690 /** 1691 * ata_sff_thaw - Thaw SFF controller port 1692 * @ap: port to thaw 1693 * 1694 * Thaw SFF controller port. 1695 * 1696 * LOCKING: 1697 * Inherited from caller. 1698 */ 1699 void ata_sff_thaw(struct ata_port *ap) 1700 { 1701 /* clear & re-enable interrupts */ 1702 ap->ops->sff_check_status(ap); 1703 ap->ops->sff_irq_clear(ap); 1704 ap->ops->sff_irq_on(ap); 1705 } 1706 1707 /** 1708 * ata_sff_prereset - prepare SFF link for reset 1709 * @link: SFF link to be reset 1710 * @deadline: deadline jiffies for the operation 1711 * 1712 * SFF link @link is about to be reset. Initialize it. It first 1713 * calls ata_std_prereset() and wait for !BSY if the port is 1714 * being softreset. 1715 * 1716 * LOCKING: 1717 * Kernel thread context (may sleep) 1718 * 1719 * RETURNS: 1720 * 0 on success, -errno otherwise. 1721 */ 1722 int ata_sff_prereset(struct ata_link *link, unsigned long deadline) 1723 { 1724 struct ata_eh_context *ehc = &link->eh_context; 1725 int rc; 1726 1727 rc = ata_std_prereset(link, deadline); 1728 if (rc) 1729 return rc; 1730 1731 /* if we're about to do hardreset, nothing more to do */ 1732 if (ehc->i.action & ATA_EH_HARDRESET) 1733 return 0; 1734 1735 /* wait for !BSY if we don't know that no device is attached */ 1736 if (!ata_link_offline(link)) { 1737 rc = ata_sff_wait_ready(link, deadline); 1738 if (rc && rc != -ENODEV) { 1739 ata_link_printk(link, KERN_WARNING, "device not ready " 1740 "(errno=%d), forcing hardreset\n", rc); 1741 ehc->i.action |= ATA_EH_HARDRESET; 1742 } 1743 } 1744 1745 return 0; 1746 } 1747 1748 /** 1749 * ata_devchk - PATA device presence detection 1750 * @ap: ATA channel to examine 1751 * @device: Device to examine (starting at zero) 1752 * 1753 * This technique was originally described in 1754 * Hale Landis's ATADRVR (www.ata-atapi.com), and 1755 * later found its way into the ATA/ATAPI spec. 1756 * 1757 * Write a pattern to the ATA shadow registers, 1758 * and if a device is present, it will respond by 1759 * correctly storing and echoing back the 1760 * ATA shadow register contents. 1761 * 1762 * LOCKING: 1763 * caller. 1764 */ 1765 static unsigned int ata_devchk(struct ata_port *ap, unsigned int device) 1766 { 1767 struct ata_ioports *ioaddr = &ap->ioaddr; 1768 u8 nsect, lbal; 1769 1770 ap->ops->sff_dev_select(ap, device); 1771 1772 iowrite8(0x55, ioaddr->nsect_addr); 1773 iowrite8(0xaa, ioaddr->lbal_addr); 1774 1775 iowrite8(0xaa, ioaddr->nsect_addr); 1776 iowrite8(0x55, ioaddr->lbal_addr); 1777 1778 iowrite8(0x55, ioaddr->nsect_addr); 1779 iowrite8(0xaa, ioaddr->lbal_addr); 1780 1781 nsect = ioread8(ioaddr->nsect_addr); 1782 lbal = ioread8(ioaddr->lbal_addr); 1783 1784 if ((nsect == 0x55) && (lbal == 0xaa)) 1785 return 1; /* we found a device */ 1786 1787 return 0; /* nothing found */ 1788 } 1789 1790 /** 1791 * ata_sff_dev_classify - Parse returned ATA device signature 1792 * @dev: ATA device to classify (starting at zero) 1793 * @present: device seems present 1794 * @r_err: Value of error register on completion 1795 * 1796 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs, 1797 * an ATA/ATAPI-defined set of values is placed in the ATA 1798 * shadow registers, indicating the results of device detection 1799 * and diagnostics. 1800 * 1801 * Select the ATA device, and read the values from the ATA shadow 1802 * registers. Then parse according to the Error register value, 1803 * and the spec-defined values examined by ata_dev_classify(). 1804 * 1805 * LOCKING: 1806 * caller. 1807 * 1808 * RETURNS: 1809 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE. 1810 */ 1811 unsigned int ata_sff_dev_classify(struct ata_device *dev, int present, 1812 u8 *r_err) 1813 { 1814 struct ata_port *ap = dev->link->ap; 1815 struct ata_taskfile tf; 1816 unsigned int class; 1817 u8 err; 1818 1819 ap->ops->sff_dev_select(ap, dev->devno); 1820 1821 memset(&tf, 0, sizeof(tf)); 1822 1823 ap->ops->sff_tf_read(ap, &tf); 1824 err = tf.feature; 1825 if (r_err) 1826 *r_err = err; 1827 1828 /* see if device passed diags: continue and warn later */ 1829 if (err == 0) 1830 /* diagnostic fail : do nothing _YET_ */ 1831 dev->horkage |= ATA_HORKAGE_DIAGNOSTIC; 1832 else if (err == 1) 1833 /* do nothing */ ; 1834 else if ((dev->devno == 0) && (err == 0x81)) 1835 /* do nothing */ ; 1836 else 1837 return ATA_DEV_NONE; 1838 1839 /* determine if device is ATA or ATAPI */ 1840 class = ata_dev_classify(&tf); 1841 1842 if (class == ATA_DEV_UNKNOWN) { 1843 /* If the device failed diagnostic, it's likely to 1844 * have reported incorrect device signature too. 1845 * Assume ATA device if the device seems present but 1846 * device signature is invalid with diagnostic 1847 * failure. 1848 */ 1849 if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC)) 1850 class = ATA_DEV_ATA; 1851 else 1852 class = ATA_DEV_NONE; 1853 } else if ((class == ATA_DEV_ATA) && 1854 (ap->ops->sff_check_status(ap) == 0)) 1855 class = ATA_DEV_NONE; 1856 1857 return class; 1858 } 1859 1860 /** 1861 * ata_sff_wait_after_reset - wait for devices to become ready after reset 1862 * @link: SFF link which is just reset 1863 * @devmask: mask of present devices 1864 * @deadline: deadline jiffies for the operation 1865 * 1866 * Wait devices attached to SFF @link to become ready after 1867 * reset. It contains preceding 150ms wait to avoid accessing TF 1868 * status register too early. 1869 * 1870 * LOCKING: 1871 * Kernel thread context (may sleep). 1872 * 1873 * RETURNS: 1874 * 0 on success, -ENODEV if some or all of devices in @devmask 1875 * don't seem to exist. -errno on other errors. 1876 */ 1877 int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask, 1878 unsigned long deadline) 1879 { 1880 struct ata_port *ap = link->ap; 1881 struct ata_ioports *ioaddr = &ap->ioaddr; 1882 unsigned int dev0 = devmask & (1 << 0); 1883 unsigned int dev1 = devmask & (1 << 1); 1884 int rc, ret = 0; 1885 1886 msleep(ATA_WAIT_AFTER_RESET); 1887 1888 /* always check readiness of the master device */ 1889 rc = ata_sff_wait_ready(link, deadline); 1890 /* -ENODEV means the odd clown forgot the D7 pulldown resistor 1891 * and TF status is 0xff, bail out on it too. 1892 */ 1893 if (rc) 1894 return rc; 1895 1896 /* if device 1 was found in ata_devchk, wait for register 1897 * access briefly, then wait for BSY to clear. 1898 */ 1899 if (dev1) { 1900 int i; 1901 1902 ap->ops->sff_dev_select(ap, 1); 1903 1904 /* Wait for register access. Some ATAPI devices fail 1905 * to set nsect/lbal after reset, so don't waste too 1906 * much time on it. We're gonna wait for !BSY anyway. 1907 */ 1908 for (i = 0; i < 2; i++) { 1909 u8 nsect, lbal; 1910 1911 nsect = ioread8(ioaddr->nsect_addr); 1912 lbal = ioread8(ioaddr->lbal_addr); 1913 if ((nsect == 1) && (lbal == 1)) 1914 break; 1915 msleep(50); /* give drive a breather */ 1916 } 1917 1918 rc = ata_sff_wait_ready(link, deadline); 1919 if (rc) { 1920 if (rc != -ENODEV) 1921 return rc; 1922 ret = rc; 1923 } 1924 } 1925 1926 /* is all this really necessary? */ 1927 ap->ops->sff_dev_select(ap, 0); 1928 if (dev1) 1929 ap->ops->sff_dev_select(ap, 1); 1930 if (dev0) 1931 ap->ops->sff_dev_select(ap, 0); 1932 1933 return ret; 1934 } 1935 1936 static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask, 1937 unsigned long deadline) 1938 { 1939 struct ata_ioports *ioaddr = &ap->ioaddr; 1940 1941 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id); 1942 1943 /* software reset. causes dev0 to be selected */ 1944 iowrite8(ap->ctl, ioaddr->ctl_addr); 1945 udelay(20); /* FIXME: flush */ 1946 iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr); 1947 udelay(20); /* FIXME: flush */ 1948 iowrite8(ap->ctl, ioaddr->ctl_addr); 1949 1950 /* wait the port to become ready */ 1951 return ata_sff_wait_after_reset(&ap->link, devmask, deadline); 1952 } 1953 1954 /** 1955 * ata_sff_softreset - reset host port via ATA SRST 1956 * @link: ATA link to reset 1957 * @classes: resulting classes of attached devices 1958 * @deadline: deadline jiffies for the operation 1959 * 1960 * Reset host port using ATA SRST. 1961 * 1962 * LOCKING: 1963 * Kernel thread context (may sleep) 1964 * 1965 * RETURNS: 1966 * 0 on success, -errno otherwise. 1967 */ 1968 int ata_sff_softreset(struct ata_link *link, unsigned int *classes, 1969 unsigned long deadline) 1970 { 1971 struct ata_port *ap = link->ap; 1972 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS; 1973 unsigned int devmask = 0; 1974 int rc; 1975 u8 err; 1976 1977 DPRINTK("ENTER\n"); 1978 1979 /* determine if device 0/1 are present */ 1980 if (ata_devchk(ap, 0)) 1981 devmask |= (1 << 0); 1982 if (slave_possible && ata_devchk(ap, 1)) 1983 devmask |= (1 << 1); 1984 1985 /* select device 0 again */ 1986 ap->ops->sff_dev_select(ap, 0); 1987 1988 /* issue bus reset */ 1989 DPRINTK("about to softreset, devmask=%x\n", devmask); 1990 rc = ata_bus_softreset(ap, devmask, deadline); 1991 /* if link is occupied, -ENODEV too is an error */ 1992 if (rc && (rc != -ENODEV || sata_scr_valid(link))) { 1993 ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc); 1994 return rc; 1995 } 1996 1997 /* determine by signature whether we have ATA or ATAPI devices */ 1998 classes[0] = ata_sff_dev_classify(&link->device[0], 1999 devmask & (1 << 0), &err); 2000 if (slave_possible && err != 0x81) 2001 classes[1] = ata_sff_dev_classify(&link->device[1], 2002 devmask & (1 << 1), &err); 2003 2004 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]); 2005 return 0; 2006 } 2007 2008 /** 2009 * sata_sff_hardreset - reset host port via SATA phy reset 2010 * @link: link to reset 2011 * @class: resulting class of attached device 2012 * @deadline: deadline jiffies for the operation 2013 * 2014 * SATA phy-reset host port using DET bits of SControl register, 2015 * wait for !BSY and classify the attached device. 2016 * 2017 * LOCKING: 2018 * Kernel thread context (may sleep) 2019 * 2020 * RETURNS: 2021 * 0 on success, -errno otherwise. 2022 */ 2023 int sata_sff_hardreset(struct ata_link *link, unsigned int *class, 2024 unsigned long deadline) 2025 { 2026 struct ata_eh_context *ehc = &link->eh_context; 2027 const unsigned long *timing = sata_ehc_deb_timing(ehc); 2028 bool online; 2029 int rc; 2030 2031 rc = sata_link_hardreset(link, timing, deadline, &online, 2032 ata_sff_check_ready); 2033 if (online) 2034 *class = ata_sff_dev_classify(link->device, 1, NULL); 2035 2036 DPRINTK("EXIT, class=%u\n", *class); 2037 return rc; 2038 } 2039 2040 /** 2041 * ata_sff_postreset - SFF postreset callback 2042 * @link: the target SFF ata_link 2043 * @classes: classes of attached devices 2044 * 2045 * This function is invoked after a successful reset. It first 2046 * calls ata_std_postreset() and performs SFF specific postreset 2047 * processing. 2048 * 2049 * LOCKING: 2050 * Kernel thread context (may sleep) 2051 */ 2052 void ata_sff_postreset(struct ata_link *link, unsigned int *classes) 2053 { 2054 struct ata_port *ap = link->ap; 2055 2056 ata_std_postreset(link, classes); 2057 2058 /* is double-select really necessary? */ 2059 if (classes[0] != ATA_DEV_NONE) 2060 ap->ops->sff_dev_select(ap, 1); 2061 if (classes[1] != ATA_DEV_NONE) 2062 ap->ops->sff_dev_select(ap, 0); 2063 2064 /* bail out if no device is present */ 2065 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) { 2066 DPRINTK("EXIT, no device\n"); 2067 return; 2068 } 2069 2070 /* set up device control */ 2071 if (ap->ioaddr.ctl_addr) 2072 iowrite8(ap->ctl, ap->ioaddr.ctl_addr); 2073 } 2074 2075 /** 2076 * ata_sff_error_handler - Stock error handler for BMDMA controller 2077 * @ap: port to handle error for 2078 * 2079 * Stock error handler for SFF controller. It can handle both 2080 * PATA and SATA controllers. Many controllers should be able to 2081 * use this EH as-is or with some added handling before and 2082 * after. 2083 * 2084 * LOCKING: 2085 * Kernel thread context (may sleep) 2086 */ 2087 void ata_sff_error_handler(struct ata_port *ap) 2088 { 2089 ata_reset_fn_t softreset = ap->ops->softreset; 2090 ata_reset_fn_t hardreset = ap->ops->hardreset; 2091 struct ata_queued_cmd *qc; 2092 unsigned long flags; 2093 int thaw = 0; 2094 2095 qc = __ata_qc_from_tag(ap, ap->link.active_tag); 2096 if (qc && !(qc->flags & ATA_QCFLAG_FAILED)) 2097 qc = NULL; 2098 2099 /* reset PIO HSM and stop DMA engine */ 2100 spin_lock_irqsave(ap->lock, flags); 2101 2102 ap->hsm_task_state = HSM_ST_IDLE; 2103 2104 if (ap->ioaddr.bmdma_addr && 2105 qc && (qc->tf.protocol == ATA_PROT_DMA || 2106 qc->tf.protocol == ATAPI_PROT_DMA)) { 2107 u8 host_stat; 2108 2109 host_stat = ap->ops->bmdma_status(ap); 2110 2111 /* BMDMA controllers indicate host bus error by 2112 * setting DMA_ERR bit and timing out. As it wasn't 2113 * really a timeout event, adjust error mask and 2114 * cancel frozen state. 2115 */ 2116 if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) { 2117 qc->err_mask = AC_ERR_HOST_BUS; 2118 thaw = 1; 2119 } 2120 2121 ap->ops->bmdma_stop(qc); 2122 } 2123 2124 ata_sff_sync(ap); /* FIXME: We don't need this */ 2125 ap->ops->sff_check_status(ap); 2126 ap->ops->sff_irq_clear(ap); 2127 2128 spin_unlock_irqrestore(ap->lock, flags); 2129 2130 if (thaw) 2131 ata_eh_thaw_port(ap); 2132 2133 /* PIO and DMA engines have been stopped, perform recovery */ 2134 2135 /* Ignore ata_sff_softreset if ctl isn't accessible and 2136 * built-in hardresets if SCR access isn't available. 2137 */ 2138 if (softreset == ata_sff_softreset && !ap->ioaddr.ctl_addr) 2139 softreset = NULL; 2140 if (ata_is_builtin_hardreset(hardreset) && !sata_scr_valid(&ap->link)) 2141 hardreset = NULL; 2142 2143 ata_do_eh(ap, ap->ops->prereset, softreset, hardreset, 2144 ap->ops->postreset); 2145 } 2146 2147 /** 2148 * ata_sff_post_internal_cmd - Stock post_internal_cmd for SFF controller 2149 * @qc: internal command to clean up 2150 * 2151 * LOCKING: 2152 * Kernel thread context (may sleep) 2153 */ 2154 void ata_sff_post_internal_cmd(struct ata_queued_cmd *qc) 2155 { 2156 struct ata_port *ap = qc->ap; 2157 unsigned long flags; 2158 2159 spin_lock_irqsave(ap->lock, flags); 2160 2161 ap->hsm_task_state = HSM_ST_IDLE; 2162 2163 if (ap->ioaddr.bmdma_addr) 2164 ata_bmdma_stop(qc); 2165 2166 spin_unlock_irqrestore(ap->lock, flags); 2167 } 2168 2169 /** 2170 * ata_sff_port_start - Set port up for dma. 2171 * @ap: Port to initialize 2172 * 2173 * Called just after data structures for each port are 2174 * initialized. Allocates space for PRD table if the device 2175 * is DMA capable SFF. 2176 * 2177 * May be used as the port_start() entry in ata_port_operations. 2178 * 2179 * LOCKING: 2180 * Inherited from caller. 2181 */ 2182 int ata_sff_port_start(struct ata_port *ap) 2183 { 2184 if (ap->ioaddr.bmdma_addr) 2185 return ata_port_start(ap); 2186 return 0; 2187 } 2188 2189 /** 2190 * ata_sff_std_ports - initialize ioaddr with standard port offsets. 2191 * @ioaddr: IO address structure to be initialized 2192 * 2193 * Utility function which initializes data_addr, error_addr, 2194 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr, 2195 * device_addr, status_addr, and command_addr to standard offsets 2196 * relative to cmd_addr. 2197 * 2198 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr. 2199 */ 2200 void ata_sff_std_ports(struct ata_ioports *ioaddr) 2201 { 2202 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA; 2203 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR; 2204 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE; 2205 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT; 2206 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL; 2207 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM; 2208 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH; 2209 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE; 2210 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS; 2211 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD; 2212 } 2213 2214 unsigned long ata_bmdma_mode_filter(struct ata_device *adev, 2215 unsigned long xfer_mask) 2216 { 2217 /* Filter out DMA modes if the device has been configured by 2218 the BIOS as PIO only */ 2219 2220 if (adev->link->ap->ioaddr.bmdma_addr == NULL) 2221 xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA); 2222 return xfer_mask; 2223 } 2224 2225 /** 2226 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction 2227 * @qc: Info associated with this ATA transaction. 2228 * 2229 * LOCKING: 2230 * spin_lock_irqsave(host lock) 2231 */ 2232 void ata_bmdma_setup(struct ata_queued_cmd *qc) 2233 { 2234 struct ata_port *ap = qc->ap; 2235 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); 2236 u8 dmactl; 2237 2238 /* load PRD table addr. */ 2239 mb(); /* make sure PRD table writes are visible to controller */ 2240 iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); 2241 2242 /* specify data direction, triple-check start bit is clear */ 2243 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); 2244 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); 2245 if (!rw) 2246 dmactl |= ATA_DMA_WR; 2247 iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); 2248 2249 /* issue r/w command */ 2250 ap->ops->sff_exec_command(ap, &qc->tf); 2251 } 2252 2253 /** 2254 * ata_bmdma_start - Start a PCI IDE BMDMA transaction 2255 * @qc: Info associated with this ATA transaction. 2256 * 2257 * LOCKING: 2258 * spin_lock_irqsave(host lock) 2259 */ 2260 void ata_bmdma_start(struct ata_queued_cmd *qc) 2261 { 2262 struct ata_port *ap = qc->ap; 2263 u8 dmactl; 2264 2265 /* start host DMA transaction */ 2266 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); 2267 iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); 2268 2269 /* Strictly, one may wish to issue an ioread8() here, to 2270 * flush the mmio write. However, control also passes 2271 * to the hardware at this point, and it will interrupt 2272 * us when we are to resume control. So, in effect, 2273 * we don't care when the mmio write flushes. 2274 * Further, a read of the DMA status register _immediately_ 2275 * following the write may not be what certain flaky hardware 2276 * is expected, so I think it is best to not add a readb() 2277 * without first all the MMIO ATA cards/mobos. 2278 * Or maybe I'm just being paranoid. 2279 * 2280 * FIXME: The posting of this write means I/O starts are 2281 * unneccessarily delayed for MMIO 2282 */ 2283 } 2284 2285 /** 2286 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer 2287 * @qc: Command we are ending DMA for 2288 * 2289 * Clears the ATA_DMA_START flag in the dma control register 2290 * 2291 * May be used as the bmdma_stop() entry in ata_port_operations. 2292 * 2293 * LOCKING: 2294 * spin_lock_irqsave(host lock) 2295 */ 2296 void ata_bmdma_stop(struct ata_queued_cmd *qc) 2297 { 2298 struct ata_port *ap = qc->ap; 2299 void __iomem *mmio = ap->ioaddr.bmdma_addr; 2300 2301 /* clear start/stop bit */ 2302 iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START, 2303 mmio + ATA_DMA_CMD); 2304 2305 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ 2306 ata_sff_dma_pause(ap); 2307 } 2308 2309 /** 2310 * ata_bmdma_status - Read PCI IDE BMDMA status 2311 * @ap: Port associated with this ATA transaction. 2312 * 2313 * Read and return BMDMA status register. 2314 * 2315 * May be used as the bmdma_status() entry in ata_port_operations. 2316 * 2317 * LOCKING: 2318 * spin_lock_irqsave(host lock) 2319 */ 2320 u8 ata_bmdma_status(struct ata_port *ap) 2321 { 2322 return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); 2323 } 2324 2325 /** 2326 * ata_bus_reset - reset host port and associated ATA channel 2327 * @ap: port to reset 2328 * 2329 * This is typically the first time we actually start issuing 2330 * commands to the ATA channel. We wait for BSY to clear, then 2331 * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its 2332 * result. Determine what devices, if any, are on the channel 2333 * by looking at the device 0/1 error register. Look at the signature 2334 * stored in each device's taskfile registers, to determine if 2335 * the device is ATA or ATAPI. 2336 * 2337 * LOCKING: 2338 * PCI/etc. bus probe sem. 2339 * Obtains host lock. 2340 * 2341 * SIDE EFFECTS: 2342 * Sets ATA_FLAG_DISABLED if bus reset fails. 2343 * 2344 * DEPRECATED: 2345 * This function is only for drivers which still use old EH and 2346 * will be removed soon. 2347 */ 2348 void ata_bus_reset(struct ata_port *ap) 2349 { 2350 struct ata_device *device = ap->link.device; 2351 struct ata_ioports *ioaddr = &ap->ioaddr; 2352 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS; 2353 u8 err; 2354 unsigned int dev0, dev1 = 0, devmask = 0; 2355 int rc; 2356 2357 DPRINTK("ENTER, host %u, port %u\n", ap->print_id, ap->port_no); 2358 2359 /* determine if device 0/1 are present */ 2360 if (ap->flags & ATA_FLAG_SATA_RESET) 2361 dev0 = 1; 2362 else { 2363 dev0 = ata_devchk(ap, 0); 2364 if (slave_possible) 2365 dev1 = ata_devchk(ap, 1); 2366 } 2367 2368 if (dev0) 2369 devmask |= (1 << 0); 2370 if (dev1) 2371 devmask |= (1 << 1); 2372 2373 /* select device 0 again */ 2374 ap->ops->sff_dev_select(ap, 0); 2375 2376 /* issue bus reset */ 2377 if (ap->flags & ATA_FLAG_SRST) { 2378 rc = ata_bus_softreset(ap, devmask, 2379 ata_deadline(jiffies, 40000)); 2380 if (rc && rc != -ENODEV) 2381 goto err_out; 2382 } 2383 2384 /* 2385 * determine by signature whether we have ATA or ATAPI devices 2386 */ 2387 device[0].class = ata_sff_dev_classify(&device[0], dev0, &err); 2388 if ((slave_possible) && (err != 0x81)) 2389 device[1].class = ata_sff_dev_classify(&device[1], dev1, &err); 2390 2391 /* is double-select really necessary? */ 2392 if (device[1].class != ATA_DEV_NONE) 2393 ap->ops->sff_dev_select(ap, 1); 2394 if (device[0].class != ATA_DEV_NONE) 2395 ap->ops->sff_dev_select(ap, 0); 2396 2397 /* if no devices were detected, disable this port */ 2398 if ((device[0].class == ATA_DEV_NONE) && 2399 (device[1].class == ATA_DEV_NONE)) 2400 goto err_out; 2401 2402 if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) { 2403 /* set up device control for ATA_FLAG_SATA_RESET */ 2404 iowrite8(ap->ctl, ioaddr->ctl_addr); 2405 } 2406 2407 DPRINTK("EXIT\n"); 2408 return; 2409 2410 err_out: 2411 ata_port_printk(ap, KERN_ERR, "disabling port\n"); 2412 ata_port_disable(ap); 2413 2414 DPRINTK("EXIT\n"); 2415 } 2416 2417 #ifdef CONFIG_PCI 2418 2419 /** 2420 * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex 2421 * @pdev: PCI device 2422 * 2423 * Some PCI ATA devices report simplex mode but in fact can be told to 2424 * enter non simplex mode. This implements the necessary logic to 2425 * perform the task on such devices. Calling it on other devices will 2426 * have -undefined- behaviour. 2427 */ 2428 int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev) 2429 { 2430 unsigned long bmdma = pci_resource_start(pdev, 4); 2431 u8 simplex; 2432 2433 if (bmdma == 0) 2434 return -ENOENT; 2435 2436 simplex = inb(bmdma + 0x02); 2437 outb(simplex & 0x60, bmdma + 0x02); 2438 simplex = inb(bmdma + 0x02); 2439 if (simplex & 0x80) 2440 return -EOPNOTSUPP; 2441 return 0; 2442 } 2443 2444 /** 2445 * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host 2446 * @host: target ATA host 2447 * 2448 * Acquire PCI BMDMA resources and initialize @host accordingly. 2449 * 2450 * LOCKING: 2451 * Inherited from calling layer (may sleep). 2452 * 2453 * RETURNS: 2454 * 0 on success, -errno otherwise. 2455 */ 2456 int ata_pci_bmdma_init(struct ata_host *host) 2457 { 2458 struct device *gdev = host->dev; 2459 struct pci_dev *pdev = to_pci_dev(gdev); 2460 int i, rc; 2461 2462 /* No BAR4 allocation: No DMA */ 2463 if (pci_resource_start(pdev, 4) == 0) 2464 return 0; 2465 2466 /* TODO: If we get no DMA mask we should fall back to PIO */ 2467 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); 2468 if (rc) 2469 return rc; 2470 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); 2471 if (rc) 2472 return rc; 2473 2474 /* request and iomap DMA region */ 2475 rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev)); 2476 if (rc) { 2477 dev_printk(KERN_ERR, gdev, "failed to request/iomap BAR4\n"); 2478 return -ENOMEM; 2479 } 2480 host->iomap = pcim_iomap_table(pdev); 2481 2482 for (i = 0; i < 2; i++) { 2483 struct ata_port *ap = host->ports[i]; 2484 void __iomem *bmdma = host->iomap[4] + 8 * i; 2485 2486 if (ata_port_is_dummy(ap)) 2487 continue; 2488 2489 ap->ioaddr.bmdma_addr = bmdma; 2490 if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) && 2491 (ioread8(bmdma + 2) & 0x80)) 2492 host->flags |= ATA_HOST_SIMPLEX; 2493 2494 ata_port_desc(ap, "bmdma 0x%llx", 2495 (unsigned long long)pci_resource_start(pdev, 4) + 8 * i); 2496 } 2497 2498 return 0; 2499 } 2500 2501 static int ata_resources_present(struct pci_dev *pdev, int port) 2502 { 2503 int i; 2504 2505 /* Check the PCI resources for this channel are enabled */ 2506 port = port * 2; 2507 for (i = 0; i < 2; i ++) { 2508 if (pci_resource_start(pdev, port + i) == 0 || 2509 pci_resource_len(pdev, port + i) == 0) 2510 return 0; 2511 } 2512 return 1; 2513 } 2514 2515 /** 2516 * ata_pci_sff_init_host - acquire native PCI ATA resources and init host 2517 * @host: target ATA host 2518 * 2519 * Acquire native PCI ATA resources for @host and initialize the 2520 * first two ports of @host accordingly. Ports marked dummy are 2521 * skipped and allocation failure makes the port dummy. 2522 * 2523 * Note that native PCI resources are valid even for legacy hosts 2524 * as we fix up pdev resources array early in boot, so this 2525 * function can be used for both native and legacy SFF hosts. 2526 * 2527 * LOCKING: 2528 * Inherited from calling layer (may sleep). 2529 * 2530 * RETURNS: 2531 * 0 if at least one port is initialized, -ENODEV if no port is 2532 * available. 2533 */ 2534 int ata_pci_sff_init_host(struct ata_host *host) 2535 { 2536 struct device *gdev = host->dev; 2537 struct pci_dev *pdev = to_pci_dev(gdev); 2538 unsigned int mask = 0; 2539 int i, rc; 2540 2541 /* request, iomap BARs and init port addresses accordingly */ 2542 for (i = 0; i < 2; i++) { 2543 struct ata_port *ap = host->ports[i]; 2544 int base = i * 2; 2545 void __iomem * const *iomap; 2546 2547 if (ata_port_is_dummy(ap)) 2548 continue; 2549 2550 /* Discard disabled ports. Some controllers show 2551 * their unused channels this way. Disabled ports are 2552 * made dummy. 2553 */ 2554 if (!ata_resources_present(pdev, i)) { 2555 ap->ops = &ata_dummy_port_ops; 2556 continue; 2557 } 2558 2559 rc = pcim_iomap_regions(pdev, 0x3 << base, 2560 dev_driver_string(gdev)); 2561 if (rc) { 2562 dev_printk(KERN_WARNING, gdev, 2563 "failed to request/iomap BARs for port %d " 2564 "(errno=%d)\n", i, rc); 2565 if (rc == -EBUSY) 2566 pcim_pin_device(pdev); 2567 ap->ops = &ata_dummy_port_ops; 2568 continue; 2569 } 2570 host->iomap = iomap = pcim_iomap_table(pdev); 2571 2572 ap->ioaddr.cmd_addr = iomap[base]; 2573 ap->ioaddr.altstatus_addr = 2574 ap->ioaddr.ctl_addr = (void __iomem *) 2575 ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS); 2576 ata_sff_std_ports(&ap->ioaddr); 2577 2578 ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx", 2579 (unsigned long long)pci_resource_start(pdev, base), 2580 (unsigned long long)pci_resource_start(pdev, base + 1)); 2581 2582 mask |= 1 << i; 2583 } 2584 2585 if (!mask) { 2586 dev_printk(KERN_ERR, gdev, "no available native port\n"); 2587 return -ENODEV; 2588 } 2589 2590 return 0; 2591 } 2592 2593 /** 2594 * ata_pci_sff_prepare_host - helper to prepare native PCI ATA host 2595 * @pdev: target PCI device 2596 * @ppi: array of port_info, must be enough for two ports 2597 * @r_host: out argument for the initialized ATA host 2598 * 2599 * Helper to allocate ATA host for @pdev, acquire all native PCI 2600 * resources and initialize it accordingly in one go. 2601 * 2602 * LOCKING: 2603 * Inherited from calling layer (may sleep). 2604 * 2605 * RETURNS: 2606 * 0 on success, -errno otherwise. 2607 */ 2608 int ata_pci_sff_prepare_host(struct pci_dev *pdev, 2609 const struct ata_port_info * const * ppi, 2610 struct ata_host **r_host) 2611 { 2612 struct ata_host *host; 2613 int rc; 2614 2615 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) 2616 return -ENOMEM; 2617 2618 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); 2619 if (!host) { 2620 dev_printk(KERN_ERR, &pdev->dev, 2621 "failed to allocate ATA host\n"); 2622 rc = -ENOMEM; 2623 goto err_out; 2624 } 2625 2626 rc = ata_pci_sff_init_host(host); 2627 if (rc) 2628 goto err_out; 2629 2630 /* init DMA related stuff */ 2631 rc = ata_pci_bmdma_init(host); 2632 if (rc) 2633 goto err_bmdma; 2634 2635 devres_remove_group(&pdev->dev, NULL); 2636 *r_host = host; 2637 return 0; 2638 2639 err_bmdma: 2640 /* This is necessary because PCI and iomap resources are 2641 * merged and releasing the top group won't release the 2642 * acquired resources if some of those have been acquired 2643 * before entering this function. 2644 */ 2645 pcim_iounmap_regions(pdev, 0xf); 2646 err_out: 2647 devres_release_group(&pdev->dev, NULL); 2648 return rc; 2649 } 2650 2651 /** 2652 * ata_pci_sff_activate_host - start SFF host, request IRQ and register it 2653 * @host: target SFF ATA host 2654 * @irq_handler: irq_handler used when requesting IRQ(s) 2655 * @sht: scsi_host_template to use when registering the host 2656 * 2657 * This is the counterpart of ata_host_activate() for SFF ATA 2658 * hosts. This separate helper is necessary because SFF hosts 2659 * use two separate interrupts in legacy mode. 2660 * 2661 * LOCKING: 2662 * Inherited from calling layer (may sleep). 2663 * 2664 * RETURNS: 2665 * 0 on success, -errno otherwise. 2666 */ 2667 int ata_pci_sff_activate_host(struct ata_host *host, 2668 irq_handler_t irq_handler, 2669 struct scsi_host_template *sht) 2670 { 2671 struct device *dev = host->dev; 2672 struct pci_dev *pdev = to_pci_dev(dev); 2673 const char *drv_name = dev_driver_string(host->dev); 2674 int legacy_mode = 0, rc; 2675 2676 rc = ata_host_start(host); 2677 if (rc) 2678 return rc; 2679 2680 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) { 2681 u8 tmp8, mask; 2682 2683 /* TODO: What if one channel is in native mode ... */ 2684 pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8); 2685 mask = (1 << 2) | (1 << 0); 2686 if ((tmp8 & mask) != mask) 2687 legacy_mode = 1; 2688 #if defined(CONFIG_NO_ATA_LEGACY) 2689 /* Some platforms with PCI limits cannot address compat 2690 port space. In that case we punt if their firmware has 2691 left a device in compatibility mode */ 2692 if (legacy_mode) { 2693 printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n"); 2694 return -EOPNOTSUPP; 2695 } 2696 #endif 2697 } 2698 2699 if (!devres_open_group(dev, NULL, GFP_KERNEL)) 2700 return -ENOMEM; 2701 2702 if (!legacy_mode && pdev->irq) { 2703 rc = devm_request_irq(dev, pdev->irq, irq_handler, 2704 IRQF_SHARED, drv_name, host); 2705 if (rc) 2706 goto out; 2707 2708 ata_port_desc(host->ports[0], "irq %d", pdev->irq); 2709 ata_port_desc(host->ports[1], "irq %d", pdev->irq); 2710 } else if (legacy_mode) { 2711 if (!ata_port_is_dummy(host->ports[0])) { 2712 rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev), 2713 irq_handler, IRQF_SHARED, 2714 drv_name, host); 2715 if (rc) 2716 goto out; 2717 2718 ata_port_desc(host->ports[0], "irq %d", 2719 ATA_PRIMARY_IRQ(pdev)); 2720 } 2721 2722 if (!ata_port_is_dummy(host->ports[1])) { 2723 rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev), 2724 irq_handler, IRQF_SHARED, 2725 drv_name, host); 2726 if (rc) 2727 goto out; 2728 2729 ata_port_desc(host->ports[1], "irq %d", 2730 ATA_SECONDARY_IRQ(pdev)); 2731 } 2732 } 2733 2734 rc = ata_host_register(host, sht); 2735 out: 2736 if (rc == 0) 2737 devres_remove_group(dev, NULL); 2738 else 2739 devres_release_group(dev, NULL); 2740 2741 return rc; 2742 } 2743 2744 /** 2745 * ata_pci_sff_init_one - Initialize/register PCI IDE host controller 2746 * @pdev: Controller to be initialized 2747 * @ppi: array of port_info, must be enough for two ports 2748 * @sht: scsi_host_template to use when registering the host 2749 * @host_priv: host private_data 2750 * 2751 * This is a helper function which can be called from a driver's 2752 * xxx_init_one() probe function if the hardware uses traditional 2753 * IDE taskfile registers. 2754 * 2755 * This function calls pci_enable_device(), reserves its register 2756 * regions, sets the dma mask, enables bus master mode, and calls 2757 * ata_device_add() 2758 * 2759 * ASSUMPTION: 2760 * Nobody makes a single channel controller that appears solely as 2761 * the secondary legacy port on PCI. 2762 * 2763 * LOCKING: 2764 * Inherited from PCI layer (may sleep). 2765 * 2766 * RETURNS: 2767 * Zero on success, negative on errno-based value on error. 2768 */ 2769 int ata_pci_sff_init_one(struct pci_dev *pdev, 2770 const struct ata_port_info * const * ppi, 2771 struct scsi_host_template *sht, void *host_priv) 2772 { 2773 struct device *dev = &pdev->dev; 2774 const struct ata_port_info *pi = NULL; 2775 struct ata_host *host = NULL; 2776 int i, rc; 2777 2778 DPRINTK("ENTER\n"); 2779 2780 /* look up the first valid port_info */ 2781 for (i = 0; i < 2 && ppi[i]; i++) { 2782 if (ppi[i]->port_ops != &ata_dummy_port_ops) { 2783 pi = ppi[i]; 2784 break; 2785 } 2786 } 2787 2788 if (!pi) { 2789 dev_printk(KERN_ERR, &pdev->dev, 2790 "no valid port_info specified\n"); 2791 return -EINVAL; 2792 } 2793 2794 if (!devres_open_group(dev, NULL, GFP_KERNEL)) 2795 return -ENOMEM; 2796 2797 rc = pcim_enable_device(pdev); 2798 if (rc) 2799 goto out; 2800 2801 /* prepare and activate SFF host */ 2802 rc = ata_pci_sff_prepare_host(pdev, ppi, &host); 2803 if (rc) 2804 goto out; 2805 host->private_data = host_priv; 2806 2807 pci_set_master(pdev); 2808 rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht); 2809 out: 2810 if (rc == 0) 2811 devres_remove_group(&pdev->dev, NULL); 2812 else 2813 devres_release_group(&pdev->dev, NULL); 2814 2815 return rc; 2816 } 2817 2818 #endif /* CONFIG_PCI */ 2819 2820 EXPORT_SYMBOL_GPL(ata_sff_port_ops); 2821 EXPORT_SYMBOL_GPL(ata_bmdma_port_ops); 2822 EXPORT_SYMBOL_GPL(ata_sff_qc_prep); 2823 EXPORT_SYMBOL_GPL(ata_sff_dumb_qc_prep); 2824 EXPORT_SYMBOL_GPL(ata_sff_dev_select); 2825 EXPORT_SYMBOL_GPL(ata_sff_check_status); 2826 EXPORT_SYMBOL_GPL(ata_sff_dma_pause); 2827 EXPORT_SYMBOL_GPL(ata_sff_pause); 2828 EXPORT_SYMBOL_GPL(ata_sff_busy_sleep); 2829 EXPORT_SYMBOL_GPL(ata_sff_wait_ready); 2830 EXPORT_SYMBOL_GPL(ata_sff_tf_load); 2831 EXPORT_SYMBOL_GPL(ata_sff_tf_read); 2832 EXPORT_SYMBOL_GPL(ata_sff_exec_command); 2833 EXPORT_SYMBOL_GPL(ata_sff_data_xfer); 2834 EXPORT_SYMBOL_GPL(ata_sff_data_xfer_noirq); 2835 EXPORT_SYMBOL_GPL(ata_sff_irq_on); 2836 EXPORT_SYMBOL_GPL(ata_sff_irq_clear); 2837 EXPORT_SYMBOL_GPL(ata_sff_hsm_move); 2838 EXPORT_SYMBOL_GPL(ata_sff_qc_issue); 2839 EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf); 2840 EXPORT_SYMBOL_GPL(ata_sff_host_intr); 2841 EXPORT_SYMBOL_GPL(ata_sff_interrupt); 2842 EXPORT_SYMBOL_GPL(ata_sff_freeze); 2843 EXPORT_SYMBOL_GPL(ata_sff_thaw); 2844 EXPORT_SYMBOL_GPL(ata_sff_prereset); 2845 EXPORT_SYMBOL_GPL(ata_sff_dev_classify); 2846 EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset); 2847 EXPORT_SYMBOL_GPL(ata_sff_softreset); 2848 EXPORT_SYMBOL_GPL(sata_sff_hardreset); 2849 EXPORT_SYMBOL_GPL(ata_sff_postreset); 2850 EXPORT_SYMBOL_GPL(ata_sff_error_handler); 2851 EXPORT_SYMBOL_GPL(ata_sff_post_internal_cmd); 2852 EXPORT_SYMBOL_GPL(ata_sff_port_start); 2853 EXPORT_SYMBOL_GPL(ata_sff_std_ports); 2854 EXPORT_SYMBOL_GPL(ata_bmdma_mode_filter); 2855 EXPORT_SYMBOL_GPL(ata_bmdma_setup); 2856 EXPORT_SYMBOL_GPL(ata_bmdma_start); 2857 EXPORT_SYMBOL_GPL(ata_bmdma_stop); 2858 EXPORT_SYMBOL_GPL(ata_bmdma_status); 2859 EXPORT_SYMBOL_GPL(ata_bus_reset); 2860 #ifdef CONFIG_PCI 2861 EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex); 2862 EXPORT_SYMBOL_GPL(ata_pci_bmdma_init); 2863 EXPORT_SYMBOL_GPL(ata_pci_sff_init_host); 2864 EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host); 2865 EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host); 2866 EXPORT_SYMBOL_GPL(ata_pci_sff_init_one); 2867 #endif /* CONFIG_PCI */ 2868