xref: /openbmc/linux/drivers/ata/libata-sff.c (revision 22246614)
1 /*
2  *  libata-sff.c - helper library for PCI IDE BMDMA
3  *
4  *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
5  *    		    Please ALWAYS copy linux-ide@vger.kernel.org
6  *		    on emails.
7  *
8  *  Copyright 2003-2006 Red Hat, Inc.  All rights reserved.
9  *  Copyright 2003-2006 Jeff Garzik
10  *
11  *
12  *  This program is free software; you can redistribute it and/or modify
13  *  it under the terms of the GNU General Public License as published by
14  *  the Free Software Foundation; either version 2, or (at your option)
15  *  any later version.
16  *
17  *  This program is distributed in the hope that it will be useful,
18  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
19  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20  *  GNU General Public License for more details.
21  *
22  *  You should have received a copy of the GNU General Public License
23  *  along with this program; see the file COPYING.  If not, write to
24  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25  *
26  *
27  *  libata documentation is available via 'make {ps|pdf}docs',
28  *  as Documentation/DocBook/libata.*
29  *
30  *  Hardware documentation available from http://www.t13.org/ and
31  *  http://www.sata-io.org/
32  *
33  */
34 
35 #include <linux/kernel.h>
36 #include <linux/pci.h>
37 #include <linux/libata.h>
38 #include <linux/highmem.h>
39 
40 #include "libata.h"
41 
42 const struct ata_port_operations ata_sff_port_ops = {
43 	.inherits		= &ata_base_port_ops,
44 
45 	.qc_prep		= ata_sff_qc_prep,
46 	.qc_issue		= ata_sff_qc_issue,
47 	.qc_fill_rtf		= ata_sff_qc_fill_rtf,
48 
49 	.freeze			= ata_sff_freeze,
50 	.thaw			= ata_sff_thaw,
51 	.prereset		= ata_sff_prereset,
52 	.softreset		= ata_sff_softreset,
53 	.hardreset		= sata_sff_hardreset,
54 	.postreset		= ata_sff_postreset,
55 	.error_handler		= ata_sff_error_handler,
56 	.post_internal_cmd	= ata_sff_post_internal_cmd,
57 
58 	.sff_dev_select		= ata_sff_dev_select,
59 	.sff_check_status	= ata_sff_check_status,
60 	.sff_tf_load		= ata_sff_tf_load,
61 	.sff_tf_read		= ata_sff_tf_read,
62 	.sff_exec_command	= ata_sff_exec_command,
63 	.sff_data_xfer		= ata_sff_data_xfer,
64 	.sff_irq_on		= ata_sff_irq_on,
65 	.sff_irq_clear		= ata_sff_irq_clear,
66 
67 	.port_start		= ata_sff_port_start,
68 };
69 
70 const struct ata_port_operations ata_bmdma_port_ops = {
71 	.inherits		= &ata_sff_port_ops,
72 
73 	.mode_filter		= ata_bmdma_mode_filter,
74 
75 	.bmdma_setup		= ata_bmdma_setup,
76 	.bmdma_start		= ata_bmdma_start,
77 	.bmdma_stop		= ata_bmdma_stop,
78 	.bmdma_status		= ata_bmdma_status,
79 };
80 
81 /**
82  *	ata_fill_sg - Fill PCI IDE PRD table
83  *	@qc: Metadata associated with taskfile to be transferred
84  *
85  *	Fill PCI IDE PRD (scatter-gather) table with segments
86  *	associated with the current disk command.
87  *
88  *	LOCKING:
89  *	spin_lock_irqsave(host lock)
90  *
91  */
92 static void ata_fill_sg(struct ata_queued_cmd *qc)
93 {
94 	struct ata_port *ap = qc->ap;
95 	struct scatterlist *sg;
96 	unsigned int si, pi;
97 
98 	pi = 0;
99 	for_each_sg(qc->sg, sg, qc->n_elem, si) {
100 		u32 addr, offset;
101 		u32 sg_len, len;
102 
103 		/* determine if physical DMA addr spans 64K boundary.
104 		 * Note h/w doesn't support 64-bit, so we unconditionally
105 		 * truncate dma_addr_t to u32.
106 		 */
107 		addr = (u32) sg_dma_address(sg);
108 		sg_len = sg_dma_len(sg);
109 
110 		while (sg_len) {
111 			offset = addr & 0xffff;
112 			len = sg_len;
113 			if ((offset + sg_len) > 0x10000)
114 				len = 0x10000 - offset;
115 
116 			ap->prd[pi].addr = cpu_to_le32(addr);
117 			ap->prd[pi].flags_len = cpu_to_le32(len & 0xffff);
118 			VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
119 
120 			pi++;
121 			sg_len -= len;
122 			addr += len;
123 		}
124 	}
125 
126 	ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
127 }
128 
129 /**
130  *	ata_fill_sg_dumb - Fill PCI IDE PRD table
131  *	@qc: Metadata associated with taskfile to be transferred
132  *
133  *	Fill PCI IDE PRD (scatter-gather) table with segments
134  *	associated with the current disk command. Perform the fill
135  *	so that we avoid writing any length 64K records for
136  *	controllers that don't follow the spec.
137  *
138  *	LOCKING:
139  *	spin_lock_irqsave(host lock)
140  *
141  */
142 static void ata_fill_sg_dumb(struct ata_queued_cmd *qc)
143 {
144 	struct ata_port *ap = qc->ap;
145 	struct scatterlist *sg;
146 	unsigned int si, pi;
147 
148 	pi = 0;
149 	for_each_sg(qc->sg, sg, qc->n_elem, si) {
150 		u32 addr, offset;
151 		u32 sg_len, len, blen;
152 
153 		/* determine if physical DMA addr spans 64K boundary.
154 		 * Note h/w doesn't support 64-bit, so we unconditionally
155 		 * truncate dma_addr_t to u32.
156 		 */
157 		addr = (u32) sg_dma_address(sg);
158 		sg_len = sg_dma_len(sg);
159 
160 		while (sg_len) {
161 			offset = addr & 0xffff;
162 			len = sg_len;
163 			if ((offset + sg_len) > 0x10000)
164 				len = 0x10000 - offset;
165 
166 			blen = len & 0xffff;
167 			ap->prd[pi].addr = cpu_to_le32(addr);
168 			if (blen == 0) {
169 			   /* Some PATA chipsets like the CS5530 can't
170 			      cope with 0x0000 meaning 64K as the spec says */
171 				ap->prd[pi].flags_len = cpu_to_le32(0x8000);
172 				blen = 0x8000;
173 				ap->prd[++pi].addr = cpu_to_le32(addr + 0x8000);
174 			}
175 			ap->prd[pi].flags_len = cpu_to_le32(blen);
176 			VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
177 
178 			pi++;
179 			sg_len -= len;
180 			addr += len;
181 		}
182 	}
183 
184 	ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
185 }
186 
187 /**
188  *	ata_sff_qc_prep - Prepare taskfile for submission
189  *	@qc: Metadata associated with taskfile to be prepared
190  *
191  *	Prepare ATA taskfile for submission.
192  *
193  *	LOCKING:
194  *	spin_lock_irqsave(host lock)
195  */
196 void ata_sff_qc_prep(struct ata_queued_cmd *qc)
197 {
198 	if (!(qc->flags & ATA_QCFLAG_DMAMAP))
199 		return;
200 
201 	ata_fill_sg(qc);
202 }
203 
204 /**
205  *	ata_sff_dumb_qc_prep - Prepare taskfile for submission
206  *	@qc: Metadata associated with taskfile to be prepared
207  *
208  *	Prepare ATA taskfile for submission.
209  *
210  *	LOCKING:
211  *	spin_lock_irqsave(host lock)
212  */
213 void ata_sff_dumb_qc_prep(struct ata_queued_cmd *qc)
214 {
215 	if (!(qc->flags & ATA_QCFLAG_DMAMAP))
216 		return;
217 
218 	ata_fill_sg_dumb(qc);
219 }
220 
221 /**
222  *	ata_sff_check_status - Read device status reg & clear interrupt
223  *	@ap: port where the device is
224  *
225  *	Reads ATA taskfile status register for currently-selected device
226  *	and return its value. This also clears pending interrupts
227  *      from this device
228  *
229  *	LOCKING:
230  *	Inherited from caller.
231  */
232 u8 ata_sff_check_status(struct ata_port *ap)
233 {
234 	return ioread8(ap->ioaddr.status_addr);
235 }
236 
237 /**
238  *	ata_sff_altstatus - Read device alternate status reg
239  *	@ap: port where the device is
240  *
241  *	Reads ATA taskfile alternate status register for
242  *	currently-selected device and return its value.
243  *
244  *	Note: may NOT be used as the check_altstatus() entry in
245  *	ata_port_operations.
246  *
247  *	LOCKING:
248  *	Inherited from caller.
249  */
250 u8 ata_sff_altstatus(struct ata_port *ap)
251 {
252 	if (ap->ops->sff_check_altstatus)
253 		return ap->ops->sff_check_altstatus(ap);
254 
255 	return ioread8(ap->ioaddr.altstatus_addr);
256 }
257 
258 /**
259  *	ata_sff_busy_sleep - sleep until BSY clears, or timeout
260  *	@ap: port containing status register to be polled
261  *	@tmout_pat: impatience timeout
262  *	@tmout: overall timeout
263  *
264  *	Sleep until ATA Status register bit BSY clears,
265  *	or a timeout occurs.
266  *
267  *	LOCKING:
268  *	Kernel thread context (may sleep).
269  *
270  *	RETURNS:
271  *	0 on success, -errno otherwise.
272  */
273 int ata_sff_busy_sleep(struct ata_port *ap,
274 		       unsigned long tmout_pat, unsigned long tmout)
275 {
276 	unsigned long timer_start, timeout;
277 	u8 status;
278 
279 	status = ata_sff_busy_wait(ap, ATA_BUSY, 300);
280 	timer_start = jiffies;
281 	timeout = timer_start + tmout_pat;
282 	while (status != 0xff && (status & ATA_BUSY) &&
283 	       time_before(jiffies, timeout)) {
284 		msleep(50);
285 		status = ata_sff_busy_wait(ap, ATA_BUSY, 3);
286 	}
287 
288 	if (status != 0xff && (status & ATA_BUSY))
289 		ata_port_printk(ap, KERN_WARNING,
290 				"port is slow to respond, please be patient "
291 				"(Status 0x%x)\n", status);
292 
293 	timeout = timer_start + tmout;
294 	while (status != 0xff && (status & ATA_BUSY) &&
295 	       time_before(jiffies, timeout)) {
296 		msleep(50);
297 		status = ap->ops->sff_check_status(ap);
298 	}
299 
300 	if (status == 0xff)
301 		return -ENODEV;
302 
303 	if (status & ATA_BUSY) {
304 		ata_port_printk(ap, KERN_ERR, "port failed to respond "
305 				"(%lu secs, Status 0x%x)\n",
306 				tmout / HZ, status);
307 		return -EBUSY;
308 	}
309 
310 	return 0;
311 }
312 
313 static int ata_sff_check_ready(struct ata_link *link)
314 {
315 	u8 status = link->ap->ops->sff_check_status(link->ap);
316 
317 	return ata_check_ready(status);
318 }
319 
320 /**
321  *	ata_sff_wait_ready - sleep until BSY clears, or timeout
322  *	@link: SFF link to wait ready status for
323  *	@deadline: deadline jiffies for the operation
324  *
325  *	Sleep until ATA Status register bit BSY clears, or timeout
326  *	occurs.
327  *
328  *	LOCKING:
329  *	Kernel thread context (may sleep).
330  *
331  *	RETURNS:
332  *	0 on success, -errno otherwise.
333  */
334 int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline)
335 {
336 	return ata_wait_ready(link, deadline, ata_sff_check_ready);
337 }
338 
339 /**
340  *	ata_sff_dev_select - Select device 0/1 on ATA bus
341  *	@ap: ATA channel to manipulate
342  *	@device: ATA device (numbered from zero) to select
343  *
344  *	Use the method defined in the ATA specification to
345  *	make either device 0, or device 1, active on the
346  *	ATA channel.  Works with both PIO and MMIO.
347  *
348  *	May be used as the dev_select() entry in ata_port_operations.
349  *
350  *	LOCKING:
351  *	caller.
352  */
353 void ata_sff_dev_select(struct ata_port *ap, unsigned int device)
354 {
355 	u8 tmp;
356 
357 	if (device == 0)
358 		tmp = ATA_DEVICE_OBS;
359 	else
360 		tmp = ATA_DEVICE_OBS | ATA_DEV1;
361 
362 	iowrite8(tmp, ap->ioaddr.device_addr);
363 	ata_sff_pause(ap);	/* needed; also flushes, for mmio */
364 }
365 
366 /**
367  *	ata_dev_select - Select device 0/1 on ATA bus
368  *	@ap: ATA channel to manipulate
369  *	@device: ATA device (numbered from zero) to select
370  *	@wait: non-zero to wait for Status register BSY bit to clear
371  *	@can_sleep: non-zero if context allows sleeping
372  *
373  *	Use the method defined in the ATA specification to
374  *	make either device 0, or device 1, active on the
375  *	ATA channel.
376  *
377  *	This is a high-level version of ata_sff_dev_select(), which
378  *	additionally provides the services of inserting the proper
379  *	pauses and status polling, where needed.
380  *
381  *	LOCKING:
382  *	caller.
383  */
384 void ata_dev_select(struct ata_port *ap, unsigned int device,
385 			   unsigned int wait, unsigned int can_sleep)
386 {
387 	if (ata_msg_probe(ap))
388 		ata_port_printk(ap, KERN_INFO, "ata_dev_select: ENTER, "
389 				"device %u, wait %u\n", device, wait);
390 
391 	if (wait)
392 		ata_wait_idle(ap);
393 
394 	ap->ops->sff_dev_select(ap, device);
395 
396 	if (wait) {
397 		if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI)
398 			msleep(150);
399 		ata_wait_idle(ap);
400 	}
401 }
402 
403 /**
404  *	ata_sff_irq_on - Enable interrupts on a port.
405  *	@ap: Port on which interrupts are enabled.
406  *
407  *	Enable interrupts on a legacy IDE device using MMIO or PIO,
408  *	wait for idle, clear any pending interrupts.
409  *
410  *	LOCKING:
411  *	Inherited from caller.
412  */
413 u8 ata_sff_irq_on(struct ata_port *ap)
414 {
415 	struct ata_ioports *ioaddr = &ap->ioaddr;
416 	u8 tmp;
417 
418 	ap->ctl &= ~ATA_NIEN;
419 	ap->last_ctl = ap->ctl;
420 
421 	if (ioaddr->ctl_addr)
422 		iowrite8(ap->ctl, ioaddr->ctl_addr);
423 	tmp = ata_wait_idle(ap);
424 
425 	ap->ops->sff_irq_clear(ap);
426 
427 	return tmp;
428 }
429 
430 /**
431  *	ata_sff_irq_clear - Clear PCI IDE BMDMA interrupt.
432  *	@ap: Port associated with this ATA transaction.
433  *
434  *	Clear interrupt and error flags in DMA status register.
435  *
436  *	May be used as the irq_clear() entry in ata_port_operations.
437  *
438  *	LOCKING:
439  *	spin_lock_irqsave(host lock)
440  */
441 void ata_sff_irq_clear(struct ata_port *ap)
442 {
443 	void __iomem *mmio = ap->ioaddr.bmdma_addr;
444 
445 	if (!mmio)
446 		return;
447 
448 	iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS);
449 }
450 
451 /**
452  *	ata_sff_tf_load - send taskfile registers to host controller
453  *	@ap: Port to which output is sent
454  *	@tf: ATA taskfile register set
455  *
456  *	Outputs ATA taskfile to standard ATA host controller.
457  *
458  *	LOCKING:
459  *	Inherited from caller.
460  */
461 void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
462 {
463 	struct ata_ioports *ioaddr = &ap->ioaddr;
464 	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
465 
466 	if (tf->ctl != ap->last_ctl) {
467 		if (ioaddr->ctl_addr)
468 			iowrite8(tf->ctl, ioaddr->ctl_addr);
469 		ap->last_ctl = tf->ctl;
470 		ata_wait_idle(ap);
471 	}
472 
473 	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
474 		WARN_ON(!ioaddr->ctl_addr);
475 		iowrite8(tf->hob_feature, ioaddr->feature_addr);
476 		iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
477 		iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
478 		iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
479 		iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
480 		VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
481 			tf->hob_feature,
482 			tf->hob_nsect,
483 			tf->hob_lbal,
484 			tf->hob_lbam,
485 			tf->hob_lbah);
486 	}
487 
488 	if (is_addr) {
489 		iowrite8(tf->feature, ioaddr->feature_addr);
490 		iowrite8(tf->nsect, ioaddr->nsect_addr);
491 		iowrite8(tf->lbal, ioaddr->lbal_addr);
492 		iowrite8(tf->lbam, ioaddr->lbam_addr);
493 		iowrite8(tf->lbah, ioaddr->lbah_addr);
494 		VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
495 			tf->feature,
496 			tf->nsect,
497 			tf->lbal,
498 			tf->lbam,
499 			tf->lbah);
500 	}
501 
502 	if (tf->flags & ATA_TFLAG_DEVICE) {
503 		iowrite8(tf->device, ioaddr->device_addr);
504 		VPRINTK("device 0x%X\n", tf->device);
505 	}
506 
507 	ata_wait_idle(ap);
508 }
509 
510 /**
511  *	ata_sff_tf_read - input device's ATA taskfile shadow registers
512  *	@ap: Port from which input is read
513  *	@tf: ATA taskfile register set for storing input
514  *
515  *	Reads ATA taskfile registers for currently-selected device
516  *	into @tf. Assumes the device has a fully SFF compliant task file
517  *	layout and behaviour. If you device does not (eg has a different
518  *	status method) then you will need to provide a replacement tf_read
519  *
520  *	LOCKING:
521  *	Inherited from caller.
522  */
523 void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
524 {
525 	struct ata_ioports *ioaddr = &ap->ioaddr;
526 
527 	tf->command = ata_sff_check_status(ap);
528 	tf->feature = ioread8(ioaddr->error_addr);
529 	tf->nsect = ioread8(ioaddr->nsect_addr);
530 	tf->lbal = ioread8(ioaddr->lbal_addr);
531 	tf->lbam = ioread8(ioaddr->lbam_addr);
532 	tf->lbah = ioread8(ioaddr->lbah_addr);
533 	tf->device = ioread8(ioaddr->device_addr);
534 
535 	if (tf->flags & ATA_TFLAG_LBA48) {
536 		if (likely(ioaddr->ctl_addr)) {
537 			iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
538 			tf->hob_feature = ioread8(ioaddr->error_addr);
539 			tf->hob_nsect = ioread8(ioaddr->nsect_addr);
540 			tf->hob_lbal = ioread8(ioaddr->lbal_addr);
541 			tf->hob_lbam = ioread8(ioaddr->lbam_addr);
542 			tf->hob_lbah = ioread8(ioaddr->lbah_addr);
543 			iowrite8(tf->ctl, ioaddr->ctl_addr);
544 			ap->last_ctl = tf->ctl;
545 		} else
546 			WARN_ON(1);
547 	}
548 }
549 
550 /**
551  *	ata_sff_exec_command - issue ATA command to host controller
552  *	@ap: port to which command is being issued
553  *	@tf: ATA taskfile register set
554  *
555  *	Issues ATA command, with proper synchronization with interrupt
556  *	handler / other threads.
557  *
558  *	LOCKING:
559  *	spin_lock_irqsave(host lock)
560  */
561 void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
562 {
563 	DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
564 
565 	iowrite8(tf->command, ap->ioaddr.command_addr);
566 	ata_sff_pause(ap);
567 }
568 
569 /**
570  *	ata_tf_to_host - issue ATA taskfile to host controller
571  *	@ap: port to which command is being issued
572  *	@tf: ATA taskfile register set
573  *
574  *	Issues ATA taskfile register set to ATA host controller,
575  *	with proper synchronization with interrupt handler and
576  *	other threads.
577  *
578  *	LOCKING:
579  *	spin_lock_irqsave(host lock)
580  */
581 static inline void ata_tf_to_host(struct ata_port *ap,
582 				  const struct ata_taskfile *tf)
583 {
584 	ap->ops->sff_tf_load(ap, tf);
585 	ap->ops->sff_exec_command(ap, tf);
586 }
587 
588 /**
589  *	ata_sff_data_xfer - Transfer data by PIO
590  *	@dev: device to target
591  *	@buf: data buffer
592  *	@buflen: buffer length
593  *	@rw: read/write
594  *
595  *	Transfer data from/to the device data register by PIO.
596  *
597  *	LOCKING:
598  *	Inherited from caller.
599  *
600  *	RETURNS:
601  *	Bytes consumed.
602  */
603 unsigned int ata_sff_data_xfer(struct ata_device *dev, unsigned char *buf,
604 			       unsigned int buflen, int rw)
605 {
606 	struct ata_port *ap = dev->link->ap;
607 	void __iomem *data_addr = ap->ioaddr.data_addr;
608 	unsigned int words = buflen >> 1;
609 
610 	/* Transfer multiple of 2 bytes */
611 	if (rw == READ)
612 		ioread16_rep(data_addr, buf, words);
613 	else
614 		iowrite16_rep(data_addr, buf, words);
615 
616 	/* Transfer trailing 1 byte, if any. */
617 	if (unlikely(buflen & 0x01)) {
618 		__le16 align_buf[1] = { 0 };
619 		unsigned char *trailing_buf = buf + buflen - 1;
620 
621 		if (rw == READ) {
622 			align_buf[0] = cpu_to_le16(ioread16(data_addr));
623 			memcpy(trailing_buf, align_buf, 1);
624 		} else {
625 			memcpy(align_buf, trailing_buf, 1);
626 			iowrite16(le16_to_cpu(align_buf[0]), data_addr);
627 		}
628 		words++;
629 	}
630 
631 	return words << 1;
632 }
633 
634 /**
635  *	ata_sff_data_xfer_noirq - Transfer data by PIO
636  *	@dev: device to target
637  *	@buf: data buffer
638  *	@buflen: buffer length
639  *	@rw: read/write
640  *
641  *	Transfer data from/to the device data register by PIO. Do the
642  *	transfer with interrupts disabled.
643  *
644  *	LOCKING:
645  *	Inherited from caller.
646  *
647  *	RETURNS:
648  *	Bytes consumed.
649  */
650 unsigned int ata_sff_data_xfer_noirq(struct ata_device *dev, unsigned char *buf,
651 				     unsigned int buflen, int rw)
652 {
653 	unsigned long flags;
654 	unsigned int consumed;
655 
656 	local_irq_save(flags);
657 	consumed = ata_sff_data_xfer(dev, buf, buflen, rw);
658 	local_irq_restore(flags);
659 
660 	return consumed;
661 }
662 
663 /**
664  *	ata_pio_sector - Transfer a sector of data.
665  *	@qc: Command on going
666  *
667  *	Transfer qc->sect_size bytes of data from/to the ATA device.
668  *
669  *	LOCKING:
670  *	Inherited from caller.
671  */
672 static void ata_pio_sector(struct ata_queued_cmd *qc)
673 {
674 	int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
675 	struct ata_port *ap = qc->ap;
676 	struct page *page;
677 	unsigned int offset;
678 	unsigned char *buf;
679 
680 	if (qc->curbytes == qc->nbytes - qc->sect_size)
681 		ap->hsm_task_state = HSM_ST_LAST;
682 
683 	page = sg_page(qc->cursg);
684 	offset = qc->cursg->offset + qc->cursg_ofs;
685 
686 	/* get the current page and offset */
687 	page = nth_page(page, (offset >> PAGE_SHIFT));
688 	offset %= PAGE_SIZE;
689 
690 	DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
691 
692 	if (PageHighMem(page)) {
693 		unsigned long flags;
694 
695 		/* FIXME: use a bounce buffer */
696 		local_irq_save(flags);
697 		buf = kmap_atomic(page, KM_IRQ0);
698 
699 		/* do the actual data transfer */
700 		ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
701 				       do_write);
702 
703 		kunmap_atomic(buf, KM_IRQ0);
704 		local_irq_restore(flags);
705 	} else {
706 		buf = page_address(page);
707 		ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
708 				       do_write);
709 	}
710 
711 	qc->curbytes += qc->sect_size;
712 	qc->cursg_ofs += qc->sect_size;
713 
714 	if (qc->cursg_ofs == qc->cursg->length) {
715 		qc->cursg = sg_next(qc->cursg);
716 		qc->cursg_ofs = 0;
717 	}
718 }
719 
720 /**
721  *	ata_pio_sectors - Transfer one or many sectors.
722  *	@qc: Command on going
723  *
724  *	Transfer one or many sectors of data from/to the
725  *	ATA device for the DRQ request.
726  *
727  *	LOCKING:
728  *	Inherited from caller.
729  */
730 static void ata_pio_sectors(struct ata_queued_cmd *qc)
731 {
732 	if (is_multi_taskfile(&qc->tf)) {
733 		/* READ/WRITE MULTIPLE */
734 		unsigned int nsect;
735 
736 		WARN_ON(qc->dev->multi_count == 0);
737 
738 		nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size,
739 			    qc->dev->multi_count);
740 		while (nsect--)
741 			ata_pio_sector(qc);
742 	} else
743 		ata_pio_sector(qc);
744 
745 	ata_sff_altstatus(qc->ap); /* flush */
746 }
747 
748 /**
749  *	atapi_send_cdb - Write CDB bytes to hardware
750  *	@ap: Port to which ATAPI device is attached.
751  *	@qc: Taskfile currently active
752  *
753  *	When device has indicated its readiness to accept
754  *	a CDB, this function is called.  Send the CDB.
755  *
756  *	LOCKING:
757  *	caller.
758  */
759 static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
760 {
761 	/* send SCSI cdb */
762 	DPRINTK("send cdb\n");
763 	WARN_ON(qc->dev->cdb_len < 12);
764 
765 	ap->ops->sff_data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1);
766 	ata_sff_altstatus(ap); /* flush */
767 
768 	switch (qc->tf.protocol) {
769 	case ATAPI_PROT_PIO:
770 		ap->hsm_task_state = HSM_ST;
771 		break;
772 	case ATAPI_PROT_NODATA:
773 		ap->hsm_task_state = HSM_ST_LAST;
774 		break;
775 	case ATAPI_PROT_DMA:
776 		ap->hsm_task_state = HSM_ST_LAST;
777 		/* initiate bmdma */
778 		ap->ops->bmdma_start(qc);
779 		break;
780 	}
781 }
782 
783 /**
784  *	__atapi_pio_bytes - Transfer data from/to the ATAPI device.
785  *	@qc: Command on going
786  *	@bytes: number of bytes
787  *
788  *	Transfer Transfer data from/to the ATAPI device.
789  *
790  *	LOCKING:
791  *	Inherited from caller.
792  *
793  */
794 static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
795 {
796 	int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ;
797 	struct ata_port *ap = qc->ap;
798 	struct ata_device *dev = qc->dev;
799 	struct ata_eh_info *ehi = &dev->link->eh_info;
800 	struct scatterlist *sg;
801 	struct page *page;
802 	unsigned char *buf;
803 	unsigned int offset, count, consumed;
804 
805 next_sg:
806 	sg = qc->cursg;
807 	if (unlikely(!sg)) {
808 		ata_ehi_push_desc(ehi, "unexpected or too much trailing data "
809 				  "buf=%u cur=%u bytes=%u",
810 				  qc->nbytes, qc->curbytes, bytes);
811 		return -1;
812 	}
813 
814 	page = sg_page(sg);
815 	offset = sg->offset + qc->cursg_ofs;
816 
817 	/* get the current page and offset */
818 	page = nth_page(page, (offset >> PAGE_SHIFT));
819 	offset %= PAGE_SIZE;
820 
821 	/* don't overrun current sg */
822 	count = min(sg->length - qc->cursg_ofs, bytes);
823 
824 	/* don't cross page boundaries */
825 	count = min(count, (unsigned int)PAGE_SIZE - offset);
826 
827 	DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
828 
829 	if (PageHighMem(page)) {
830 		unsigned long flags;
831 
832 		/* FIXME: use bounce buffer */
833 		local_irq_save(flags);
834 		buf = kmap_atomic(page, KM_IRQ0);
835 
836 		/* do the actual data transfer */
837 		consumed = ap->ops->sff_data_xfer(dev,  buf + offset, count, rw);
838 
839 		kunmap_atomic(buf, KM_IRQ0);
840 		local_irq_restore(flags);
841 	} else {
842 		buf = page_address(page);
843 		consumed = ap->ops->sff_data_xfer(dev,  buf + offset, count, rw);
844 	}
845 
846 	bytes -= min(bytes, consumed);
847 	qc->curbytes += count;
848 	qc->cursg_ofs += count;
849 
850 	if (qc->cursg_ofs == sg->length) {
851 		qc->cursg = sg_next(qc->cursg);
852 		qc->cursg_ofs = 0;
853 	}
854 
855 	/* consumed can be larger than count only for the last transfer */
856 	WARN_ON(qc->cursg && count != consumed);
857 
858 	if (bytes)
859 		goto next_sg;
860 	return 0;
861 }
862 
863 /**
864  *	atapi_pio_bytes - Transfer data from/to the ATAPI device.
865  *	@qc: Command on going
866  *
867  *	Transfer Transfer data from/to the ATAPI device.
868  *
869  *	LOCKING:
870  *	Inherited from caller.
871  */
872 static void atapi_pio_bytes(struct ata_queued_cmd *qc)
873 {
874 	struct ata_port *ap = qc->ap;
875 	struct ata_device *dev = qc->dev;
876 	struct ata_eh_info *ehi = &dev->link->eh_info;
877 	unsigned int ireason, bc_lo, bc_hi, bytes;
878 	int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
879 
880 	/* Abuse qc->result_tf for temp storage of intermediate TF
881 	 * here to save some kernel stack usage.
882 	 * For normal completion, qc->result_tf is not relevant. For
883 	 * error, qc->result_tf is later overwritten by ata_qc_complete().
884 	 * So, the correctness of qc->result_tf is not affected.
885 	 */
886 	ap->ops->sff_tf_read(ap, &qc->result_tf);
887 	ireason = qc->result_tf.nsect;
888 	bc_lo = qc->result_tf.lbam;
889 	bc_hi = qc->result_tf.lbah;
890 	bytes = (bc_hi << 8) | bc_lo;
891 
892 	/* shall be cleared to zero, indicating xfer of data */
893 	if (unlikely(ireason & (1 << 0)))
894 		goto atapi_check;
895 
896 	/* make sure transfer direction matches expected */
897 	i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
898 	if (unlikely(do_write != i_write))
899 		goto atapi_check;
900 
901 	if (unlikely(!bytes))
902 		goto atapi_check;
903 
904 	VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes);
905 
906 	if (unlikely(__atapi_pio_bytes(qc, bytes)))
907 		goto err_out;
908 	ata_sff_altstatus(ap); /* flush */
909 
910 	return;
911 
912  atapi_check:
913 	ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)",
914 			  ireason, bytes);
915  err_out:
916 	qc->err_mask |= AC_ERR_HSM;
917 	ap->hsm_task_state = HSM_ST_ERR;
918 }
919 
920 /**
921  *	ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
922  *	@ap: the target ata_port
923  *	@qc: qc on going
924  *
925  *	RETURNS:
926  *	1 if ok in workqueue, 0 otherwise.
927  */
928 static inline int ata_hsm_ok_in_wq(struct ata_port *ap, struct ata_queued_cmd *qc)
929 {
930 	if (qc->tf.flags & ATA_TFLAG_POLLING)
931 		return 1;
932 
933 	if (ap->hsm_task_state == HSM_ST_FIRST) {
934 		if (qc->tf.protocol == ATA_PROT_PIO &&
935 		    (qc->tf.flags & ATA_TFLAG_WRITE))
936 		    return 1;
937 
938 		if (ata_is_atapi(qc->tf.protocol) &&
939 		    !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
940 			return 1;
941 	}
942 
943 	return 0;
944 }
945 
946 /**
947  *	ata_hsm_qc_complete - finish a qc running on standard HSM
948  *	@qc: Command to complete
949  *	@in_wq: 1 if called from workqueue, 0 otherwise
950  *
951  *	Finish @qc which is running on standard HSM.
952  *
953  *	LOCKING:
954  *	If @in_wq is zero, spin_lock_irqsave(host lock).
955  *	Otherwise, none on entry and grabs host lock.
956  */
957 static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
958 {
959 	struct ata_port *ap = qc->ap;
960 	unsigned long flags;
961 
962 	if (ap->ops->error_handler) {
963 		if (in_wq) {
964 			spin_lock_irqsave(ap->lock, flags);
965 
966 			/* EH might have kicked in while host lock is
967 			 * released.
968 			 */
969 			qc = ata_qc_from_tag(ap, qc->tag);
970 			if (qc) {
971 				if (likely(!(qc->err_mask & AC_ERR_HSM))) {
972 					ap->ops->sff_irq_on(ap);
973 					ata_qc_complete(qc);
974 				} else
975 					ata_port_freeze(ap);
976 			}
977 
978 			spin_unlock_irqrestore(ap->lock, flags);
979 		} else {
980 			if (likely(!(qc->err_mask & AC_ERR_HSM)))
981 				ata_qc_complete(qc);
982 			else
983 				ata_port_freeze(ap);
984 		}
985 	} else {
986 		if (in_wq) {
987 			spin_lock_irqsave(ap->lock, flags);
988 			ap->ops->sff_irq_on(ap);
989 			ata_qc_complete(qc);
990 			spin_unlock_irqrestore(ap->lock, flags);
991 		} else
992 			ata_qc_complete(qc);
993 	}
994 }
995 
996 /**
997  *	ata_sff_hsm_move - move the HSM to the next state.
998  *	@ap: the target ata_port
999  *	@qc: qc on going
1000  *	@status: current device status
1001  *	@in_wq: 1 if called from workqueue, 0 otherwise
1002  *
1003  *	RETURNS:
1004  *	1 when poll next status needed, 0 otherwise.
1005  */
1006 int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
1007 		     u8 status, int in_wq)
1008 {
1009 	unsigned long flags = 0;
1010 	int poll_next;
1011 
1012 	WARN_ON((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
1013 
1014 	/* Make sure ata_sff_qc_issue() does not throw things
1015 	 * like DMA polling into the workqueue. Notice that
1016 	 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
1017 	 */
1018 	WARN_ON(in_wq != ata_hsm_ok_in_wq(ap, qc));
1019 
1020 fsm_start:
1021 	DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n",
1022 		ap->print_id, qc->tf.protocol, ap->hsm_task_state, status);
1023 
1024 	switch (ap->hsm_task_state) {
1025 	case HSM_ST_FIRST:
1026 		/* Send first data block or PACKET CDB */
1027 
1028 		/* If polling, we will stay in the work queue after
1029 		 * sending the data. Otherwise, interrupt handler
1030 		 * takes over after sending the data.
1031 		 */
1032 		poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
1033 
1034 		/* check device status */
1035 		if (unlikely((status & ATA_DRQ) == 0)) {
1036 			/* handle BSY=0, DRQ=0 as error */
1037 			if (likely(status & (ATA_ERR | ATA_DF)))
1038 				/* device stops HSM for abort/error */
1039 				qc->err_mask |= AC_ERR_DEV;
1040 			else
1041 				/* HSM violation. Let EH handle this */
1042 				qc->err_mask |= AC_ERR_HSM;
1043 
1044 			ap->hsm_task_state = HSM_ST_ERR;
1045 			goto fsm_start;
1046 		}
1047 
1048 		/* Device should not ask for data transfer (DRQ=1)
1049 		 * when it finds something wrong.
1050 		 * We ignore DRQ here and stop the HSM by
1051 		 * changing hsm_task_state to HSM_ST_ERR and
1052 		 * let the EH abort the command or reset the device.
1053 		 */
1054 		if (unlikely(status & (ATA_ERR | ATA_DF))) {
1055 			/* Some ATAPI tape drives forget to clear the ERR bit
1056 			 * when doing the next command (mostly request sense).
1057 			 * We ignore ERR here to workaround and proceed sending
1058 			 * the CDB.
1059 			 */
1060 			if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
1061 				ata_port_printk(ap, KERN_WARNING,
1062 						"DRQ=1 with device error, "
1063 						"dev_stat 0x%X\n", status);
1064 				qc->err_mask |= AC_ERR_HSM;
1065 				ap->hsm_task_state = HSM_ST_ERR;
1066 				goto fsm_start;
1067 			}
1068 		}
1069 
1070 		/* Send the CDB (atapi) or the first data block (ata pio out).
1071 		 * During the state transition, interrupt handler shouldn't
1072 		 * be invoked before the data transfer is complete and
1073 		 * hsm_task_state is changed. Hence, the following locking.
1074 		 */
1075 		if (in_wq)
1076 			spin_lock_irqsave(ap->lock, flags);
1077 
1078 		if (qc->tf.protocol == ATA_PROT_PIO) {
1079 			/* PIO data out protocol.
1080 			 * send first data block.
1081 			 */
1082 
1083 			/* ata_pio_sectors() might change the state
1084 			 * to HSM_ST_LAST. so, the state is changed here
1085 			 * before ata_pio_sectors().
1086 			 */
1087 			ap->hsm_task_state = HSM_ST;
1088 			ata_pio_sectors(qc);
1089 		} else
1090 			/* send CDB */
1091 			atapi_send_cdb(ap, qc);
1092 
1093 		if (in_wq)
1094 			spin_unlock_irqrestore(ap->lock, flags);
1095 
1096 		/* if polling, ata_pio_task() handles the rest.
1097 		 * otherwise, interrupt handler takes over from here.
1098 		 */
1099 		break;
1100 
1101 	case HSM_ST:
1102 		/* complete command or read/write the data register */
1103 		if (qc->tf.protocol == ATAPI_PROT_PIO) {
1104 			/* ATAPI PIO protocol */
1105 			if ((status & ATA_DRQ) == 0) {
1106 				/* No more data to transfer or device error.
1107 				 * Device error will be tagged in HSM_ST_LAST.
1108 				 */
1109 				ap->hsm_task_state = HSM_ST_LAST;
1110 				goto fsm_start;
1111 			}
1112 
1113 			/* Device should not ask for data transfer (DRQ=1)
1114 			 * when it finds something wrong.
1115 			 * We ignore DRQ here and stop the HSM by
1116 			 * changing hsm_task_state to HSM_ST_ERR and
1117 			 * let the EH abort the command or reset the device.
1118 			 */
1119 			if (unlikely(status & (ATA_ERR | ATA_DF))) {
1120 				ata_port_printk(ap, KERN_WARNING, "DRQ=1 with "
1121 						"device error, dev_stat 0x%X\n",
1122 						status);
1123 				qc->err_mask |= AC_ERR_HSM;
1124 				ap->hsm_task_state = HSM_ST_ERR;
1125 				goto fsm_start;
1126 			}
1127 
1128 			atapi_pio_bytes(qc);
1129 
1130 			if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
1131 				/* bad ireason reported by device */
1132 				goto fsm_start;
1133 
1134 		} else {
1135 			/* ATA PIO protocol */
1136 			if (unlikely((status & ATA_DRQ) == 0)) {
1137 				/* handle BSY=0, DRQ=0 as error */
1138 				if (likely(status & (ATA_ERR | ATA_DF)))
1139 					/* device stops HSM for abort/error */
1140 					qc->err_mask |= AC_ERR_DEV;
1141 				else
1142 					/* HSM violation. Let EH handle this.
1143 					 * Phantom devices also trigger this
1144 					 * condition.  Mark hint.
1145 					 */
1146 					qc->err_mask |= AC_ERR_HSM |
1147 							AC_ERR_NODEV_HINT;
1148 
1149 				ap->hsm_task_state = HSM_ST_ERR;
1150 				goto fsm_start;
1151 			}
1152 
1153 			/* For PIO reads, some devices may ask for
1154 			 * data transfer (DRQ=1) alone with ERR=1.
1155 			 * We respect DRQ here and transfer one
1156 			 * block of junk data before changing the
1157 			 * hsm_task_state to HSM_ST_ERR.
1158 			 *
1159 			 * For PIO writes, ERR=1 DRQ=1 doesn't make
1160 			 * sense since the data block has been
1161 			 * transferred to the device.
1162 			 */
1163 			if (unlikely(status & (ATA_ERR | ATA_DF))) {
1164 				/* data might be corrputed */
1165 				qc->err_mask |= AC_ERR_DEV;
1166 
1167 				if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
1168 					ata_pio_sectors(qc);
1169 					status = ata_wait_idle(ap);
1170 				}
1171 
1172 				if (status & (ATA_BUSY | ATA_DRQ))
1173 					qc->err_mask |= AC_ERR_HSM;
1174 
1175 				/* ata_pio_sectors() might change the
1176 				 * state to HSM_ST_LAST. so, the state
1177 				 * is changed after ata_pio_sectors().
1178 				 */
1179 				ap->hsm_task_state = HSM_ST_ERR;
1180 				goto fsm_start;
1181 			}
1182 
1183 			ata_pio_sectors(qc);
1184 
1185 			if (ap->hsm_task_state == HSM_ST_LAST &&
1186 			    (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
1187 				/* all data read */
1188 				status = ata_wait_idle(ap);
1189 				goto fsm_start;
1190 			}
1191 		}
1192 
1193 		poll_next = 1;
1194 		break;
1195 
1196 	case HSM_ST_LAST:
1197 		if (unlikely(!ata_ok(status))) {
1198 			qc->err_mask |= __ac_err_mask(status);
1199 			ap->hsm_task_state = HSM_ST_ERR;
1200 			goto fsm_start;
1201 		}
1202 
1203 		/* no more data to transfer */
1204 		DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n",
1205 			ap->print_id, qc->dev->devno, status);
1206 
1207 		WARN_ON(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM));
1208 
1209 		ap->hsm_task_state = HSM_ST_IDLE;
1210 
1211 		/* complete taskfile transaction */
1212 		ata_hsm_qc_complete(qc, in_wq);
1213 
1214 		poll_next = 0;
1215 		break;
1216 
1217 	case HSM_ST_ERR:
1218 		/* make sure qc->err_mask is available to
1219 		 * know what's wrong and recover
1220 		 */
1221 		WARN_ON(!(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM)));
1222 
1223 		ap->hsm_task_state = HSM_ST_IDLE;
1224 
1225 		/* complete taskfile transaction */
1226 		ata_hsm_qc_complete(qc, in_wq);
1227 
1228 		poll_next = 0;
1229 		break;
1230 	default:
1231 		poll_next = 0;
1232 		BUG();
1233 	}
1234 
1235 	return poll_next;
1236 }
1237 
1238 void ata_pio_task(struct work_struct *work)
1239 {
1240 	struct ata_port *ap =
1241 		container_of(work, struct ata_port, port_task.work);
1242 	struct ata_queued_cmd *qc = ap->port_task_data;
1243 	u8 status;
1244 	int poll_next;
1245 
1246 fsm_start:
1247 	WARN_ON(ap->hsm_task_state == HSM_ST_IDLE);
1248 
1249 	/*
1250 	 * This is purely heuristic.  This is a fast path.
1251 	 * Sometimes when we enter, BSY will be cleared in
1252 	 * a chk-status or two.  If not, the drive is probably seeking
1253 	 * or something.  Snooze for a couple msecs, then
1254 	 * chk-status again.  If still busy, queue delayed work.
1255 	 */
1256 	status = ata_sff_busy_wait(ap, ATA_BUSY, 5);
1257 	if (status & ATA_BUSY) {
1258 		msleep(2);
1259 		status = ata_sff_busy_wait(ap, ATA_BUSY, 10);
1260 		if (status & ATA_BUSY) {
1261 			ata_pio_queue_task(ap, qc, ATA_SHORT_PAUSE);
1262 			return;
1263 		}
1264 	}
1265 
1266 	/* move the HSM */
1267 	poll_next = ata_sff_hsm_move(ap, qc, status, 1);
1268 
1269 	/* another command or interrupt handler
1270 	 * may be running at this point.
1271 	 */
1272 	if (poll_next)
1273 		goto fsm_start;
1274 }
1275 
1276 /**
1277  *	ata_sff_qc_issue - issue taskfile to device in proto-dependent manner
1278  *	@qc: command to issue to device
1279  *
1280  *	Using various libata functions and hooks, this function
1281  *	starts an ATA command.  ATA commands are grouped into
1282  *	classes called "protocols", and issuing each type of protocol
1283  *	is slightly different.
1284  *
1285  *	May be used as the qc_issue() entry in ata_port_operations.
1286  *
1287  *	LOCKING:
1288  *	spin_lock_irqsave(host lock)
1289  *
1290  *	RETURNS:
1291  *	Zero on success, AC_ERR_* mask on failure
1292  */
1293 unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc)
1294 {
1295 	struct ata_port *ap = qc->ap;
1296 
1297 	/* Use polling pio if the LLD doesn't handle
1298 	 * interrupt driven pio and atapi CDB interrupt.
1299 	 */
1300 	if (ap->flags & ATA_FLAG_PIO_POLLING) {
1301 		switch (qc->tf.protocol) {
1302 		case ATA_PROT_PIO:
1303 		case ATA_PROT_NODATA:
1304 		case ATAPI_PROT_PIO:
1305 		case ATAPI_PROT_NODATA:
1306 			qc->tf.flags |= ATA_TFLAG_POLLING;
1307 			break;
1308 		case ATAPI_PROT_DMA:
1309 			if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
1310 				/* see ata_dma_blacklisted() */
1311 				BUG();
1312 			break;
1313 		default:
1314 			break;
1315 		}
1316 	}
1317 
1318 	/* select the device */
1319 	ata_dev_select(ap, qc->dev->devno, 1, 0);
1320 
1321 	/* start the command */
1322 	switch (qc->tf.protocol) {
1323 	case ATA_PROT_NODATA:
1324 		if (qc->tf.flags & ATA_TFLAG_POLLING)
1325 			ata_qc_set_polling(qc);
1326 
1327 		ata_tf_to_host(ap, &qc->tf);
1328 		ap->hsm_task_state = HSM_ST_LAST;
1329 
1330 		if (qc->tf.flags & ATA_TFLAG_POLLING)
1331 			ata_pio_queue_task(ap, qc, 0);
1332 
1333 		break;
1334 
1335 	case ATA_PROT_DMA:
1336 		WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
1337 
1338 		ap->ops->sff_tf_load(ap, &qc->tf);  /* load tf registers */
1339 		ap->ops->bmdma_setup(qc);	    /* set up bmdma */
1340 		ap->ops->bmdma_start(qc);	    /* initiate bmdma */
1341 		ap->hsm_task_state = HSM_ST_LAST;
1342 		break;
1343 
1344 	case ATA_PROT_PIO:
1345 		if (qc->tf.flags & ATA_TFLAG_POLLING)
1346 			ata_qc_set_polling(qc);
1347 
1348 		ata_tf_to_host(ap, &qc->tf);
1349 
1350 		if (qc->tf.flags & ATA_TFLAG_WRITE) {
1351 			/* PIO data out protocol */
1352 			ap->hsm_task_state = HSM_ST_FIRST;
1353 			ata_pio_queue_task(ap, qc, 0);
1354 
1355 			/* always send first data block using
1356 			 * the ata_pio_task() codepath.
1357 			 */
1358 		} else {
1359 			/* PIO data in protocol */
1360 			ap->hsm_task_state = HSM_ST;
1361 
1362 			if (qc->tf.flags & ATA_TFLAG_POLLING)
1363 				ata_pio_queue_task(ap, qc, 0);
1364 
1365 			/* if polling, ata_pio_task() handles the rest.
1366 			 * otherwise, interrupt handler takes over from here.
1367 			 */
1368 		}
1369 
1370 		break;
1371 
1372 	case ATAPI_PROT_PIO:
1373 	case ATAPI_PROT_NODATA:
1374 		if (qc->tf.flags & ATA_TFLAG_POLLING)
1375 			ata_qc_set_polling(qc);
1376 
1377 		ata_tf_to_host(ap, &qc->tf);
1378 
1379 		ap->hsm_task_state = HSM_ST_FIRST;
1380 
1381 		/* send cdb by polling if no cdb interrupt */
1382 		if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
1383 		    (qc->tf.flags & ATA_TFLAG_POLLING))
1384 			ata_pio_queue_task(ap, qc, 0);
1385 		break;
1386 
1387 	case ATAPI_PROT_DMA:
1388 		WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
1389 
1390 		ap->ops->sff_tf_load(ap, &qc->tf);  /* load tf registers */
1391 		ap->ops->bmdma_setup(qc);	    /* set up bmdma */
1392 		ap->hsm_task_state = HSM_ST_FIRST;
1393 
1394 		/* send cdb by polling if no cdb interrupt */
1395 		if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1396 			ata_pio_queue_task(ap, qc, 0);
1397 		break;
1398 
1399 	default:
1400 		WARN_ON(1);
1401 		return AC_ERR_SYSTEM;
1402 	}
1403 
1404 	return 0;
1405 }
1406 
1407 /**
1408  *	ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read
1409  *	@qc: qc to fill result TF for
1410  *
1411  *	@qc is finished and result TF needs to be filled.  Fill it
1412  *	using ->sff_tf_read.
1413  *
1414  *	LOCKING:
1415  *	spin_lock_irqsave(host lock)
1416  *
1417  *	RETURNS:
1418  *	true indicating that result TF is successfully filled.
1419  */
1420 bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc)
1421 {
1422 	qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf);
1423 	return true;
1424 }
1425 
1426 /**
1427  *	ata_sff_host_intr - Handle host interrupt for given (port, task)
1428  *	@ap: Port on which interrupt arrived (possibly...)
1429  *	@qc: Taskfile currently active in engine
1430  *
1431  *	Handle host interrupt for given queued command.  Currently,
1432  *	only DMA interrupts are handled.  All other commands are
1433  *	handled via polling with interrupts disabled (nIEN bit).
1434  *
1435  *	LOCKING:
1436  *	spin_lock_irqsave(host lock)
1437  *
1438  *	RETURNS:
1439  *	One if interrupt was handled, zero if not (shared irq).
1440  */
1441 inline unsigned int ata_sff_host_intr(struct ata_port *ap,
1442 				      struct ata_queued_cmd *qc)
1443 {
1444 	struct ata_eh_info *ehi = &ap->link.eh_info;
1445 	u8 status, host_stat = 0;
1446 
1447 	VPRINTK("ata%u: protocol %d task_state %d\n",
1448 		ap->print_id, qc->tf.protocol, ap->hsm_task_state);
1449 
1450 	/* Check whether we are expecting interrupt in this state */
1451 	switch (ap->hsm_task_state) {
1452 	case HSM_ST_FIRST:
1453 		/* Some pre-ATAPI-4 devices assert INTRQ
1454 		 * at this state when ready to receive CDB.
1455 		 */
1456 
1457 		/* Check the ATA_DFLAG_CDB_INTR flag is enough here.
1458 		 * The flag was turned on only for atapi devices.  No
1459 		 * need to check ata_is_atapi(qc->tf.protocol) again.
1460 		 */
1461 		if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1462 			goto idle_irq;
1463 		break;
1464 	case HSM_ST_LAST:
1465 		if (qc->tf.protocol == ATA_PROT_DMA ||
1466 		    qc->tf.protocol == ATAPI_PROT_DMA) {
1467 			/* check status of DMA engine */
1468 			host_stat = ap->ops->bmdma_status(ap);
1469 			VPRINTK("ata%u: host_stat 0x%X\n",
1470 				ap->print_id, host_stat);
1471 
1472 			/* if it's not our irq... */
1473 			if (!(host_stat & ATA_DMA_INTR))
1474 				goto idle_irq;
1475 
1476 			/* before we do anything else, clear DMA-Start bit */
1477 			ap->ops->bmdma_stop(qc);
1478 
1479 			if (unlikely(host_stat & ATA_DMA_ERR)) {
1480 				/* error when transfering data to/from memory */
1481 				qc->err_mask |= AC_ERR_HOST_BUS;
1482 				ap->hsm_task_state = HSM_ST_ERR;
1483 			}
1484 		}
1485 		break;
1486 	case HSM_ST:
1487 		break;
1488 	default:
1489 		goto idle_irq;
1490 	}
1491 
1492 	/* check altstatus */
1493 	status = ata_sff_altstatus(ap);
1494 	if (status & ATA_BUSY)
1495 		goto idle_irq;
1496 
1497 	/* check main status, clearing INTRQ */
1498 	status = ap->ops->sff_check_status(ap);
1499 	if (unlikely(status & ATA_BUSY))
1500 		goto idle_irq;
1501 
1502 	/* ack bmdma irq events */
1503 	ap->ops->sff_irq_clear(ap);
1504 
1505 	ata_sff_hsm_move(ap, qc, status, 0);
1506 
1507 	if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA ||
1508 				       qc->tf.protocol == ATAPI_PROT_DMA))
1509 		ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
1510 
1511 	return 1;	/* irq handled */
1512 
1513 idle_irq:
1514 	ap->stats.idle_irq++;
1515 
1516 #ifdef ATA_IRQ_TRAP
1517 	if ((ap->stats.idle_irq % 1000) == 0) {
1518 		ap->ops->sff_check_status(ap);
1519 		ap->ops->sff_irq_clear(ap);
1520 		ata_port_printk(ap, KERN_WARNING, "irq trap\n");
1521 		return 1;
1522 	}
1523 #endif
1524 	return 0;	/* irq not handled */
1525 }
1526 
1527 /**
1528  *	ata_sff_interrupt - Default ATA host interrupt handler
1529  *	@irq: irq line (unused)
1530  *	@dev_instance: pointer to our ata_host information structure
1531  *
1532  *	Default interrupt handler for PCI IDE devices.  Calls
1533  *	ata_sff_host_intr() for each port that is not disabled.
1534  *
1535  *	LOCKING:
1536  *	Obtains host lock during operation.
1537  *
1538  *	RETURNS:
1539  *	IRQ_NONE or IRQ_HANDLED.
1540  */
1541 irqreturn_t ata_sff_interrupt(int irq, void *dev_instance)
1542 {
1543 	struct ata_host *host = dev_instance;
1544 	unsigned int i;
1545 	unsigned int handled = 0;
1546 	unsigned long flags;
1547 
1548 	/* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
1549 	spin_lock_irqsave(&host->lock, flags);
1550 
1551 	for (i = 0; i < host->n_ports; i++) {
1552 		struct ata_port *ap;
1553 
1554 		ap = host->ports[i];
1555 		if (ap &&
1556 		    !(ap->flags & ATA_FLAG_DISABLED)) {
1557 			struct ata_queued_cmd *qc;
1558 
1559 			qc = ata_qc_from_tag(ap, ap->link.active_tag);
1560 			if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) &&
1561 			    (qc->flags & ATA_QCFLAG_ACTIVE))
1562 				handled |= ata_sff_host_intr(ap, qc);
1563 		}
1564 	}
1565 
1566 	spin_unlock_irqrestore(&host->lock, flags);
1567 
1568 	return IRQ_RETVAL(handled);
1569 }
1570 
1571 /**
1572  *	ata_sff_freeze - Freeze SFF controller port
1573  *	@ap: port to freeze
1574  *
1575  *	Freeze BMDMA controller port.
1576  *
1577  *	LOCKING:
1578  *	Inherited from caller.
1579  */
1580 void ata_sff_freeze(struct ata_port *ap)
1581 {
1582 	struct ata_ioports *ioaddr = &ap->ioaddr;
1583 
1584 	ap->ctl |= ATA_NIEN;
1585 	ap->last_ctl = ap->ctl;
1586 
1587 	if (ioaddr->ctl_addr)
1588 		iowrite8(ap->ctl, ioaddr->ctl_addr);
1589 
1590 	/* Under certain circumstances, some controllers raise IRQ on
1591 	 * ATA_NIEN manipulation.  Also, many controllers fail to mask
1592 	 * previously pending IRQ on ATA_NIEN assertion.  Clear it.
1593 	 */
1594 	ap->ops->sff_check_status(ap);
1595 
1596 	ap->ops->sff_irq_clear(ap);
1597 }
1598 
1599 /**
1600  *	ata_sff_thaw - Thaw SFF controller port
1601  *	@ap: port to thaw
1602  *
1603  *	Thaw SFF controller port.
1604  *
1605  *	LOCKING:
1606  *	Inherited from caller.
1607  */
1608 void ata_sff_thaw(struct ata_port *ap)
1609 {
1610 	/* clear & re-enable interrupts */
1611 	ap->ops->sff_check_status(ap);
1612 	ap->ops->sff_irq_clear(ap);
1613 	ap->ops->sff_irq_on(ap);
1614 }
1615 
1616 /**
1617  *	ata_sff_prereset - prepare SFF link for reset
1618  *	@link: SFF link to be reset
1619  *	@deadline: deadline jiffies for the operation
1620  *
1621  *	SFF link @link is about to be reset.  Initialize it.  It first
1622  *	calls ata_std_prereset() and wait for !BSY if the port is
1623  *	being softreset.
1624  *
1625  *	LOCKING:
1626  *	Kernel thread context (may sleep)
1627  *
1628  *	RETURNS:
1629  *	0 on success, -errno otherwise.
1630  */
1631 int ata_sff_prereset(struct ata_link *link, unsigned long deadline)
1632 {
1633 	struct ata_eh_context *ehc = &link->eh_context;
1634 	int rc;
1635 
1636 	rc = ata_std_prereset(link, deadline);
1637 	if (rc)
1638 		return rc;
1639 
1640 	/* if we're about to do hardreset, nothing more to do */
1641 	if (ehc->i.action & ATA_EH_HARDRESET)
1642 		return 0;
1643 
1644 	/* wait for !BSY if we don't know that no device is attached */
1645 	if (!ata_link_offline(link)) {
1646 		rc = ata_sff_wait_ready(link, deadline);
1647 		if (rc && rc != -ENODEV) {
1648 			ata_link_printk(link, KERN_WARNING, "device not ready "
1649 					"(errno=%d), forcing hardreset\n", rc);
1650 			ehc->i.action |= ATA_EH_HARDRESET;
1651 		}
1652 	}
1653 
1654 	return 0;
1655 }
1656 
1657 /**
1658  *	ata_devchk - PATA device presence detection
1659  *	@ap: ATA channel to examine
1660  *	@device: Device to examine (starting at zero)
1661  *
1662  *	This technique was originally described in
1663  *	Hale Landis's ATADRVR (www.ata-atapi.com), and
1664  *	later found its way into the ATA/ATAPI spec.
1665  *
1666  *	Write a pattern to the ATA shadow registers,
1667  *	and if a device is present, it will respond by
1668  *	correctly storing and echoing back the
1669  *	ATA shadow register contents.
1670  *
1671  *	LOCKING:
1672  *	caller.
1673  */
1674 static unsigned int ata_devchk(struct ata_port *ap, unsigned int device)
1675 {
1676 	struct ata_ioports *ioaddr = &ap->ioaddr;
1677 	u8 nsect, lbal;
1678 
1679 	ap->ops->sff_dev_select(ap, device);
1680 
1681 	iowrite8(0x55, ioaddr->nsect_addr);
1682 	iowrite8(0xaa, ioaddr->lbal_addr);
1683 
1684 	iowrite8(0xaa, ioaddr->nsect_addr);
1685 	iowrite8(0x55, ioaddr->lbal_addr);
1686 
1687 	iowrite8(0x55, ioaddr->nsect_addr);
1688 	iowrite8(0xaa, ioaddr->lbal_addr);
1689 
1690 	nsect = ioread8(ioaddr->nsect_addr);
1691 	lbal = ioread8(ioaddr->lbal_addr);
1692 
1693 	if ((nsect == 0x55) && (lbal == 0xaa))
1694 		return 1;	/* we found a device */
1695 
1696 	return 0;		/* nothing found */
1697 }
1698 
1699 /**
1700  *	ata_sff_dev_classify - Parse returned ATA device signature
1701  *	@dev: ATA device to classify (starting at zero)
1702  *	@present: device seems present
1703  *	@r_err: Value of error register on completion
1704  *
1705  *	After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
1706  *	an ATA/ATAPI-defined set of values is placed in the ATA
1707  *	shadow registers, indicating the results of device detection
1708  *	and diagnostics.
1709  *
1710  *	Select the ATA device, and read the values from the ATA shadow
1711  *	registers.  Then parse according to the Error register value,
1712  *	and the spec-defined values examined by ata_dev_classify().
1713  *
1714  *	LOCKING:
1715  *	caller.
1716  *
1717  *	RETURNS:
1718  *	Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
1719  */
1720 unsigned int ata_sff_dev_classify(struct ata_device *dev, int present,
1721 				  u8 *r_err)
1722 {
1723 	struct ata_port *ap = dev->link->ap;
1724 	struct ata_taskfile tf;
1725 	unsigned int class;
1726 	u8 err;
1727 
1728 	ap->ops->sff_dev_select(ap, dev->devno);
1729 
1730 	memset(&tf, 0, sizeof(tf));
1731 
1732 	ap->ops->sff_tf_read(ap, &tf);
1733 	err = tf.feature;
1734 	if (r_err)
1735 		*r_err = err;
1736 
1737 	/* see if device passed diags: continue and warn later */
1738 	if (err == 0)
1739 		/* diagnostic fail : do nothing _YET_ */
1740 		dev->horkage |= ATA_HORKAGE_DIAGNOSTIC;
1741 	else if (err == 1)
1742 		/* do nothing */ ;
1743 	else if ((dev->devno == 0) && (err == 0x81))
1744 		/* do nothing */ ;
1745 	else
1746 		return ATA_DEV_NONE;
1747 
1748 	/* determine if device is ATA or ATAPI */
1749 	class = ata_dev_classify(&tf);
1750 
1751 	if (class == ATA_DEV_UNKNOWN) {
1752 		/* If the device failed diagnostic, it's likely to
1753 		 * have reported incorrect device signature too.
1754 		 * Assume ATA device if the device seems present but
1755 		 * device signature is invalid with diagnostic
1756 		 * failure.
1757 		 */
1758 		if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC))
1759 			class = ATA_DEV_ATA;
1760 		else
1761 			class = ATA_DEV_NONE;
1762 	} else if ((class == ATA_DEV_ATA) &&
1763 		   (ap->ops->sff_check_status(ap) == 0))
1764 		class = ATA_DEV_NONE;
1765 
1766 	return class;
1767 }
1768 
1769 /**
1770  *	ata_sff_wait_after_reset - wait for devices to become ready after reset
1771  *	@link: SFF link which is just reset
1772  *	@devmask: mask of present devices
1773  *	@deadline: deadline jiffies for the operation
1774  *
1775  *	Wait devices attached to SFF @link to become ready after
1776  *	reset.  It contains preceding 150ms wait to avoid accessing TF
1777  *	status register too early.
1778  *
1779  *	LOCKING:
1780  *	Kernel thread context (may sleep).
1781  *
1782  *	RETURNS:
1783  *	0 on success, -ENODEV if some or all of devices in @devmask
1784  *	don't seem to exist.  -errno on other errors.
1785  */
1786 int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask,
1787 			     unsigned long deadline)
1788 {
1789 	struct ata_port *ap = link->ap;
1790 	struct ata_ioports *ioaddr = &ap->ioaddr;
1791 	unsigned int dev0 = devmask & (1 << 0);
1792 	unsigned int dev1 = devmask & (1 << 1);
1793 	int rc, ret = 0;
1794 
1795 	msleep(ATA_WAIT_AFTER_RESET_MSECS);
1796 
1797 	/* always check readiness of the master device */
1798 	rc = ata_sff_wait_ready(link, deadline);
1799 	/* -ENODEV means the odd clown forgot the D7 pulldown resistor
1800 	 * and TF status is 0xff, bail out on it too.
1801 	 */
1802 	if (rc)
1803 		return rc;
1804 
1805 	/* if device 1 was found in ata_devchk, wait for register
1806 	 * access briefly, then wait for BSY to clear.
1807 	 */
1808 	if (dev1) {
1809 		int i;
1810 
1811 		ap->ops->sff_dev_select(ap, 1);
1812 
1813 		/* Wait for register access.  Some ATAPI devices fail
1814 		 * to set nsect/lbal after reset, so don't waste too
1815 		 * much time on it.  We're gonna wait for !BSY anyway.
1816 		 */
1817 		for (i = 0; i < 2; i++) {
1818 			u8 nsect, lbal;
1819 
1820 			nsect = ioread8(ioaddr->nsect_addr);
1821 			lbal = ioread8(ioaddr->lbal_addr);
1822 			if ((nsect == 1) && (lbal == 1))
1823 				break;
1824 			msleep(50);	/* give drive a breather */
1825 		}
1826 
1827 		rc = ata_sff_wait_ready(link, deadline);
1828 		if (rc) {
1829 			if (rc != -ENODEV)
1830 				return rc;
1831 			ret = rc;
1832 		}
1833 	}
1834 
1835 	/* is all this really necessary? */
1836 	ap->ops->sff_dev_select(ap, 0);
1837 	if (dev1)
1838 		ap->ops->sff_dev_select(ap, 1);
1839 	if (dev0)
1840 		ap->ops->sff_dev_select(ap, 0);
1841 
1842 	return ret;
1843 }
1844 
1845 static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask,
1846 			     unsigned long deadline)
1847 {
1848 	struct ata_ioports *ioaddr = &ap->ioaddr;
1849 
1850 	DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
1851 
1852 	/* software reset.  causes dev0 to be selected */
1853 	iowrite8(ap->ctl, ioaddr->ctl_addr);
1854 	udelay(20);	/* FIXME: flush */
1855 	iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
1856 	udelay(20);	/* FIXME: flush */
1857 	iowrite8(ap->ctl, ioaddr->ctl_addr);
1858 
1859 	/* wait the port to become ready */
1860 	return ata_sff_wait_after_reset(&ap->link, devmask, deadline);
1861 }
1862 
1863 /**
1864  *	ata_sff_softreset - reset host port via ATA SRST
1865  *	@link: ATA link to reset
1866  *	@classes: resulting classes of attached devices
1867  *	@deadline: deadline jiffies for the operation
1868  *
1869  *	Reset host port using ATA SRST.
1870  *
1871  *	LOCKING:
1872  *	Kernel thread context (may sleep)
1873  *
1874  *	RETURNS:
1875  *	0 on success, -errno otherwise.
1876  */
1877 int ata_sff_softreset(struct ata_link *link, unsigned int *classes,
1878 		      unsigned long deadline)
1879 {
1880 	struct ata_port *ap = link->ap;
1881 	unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
1882 	unsigned int devmask = 0;
1883 	int rc;
1884 	u8 err;
1885 
1886 	DPRINTK("ENTER\n");
1887 
1888 	/* determine if device 0/1 are present */
1889 	if (ata_devchk(ap, 0))
1890 		devmask |= (1 << 0);
1891 	if (slave_possible && ata_devchk(ap, 1))
1892 		devmask |= (1 << 1);
1893 
1894 	/* select device 0 again */
1895 	ap->ops->sff_dev_select(ap, 0);
1896 
1897 	/* issue bus reset */
1898 	DPRINTK("about to softreset, devmask=%x\n", devmask);
1899 	rc = ata_bus_softreset(ap, devmask, deadline);
1900 	/* if link is occupied, -ENODEV too is an error */
1901 	if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
1902 		ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc);
1903 		return rc;
1904 	}
1905 
1906 	/* determine by signature whether we have ATA or ATAPI devices */
1907 	classes[0] = ata_sff_dev_classify(&link->device[0],
1908 					  devmask & (1 << 0), &err);
1909 	if (slave_possible && err != 0x81)
1910 		classes[1] = ata_sff_dev_classify(&link->device[1],
1911 						  devmask & (1 << 1), &err);
1912 
1913 	DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
1914 	return 0;
1915 }
1916 
1917 /**
1918  *	sata_sff_hardreset - reset host port via SATA phy reset
1919  *	@link: link to reset
1920  *	@class: resulting class of attached device
1921  *	@deadline: deadline jiffies for the operation
1922  *
1923  *	SATA phy-reset host port using DET bits of SControl register,
1924  *	wait for !BSY and classify the attached device.
1925  *
1926  *	LOCKING:
1927  *	Kernel thread context (may sleep)
1928  *
1929  *	RETURNS:
1930  *	0 on success, -errno otherwise.
1931  */
1932 int sata_sff_hardreset(struct ata_link *link, unsigned int *class,
1933 		       unsigned long deadline)
1934 {
1935 	struct ata_eh_context *ehc = &link->eh_context;
1936 	const unsigned long *timing = sata_ehc_deb_timing(ehc);
1937 	bool online;
1938 	int rc;
1939 
1940 	rc = sata_link_hardreset(link, timing, deadline, &online,
1941 				 ata_sff_check_ready);
1942 	if (online)
1943 		*class = ata_sff_dev_classify(link->device, 1, NULL);
1944 
1945 	DPRINTK("EXIT, class=%u\n", *class);
1946 	return rc;
1947 }
1948 
1949 /**
1950  *	ata_sff_postreset - SFF postreset callback
1951  *	@link: the target SFF ata_link
1952  *	@classes: classes of attached devices
1953  *
1954  *	This function is invoked after a successful reset.  It first
1955  *	calls ata_std_postreset() and performs SFF specific postreset
1956  *	processing.
1957  *
1958  *	LOCKING:
1959  *	Kernel thread context (may sleep)
1960  */
1961 void ata_sff_postreset(struct ata_link *link, unsigned int *classes)
1962 {
1963 	struct ata_port *ap = link->ap;
1964 
1965 	ata_std_postreset(link, classes);
1966 
1967 	/* is double-select really necessary? */
1968 	if (classes[0] != ATA_DEV_NONE)
1969 		ap->ops->sff_dev_select(ap, 1);
1970 	if (classes[1] != ATA_DEV_NONE)
1971 		ap->ops->sff_dev_select(ap, 0);
1972 
1973 	/* bail out if no device is present */
1974 	if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
1975 		DPRINTK("EXIT, no device\n");
1976 		return;
1977 	}
1978 
1979 	/* set up device control */
1980 	if (ap->ioaddr.ctl_addr)
1981 		iowrite8(ap->ctl, ap->ioaddr.ctl_addr);
1982 }
1983 
1984 /**
1985  *	ata_sff_error_handler - Stock error handler for BMDMA controller
1986  *	@ap: port to handle error for
1987  *
1988  *	Stock error handler for SFF controller.  It can handle both
1989  *	PATA and SATA controllers.  Many controllers should be able to
1990  *	use this EH as-is or with some added handling before and
1991  *	after.
1992  *
1993  *	LOCKING:
1994  *	Kernel thread context (may sleep)
1995  */
1996 void ata_sff_error_handler(struct ata_port *ap)
1997 {
1998 	ata_reset_fn_t softreset = ap->ops->softreset;
1999 	ata_reset_fn_t hardreset = ap->ops->hardreset;
2000 	struct ata_queued_cmd *qc;
2001 	unsigned long flags;
2002 	int thaw = 0;
2003 
2004 	qc = __ata_qc_from_tag(ap, ap->link.active_tag);
2005 	if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
2006 		qc = NULL;
2007 
2008 	/* reset PIO HSM and stop DMA engine */
2009 	spin_lock_irqsave(ap->lock, flags);
2010 
2011 	ap->hsm_task_state = HSM_ST_IDLE;
2012 
2013 	if (ap->ioaddr.bmdma_addr &&
2014 	    qc && (qc->tf.protocol == ATA_PROT_DMA ||
2015 		   qc->tf.protocol == ATAPI_PROT_DMA)) {
2016 		u8 host_stat;
2017 
2018 		host_stat = ap->ops->bmdma_status(ap);
2019 
2020 		/* BMDMA controllers indicate host bus error by
2021 		 * setting DMA_ERR bit and timing out.  As it wasn't
2022 		 * really a timeout event, adjust error mask and
2023 		 * cancel frozen state.
2024 		 */
2025 		if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) {
2026 			qc->err_mask = AC_ERR_HOST_BUS;
2027 			thaw = 1;
2028 		}
2029 
2030 		ap->ops->bmdma_stop(qc);
2031 	}
2032 
2033 	ata_sff_altstatus(ap);
2034 	ap->ops->sff_check_status(ap);
2035 	ap->ops->sff_irq_clear(ap);
2036 
2037 	spin_unlock_irqrestore(ap->lock, flags);
2038 
2039 	if (thaw)
2040 		ata_eh_thaw_port(ap);
2041 
2042 	/* PIO and DMA engines have been stopped, perform recovery */
2043 
2044 	/* Ignore ata_sff_softreset if ctl isn't accessible and
2045 	 * built-in hardresets if SCR access isn't available.
2046 	 */
2047 	if (softreset == ata_sff_softreset && !ap->ioaddr.ctl_addr)
2048 		softreset = NULL;
2049 	if (ata_is_builtin_hardreset(hardreset) && !sata_scr_valid(&ap->link))
2050 		hardreset = NULL;
2051 
2052 	ata_do_eh(ap, ap->ops->prereset, softreset, hardreset,
2053 		  ap->ops->postreset);
2054 }
2055 
2056 /**
2057  *	ata_sff_post_internal_cmd - Stock post_internal_cmd for SFF controller
2058  *	@qc: internal command to clean up
2059  *
2060  *	LOCKING:
2061  *	Kernel thread context (may sleep)
2062  */
2063 void ata_sff_post_internal_cmd(struct ata_queued_cmd *qc)
2064 {
2065 	if (qc->ap->ioaddr.bmdma_addr)
2066 		ata_bmdma_stop(qc);
2067 }
2068 
2069 /**
2070  *	ata_sff_port_start - Set port up for dma.
2071  *	@ap: Port to initialize
2072  *
2073  *	Called just after data structures for each port are
2074  *	initialized.  Allocates space for PRD table if the device
2075  *	is DMA capable SFF.
2076  *
2077  *	May be used as the port_start() entry in ata_port_operations.
2078  *
2079  *	LOCKING:
2080  *	Inherited from caller.
2081  */
2082 int ata_sff_port_start(struct ata_port *ap)
2083 {
2084 	if (ap->ioaddr.bmdma_addr)
2085 		return ata_port_start(ap);
2086 	return 0;
2087 }
2088 
2089 /**
2090  *	ata_sff_std_ports - initialize ioaddr with standard port offsets.
2091  *	@ioaddr: IO address structure to be initialized
2092  *
2093  *	Utility function which initializes data_addr, error_addr,
2094  *	feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
2095  *	device_addr, status_addr, and command_addr to standard offsets
2096  *	relative to cmd_addr.
2097  *
2098  *	Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
2099  */
2100 void ata_sff_std_ports(struct ata_ioports *ioaddr)
2101 {
2102 	ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
2103 	ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
2104 	ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
2105 	ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
2106 	ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
2107 	ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
2108 	ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
2109 	ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
2110 	ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
2111 	ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
2112 }
2113 
2114 unsigned long ata_bmdma_mode_filter(struct ata_device *adev,
2115 				    unsigned long xfer_mask)
2116 {
2117 	/* Filter out DMA modes if the device has been configured by
2118 	   the BIOS as PIO only */
2119 
2120 	if (adev->link->ap->ioaddr.bmdma_addr == NULL)
2121 		xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
2122 	return xfer_mask;
2123 }
2124 
2125 /**
2126  *	ata_bmdma_setup - Set up PCI IDE BMDMA transaction
2127  *	@qc: Info associated with this ATA transaction.
2128  *
2129  *	LOCKING:
2130  *	spin_lock_irqsave(host lock)
2131  */
2132 void ata_bmdma_setup(struct ata_queued_cmd *qc)
2133 {
2134 	struct ata_port *ap = qc->ap;
2135 	unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
2136 	u8 dmactl;
2137 
2138 	/* load PRD table addr. */
2139 	mb();	/* make sure PRD table writes are visible to controller */
2140 	iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
2141 
2142 	/* specify data direction, triple-check start bit is clear */
2143 	dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2144 	dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
2145 	if (!rw)
2146 		dmactl |= ATA_DMA_WR;
2147 	iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2148 
2149 	/* issue r/w command */
2150 	ap->ops->sff_exec_command(ap, &qc->tf);
2151 }
2152 
2153 /**
2154  *	ata_bmdma_start - Start a PCI IDE BMDMA transaction
2155  *	@qc: Info associated with this ATA transaction.
2156  *
2157  *	LOCKING:
2158  *	spin_lock_irqsave(host lock)
2159  */
2160 void ata_bmdma_start(struct ata_queued_cmd *qc)
2161 {
2162 	struct ata_port *ap = qc->ap;
2163 	u8 dmactl;
2164 
2165 	/* start host DMA transaction */
2166 	dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2167 	iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2168 
2169 	/* Strictly, one may wish to issue an ioread8() here, to
2170 	 * flush the mmio write.  However, control also passes
2171 	 * to the hardware at this point, and it will interrupt
2172 	 * us when we are to resume control.  So, in effect,
2173 	 * we don't care when the mmio write flushes.
2174 	 * Further, a read of the DMA status register _immediately_
2175 	 * following the write may not be what certain flaky hardware
2176 	 * is expected, so I think it is best to not add a readb()
2177 	 * without first all the MMIO ATA cards/mobos.
2178 	 * Or maybe I'm just being paranoid.
2179 	 *
2180 	 * FIXME: The posting of this write means I/O starts are
2181 	 * unneccessarily delayed for MMIO
2182 	 */
2183 }
2184 
2185 /**
2186  *	ata_bmdma_stop - Stop PCI IDE BMDMA transfer
2187  *	@qc: Command we are ending DMA for
2188  *
2189  *	Clears the ATA_DMA_START flag in the dma control register
2190  *
2191  *	May be used as the bmdma_stop() entry in ata_port_operations.
2192  *
2193  *	LOCKING:
2194  *	spin_lock_irqsave(host lock)
2195  */
2196 void ata_bmdma_stop(struct ata_queued_cmd *qc)
2197 {
2198 	struct ata_port *ap = qc->ap;
2199 	void __iomem *mmio = ap->ioaddr.bmdma_addr;
2200 
2201 	/* clear start/stop bit */
2202 	iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
2203 		 mmio + ATA_DMA_CMD);
2204 
2205 	/* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
2206 	ata_sff_altstatus(ap);        /* dummy read */
2207 }
2208 
2209 /**
2210  *	ata_bmdma_status - Read PCI IDE BMDMA status
2211  *	@ap: Port associated with this ATA transaction.
2212  *
2213  *	Read and return BMDMA status register.
2214  *
2215  *	May be used as the bmdma_status() entry in ata_port_operations.
2216  *
2217  *	LOCKING:
2218  *	spin_lock_irqsave(host lock)
2219  */
2220 u8 ata_bmdma_status(struct ata_port *ap)
2221 {
2222 	return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
2223 }
2224 
2225 /**
2226  *	ata_bus_reset - reset host port and associated ATA channel
2227  *	@ap: port to reset
2228  *
2229  *	This is typically the first time we actually start issuing
2230  *	commands to the ATA channel.  We wait for BSY to clear, then
2231  *	issue EXECUTE DEVICE DIAGNOSTIC command, polling for its
2232  *	result.  Determine what devices, if any, are on the channel
2233  *	by looking at the device 0/1 error register.  Look at the signature
2234  *	stored in each device's taskfile registers, to determine if
2235  *	the device is ATA or ATAPI.
2236  *
2237  *	LOCKING:
2238  *	PCI/etc. bus probe sem.
2239  *	Obtains host lock.
2240  *
2241  *	SIDE EFFECTS:
2242  *	Sets ATA_FLAG_DISABLED if bus reset fails.
2243  *
2244  *	DEPRECATED:
2245  *	This function is only for drivers which still use old EH and
2246  *	will be removed soon.
2247  */
2248 void ata_bus_reset(struct ata_port *ap)
2249 {
2250 	struct ata_device *device = ap->link.device;
2251 	struct ata_ioports *ioaddr = &ap->ioaddr;
2252 	unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2253 	u8 err;
2254 	unsigned int dev0, dev1 = 0, devmask = 0;
2255 	int rc;
2256 
2257 	DPRINTK("ENTER, host %u, port %u\n", ap->print_id, ap->port_no);
2258 
2259 	/* determine if device 0/1 are present */
2260 	if (ap->flags & ATA_FLAG_SATA_RESET)
2261 		dev0 = 1;
2262 	else {
2263 		dev0 = ata_devchk(ap, 0);
2264 		if (slave_possible)
2265 			dev1 = ata_devchk(ap, 1);
2266 	}
2267 
2268 	if (dev0)
2269 		devmask |= (1 << 0);
2270 	if (dev1)
2271 		devmask |= (1 << 1);
2272 
2273 	/* select device 0 again */
2274 	ap->ops->sff_dev_select(ap, 0);
2275 
2276 	/* issue bus reset */
2277 	if (ap->flags & ATA_FLAG_SRST) {
2278 		rc = ata_bus_softreset(ap, devmask, jiffies + 40 * HZ);
2279 		if (rc && rc != -ENODEV)
2280 			goto err_out;
2281 	}
2282 
2283 	/*
2284 	 * determine by signature whether we have ATA or ATAPI devices
2285 	 */
2286 	device[0].class = ata_sff_dev_classify(&device[0], dev0, &err);
2287 	if ((slave_possible) && (err != 0x81))
2288 		device[1].class = ata_sff_dev_classify(&device[1], dev1, &err);
2289 
2290 	/* is double-select really necessary? */
2291 	if (device[1].class != ATA_DEV_NONE)
2292 		ap->ops->sff_dev_select(ap, 1);
2293 	if (device[0].class != ATA_DEV_NONE)
2294 		ap->ops->sff_dev_select(ap, 0);
2295 
2296 	/* if no devices were detected, disable this port */
2297 	if ((device[0].class == ATA_DEV_NONE) &&
2298 	    (device[1].class == ATA_DEV_NONE))
2299 		goto err_out;
2300 
2301 	if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) {
2302 		/* set up device control for ATA_FLAG_SATA_RESET */
2303 		iowrite8(ap->ctl, ioaddr->ctl_addr);
2304 	}
2305 
2306 	DPRINTK("EXIT\n");
2307 	return;
2308 
2309 err_out:
2310 	ata_port_printk(ap, KERN_ERR, "disabling port\n");
2311 	ata_port_disable(ap);
2312 
2313 	DPRINTK("EXIT\n");
2314 }
2315 
2316 #ifdef CONFIG_PCI
2317 
2318 /**
2319  *	ata_pci_bmdma_clear_simplex -	attempt to kick device out of simplex
2320  *	@pdev: PCI device
2321  *
2322  *	Some PCI ATA devices report simplex mode but in fact can be told to
2323  *	enter non simplex mode. This implements the necessary logic to
2324  *	perform the task on such devices. Calling it on other devices will
2325  *	have -undefined- behaviour.
2326  */
2327 int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev)
2328 {
2329 	unsigned long bmdma = pci_resource_start(pdev, 4);
2330 	u8 simplex;
2331 
2332 	if (bmdma == 0)
2333 		return -ENOENT;
2334 
2335 	simplex = inb(bmdma + 0x02);
2336 	outb(simplex & 0x60, bmdma + 0x02);
2337 	simplex = inb(bmdma + 0x02);
2338 	if (simplex & 0x80)
2339 		return -EOPNOTSUPP;
2340 	return 0;
2341 }
2342 
2343 /**
2344  *	ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host
2345  *	@host: target ATA host
2346  *
2347  *	Acquire PCI BMDMA resources and initialize @host accordingly.
2348  *
2349  *	LOCKING:
2350  *	Inherited from calling layer (may sleep).
2351  *
2352  *	RETURNS:
2353  *	0 on success, -errno otherwise.
2354  */
2355 int ata_pci_bmdma_init(struct ata_host *host)
2356 {
2357 	struct device *gdev = host->dev;
2358 	struct pci_dev *pdev = to_pci_dev(gdev);
2359 	int i, rc;
2360 
2361 	/* No BAR4 allocation: No DMA */
2362 	if (pci_resource_start(pdev, 4) == 0)
2363 		return 0;
2364 
2365 	/* TODO: If we get no DMA mask we should fall back to PIO */
2366 	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
2367 	if (rc)
2368 		return rc;
2369 	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
2370 	if (rc)
2371 		return rc;
2372 
2373 	/* request and iomap DMA region */
2374 	rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev));
2375 	if (rc) {
2376 		dev_printk(KERN_ERR, gdev, "failed to request/iomap BAR4\n");
2377 		return -ENOMEM;
2378 	}
2379 	host->iomap = pcim_iomap_table(pdev);
2380 
2381 	for (i = 0; i < 2; i++) {
2382 		struct ata_port *ap = host->ports[i];
2383 		void __iomem *bmdma = host->iomap[4] + 8 * i;
2384 
2385 		if (ata_port_is_dummy(ap))
2386 			continue;
2387 
2388 		ap->ioaddr.bmdma_addr = bmdma;
2389 		if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) &&
2390 		    (ioread8(bmdma + 2) & 0x80))
2391 			host->flags |= ATA_HOST_SIMPLEX;
2392 
2393 		ata_port_desc(ap, "bmdma 0x%llx",
2394 			(unsigned long long)pci_resource_start(pdev, 4) + 8 * i);
2395 	}
2396 
2397 	return 0;
2398 }
2399 
2400 static int ata_resources_present(struct pci_dev *pdev, int port)
2401 {
2402 	int i;
2403 
2404 	/* Check the PCI resources for this channel are enabled */
2405 	port = port * 2;
2406 	for (i = 0; i < 2; i ++) {
2407 		if (pci_resource_start(pdev, port + i) == 0 ||
2408 		    pci_resource_len(pdev, port + i) == 0)
2409 			return 0;
2410 	}
2411 	return 1;
2412 }
2413 
2414 /**
2415  *	ata_pci_sff_init_host - acquire native PCI ATA resources and init host
2416  *	@host: target ATA host
2417  *
2418  *	Acquire native PCI ATA resources for @host and initialize the
2419  *	first two ports of @host accordingly.  Ports marked dummy are
2420  *	skipped and allocation failure makes the port dummy.
2421  *
2422  *	Note that native PCI resources are valid even for legacy hosts
2423  *	as we fix up pdev resources array early in boot, so this
2424  *	function can be used for both native and legacy SFF hosts.
2425  *
2426  *	LOCKING:
2427  *	Inherited from calling layer (may sleep).
2428  *
2429  *	RETURNS:
2430  *	0 if at least one port is initialized, -ENODEV if no port is
2431  *	available.
2432  */
2433 int ata_pci_sff_init_host(struct ata_host *host)
2434 {
2435 	struct device *gdev = host->dev;
2436 	struct pci_dev *pdev = to_pci_dev(gdev);
2437 	unsigned int mask = 0;
2438 	int i, rc;
2439 
2440 	/* request, iomap BARs and init port addresses accordingly */
2441 	for (i = 0; i < 2; i++) {
2442 		struct ata_port *ap = host->ports[i];
2443 		int base = i * 2;
2444 		void __iomem * const *iomap;
2445 
2446 		if (ata_port_is_dummy(ap))
2447 			continue;
2448 
2449 		/* Discard disabled ports.  Some controllers show
2450 		 * their unused channels this way.  Disabled ports are
2451 		 * made dummy.
2452 		 */
2453 		if (!ata_resources_present(pdev, i)) {
2454 			ap->ops = &ata_dummy_port_ops;
2455 			continue;
2456 		}
2457 
2458 		rc = pcim_iomap_regions(pdev, 0x3 << base,
2459 					dev_driver_string(gdev));
2460 		if (rc) {
2461 			dev_printk(KERN_WARNING, gdev,
2462 				   "failed to request/iomap BARs for port %d "
2463 				   "(errno=%d)\n", i, rc);
2464 			if (rc == -EBUSY)
2465 				pcim_pin_device(pdev);
2466 			ap->ops = &ata_dummy_port_ops;
2467 			continue;
2468 		}
2469 		host->iomap = iomap = pcim_iomap_table(pdev);
2470 
2471 		ap->ioaddr.cmd_addr = iomap[base];
2472 		ap->ioaddr.altstatus_addr =
2473 		ap->ioaddr.ctl_addr = (void __iomem *)
2474 			((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS);
2475 		ata_sff_std_ports(&ap->ioaddr);
2476 
2477 		ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
2478 			(unsigned long long)pci_resource_start(pdev, base),
2479 			(unsigned long long)pci_resource_start(pdev, base + 1));
2480 
2481 		mask |= 1 << i;
2482 	}
2483 
2484 	if (!mask) {
2485 		dev_printk(KERN_ERR, gdev, "no available native port\n");
2486 		return -ENODEV;
2487 	}
2488 
2489 	return 0;
2490 }
2491 
2492 /**
2493  *	ata_pci_sff_prepare_host - helper to prepare native PCI ATA host
2494  *	@pdev: target PCI device
2495  *	@ppi: array of port_info, must be enough for two ports
2496  *	@r_host: out argument for the initialized ATA host
2497  *
2498  *	Helper to allocate ATA host for @pdev, acquire all native PCI
2499  *	resources and initialize it accordingly in one go.
2500  *
2501  *	LOCKING:
2502  *	Inherited from calling layer (may sleep).
2503  *
2504  *	RETURNS:
2505  *	0 on success, -errno otherwise.
2506  */
2507 int ata_pci_sff_prepare_host(struct pci_dev *pdev,
2508 			     const struct ata_port_info * const * ppi,
2509 			     struct ata_host **r_host)
2510 {
2511 	struct ata_host *host;
2512 	int rc;
2513 
2514 	if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
2515 		return -ENOMEM;
2516 
2517 	host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
2518 	if (!host) {
2519 		dev_printk(KERN_ERR, &pdev->dev,
2520 			   "failed to allocate ATA host\n");
2521 		rc = -ENOMEM;
2522 		goto err_out;
2523 	}
2524 
2525 	rc = ata_pci_sff_init_host(host);
2526 	if (rc)
2527 		goto err_out;
2528 
2529 	/* init DMA related stuff */
2530 	rc = ata_pci_bmdma_init(host);
2531 	if (rc)
2532 		goto err_bmdma;
2533 
2534 	devres_remove_group(&pdev->dev, NULL);
2535 	*r_host = host;
2536 	return 0;
2537 
2538  err_bmdma:
2539 	/* This is necessary because PCI and iomap resources are
2540 	 * merged and releasing the top group won't release the
2541 	 * acquired resources if some of those have been acquired
2542 	 * before entering this function.
2543 	 */
2544 	pcim_iounmap_regions(pdev, 0xf);
2545  err_out:
2546 	devres_release_group(&pdev->dev, NULL);
2547 	return rc;
2548 }
2549 
2550 /**
2551  *	ata_pci_sff_activate_host - start SFF host, request IRQ and register it
2552  *	@host: target SFF ATA host
2553  *	@irq_handler: irq_handler used when requesting IRQ(s)
2554  *	@sht: scsi_host_template to use when registering the host
2555  *
2556  *	This is the counterpart of ata_host_activate() for SFF ATA
2557  *	hosts.  This separate helper is necessary because SFF hosts
2558  *	use two separate interrupts in legacy mode.
2559  *
2560  *	LOCKING:
2561  *	Inherited from calling layer (may sleep).
2562  *
2563  *	RETURNS:
2564  *	0 on success, -errno otherwise.
2565  */
2566 int ata_pci_sff_activate_host(struct ata_host *host,
2567 			      irq_handler_t irq_handler,
2568 			      struct scsi_host_template *sht)
2569 {
2570 	struct device *dev = host->dev;
2571 	struct pci_dev *pdev = to_pci_dev(dev);
2572 	const char *drv_name = dev_driver_string(host->dev);
2573 	int legacy_mode = 0, rc;
2574 
2575 	rc = ata_host_start(host);
2576 	if (rc)
2577 		return rc;
2578 
2579 	if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
2580 		u8 tmp8, mask;
2581 
2582 		/* TODO: What if one channel is in native mode ... */
2583 		pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
2584 		mask = (1 << 2) | (1 << 0);
2585 		if ((tmp8 & mask) != mask)
2586 			legacy_mode = 1;
2587 #if defined(CONFIG_NO_ATA_LEGACY)
2588 		/* Some platforms with PCI limits cannot address compat
2589 		   port space. In that case we punt if their firmware has
2590 		   left a device in compatibility mode */
2591 		if (legacy_mode) {
2592 			printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n");
2593 			return -EOPNOTSUPP;
2594 		}
2595 #endif
2596 	}
2597 
2598 	if (!devres_open_group(dev, NULL, GFP_KERNEL))
2599 		return -ENOMEM;
2600 
2601 	if (!legacy_mode && pdev->irq) {
2602 		rc = devm_request_irq(dev, pdev->irq, irq_handler,
2603 				      IRQF_SHARED, drv_name, host);
2604 		if (rc)
2605 			goto out;
2606 
2607 		ata_port_desc(host->ports[0], "irq %d", pdev->irq);
2608 		ata_port_desc(host->ports[1], "irq %d", pdev->irq);
2609 	} else if (legacy_mode) {
2610 		if (!ata_port_is_dummy(host->ports[0])) {
2611 			rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev),
2612 					      irq_handler, IRQF_SHARED,
2613 					      drv_name, host);
2614 			if (rc)
2615 				goto out;
2616 
2617 			ata_port_desc(host->ports[0], "irq %d",
2618 				      ATA_PRIMARY_IRQ(pdev));
2619 		}
2620 
2621 		if (!ata_port_is_dummy(host->ports[1])) {
2622 			rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev),
2623 					      irq_handler, IRQF_SHARED,
2624 					      drv_name, host);
2625 			if (rc)
2626 				goto out;
2627 
2628 			ata_port_desc(host->ports[1], "irq %d",
2629 				      ATA_SECONDARY_IRQ(pdev));
2630 		}
2631 	}
2632 
2633 	rc = ata_host_register(host, sht);
2634  out:
2635 	if (rc == 0)
2636 		devres_remove_group(dev, NULL);
2637 	else
2638 		devres_release_group(dev, NULL);
2639 
2640 	return rc;
2641 }
2642 
2643 /**
2644  *	ata_pci_sff_init_one - Initialize/register PCI IDE host controller
2645  *	@pdev: Controller to be initialized
2646  *	@ppi: array of port_info, must be enough for two ports
2647  *	@sht: scsi_host_template to use when registering the host
2648  *	@host_priv: host private_data
2649  *
2650  *	This is a helper function which can be called from a driver's
2651  *	xxx_init_one() probe function if the hardware uses traditional
2652  *	IDE taskfile registers.
2653  *
2654  *	This function calls pci_enable_device(), reserves its register
2655  *	regions, sets the dma mask, enables bus master mode, and calls
2656  *	ata_device_add()
2657  *
2658  *	ASSUMPTION:
2659  *	Nobody makes a single channel controller that appears solely as
2660  *	the secondary legacy port on PCI.
2661  *
2662  *	LOCKING:
2663  *	Inherited from PCI layer (may sleep).
2664  *
2665  *	RETURNS:
2666  *	Zero on success, negative on errno-based value on error.
2667  */
2668 int ata_pci_sff_init_one(struct pci_dev *pdev,
2669 			 const struct ata_port_info * const * ppi,
2670 			 struct scsi_host_template *sht, void *host_priv)
2671 {
2672 	struct device *dev = &pdev->dev;
2673 	const struct ata_port_info *pi = NULL;
2674 	struct ata_host *host = NULL;
2675 	int i, rc;
2676 
2677 	DPRINTK("ENTER\n");
2678 
2679 	/* look up the first valid port_info */
2680 	for (i = 0; i < 2 && ppi[i]; i++) {
2681 		if (ppi[i]->port_ops != &ata_dummy_port_ops) {
2682 			pi = ppi[i];
2683 			break;
2684 		}
2685 	}
2686 
2687 	if (!pi) {
2688 		dev_printk(KERN_ERR, &pdev->dev,
2689 			   "no valid port_info specified\n");
2690 		return -EINVAL;
2691 	}
2692 
2693 	if (!devres_open_group(dev, NULL, GFP_KERNEL))
2694 		return -ENOMEM;
2695 
2696 	rc = pcim_enable_device(pdev);
2697 	if (rc)
2698 		goto out;
2699 
2700 	/* prepare and activate SFF host */
2701 	rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
2702 	if (rc)
2703 		goto out;
2704 	host->private_data = host_priv;
2705 
2706 	pci_set_master(pdev);
2707 	rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht);
2708  out:
2709 	if (rc == 0)
2710 		devres_remove_group(&pdev->dev, NULL);
2711 	else
2712 		devres_release_group(&pdev->dev, NULL);
2713 
2714 	return rc;
2715 }
2716 
2717 #endif /* CONFIG_PCI */
2718 
2719 EXPORT_SYMBOL_GPL(ata_sff_port_ops);
2720 EXPORT_SYMBOL_GPL(ata_bmdma_port_ops);
2721 EXPORT_SYMBOL_GPL(ata_sff_qc_prep);
2722 EXPORT_SYMBOL_GPL(ata_sff_dumb_qc_prep);
2723 EXPORT_SYMBOL_GPL(ata_sff_dev_select);
2724 EXPORT_SYMBOL_GPL(ata_sff_check_status);
2725 EXPORT_SYMBOL_GPL(ata_sff_altstatus);
2726 EXPORT_SYMBOL_GPL(ata_sff_busy_sleep);
2727 EXPORT_SYMBOL_GPL(ata_sff_wait_ready);
2728 EXPORT_SYMBOL_GPL(ata_sff_tf_load);
2729 EXPORT_SYMBOL_GPL(ata_sff_tf_read);
2730 EXPORT_SYMBOL_GPL(ata_sff_exec_command);
2731 EXPORT_SYMBOL_GPL(ata_sff_data_xfer);
2732 EXPORT_SYMBOL_GPL(ata_sff_data_xfer_noirq);
2733 EXPORT_SYMBOL_GPL(ata_sff_irq_on);
2734 EXPORT_SYMBOL_GPL(ata_sff_irq_clear);
2735 EXPORT_SYMBOL_GPL(ata_sff_hsm_move);
2736 EXPORT_SYMBOL_GPL(ata_sff_qc_issue);
2737 EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf);
2738 EXPORT_SYMBOL_GPL(ata_sff_host_intr);
2739 EXPORT_SYMBOL_GPL(ata_sff_interrupt);
2740 EXPORT_SYMBOL_GPL(ata_sff_freeze);
2741 EXPORT_SYMBOL_GPL(ata_sff_thaw);
2742 EXPORT_SYMBOL_GPL(ata_sff_prereset);
2743 EXPORT_SYMBOL_GPL(ata_sff_dev_classify);
2744 EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset);
2745 EXPORT_SYMBOL_GPL(ata_sff_softreset);
2746 EXPORT_SYMBOL_GPL(sata_sff_hardreset);
2747 EXPORT_SYMBOL_GPL(ata_sff_postreset);
2748 EXPORT_SYMBOL_GPL(ata_sff_error_handler);
2749 EXPORT_SYMBOL_GPL(ata_sff_post_internal_cmd);
2750 EXPORT_SYMBOL_GPL(ata_sff_port_start);
2751 EXPORT_SYMBOL_GPL(ata_sff_std_ports);
2752 EXPORT_SYMBOL_GPL(ata_bmdma_mode_filter);
2753 EXPORT_SYMBOL_GPL(ata_bmdma_setup);
2754 EXPORT_SYMBOL_GPL(ata_bmdma_start);
2755 EXPORT_SYMBOL_GPL(ata_bmdma_stop);
2756 EXPORT_SYMBOL_GPL(ata_bmdma_status);
2757 EXPORT_SYMBOL_GPL(ata_bus_reset);
2758 #ifdef CONFIG_PCI
2759 EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex);
2760 EXPORT_SYMBOL_GPL(ata_pci_bmdma_init);
2761 EXPORT_SYMBOL_GPL(ata_pci_sff_init_host);
2762 EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host);
2763 EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host);
2764 EXPORT_SYMBOL_GPL(ata_pci_sff_init_one);
2765 #endif /* CONFIG_PCI */
2766