1 /* 2 * libahci.c - Common AHCI SATA low-level routines 3 * 4 * Maintained by: Tejun Heo <tj@kernel.org> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2004-2005 Red Hat, Inc. 9 * 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; see the file COPYING. If not, write to 23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * 26 * libata documentation is available via 'make {ps|pdf}docs', 27 * as Documentation/driver-api/libata.rst 28 * 29 * AHCI hardware documentation: 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 32 * 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/gfp.h> 37 #include <linux/module.h> 38 #include <linux/blkdev.h> 39 #include <linux/delay.h> 40 #include <linux/interrupt.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/device.h> 43 #include <scsi/scsi_host.h> 44 #include <scsi/scsi_cmnd.h> 45 #include <linux/libata.h> 46 #include <linux/pci.h> 47 #include "ahci.h" 48 #include "libata.h" 49 50 static int ahci_skip_host_reset; 51 int ahci_ignore_sss; 52 EXPORT_SYMBOL_GPL(ahci_ignore_sss); 53 54 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); 55 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); 56 57 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444); 58 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)"); 59 60 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 61 unsigned hints); 62 static ssize_t ahci_led_show(struct ata_port *ap, char *buf); 63 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 64 size_t size); 65 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 66 ssize_t size); 67 68 69 70 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); 71 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); 72 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc); 73 static int ahci_port_start(struct ata_port *ap); 74 static void ahci_port_stop(struct ata_port *ap); 75 static void ahci_qc_prep(struct ata_queued_cmd *qc); 76 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc); 77 static void ahci_freeze(struct ata_port *ap); 78 static void ahci_thaw(struct ata_port *ap); 79 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep); 80 static void ahci_enable_fbs(struct ata_port *ap); 81 static void ahci_disable_fbs(struct ata_port *ap); 82 static void ahci_pmp_attach(struct ata_port *ap); 83 static void ahci_pmp_detach(struct ata_port *ap); 84 static int ahci_softreset(struct ata_link *link, unsigned int *class, 85 unsigned long deadline); 86 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class, 87 unsigned long deadline); 88 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 89 unsigned long deadline); 90 static void ahci_postreset(struct ata_link *link, unsigned int *class); 91 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); 92 static void ahci_dev_config(struct ata_device *dev); 93 #ifdef CONFIG_PM 94 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); 95 #endif 96 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf); 97 static ssize_t ahci_activity_store(struct ata_device *dev, 98 enum sw_activity val); 99 static void ahci_init_sw_activity(struct ata_link *link); 100 101 static ssize_t ahci_show_host_caps(struct device *dev, 102 struct device_attribute *attr, char *buf); 103 static ssize_t ahci_show_host_cap2(struct device *dev, 104 struct device_attribute *attr, char *buf); 105 static ssize_t ahci_show_host_version(struct device *dev, 106 struct device_attribute *attr, char *buf); 107 static ssize_t ahci_show_port_cmd(struct device *dev, 108 struct device_attribute *attr, char *buf); 109 static ssize_t ahci_read_em_buffer(struct device *dev, 110 struct device_attribute *attr, char *buf); 111 static ssize_t ahci_store_em_buffer(struct device *dev, 112 struct device_attribute *attr, 113 const char *buf, size_t size); 114 static ssize_t ahci_show_em_supported(struct device *dev, 115 struct device_attribute *attr, char *buf); 116 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance); 117 118 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL); 119 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL); 120 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL); 121 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL); 122 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO, 123 ahci_read_em_buffer, ahci_store_em_buffer); 124 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL); 125 126 struct device_attribute *ahci_shost_attrs[] = { 127 &dev_attr_link_power_management_policy, 128 &dev_attr_em_message_type, 129 &dev_attr_em_message, 130 &dev_attr_ahci_host_caps, 131 &dev_attr_ahci_host_cap2, 132 &dev_attr_ahci_host_version, 133 &dev_attr_ahci_port_cmd, 134 &dev_attr_em_buffer, 135 &dev_attr_em_message_supported, 136 NULL 137 }; 138 EXPORT_SYMBOL_GPL(ahci_shost_attrs); 139 140 struct device_attribute *ahci_sdev_attrs[] = { 141 &dev_attr_sw_activity, 142 &dev_attr_unload_heads, 143 &dev_attr_ncq_prio_enable, 144 NULL 145 }; 146 EXPORT_SYMBOL_GPL(ahci_sdev_attrs); 147 148 struct ata_port_operations ahci_ops = { 149 .inherits = &sata_pmp_port_ops, 150 151 .qc_defer = ahci_pmp_qc_defer, 152 .qc_prep = ahci_qc_prep, 153 .qc_issue = ahci_qc_issue, 154 .qc_fill_rtf = ahci_qc_fill_rtf, 155 156 .freeze = ahci_freeze, 157 .thaw = ahci_thaw, 158 .softreset = ahci_softreset, 159 .hardreset = ahci_hardreset, 160 .postreset = ahci_postreset, 161 .pmp_softreset = ahci_softreset, 162 .error_handler = ahci_error_handler, 163 .post_internal_cmd = ahci_post_internal_cmd, 164 .dev_config = ahci_dev_config, 165 166 .scr_read = ahci_scr_read, 167 .scr_write = ahci_scr_write, 168 .pmp_attach = ahci_pmp_attach, 169 .pmp_detach = ahci_pmp_detach, 170 171 .set_lpm = ahci_set_lpm, 172 .em_show = ahci_led_show, 173 .em_store = ahci_led_store, 174 .sw_activity_show = ahci_activity_show, 175 .sw_activity_store = ahci_activity_store, 176 .transmit_led_message = ahci_transmit_led_message, 177 #ifdef CONFIG_PM 178 .port_suspend = ahci_port_suspend, 179 .port_resume = ahci_port_resume, 180 #endif 181 .port_start = ahci_port_start, 182 .port_stop = ahci_port_stop, 183 }; 184 EXPORT_SYMBOL_GPL(ahci_ops); 185 186 struct ata_port_operations ahci_pmp_retry_srst_ops = { 187 .inherits = &ahci_ops, 188 .softreset = ahci_pmp_retry_softreset, 189 }; 190 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops); 191 192 static bool ahci_em_messages __read_mostly = true; 193 EXPORT_SYMBOL_GPL(ahci_em_messages); 194 module_param(ahci_em_messages, bool, 0444); 195 /* add other LED protocol types when they become supported */ 196 MODULE_PARM_DESC(ahci_em_messages, 197 "AHCI Enclosure Management Message control (0 = off, 1 = on)"); 198 199 /* device sleep idle timeout in ms */ 200 static int devslp_idle_timeout __read_mostly = 1000; 201 module_param(devslp_idle_timeout, int, 0644); 202 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout"); 203 204 static void ahci_enable_ahci(void __iomem *mmio) 205 { 206 int i; 207 u32 tmp; 208 209 /* turn on AHCI_EN */ 210 tmp = readl(mmio + HOST_CTL); 211 if (tmp & HOST_AHCI_EN) 212 return; 213 214 /* Some controllers need AHCI_EN to be written multiple times. 215 * Try a few times before giving up. 216 */ 217 for (i = 0; i < 5; i++) { 218 tmp |= HOST_AHCI_EN; 219 writel(tmp, mmio + HOST_CTL); 220 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ 221 if (tmp & HOST_AHCI_EN) 222 return; 223 msleep(10); 224 } 225 226 WARN_ON(1); 227 } 228 229 /** 230 * ahci_rpm_get_port - Make sure the port is powered on 231 * @ap: Port to power on 232 * 233 * Whenever there is need to access the AHCI host registers outside of 234 * normal execution paths, call this function to make sure the host is 235 * actually powered on. 236 */ 237 static int ahci_rpm_get_port(struct ata_port *ap) 238 { 239 return pm_runtime_get_sync(ap->dev); 240 } 241 242 /** 243 * ahci_rpm_put_port - Undoes ahci_rpm_get_port() 244 * @ap: Port to power down 245 * 246 * Undoes ahci_rpm_get_port() and possibly powers down the AHCI host 247 * if it has no more active users. 248 */ 249 static void ahci_rpm_put_port(struct ata_port *ap) 250 { 251 pm_runtime_put(ap->dev); 252 } 253 254 static ssize_t ahci_show_host_caps(struct device *dev, 255 struct device_attribute *attr, char *buf) 256 { 257 struct Scsi_Host *shost = class_to_shost(dev); 258 struct ata_port *ap = ata_shost_to_port(shost); 259 struct ahci_host_priv *hpriv = ap->host->private_data; 260 261 return sprintf(buf, "%x\n", hpriv->cap); 262 } 263 264 static ssize_t ahci_show_host_cap2(struct device *dev, 265 struct device_attribute *attr, char *buf) 266 { 267 struct Scsi_Host *shost = class_to_shost(dev); 268 struct ata_port *ap = ata_shost_to_port(shost); 269 struct ahci_host_priv *hpriv = ap->host->private_data; 270 271 return sprintf(buf, "%x\n", hpriv->cap2); 272 } 273 274 static ssize_t ahci_show_host_version(struct device *dev, 275 struct device_attribute *attr, char *buf) 276 { 277 struct Scsi_Host *shost = class_to_shost(dev); 278 struct ata_port *ap = ata_shost_to_port(shost); 279 struct ahci_host_priv *hpriv = ap->host->private_data; 280 281 return sprintf(buf, "%x\n", hpriv->version); 282 } 283 284 static ssize_t ahci_show_port_cmd(struct device *dev, 285 struct device_attribute *attr, char *buf) 286 { 287 struct Scsi_Host *shost = class_to_shost(dev); 288 struct ata_port *ap = ata_shost_to_port(shost); 289 void __iomem *port_mmio = ahci_port_base(ap); 290 ssize_t ret; 291 292 ahci_rpm_get_port(ap); 293 ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD)); 294 ahci_rpm_put_port(ap); 295 296 return ret; 297 } 298 299 static ssize_t ahci_read_em_buffer(struct device *dev, 300 struct device_attribute *attr, char *buf) 301 { 302 struct Scsi_Host *shost = class_to_shost(dev); 303 struct ata_port *ap = ata_shost_to_port(shost); 304 struct ahci_host_priv *hpriv = ap->host->private_data; 305 void __iomem *mmio = hpriv->mmio; 306 void __iomem *em_mmio = mmio + hpriv->em_loc; 307 u32 em_ctl, msg; 308 unsigned long flags; 309 size_t count; 310 int i; 311 312 ahci_rpm_get_port(ap); 313 spin_lock_irqsave(ap->lock, flags); 314 315 em_ctl = readl(mmio + HOST_EM_CTL); 316 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT || 317 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) { 318 spin_unlock_irqrestore(ap->lock, flags); 319 ahci_rpm_put_port(ap); 320 return -EINVAL; 321 } 322 323 if (!(em_ctl & EM_CTL_MR)) { 324 spin_unlock_irqrestore(ap->lock, flags); 325 ahci_rpm_put_port(ap); 326 return -EAGAIN; 327 } 328 329 if (!(em_ctl & EM_CTL_SMB)) 330 em_mmio += hpriv->em_buf_sz; 331 332 count = hpriv->em_buf_sz; 333 334 /* the count should not be larger than PAGE_SIZE */ 335 if (count > PAGE_SIZE) { 336 if (printk_ratelimit()) 337 ata_port_warn(ap, 338 "EM read buffer size too large: " 339 "buffer size %u, page size %lu\n", 340 hpriv->em_buf_sz, PAGE_SIZE); 341 count = PAGE_SIZE; 342 } 343 344 for (i = 0; i < count; i += 4) { 345 msg = readl(em_mmio + i); 346 buf[i] = msg & 0xff; 347 buf[i + 1] = (msg >> 8) & 0xff; 348 buf[i + 2] = (msg >> 16) & 0xff; 349 buf[i + 3] = (msg >> 24) & 0xff; 350 } 351 352 spin_unlock_irqrestore(ap->lock, flags); 353 ahci_rpm_put_port(ap); 354 355 return i; 356 } 357 358 static ssize_t ahci_store_em_buffer(struct device *dev, 359 struct device_attribute *attr, 360 const char *buf, size_t size) 361 { 362 struct Scsi_Host *shost = class_to_shost(dev); 363 struct ata_port *ap = ata_shost_to_port(shost); 364 struct ahci_host_priv *hpriv = ap->host->private_data; 365 void __iomem *mmio = hpriv->mmio; 366 void __iomem *em_mmio = mmio + hpriv->em_loc; 367 const unsigned char *msg_buf = buf; 368 u32 em_ctl, msg; 369 unsigned long flags; 370 int i; 371 372 /* check size validity */ 373 if (!(ap->flags & ATA_FLAG_EM) || 374 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) || 375 size % 4 || size > hpriv->em_buf_sz) 376 return -EINVAL; 377 378 ahci_rpm_get_port(ap); 379 spin_lock_irqsave(ap->lock, flags); 380 381 em_ctl = readl(mmio + HOST_EM_CTL); 382 if (em_ctl & EM_CTL_TM) { 383 spin_unlock_irqrestore(ap->lock, flags); 384 ahci_rpm_put_port(ap); 385 return -EBUSY; 386 } 387 388 for (i = 0; i < size; i += 4) { 389 msg = msg_buf[i] | msg_buf[i + 1] << 8 | 390 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24; 391 writel(msg, em_mmio + i); 392 } 393 394 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 395 396 spin_unlock_irqrestore(ap->lock, flags); 397 ahci_rpm_put_port(ap); 398 399 return size; 400 } 401 402 static ssize_t ahci_show_em_supported(struct device *dev, 403 struct device_attribute *attr, char *buf) 404 { 405 struct Scsi_Host *shost = class_to_shost(dev); 406 struct ata_port *ap = ata_shost_to_port(shost); 407 struct ahci_host_priv *hpriv = ap->host->private_data; 408 void __iomem *mmio = hpriv->mmio; 409 u32 em_ctl; 410 411 ahci_rpm_get_port(ap); 412 em_ctl = readl(mmio + HOST_EM_CTL); 413 ahci_rpm_put_port(ap); 414 415 return sprintf(buf, "%s%s%s%s\n", 416 em_ctl & EM_CTL_LED ? "led " : "", 417 em_ctl & EM_CTL_SAFTE ? "saf-te " : "", 418 em_ctl & EM_CTL_SES ? "ses-2 " : "", 419 em_ctl & EM_CTL_SGPIO ? "sgpio " : ""); 420 } 421 422 /** 423 * ahci_save_initial_config - Save and fixup initial config values 424 * @dev: target AHCI device 425 * @hpriv: host private area to store config values 426 * 427 * Some registers containing configuration info might be setup by 428 * BIOS and might be cleared on reset. This function saves the 429 * initial values of those registers into @hpriv such that they 430 * can be restored after controller reset. 431 * 432 * If inconsistent, config values are fixed up by this function. 433 * 434 * If it is not set already this function sets hpriv->start_engine to 435 * ahci_start_engine. 436 * 437 * LOCKING: 438 * None. 439 */ 440 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv) 441 { 442 void __iomem *mmio = hpriv->mmio; 443 u32 cap, cap2, vers, port_map; 444 int i; 445 446 /* make sure AHCI mode is enabled before accessing CAP */ 447 ahci_enable_ahci(mmio); 448 449 /* Values prefixed with saved_ are written back to host after 450 * reset. Values without are used for driver operation. 451 */ 452 hpriv->saved_cap = cap = readl(mmio + HOST_CAP); 453 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); 454 455 /* CAP2 register is only defined for AHCI 1.2 and later */ 456 vers = readl(mmio + HOST_VERSION); 457 if ((vers >> 16) > 1 || 458 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200)) 459 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2); 460 else 461 hpriv->saved_cap2 = cap2 = 0; 462 463 /* some chips have errata preventing 64bit use */ 464 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { 465 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n"); 466 cap &= ~HOST_CAP_64; 467 } 468 469 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { 470 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n"); 471 cap &= ~HOST_CAP_NCQ; 472 } 473 474 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) { 475 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n"); 476 cap |= HOST_CAP_NCQ; 477 } 478 479 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { 480 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n"); 481 cap &= ~HOST_CAP_PMP; 482 } 483 484 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) { 485 dev_info(dev, 486 "controller can't do SNTF, turning off CAP_SNTF\n"); 487 cap &= ~HOST_CAP_SNTF; 488 } 489 490 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) { 491 dev_info(dev, 492 "controller can't do DEVSLP, turning off\n"); 493 cap2 &= ~HOST_CAP2_SDS; 494 cap2 &= ~HOST_CAP2_SADM; 495 } 496 497 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) { 498 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n"); 499 cap |= HOST_CAP_FBS; 500 } 501 502 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) { 503 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n"); 504 cap &= ~HOST_CAP_FBS; 505 } 506 507 if (!(cap & HOST_CAP_ALPM) && (hpriv->flags & AHCI_HFLAG_YES_ALPM)) { 508 dev_info(dev, "controller can do ALPM, turning on CAP_ALPM\n"); 509 cap |= HOST_CAP_ALPM; 510 } 511 512 if (hpriv->force_port_map && port_map != hpriv->force_port_map) { 513 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n", 514 port_map, hpriv->force_port_map); 515 port_map = hpriv->force_port_map; 516 hpriv->saved_port_map = port_map; 517 } 518 519 if (hpriv->mask_port_map) { 520 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n", 521 port_map, 522 port_map & hpriv->mask_port_map); 523 port_map &= hpriv->mask_port_map; 524 } 525 526 /* cross check port_map and cap.n_ports */ 527 if (port_map) { 528 int map_ports = 0; 529 530 for (i = 0; i < AHCI_MAX_PORTS; i++) 531 if (port_map & (1 << i)) 532 map_ports++; 533 534 /* If PI has more ports than n_ports, whine, clear 535 * port_map and let it be generated from n_ports. 536 */ 537 if (map_ports > ahci_nr_ports(cap)) { 538 dev_warn(dev, 539 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n", 540 port_map, ahci_nr_ports(cap)); 541 port_map = 0; 542 } 543 } 544 545 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */ 546 if (!port_map && vers < 0x10300) { 547 port_map = (1 << ahci_nr_ports(cap)) - 1; 548 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map); 549 550 /* write the fixed up value to the PI register */ 551 hpriv->saved_port_map = port_map; 552 } 553 554 /* record values to use during operation */ 555 hpriv->cap = cap; 556 hpriv->cap2 = cap2; 557 hpriv->version = readl(mmio + HOST_VERSION); 558 hpriv->port_map = port_map; 559 560 if (!hpriv->start_engine) 561 hpriv->start_engine = ahci_start_engine; 562 563 if (!hpriv->stop_engine) 564 hpriv->stop_engine = ahci_stop_engine; 565 566 if (!hpriv->irq_handler) 567 hpriv->irq_handler = ahci_single_level_irq_intr; 568 } 569 EXPORT_SYMBOL_GPL(ahci_save_initial_config); 570 571 /** 572 * ahci_restore_initial_config - Restore initial config 573 * @host: target ATA host 574 * 575 * Restore initial config stored by ahci_save_initial_config(). 576 * 577 * LOCKING: 578 * None. 579 */ 580 static void ahci_restore_initial_config(struct ata_host *host) 581 { 582 struct ahci_host_priv *hpriv = host->private_data; 583 void __iomem *mmio = hpriv->mmio; 584 585 writel(hpriv->saved_cap, mmio + HOST_CAP); 586 if (hpriv->saved_cap2) 587 writel(hpriv->saved_cap2, mmio + HOST_CAP2); 588 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); 589 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ 590 } 591 592 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) 593 { 594 static const int offset[] = { 595 [SCR_STATUS] = PORT_SCR_STAT, 596 [SCR_CONTROL] = PORT_SCR_CTL, 597 [SCR_ERROR] = PORT_SCR_ERR, 598 [SCR_ACTIVE] = PORT_SCR_ACT, 599 [SCR_NOTIFICATION] = PORT_SCR_NTF, 600 }; 601 struct ahci_host_priv *hpriv = ap->host->private_data; 602 603 if (sc_reg < ARRAY_SIZE(offset) && 604 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) 605 return offset[sc_reg]; 606 return 0; 607 } 608 609 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) 610 { 611 void __iomem *port_mmio = ahci_port_base(link->ap); 612 int offset = ahci_scr_offset(link->ap, sc_reg); 613 614 if (offset) { 615 *val = readl(port_mmio + offset); 616 return 0; 617 } 618 return -EINVAL; 619 } 620 621 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) 622 { 623 void __iomem *port_mmio = ahci_port_base(link->ap); 624 int offset = ahci_scr_offset(link->ap, sc_reg); 625 626 if (offset) { 627 writel(val, port_mmio + offset); 628 return 0; 629 } 630 return -EINVAL; 631 } 632 633 void ahci_start_engine(struct ata_port *ap) 634 { 635 void __iomem *port_mmio = ahci_port_base(ap); 636 u32 tmp; 637 638 /* start DMA */ 639 tmp = readl(port_mmio + PORT_CMD); 640 tmp |= PORT_CMD_START; 641 writel(tmp, port_mmio + PORT_CMD); 642 readl(port_mmio + PORT_CMD); /* flush */ 643 } 644 EXPORT_SYMBOL_GPL(ahci_start_engine); 645 646 int ahci_stop_engine(struct ata_port *ap) 647 { 648 void __iomem *port_mmio = ahci_port_base(ap); 649 struct ahci_host_priv *hpriv = ap->host->private_data; 650 u32 tmp; 651 652 /* 653 * On some controllers, stopping a port's DMA engine while the port 654 * is in ALPM state (partial or slumber) results in failures on 655 * subsequent DMA engine starts. For those controllers, put the 656 * port back in active state before stopping its DMA engine. 657 */ 658 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) && 659 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) && 660 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) { 661 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n"); 662 return -EIO; 663 } 664 665 tmp = readl(port_mmio + PORT_CMD); 666 667 /* check if the HBA is idle */ 668 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) 669 return 0; 670 671 /* 672 * Don't try to issue commands but return with ENODEV if the 673 * AHCI controller not available anymore (e.g. due to PCIe hot 674 * unplugging). Otherwise a 500ms delay for each port is added. 675 */ 676 if (tmp == 0xffffffff) { 677 dev_err(ap->host->dev, "AHCI controller unavailable!\n"); 678 return -ENODEV; 679 } 680 681 /* setting HBA to idle */ 682 tmp &= ~PORT_CMD_START; 683 writel(tmp, port_mmio + PORT_CMD); 684 685 /* wait for engine to stop. This could be as long as 500 msec */ 686 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 687 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); 688 if (tmp & PORT_CMD_LIST_ON) 689 return -EIO; 690 691 return 0; 692 } 693 EXPORT_SYMBOL_GPL(ahci_stop_engine); 694 695 void ahci_start_fis_rx(struct ata_port *ap) 696 { 697 void __iomem *port_mmio = ahci_port_base(ap); 698 struct ahci_host_priv *hpriv = ap->host->private_data; 699 struct ahci_port_priv *pp = ap->private_data; 700 u32 tmp; 701 702 /* set FIS registers */ 703 if (hpriv->cap & HOST_CAP_64) 704 writel((pp->cmd_slot_dma >> 16) >> 16, 705 port_mmio + PORT_LST_ADDR_HI); 706 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); 707 708 if (hpriv->cap & HOST_CAP_64) 709 writel((pp->rx_fis_dma >> 16) >> 16, 710 port_mmio + PORT_FIS_ADDR_HI); 711 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); 712 713 /* enable FIS reception */ 714 tmp = readl(port_mmio + PORT_CMD); 715 tmp |= PORT_CMD_FIS_RX; 716 writel(tmp, port_mmio + PORT_CMD); 717 718 /* flush */ 719 readl(port_mmio + PORT_CMD); 720 } 721 EXPORT_SYMBOL_GPL(ahci_start_fis_rx); 722 723 static int ahci_stop_fis_rx(struct ata_port *ap) 724 { 725 void __iomem *port_mmio = ahci_port_base(ap); 726 u32 tmp; 727 728 /* disable FIS reception */ 729 tmp = readl(port_mmio + PORT_CMD); 730 tmp &= ~PORT_CMD_FIS_RX; 731 writel(tmp, port_mmio + PORT_CMD); 732 733 /* wait for completion, spec says 500ms, give it 1000 */ 734 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON, 735 PORT_CMD_FIS_ON, 10, 1000); 736 if (tmp & PORT_CMD_FIS_ON) 737 return -EBUSY; 738 739 return 0; 740 } 741 742 static void ahci_power_up(struct ata_port *ap) 743 { 744 struct ahci_host_priv *hpriv = ap->host->private_data; 745 void __iomem *port_mmio = ahci_port_base(ap); 746 u32 cmd; 747 748 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 749 750 /* spin up device */ 751 if (hpriv->cap & HOST_CAP_SSS) { 752 cmd |= PORT_CMD_SPIN_UP; 753 writel(cmd, port_mmio + PORT_CMD); 754 } 755 756 /* wake up link */ 757 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); 758 } 759 760 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 761 unsigned int hints) 762 { 763 struct ata_port *ap = link->ap; 764 struct ahci_host_priv *hpriv = ap->host->private_data; 765 struct ahci_port_priv *pp = ap->private_data; 766 void __iomem *port_mmio = ahci_port_base(ap); 767 768 if (policy != ATA_LPM_MAX_POWER) { 769 /* wakeup flag only applies to the max power policy */ 770 hints &= ~ATA_LPM_WAKE_ONLY; 771 772 /* 773 * Disable interrupts on Phy Ready. This keeps us from 774 * getting woken up due to spurious phy ready 775 * interrupts. 776 */ 777 pp->intr_mask &= ~PORT_IRQ_PHYRDY; 778 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 779 780 sata_link_scr_lpm(link, policy, false); 781 } 782 783 if (hpriv->cap & HOST_CAP_ALPM) { 784 u32 cmd = readl(port_mmio + PORT_CMD); 785 786 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) { 787 if (!(hints & ATA_LPM_WAKE_ONLY)) 788 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE); 789 cmd |= PORT_CMD_ICC_ACTIVE; 790 791 writel(cmd, port_mmio + PORT_CMD); 792 readl(port_mmio + PORT_CMD); 793 794 /* wait 10ms to be sure we've come out of LPM state */ 795 ata_msleep(ap, 10); 796 797 if (hints & ATA_LPM_WAKE_ONLY) 798 return 0; 799 } else { 800 cmd |= PORT_CMD_ALPE; 801 if (policy == ATA_LPM_MIN_POWER) 802 cmd |= PORT_CMD_ASP; 803 804 /* write out new cmd value */ 805 writel(cmd, port_mmio + PORT_CMD); 806 } 807 } 808 809 /* set aggressive device sleep */ 810 if ((hpriv->cap2 & HOST_CAP2_SDS) && 811 (hpriv->cap2 & HOST_CAP2_SADM) && 812 (link->device->flags & ATA_DFLAG_DEVSLP)) { 813 if (policy == ATA_LPM_MIN_POWER) 814 ahci_set_aggressive_devslp(ap, true); 815 else 816 ahci_set_aggressive_devslp(ap, false); 817 } 818 819 if (policy == ATA_LPM_MAX_POWER) { 820 sata_link_scr_lpm(link, policy, false); 821 822 /* turn PHYRDY IRQ back on */ 823 pp->intr_mask |= PORT_IRQ_PHYRDY; 824 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 825 } 826 827 return 0; 828 } 829 830 #ifdef CONFIG_PM 831 static void ahci_power_down(struct ata_port *ap) 832 { 833 struct ahci_host_priv *hpriv = ap->host->private_data; 834 void __iomem *port_mmio = ahci_port_base(ap); 835 u32 cmd, scontrol; 836 837 if (!(hpriv->cap & HOST_CAP_SSS)) 838 return; 839 840 /* put device into listen mode, first set PxSCTL.DET to 0 */ 841 scontrol = readl(port_mmio + PORT_SCR_CTL); 842 scontrol &= ~0xf; 843 writel(scontrol, port_mmio + PORT_SCR_CTL); 844 845 /* then set PxCMD.SUD to 0 */ 846 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 847 cmd &= ~PORT_CMD_SPIN_UP; 848 writel(cmd, port_mmio + PORT_CMD); 849 } 850 #endif 851 852 static void ahci_start_port(struct ata_port *ap) 853 { 854 struct ahci_host_priv *hpriv = ap->host->private_data; 855 struct ahci_port_priv *pp = ap->private_data; 856 struct ata_link *link; 857 struct ahci_em_priv *emp; 858 ssize_t rc; 859 int i; 860 861 /* enable FIS reception */ 862 ahci_start_fis_rx(ap); 863 864 /* enable DMA */ 865 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE)) 866 hpriv->start_engine(ap); 867 868 /* turn on LEDs */ 869 if (ap->flags & ATA_FLAG_EM) { 870 ata_for_each_link(link, ap, EDGE) { 871 emp = &pp->em_priv[link->pmp]; 872 873 /* EM Transmit bit maybe busy during init */ 874 for (i = 0; i < EM_MAX_RETRY; i++) { 875 rc = ap->ops->transmit_led_message(ap, 876 emp->led_state, 877 4); 878 /* 879 * If busy, give a breather but do not 880 * release EH ownership by using msleep() 881 * instead of ata_msleep(). EM Transmit 882 * bit is busy for the whole host and 883 * releasing ownership will cause other 884 * ports to fail the same way. 885 */ 886 if (rc == -EBUSY) 887 msleep(1); 888 else 889 break; 890 } 891 } 892 } 893 894 if (ap->flags & ATA_FLAG_SW_ACTIVITY) 895 ata_for_each_link(link, ap, EDGE) 896 ahci_init_sw_activity(link); 897 898 } 899 900 static int ahci_deinit_port(struct ata_port *ap, const char **emsg) 901 { 902 int rc; 903 struct ahci_host_priv *hpriv = ap->host->private_data; 904 905 /* disable DMA */ 906 rc = hpriv->stop_engine(ap); 907 if (rc) { 908 *emsg = "failed to stop engine"; 909 return rc; 910 } 911 912 /* disable FIS reception */ 913 rc = ahci_stop_fis_rx(ap); 914 if (rc) { 915 *emsg = "failed stop FIS RX"; 916 return rc; 917 } 918 919 return 0; 920 } 921 922 int ahci_reset_controller(struct ata_host *host) 923 { 924 struct ahci_host_priv *hpriv = host->private_data; 925 void __iomem *mmio = hpriv->mmio; 926 u32 tmp; 927 928 /* we must be in AHCI mode, before using anything 929 * AHCI-specific, such as HOST_RESET. 930 */ 931 ahci_enable_ahci(mmio); 932 933 /* global controller reset */ 934 if (!ahci_skip_host_reset) { 935 tmp = readl(mmio + HOST_CTL); 936 if ((tmp & HOST_RESET) == 0) { 937 writel(tmp | HOST_RESET, mmio + HOST_CTL); 938 readl(mmio + HOST_CTL); /* flush */ 939 } 940 941 /* 942 * to perform host reset, OS should set HOST_RESET 943 * and poll until this bit is read to be "0". 944 * reset must complete within 1 second, or 945 * the hardware should be considered fried. 946 */ 947 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET, 948 HOST_RESET, 10, 1000); 949 950 if (tmp & HOST_RESET) { 951 dev_err(host->dev, "controller reset failed (0x%x)\n", 952 tmp); 953 return -EIO; 954 } 955 956 /* turn on AHCI mode */ 957 ahci_enable_ahci(mmio); 958 959 /* Some registers might be cleared on reset. Restore 960 * initial values. 961 */ 962 if (!(hpriv->flags & AHCI_HFLAG_NO_WRITE_TO_RO)) 963 ahci_restore_initial_config(host); 964 } else 965 dev_info(host->dev, "skipping global host reset\n"); 966 967 return 0; 968 } 969 EXPORT_SYMBOL_GPL(ahci_reset_controller); 970 971 static void ahci_sw_activity(struct ata_link *link) 972 { 973 struct ata_port *ap = link->ap; 974 struct ahci_port_priv *pp = ap->private_data; 975 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 976 977 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY)) 978 return; 979 980 emp->activity++; 981 if (!timer_pending(&emp->timer)) 982 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10)); 983 } 984 985 static void ahci_sw_activity_blink(struct timer_list *t) 986 { 987 struct ahci_em_priv *emp = from_timer(emp, t, timer); 988 struct ata_link *link = emp->link; 989 struct ata_port *ap = link->ap; 990 991 unsigned long led_message = emp->led_state; 992 u32 activity_led_state; 993 unsigned long flags; 994 995 led_message &= EM_MSG_LED_VALUE; 996 led_message |= ap->port_no | (link->pmp << 8); 997 998 /* check to see if we've had activity. If so, 999 * toggle state of LED and reset timer. If not, 1000 * turn LED to desired idle state. 1001 */ 1002 spin_lock_irqsave(ap->lock, flags); 1003 if (emp->saved_activity != emp->activity) { 1004 emp->saved_activity = emp->activity; 1005 /* get the current LED state */ 1006 activity_led_state = led_message & EM_MSG_LED_VALUE_ON; 1007 1008 if (activity_led_state) 1009 activity_led_state = 0; 1010 else 1011 activity_led_state = 1; 1012 1013 /* clear old state */ 1014 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 1015 1016 /* toggle state */ 1017 led_message |= (activity_led_state << 16); 1018 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100)); 1019 } else { 1020 /* switch to idle */ 1021 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 1022 if (emp->blink_policy == BLINK_OFF) 1023 led_message |= (1 << 16); 1024 } 1025 spin_unlock_irqrestore(ap->lock, flags); 1026 ap->ops->transmit_led_message(ap, led_message, 4); 1027 } 1028 1029 static void ahci_init_sw_activity(struct ata_link *link) 1030 { 1031 struct ata_port *ap = link->ap; 1032 struct ahci_port_priv *pp = ap->private_data; 1033 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1034 1035 /* init activity stats, setup timer */ 1036 emp->saved_activity = emp->activity = 0; 1037 emp->link = link; 1038 timer_setup(&emp->timer, ahci_sw_activity_blink, 0); 1039 1040 /* check our blink policy and set flag for link if it's enabled */ 1041 if (emp->blink_policy) 1042 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1043 } 1044 1045 int ahci_reset_em(struct ata_host *host) 1046 { 1047 struct ahci_host_priv *hpriv = host->private_data; 1048 void __iomem *mmio = hpriv->mmio; 1049 u32 em_ctl; 1050 1051 em_ctl = readl(mmio + HOST_EM_CTL); 1052 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST)) 1053 return -EINVAL; 1054 1055 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL); 1056 return 0; 1057 } 1058 EXPORT_SYMBOL_GPL(ahci_reset_em); 1059 1060 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 1061 ssize_t size) 1062 { 1063 struct ahci_host_priv *hpriv = ap->host->private_data; 1064 struct ahci_port_priv *pp = ap->private_data; 1065 void __iomem *mmio = hpriv->mmio; 1066 u32 em_ctl; 1067 u32 message[] = {0, 0}; 1068 unsigned long flags; 1069 int pmp; 1070 struct ahci_em_priv *emp; 1071 1072 /* get the slot number from the message */ 1073 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1074 if (pmp < EM_MAX_SLOTS) 1075 emp = &pp->em_priv[pmp]; 1076 else 1077 return -EINVAL; 1078 1079 ahci_rpm_get_port(ap); 1080 spin_lock_irqsave(ap->lock, flags); 1081 1082 /* 1083 * if we are still busy transmitting a previous message, 1084 * do not allow 1085 */ 1086 em_ctl = readl(mmio + HOST_EM_CTL); 1087 if (em_ctl & EM_CTL_TM) { 1088 spin_unlock_irqrestore(ap->lock, flags); 1089 ahci_rpm_put_port(ap); 1090 return -EBUSY; 1091 } 1092 1093 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) { 1094 /* 1095 * create message header - this is all zero except for 1096 * the message size, which is 4 bytes. 1097 */ 1098 message[0] |= (4 << 8); 1099 1100 /* ignore 0:4 of byte zero, fill in port info yourself */ 1101 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no); 1102 1103 /* write message to EM_LOC */ 1104 writel(message[0], mmio + hpriv->em_loc); 1105 writel(message[1], mmio + hpriv->em_loc+4); 1106 1107 /* 1108 * tell hardware to transmit the message 1109 */ 1110 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 1111 } 1112 1113 /* save off new led state for port/slot */ 1114 emp->led_state = state; 1115 1116 spin_unlock_irqrestore(ap->lock, flags); 1117 ahci_rpm_put_port(ap); 1118 1119 return size; 1120 } 1121 1122 static ssize_t ahci_led_show(struct ata_port *ap, char *buf) 1123 { 1124 struct ahci_port_priv *pp = ap->private_data; 1125 struct ata_link *link; 1126 struct ahci_em_priv *emp; 1127 int rc = 0; 1128 1129 ata_for_each_link(link, ap, EDGE) { 1130 emp = &pp->em_priv[link->pmp]; 1131 rc += sprintf(buf, "%lx\n", emp->led_state); 1132 } 1133 return rc; 1134 } 1135 1136 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 1137 size_t size) 1138 { 1139 unsigned int state; 1140 int pmp; 1141 struct ahci_port_priv *pp = ap->private_data; 1142 struct ahci_em_priv *emp; 1143 1144 if (kstrtouint(buf, 0, &state) < 0) 1145 return -EINVAL; 1146 1147 /* get the slot number from the message */ 1148 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1149 if (pmp < EM_MAX_SLOTS) 1150 emp = &pp->em_priv[pmp]; 1151 else 1152 return -EINVAL; 1153 1154 /* mask off the activity bits if we are in sw_activity 1155 * mode, user should turn off sw_activity before setting 1156 * activity led through em_message 1157 */ 1158 if (emp->blink_policy) 1159 state &= ~EM_MSG_LED_VALUE_ACTIVITY; 1160 1161 return ap->ops->transmit_led_message(ap, state, size); 1162 } 1163 1164 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val) 1165 { 1166 struct ata_link *link = dev->link; 1167 struct ata_port *ap = link->ap; 1168 struct ahci_port_priv *pp = ap->private_data; 1169 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1170 u32 port_led_state = emp->led_state; 1171 1172 /* save the desired Activity LED behavior */ 1173 if (val == OFF) { 1174 /* clear LFLAG */ 1175 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY); 1176 1177 /* set the LED to OFF */ 1178 port_led_state &= EM_MSG_LED_VALUE_OFF; 1179 port_led_state |= (ap->port_no | (link->pmp << 8)); 1180 ap->ops->transmit_led_message(ap, port_led_state, 4); 1181 } else { 1182 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1183 if (val == BLINK_OFF) { 1184 /* set LED to ON for idle */ 1185 port_led_state &= EM_MSG_LED_VALUE_OFF; 1186 port_led_state |= (ap->port_no | (link->pmp << 8)); 1187 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */ 1188 ap->ops->transmit_led_message(ap, port_led_state, 4); 1189 } 1190 } 1191 emp->blink_policy = val; 1192 return 0; 1193 } 1194 1195 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf) 1196 { 1197 struct ata_link *link = dev->link; 1198 struct ata_port *ap = link->ap; 1199 struct ahci_port_priv *pp = ap->private_data; 1200 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1201 1202 /* display the saved value of activity behavior for this 1203 * disk. 1204 */ 1205 return sprintf(buf, "%d\n", emp->blink_policy); 1206 } 1207 1208 static void ahci_port_init(struct device *dev, struct ata_port *ap, 1209 int port_no, void __iomem *mmio, 1210 void __iomem *port_mmio) 1211 { 1212 struct ahci_host_priv *hpriv = ap->host->private_data; 1213 const char *emsg = NULL; 1214 int rc; 1215 u32 tmp; 1216 1217 /* make sure port is not active */ 1218 rc = ahci_deinit_port(ap, &emsg); 1219 if (rc) 1220 dev_warn(dev, "%s (%d)\n", emsg, rc); 1221 1222 /* clear SError */ 1223 tmp = readl(port_mmio + PORT_SCR_ERR); 1224 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); 1225 writel(tmp, port_mmio + PORT_SCR_ERR); 1226 1227 /* clear port IRQ */ 1228 tmp = readl(port_mmio + PORT_IRQ_STAT); 1229 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 1230 if (tmp) 1231 writel(tmp, port_mmio + PORT_IRQ_STAT); 1232 1233 writel(1 << port_no, mmio + HOST_IRQ_STAT); 1234 1235 /* mark esata ports */ 1236 tmp = readl(port_mmio + PORT_CMD); 1237 if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS)) 1238 ap->pflags |= ATA_PFLAG_EXTERNAL; 1239 } 1240 1241 void ahci_init_controller(struct ata_host *host) 1242 { 1243 struct ahci_host_priv *hpriv = host->private_data; 1244 void __iomem *mmio = hpriv->mmio; 1245 int i; 1246 void __iomem *port_mmio; 1247 u32 tmp; 1248 1249 for (i = 0; i < host->n_ports; i++) { 1250 struct ata_port *ap = host->ports[i]; 1251 1252 port_mmio = ahci_port_base(ap); 1253 if (ata_port_is_dummy(ap)) 1254 continue; 1255 1256 ahci_port_init(host->dev, ap, i, mmio, port_mmio); 1257 } 1258 1259 tmp = readl(mmio + HOST_CTL); 1260 VPRINTK("HOST_CTL 0x%x\n", tmp); 1261 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); 1262 tmp = readl(mmio + HOST_CTL); 1263 VPRINTK("HOST_CTL 0x%x\n", tmp); 1264 } 1265 EXPORT_SYMBOL_GPL(ahci_init_controller); 1266 1267 static void ahci_dev_config(struct ata_device *dev) 1268 { 1269 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data; 1270 1271 if (hpriv->flags & AHCI_HFLAG_SECT255) { 1272 dev->max_sectors = 255; 1273 ata_dev_info(dev, 1274 "SB600 AHCI: limiting to 255 sectors per cmd\n"); 1275 } 1276 } 1277 1278 unsigned int ahci_dev_classify(struct ata_port *ap) 1279 { 1280 void __iomem *port_mmio = ahci_port_base(ap); 1281 struct ata_taskfile tf; 1282 u32 tmp; 1283 1284 tmp = readl(port_mmio + PORT_SIG); 1285 tf.lbah = (tmp >> 24) & 0xff; 1286 tf.lbam = (tmp >> 16) & 0xff; 1287 tf.lbal = (tmp >> 8) & 0xff; 1288 tf.nsect = (tmp) & 0xff; 1289 1290 return ata_dev_classify(&tf); 1291 } 1292 EXPORT_SYMBOL_GPL(ahci_dev_classify); 1293 1294 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 1295 u32 opts) 1296 { 1297 dma_addr_t cmd_tbl_dma; 1298 1299 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; 1300 1301 pp->cmd_slot[tag].opts = cpu_to_le32(opts); 1302 pp->cmd_slot[tag].status = 0; 1303 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); 1304 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); 1305 } 1306 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot); 1307 1308 int ahci_kick_engine(struct ata_port *ap) 1309 { 1310 void __iomem *port_mmio = ahci_port_base(ap); 1311 struct ahci_host_priv *hpriv = ap->host->private_data; 1312 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1313 u32 tmp; 1314 int busy, rc; 1315 1316 /* stop engine */ 1317 rc = hpriv->stop_engine(ap); 1318 if (rc) 1319 goto out_restart; 1320 1321 /* need to do CLO? 1322 * always do CLO if PMP is attached (AHCI-1.3 9.2) 1323 */ 1324 busy = status & (ATA_BUSY | ATA_DRQ); 1325 if (!busy && !sata_pmp_attached(ap)) { 1326 rc = 0; 1327 goto out_restart; 1328 } 1329 1330 if (!(hpriv->cap & HOST_CAP_CLO)) { 1331 rc = -EOPNOTSUPP; 1332 goto out_restart; 1333 } 1334 1335 /* perform CLO */ 1336 tmp = readl(port_mmio + PORT_CMD); 1337 tmp |= PORT_CMD_CLO; 1338 writel(tmp, port_mmio + PORT_CMD); 1339 1340 rc = 0; 1341 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 1342 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); 1343 if (tmp & PORT_CMD_CLO) 1344 rc = -EIO; 1345 1346 /* restart engine */ 1347 out_restart: 1348 hpriv->start_engine(ap); 1349 return rc; 1350 } 1351 EXPORT_SYMBOL_GPL(ahci_kick_engine); 1352 1353 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, 1354 struct ata_taskfile *tf, int is_cmd, u16 flags, 1355 unsigned long timeout_msec) 1356 { 1357 const u32 cmd_fis_len = 5; /* five dwords */ 1358 struct ahci_port_priv *pp = ap->private_data; 1359 void __iomem *port_mmio = ahci_port_base(ap); 1360 u8 *fis = pp->cmd_tbl; 1361 u32 tmp; 1362 1363 /* prep the command */ 1364 ata_tf_to_fis(tf, pmp, is_cmd, fis); 1365 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); 1366 1367 /* set port value for softreset of Port Multiplier */ 1368 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) { 1369 tmp = readl(port_mmio + PORT_FBS); 1370 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); 1371 tmp |= pmp << PORT_FBS_DEV_OFFSET; 1372 writel(tmp, port_mmio + PORT_FBS); 1373 pp->fbs_last_dev = pmp; 1374 } 1375 1376 /* issue & wait */ 1377 writel(1, port_mmio + PORT_CMD_ISSUE); 1378 1379 if (timeout_msec) { 1380 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE, 1381 0x1, 0x1, 1, timeout_msec); 1382 if (tmp & 0x1) { 1383 ahci_kick_engine(ap); 1384 return -EBUSY; 1385 } 1386 } else 1387 readl(port_mmio + PORT_CMD_ISSUE); /* flush */ 1388 1389 return 0; 1390 } 1391 1392 int ahci_do_softreset(struct ata_link *link, unsigned int *class, 1393 int pmp, unsigned long deadline, 1394 int (*check_ready)(struct ata_link *link)) 1395 { 1396 struct ata_port *ap = link->ap; 1397 struct ahci_host_priv *hpriv = ap->host->private_data; 1398 struct ahci_port_priv *pp = ap->private_data; 1399 const char *reason = NULL; 1400 unsigned long now, msecs; 1401 struct ata_taskfile tf; 1402 bool fbs_disabled = false; 1403 int rc; 1404 1405 DPRINTK("ENTER\n"); 1406 1407 /* prepare for SRST (AHCI-1.1 10.4.1) */ 1408 rc = ahci_kick_engine(ap); 1409 if (rc && rc != -EOPNOTSUPP) 1410 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc); 1411 1412 /* 1413 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall 1414 * clear PxFBS.EN to '0' prior to issuing software reset to devices 1415 * that is attached to port multiplier. 1416 */ 1417 if (!ata_is_host_link(link) && pp->fbs_enabled) { 1418 ahci_disable_fbs(ap); 1419 fbs_disabled = true; 1420 } 1421 1422 ata_tf_init(link->device, &tf); 1423 1424 /* issue the first H2D Register FIS */ 1425 msecs = 0; 1426 now = jiffies; 1427 if (time_after(deadline, now)) 1428 msecs = jiffies_to_msecs(deadline - now); 1429 1430 tf.ctl |= ATA_SRST; 1431 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, 1432 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { 1433 rc = -EIO; 1434 reason = "1st FIS failed"; 1435 goto fail; 1436 } 1437 1438 /* spec says at least 5us, but be generous and sleep for 1ms */ 1439 ata_msleep(ap, 1); 1440 1441 /* issue the second H2D Register FIS */ 1442 tf.ctl &= ~ATA_SRST; 1443 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); 1444 1445 /* wait for link to become ready */ 1446 rc = ata_wait_after_reset(link, deadline, check_ready); 1447 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) { 1448 /* 1449 * Workaround for cases where link online status can't 1450 * be trusted. Treat device readiness timeout as link 1451 * offline. 1452 */ 1453 ata_link_info(link, "device not ready, treating as offline\n"); 1454 *class = ATA_DEV_NONE; 1455 } else if (rc) { 1456 /* link occupied, -ENODEV too is an error */ 1457 reason = "device not ready"; 1458 goto fail; 1459 } else 1460 *class = ahci_dev_classify(ap); 1461 1462 /* re-enable FBS if disabled before */ 1463 if (fbs_disabled) 1464 ahci_enable_fbs(ap); 1465 1466 DPRINTK("EXIT, class=%u\n", *class); 1467 return 0; 1468 1469 fail: 1470 ata_link_err(link, "softreset failed (%s)\n", reason); 1471 return rc; 1472 } 1473 1474 int ahci_check_ready(struct ata_link *link) 1475 { 1476 void __iomem *port_mmio = ahci_port_base(link->ap); 1477 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1478 1479 return ata_check_ready(status); 1480 } 1481 EXPORT_SYMBOL_GPL(ahci_check_ready); 1482 1483 static int ahci_softreset(struct ata_link *link, unsigned int *class, 1484 unsigned long deadline) 1485 { 1486 int pmp = sata_srst_pmp(link); 1487 1488 DPRINTK("ENTER\n"); 1489 1490 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready); 1491 } 1492 EXPORT_SYMBOL_GPL(ahci_do_softreset); 1493 1494 static int ahci_bad_pmp_check_ready(struct ata_link *link) 1495 { 1496 void __iomem *port_mmio = ahci_port_base(link->ap); 1497 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1498 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT); 1499 1500 /* 1501 * There is no need to check TFDATA if BAD PMP is found due to HW bug, 1502 * which can save timeout delay. 1503 */ 1504 if (irq_status & PORT_IRQ_BAD_PMP) 1505 return -EIO; 1506 1507 return ata_check_ready(status); 1508 } 1509 1510 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class, 1511 unsigned long deadline) 1512 { 1513 struct ata_port *ap = link->ap; 1514 void __iomem *port_mmio = ahci_port_base(ap); 1515 int pmp = sata_srst_pmp(link); 1516 int rc; 1517 u32 irq_sts; 1518 1519 DPRINTK("ENTER\n"); 1520 1521 rc = ahci_do_softreset(link, class, pmp, deadline, 1522 ahci_bad_pmp_check_ready); 1523 1524 /* 1525 * Soft reset fails with IPMS set when PMP is enabled but 1526 * SATA HDD/ODD is connected to SATA port, do soft reset 1527 * again to port 0. 1528 */ 1529 if (rc == -EIO) { 1530 irq_sts = readl(port_mmio + PORT_IRQ_STAT); 1531 if (irq_sts & PORT_IRQ_BAD_PMP) { 1532 ata_link_warn(link, 1533 "applying PMP SRST workaround " 1534 "and retrying\n"); 1535 rc = ahci_do_softreset(link, class, 0, deadline, 1536 ahci_check_ready); 1537 } 1538 } 1539 1540 return rc; 1541 } 1542 1543 int ahci_do_hardreset(struct ata_link *link, unsigned int *class, 1544 unsigned long deadline, bool *online) 1545 { 1546 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 1547 struct ata_port *ap = link->ap; 1548 struct ahci_port_priv *pp = ap->private_data; 1549 struct ahci_host_priv *hpriv = ap->host->private_data; 1550 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 1551 struct ata_taskfile tf; 1552 int rc; 1553 1554 DPRINTK("ENTER\n"); 1555 1556 hpriv->stop_engine(ap); 1557 1558 /* clear D2H reception area to properly wait for D2H FIS */ 1559 ata_tf_init(link->device, &tf); 1560 tf.command = ATA_BUSY; 1561 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 1562 1563 rc = sata_link_hardreset(link, timing, deadline, online, 1564 ahci_check_ready); 1565 1566 hpriv->start_engine(ap); 1567 1568 if (*online) 1569 *class = ahci_dev_classify(ap); 1570 1571 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 1572 return rc; 1573 } 1574 EXPORT_SYMBOL_GPL(ahci_do_hardreset); 1575 1576 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 1577 unsigned long deadline) 1578 { 1579 bool online; 1580 1581 return ahci_do_hardreset(link, class, deadline, &online); 1582 } 1583 1584 static void ahci_postreset(struct ata_link *link, unsigned int *class) 1585 { 1586 struct ata_port *ap = link->ap; 1587 void __iomem *port_mmio = ahci_port_base(ap); 1588 u32 new_tmp, tmp; 1589 1590 ata_std_postreset(link, class); 1591 1592 /* Make sure port's ATAPI bit is set appropriately */ 1593 new_tmp = tmp = readl(port_mmio + PORT_CMD); 1594 if (*class == ATA_DEV_ATAPI) 1595 new_tmp |= PORT_CMD_ATAPI; 1596 else 1597 new_tmp &= ~PORT_CMD_ATAPI; 1598 if (new_tmp != tmp) { 1599 writel(new_tmp, port_mmio + PORT_CMD); 1600 readl(port_mmio + PORT_CMD); /* flush */ 1601 } 1602 } 1603 1604 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) 1605 { 1606 struct scatterlist *sg; 1607 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; 1608 unsigned int si; 1609 1610 VPRINTK("ENTER\n"); 1611 1612 /* 1613 * Next, the S/G list. 1614 */ 1615 for_each_sg(qc->sg, sg, qc->n_elem, si) { 1616 dma_addr_t addr = sg_dma_address(sg); 1617 u32 sg_len = sg_dma_len(sg); 1618 1619 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); 1620 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); 1621 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); 1622 } 1623 1624 return si; 1625 } 1626 1627 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc) 1628 { 1629 struct ata_port *ap = qc->ap; 1630 struct ahci_port_priv *pp = ap->private_data; 1631 1632 if (!sata_pmp_attached(ap) || pp->fbs_enabled) 1633 return ata_std_qc_defer(qc); 1634 else 1635 return sata_pmp_qc_defer_cmd_switch(qc); 1636 } 1637 1638 static void ahci_qc_prep(struct ata_queued_cmd *qc) 1639 { 1640 struct ata_port *ap = qc->ap; 1641 struct ahci_port_priv *pp = ap->private_data; 1642 int is_atapi = ata_is_atapi(qc->tf.protocol); 1643 void *cmd_tbl; 1644 u32 opts; 1645 const u32 cmd_fis_len = 5; /* five dwords */ 1646 unsigned int n_elem; 1647 1648 /* 1649 * Fill in command table information. First, the header, 1650 * a SATA Register - Host to Device command FIS. 1651 */ 1652 cmd_tbl = pp->cmd_tbl + qc->hw_tag * AHCI_CMD_TBL_SZ; 1653 1654 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); 1655 if (is_atapi) { 1656 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); 1657 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); 1658 } 1659 1660 n_elem = 0; 1661 if (qc->flags & ATA_QCFLAG_DMAMAP) 1662 n_elem = ahci_fill_sg(qc, cmd_tbl); 1663 1664 /* 1665 * Fill in command slot information. 1666 */ 1667 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); 1668 if (qc->tf.flags & ATA_TFLAG_WRITE) 1669 opts |= AHCI_CMD_WRITE; 1670 if (is_atapi) 1671 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; 1672 1673 ahci_fill_cmd_slot(pp, qc->hw_tag, opts); 1674 } 1675 1676 static void ahci_fbs_dec_intr(struct ata_port *ap) 1677 { 1678 struct ahci_port_priv *pp = ap->private_data; 1679 void __iomem *port_mmio = ahci_port_base(ap); 1680 u32 fbs = readl(port_mmio + PORT_FBS); 1681 int retries = 3; 1682 1683 DPRINTK("ENTER\n"); 1684 BUG_ON(!pp->fbs_enabled); 1685 1686 /* time to wait for DEC is not specified by AHCI spec, 1687 * add a retry loop for safety. 1688 */ 1689 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS); 1690 fbs = readl(port_mmio + PORT_FBS); 1691 while ((fbs & PORT_FBS_DEC) && retries--) { 1692 udelay(1); 1693 fbs = readl(port_mmio + PORT_FBS); 1694 } 1695 1696 if (fbs & PORT_FBS_DEC) 1697 dev_err(ap->host->dev, "failed to clear device error\n"); 1698 } 1699 1700 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) 1701 { 1702 struct ahci_host_priv *hpriv = ap->host->private_data; 1703 struct ahci_port_priv *pp = ap->private_data; 1704 struct ata_eh_info *host_ehi = &ap->link.eh_info; 1705 struct ata_link *link = NULL; 1706 struct ata_queued_cmd *active_qc; 1707 struct ata_eh_info *active_ehi; 1708 bool fbs_need_dec = false; 1709 u32 serror; 1710 1711 /* determine active link with error */ 1712 if (pp->fbs_enabled) { 1713 void __iomem *port_mmio = ahci_port_base(ap); 1714 u32 fbs = readl(port_mmio + PORT_FBS); 1715 int pmp = fbs >> PORT_FBS_DWE_OFFSET; 1716 1717 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) { 1718 link = &ap->pmp_link[pmp]; 1719 fbs_need_dec = true; 1720 } 1721 1722 } else 1723 ata_for_each_link(link, ap, EDGE) 1724 if (ata_link_active(link)) 1725 break; 1726 1727 if (!link) 1728 link = &ap->link; 1729 1730 active_qc = ata_qc_from_tag(ap, link->active_tag); 1731 active_ehi = &link->eh_info; 1732 1733 /* record irq stat */ 1734 ata_ehi_clear_desc(host_ehi); 1735 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); 1736 1737 /* AHCI needs SError cleared; otherwise, it might lock up */ 1738 ahci_scr_read(&ap->link, SCR_ERROR, &serror); 1739 ahci_scr_write(&ap->link, SCR_ERROR, serror); 1740 host_ehi->serror |= serror; 1741 1742 /* some controllers set IRQ_IF_ERR on device errors, ignore it */ 1743 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) 1744 irq_stat &= ~PORT_IRQ_IF_ERR; 1745 1746 if (irq_stat & PORT_IRQ_TF_ERR) { 1747 /* If qc is active, charge it; otherwise, the active 1748 * link. There's no active qc on NCQ errors. It will 1749 * be determined by EH by reading log page 10h. 1750 */ 1751 if (active_qc) 1752 active_qc->err_mask |= AC_ERR_DEV; 1753 else 1754 active_ehi->err_mask |= AC_ERR_DEV; 1755 1756 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) 1757 host_ehi->serror &= ~SERR_INTERNAL; 1758 } 1759 1760 if (irq_stat & PORT_IRQ_UNK_FIS) { 1761 u32 *unk = pp->rx_fis + RX_FIS_UNK; 1762 1763 active_ehi->err_mask |= AC_ERR_HSM; 1764 active_ehi->action |= ATA_EH_RESET; 1765 ata_ehi_push_desc(active_ehi, 1766 "unknown FIS %08x %08x %08x %08x" , 1767 unk[0], unk[1], unk[2], unk[3]); 1768 } 1769 1770 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) { 1771 active_ehi->err_mask |= AC_ERR_HSM; 1772 active_ehi->action |= ATA_EH_RESET; 1773 ata_ehi_push_desc(active_ehi, "incorrect PMP"); 1774 } 1775 1776 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { 1777 host_ehi->err_mask |= AC_ERR_HOST_BUS; 1778 host_ehi->action |= ATA_EH_RESET; 1779 ata_ehi_push_desc(host_ehi, "host bus error"); 1780 } 1781 1782 if (irq_stat & PORT_IRQ_IF_ERR) { 1783 if (fbs_need_dec) 1784 active_ehi->err_mask |= AC_ERR_DEV; 1785 else { 1786 host_ehi->err_mask |= AC_ERR_ATA_BUS; 1787 host_ehi->action |= ATA_EH_RESET; 1788 } 1789 1790 ata_ehi_push_desc(host_ehi, "interface fatal error"); 1791 } 1792 1793 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { 1794 ata_ehi_hotplugged(host_ehi); 1795 ata_ehi_push_desc(host_ehi, "%s", 1796 irq_stat & PORT_IRQ_CONNECT ? 1797 "connection status changed" : "PHY RDY changed"); 1798 } 1799 1800 /* okay, let's hand over to EH */ 1801 1802 if (irq_stat & PORT_IRQ_FREEZE) 1803 ata_port_freeze(ap); 1804 else if (fbs_need_dec) { 1805 ata_link_abort(link); 1806 ahci_fbs_dec_intr(ap); 1807 } else 1808 ata_port_abort(ap); 1809 } 1810 1811 static void ahci_handle_port_interrupt(struct ata_port *ap, 1812 void __iomem *port_mmio, u32 status) 1813 { 1814 struct ata_eh_info *ehi = &ap->link.eh_info; 1815 struct ahci_port_priv *pp = ap->private_data; 1816 struct ahci_host_priv *hpriv = ap->host->private_data; 1817 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING); 1818 u32 qc_active = 0; 1819 int rc; 1820 1821 /* ignore BAD_PMP while resetting */ 1822 if (unlikely(resetting)) 1823 status &= ~PORT_IRQ_BAD_PMP; 1824 1825 if (sata_lpm_ignore_phy_events(&ap->link)) { 1826 status &= ~PORT_IRQ_PHYRDY; 1827 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG); 1828 } 1829 1830 if (unlikely(status & PORT_IRQ_ERROR)) { 1831 ahci_error_intr(ap, status); 1832 return; 1833 } 1834 1835 if (status & PORT_IRQ_SDB_FIS) { 1836 /* If SNotification is available, leave notification 1837 * handling to sata_async_notification(). If not, 1838 * emulate it by snooping SDB FIS RX area. 1839 * 1840 * Snooping FIS RX area is probably cheaper than 1841 * poking SNotification but some constrollers which 1842 * implement SNotification, ICH9 for example, don't 1843 * store AN SDB FIS into receive area. 1844 */ 1845 if (hpriv->cap & HOST_CAP_SNTF) 1846 sata_async_notification(ap); 1847 else { 1848 /* If the 'N' bit in word 0 of the FIS is set, 1849 * we just received asynchronous notification. 1850 * Tell libata about it. 1851 * 1852 * Lack of SNotification should not appear in 1853 * ahci 1.2, so the workaround is unnecessary 1854 * when FBS is enabled. 1855 */ 1856 if (pp->fbs_enabled) 1857 WARN_ON_ONCE(1); 1858 else { 1859 const __le32 *f = pp->rx_fis + RX_FIS_SDB; 1860 u32 f0 = le32_to_cpu(f[0]); 1861 if (f0 & (1 << 15)) 1862 sata_async_notification(ap); 1863 } 1864 } 1865 } 1866 1867 /* pp->active_link is not reliable once FBS is enabled, both 1868 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because 1869 * NCQ and non-NCQ commands may be in flight at the same time. 1870 */ 1871 if (pp->fbs_enabled) { 1872 if (ap->qc_active) { 1873 qc_active = readl(port_mmio + PORT_SCR_ACT); 1874 qc_active |= readl(port_mmio + PORT_CMD_ISSUE); 1875 } 1876 } else { 1877 /* pp->active_link is valid iff any command is in flight */ 1878 if (ap->qc_active && pp->active_link->sactive) 1879 qc_active = readl(port_mmio + PORT_SCR_ACT); 1880 else 1881 qc_active = readl(port_mmio + PORT_CMD_ISSUE); 1882 } 1883 1884 1885 rc = ata_qc_complete_multiple(ap, qc_active); 1886 1887 /* while resetting, invalid completions are expected */ 1888 if (unlikely(rc < 0 && !resetting)) { 1889 ehi->err_mask |= AC_ERR_HSM; 1890 ehi->action |= ATA_EH_RESET; 1891 ata_port_freeze(ap); 1892 } 1893 } 1894 1895 static void ahci_port_intr(struct ata_port *ap) 1896 { 1897 void __iomem *port_mmio = ahci_port_base(ap); 1898 u32 status; 1899 1900 status = readl(port_mmio + PORT_IRQ_STAT); 1901 writel(status, port_mmio + PORT_IRQ_STAT); 1902 1903 ahci_handle_port_interrupt(ap, port_mmio, status); 1904 } 1905 1906 static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance) 1907 { 1908 struct ata_port *ap = dev_instance; 1909 void __iomem *port_mmio = ahci_port_base(ap); 1910 u32 status; 1911 1912 VPRINTK("ENTER\n"); 1913 1914 status = readl(port_mmio + PORT_IRQ_STAT); 1915 writel(status, port_mmio + PORT_IRQ_STAT); 1916 1917 spin_lock(ap->lock); 1918 ahci_handle_port_interrupt(ap, port_mmio, status); 1919 spin_unlock(ap->lock); 1920 1921 VPRINTK("EXIT\n"); 1922 1923 return IRQ_HANDLED; 1924 } 1925 1926 u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked) 1927 { 1928 unsigned int i, handled = 0; 1929 1930 for (i = 0; i < host->n_ports; i++) { 1931 struct ata_port *ap; 1932 1933 if (!(irq_masked & (1 << i))) 1934 continue; 1935 1936 ap = host->ports[i]; 1937 if (ap) { 1938 ahci_port_intr(ap); 1939 VPRINTK("port %u\n", i); 1940 } else { 1941 VPRINTK("port %u (no irq)\n", i); 1942 if (ata_ratelimit()) 1943 dev_warn(host->dev, 1944 "interrupt on disabled port %u\n", i); 1945 } 1946 1947 handled = 1; 1948 } 1949 1950 return handled; 1951 } 1952 EXPORT_SYMBOL_GPL(ahci_handle_port_intr); 1953 1954 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance) 1955 { 1956 struct ata_host *host = dev_instance; 1957 struct ahci_host_priv *hpriv; 1958 unsigned int rc = 0; 1959 void __iomem *mmio; 1960 u32 irq_stat, irq_masked; 1961 1962 VPRINTK("ENTER\n"); 1963 1964 hpriv = host->private_data; 1965 mmio = hpriv->mmio; 1966 1967 /* sigh. 0xffffffff is a valid return from h/w */ 1968 irq_stat = readl(mmio + HOST_IRQ_STAT); 1969 if (!irq_stat) 1970 return IRQ_NONE; 1971 1972 irq_masked = irq_stat & hpriv->port_map; 1973 1974 spin_lock(&host->lock); 1975 1976 rc = ahci_handle_port_intr(host, irq_masked); 1977 1978 /* HOST_IRQ_STAT behaves as level triggered latch meaning that 1979 * it should be cleared after all the port events are cleared; 1980 * otherwise, it will raise a spurious interrupt after each 1981 * valid one. Please read section 10.6.2 of ahci 1.1 for more 1982 * information. 1983 * 1984 * Also, use the unmasked value to clear interrupt as spurious 1985 * pending event on a dummy port might cause screaming IRQ. 1986 */ 1987 writel(irq_stat, mmio + HOST_IRQ_STAT); 1988 1989 spin_unlock(&host->lock); 1990 1991 VPRINTK("EXIT\n"); 1992 1993 return IRQ_RETVAL(rc); 1994 } 1995 1996 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) 1997 { 1998 struct ata_port *ap = qc->ap; 1999 void __iomem *port_mmio = ahci_port_base(ap); 2000 struct ahci_port_priv *pp = ap->private_data; 2001 2002 /* Keep track of the currently active link. It will be used 2003 * in completion path to determine whether NCQ phase is in 2004 * progress. 2005 */ 2006 pp->active_link = qc->dev->link; 2007 2008 if (ata_is_ncq(qc->tf.protocol)) 2009 writel(1 << qc->hw_tag, port_mmio + PORT_SCR_ACT); 2010 2011 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) { 2012 u32 fbs = readl(port_mmio + PORT_FBS); 2013 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); 2014 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET; 2015 writel(fbs, port_mmio + PORT_FBS); 2016 pp->fbs_last_dev = qc->dev->link->pmp; 2017 } 2018 2019 writel(1 << qc->hw_tag, port_mmio + PORT_CMD_ISSUE); 2020 2021 ahci_sw_activity(qc->dev->link); 2022 2023 return 0; 2024 } 2025 EXPORT_SYMBOL_GPL(ahci_qc_issue); 2026 2027 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc) 2028 { 2029 struct ahci_port_priv *pp = qc->ap->private_data; 2030 u8 *rx_fis = pp->rx_fis; 2031 2032 if (pp->fbs_enabled) 2033 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ; 2034 2035 /* 2036 * After a successful execution of an ATA PIO data-in command, 2037 * the device doesn't send D2H Reg FIS to update the TF and 2038 * the host should take TF and E_Status from the preceding PIO 2039 * Setup FIS. 2040 */ 2041 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE && 2042 !(qc->flags & ATA_QCFLAG_FAILED)) { 2043 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf); 2044 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15]; 2045 } else 2046 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf); 2047 2048 return true; 2049 } 2050 2051 static void ahci_freeze(struct ata_port *ap) 2052 { 2053 void __iomem *port_mmio = ahci_port_base(ap); 2054 2055 /* turn IRQ off */ 2056 writel(0, port_mmio + PORT_IRQ_MASK); 2057 } 2058 2059 static void ahci_thaw(struct ata_port *ap) 2060 { 2061 struct ahci_host_priv *hpriv = ap->host->private_data; 2062 void __iomem *mmio = hpriv->mmio; 2063 void __iomem *port_mmio = ahci_port_base(ap); 2064 u32 tmp; 2065 struct ahci_port_priv *pp = ap->private_data; 2066 2067 /* clear IRQ */ 2068 tmp = readl(port_mmio + PORT_IRQ_STAT); 2069 writel(tmp, port_mmio + PORT_IRQ_STAT); 2070 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); 2071 2072 /* turn IRQ back on */ 2073 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2074 } 2075 2076 void ahci_error_handler(struct ata_port *ap) 2077 { 2078 struct ahci_host_priv *hpriv = ap->host->private_data; 2079 2080 if (!(ap->pflags & ATA_PFLAG_FROZEN)) { 2081 /* restart engine */ 2082 hpriv->stop_engine(ap); 2083 hpriv->start_engine(ap); 2084 } 2085 2086 sata_pmp_error_handler(ap); 2087 2088 if (!ata_dev_enabled(ap->link.device)) 2089 hpriv->stop_engine(ap); 2090 } 2091 EXPORT_SYMBOL_GPL(ahci_error_handler); 2092 2093 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) 2094 { 2095 struct ata_port *ap = qc->ap; 2096 2097 /* make DMA engine forget about the failed command */ 2098 if (qc->flags & ATA_QCFLAG_FAILED) 2099 ahci_kick_engine(ap); 2100 } 2101 2102 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep) 2103 { 2104 struct ahci_host_priv *hpriv = ap->host->private_data; 2105 void __iomem *port_mmio = ahci_port_base(ap); 2106 struct ata_device *dev = ap->link.device; 2107 u32 devslp, dm, dito, mdat, deto; 2108 int rc; 2109 unsigned int err_mask; 2110 2111 devslp = readl(port_mmio + PORT_DEVSLP); 2112 if (!(devslp & PORT_DEVSLP_DSP)) { 2113 dev_info(ap->host->dev, "port does not support device sleep\n"); 2114 return; 2115 } 2116 2117 /* disable device sleep */ 2118 if (!sleep) { 2119 if (devslp & PORT_DEVSLP_ADSE) { 2120 writel(devslp & ~PORT_DEVSLP_ADSE, 2121 port_mmio + PORT_DEVSLP); 2122 err_mask = ata_dev_set_feature(dev, 2123 SETFEATURES_SATA_DISABLE, 2124 SATA_DEVSLP); 2125 if (err_mask && err_mask != AC_ERR_DEV) 2126 ata_dev_warn(dev, "failed to disable DEVSLP\n"); 2127 } 2128 return; 2129 } 2130 2131 /* device sleep was already enabled */ 2132 if (devslp & PORT_DEVSLP_ADSE) 2133 return; 2134 2135 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */ 2136 rc = hpriv->stop_engine(ap); 2137 if (rc) 2138 return; 2139 2140 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET; 2141 dito = devslp_idle_timeout / (dm + 1); 2142 if (dito > 0x3ff) 2143 dito = 0x3ff; 2144 2145 /* Use the nominal value 10 ms if the read MDAT is zero, 2146 * the nominal value of DETO is 20 ms. 2147 */ 2148 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] & 2149 ATA_LOG_DEVSLP_VALID_MASK) { 2150 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] & 2151 ATA_LOG_DEVSLP_MDAT_MASK; 2152 if (!mdat) 2153 mdat = 10; 2154 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO]; 2155 if (!deto) 2156 deto = 20; 2157 } else { 2158 mdat = 10; 2159 deto = 20; 2160 } 2161 2162 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) | 2163 (mdat << PORT_DEVSLP_MDAT_OFFSET) | 2164 (deto << PORT_DEVSLP_DETO_OFFSET) | 2165 PORT_DEVSLP_ADSE); 2166 writel(devslp, port_mmio + PORT_DEVSLP); 2167 2168 hpriv->start_engine(ap); 2169 2170 /* enable device sleep feature for the drive */ 2171 err_mask = ata_dev_set_feature(dev, 2172 SETFEATURES_SATA_ENABLE, 2173 SATA_DEVSLP); 2174 if (err_mask && err_mask != AC_ERR_DEV) 2175 ata_dev_warn(dev, "failed to enable DEVSLP\n"); 2176 } 2177 2178 static void ahci_enable_fbs(struct ata_port *ap) 2179 { 2180 struct ahci_host_priv *hpriv = ap->host->private_data; 2181 struct ahci_port_priv *pp = ap->private_data; 2182 void __iomem *port_mmio = ahci_port_base(ap); 2183 u32 fbs; 2184 int rc; 2185 2186 if (!pp->fbs_supported) 2187 return; 2188 2189 fbs = readl(port_mmio + PORT_FBS); 2190 if (fbs & PORT_FBS_EN) { 2191 pp->fbs_enabled = true; 2192 pp->fbs_last_dev = -1; /* initialization */ 2193 return; 2194 } 2195 2196 rc = hpriv->stop_engine(ap); 2197 if (rc) 2198 return; 2199 2200 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS); 2201 fbs = readl(port_mmio + PORT_FBS); 2202 if (fbs & PORT_FBS_EN) { 2203 dev_info(ap->host->dev, "FBS is enabled\n"); 2204 pp->fbs_enabled = true; 2205 pp->fbs_last_dev = -1; /* initialization */ 2206 } else 2207 dev_err(ap->host->dev, "Failed to enable FBS\n"); 2208 2209 hpriv->start_engine(ap); 2210 } 2211 2212 static void ahci_disable_fbs(struct ata_port *ap) 2213 { 2214 struct ahci_host_priv *hpriv = ap->host->private_data; 2215 struct ahci_port_priv *pp = ap->private_data; 2216 void __iomem *port_mmio = ahci_port_base(ap); 2217 u32 fbs; 2218 int rc; 2219 2220 if (!pp->fbs_supported) 2221 return; 2222 2223 fbs = readl(port_mmio + PORT_FBS); 2224 if ((fbs & PORT_FBS_EN) == 0) { 2225 pp->fbs_enabled = false; 2226 return; 2227 } 2228 2229 rc = hpriv->stop_engine(ap); 2230 if (rc) 2231 return; 2232 2233 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS); 2234 fbs = readl(port_mmio + PORT_FBS); 2235 if (fbs & PORT_FBS_EN) 2236 dev_err(ap->host->dev, "Failed to disable FBS\n"); 2237 else { 2238 dev_info(ap->host->dev, "FBS is disabled\n"); 2239 pp->fbs_enabled = false; 2240 } 2241 2242 hpriv->start_engine(ap); 2243 } 2244 2245 static void ahci_pmp_attach(struct ata_port *ap) 2246 { 2247 void __iomem *port_mmio = ahci_port_base(ap); 2248 struct ahci_port_priv *pp = ap->private_data; 2249 u32 cmd; 2250 2251 cmd = readl(port_mmio + PORT_CMD); 2252 cmd |= PORT_CMD_PMP; 2253 writel(cmd, port_mmio + PORT_CMD); 2254 2255 ahci_enable_fbs(ap); 2256 2257 pp->intr_mask |= PORT_IRQ_BAD_PMP; 2258 2259 /* 2260 * We must not change the port interrupt mask register if the 2261 * port is marked frozen, the value in pp->intr_mask will be 2262 * restored later when the port is thawed. 2263 * 2264 * Note that during initialization, the port is marked as 2265 * frozen since the irq handler is not yet registered. 2266 */ 2267 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 2268 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2269 } 2270 2271 static void ahci_pmp_detach(struct ata_port *ap) 2272 { 2273 void __iomem *port_mmio = ahci_port_base(ap); 2274 struct ahci_port_priv *pp = ap->private_data; 2275 u32 cmd; 2276 2277 ahci_disable_fbs(ap); 2278 2279 cmd = readl(port_mmio + PORT_CMD); 2280 cmd &= ~PORT_CMD_PMP; 2281 writel(cmd, port_mmio + PORT_CMD); 2282 2283 pp->intr_mask &= ~PORT_IRQ_BAD_PMP; 2284 2285 /* see comment above in ahci_pmp_attach() */ 2286 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 2287 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2288 } 2289 2290 int ahci_port_resume(struct ata_port *ap) 2291 { 2292 ahci_rpm_get_port(ap); 2293 2294 ahci_power_up(ap); 2295 ahci_start_port(ap); 2296 2297 if (sata_pmp_attached(ap)) 2298 ahci_pmp_attach(ap); 2299 else 2300 ahci_pmp_detach(ap); 2301 2302 return 0; 2303 } 2304 EXPORT_SYMBOL_GPL(ahci_port_resume); 2305 2306 #ifdef CONFIG_PM 2307 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) 2308 { 2309 const char *emsg = NULL; 2310 int rc; 2311 2312 rc = ahci_deinit_port(ap, &emsg); 2313 if (rc == 0) 2314 ahci_power_down(ap); 2315 else { 2316 ata_port_err(ap, "%s (%d)\n", emsg, rc); 2317 ata_port_freeze(ap); 2318 } 2319 2320 ahci_rpm_put_port(ap); 2321 return rc; 2322 } 2323 #endif 2324 2325 static int ahci_port_start(struct ata_port *ap) 2326 { 2327 struct ahci_host_priv *hpriv = ap->host->private_data; 2328 struct device *dev = ap->host->dev; 2329 struct ahci_port_priv *pp; 2330 void *mem; 2331 dma_addr_t mem_dma; 2332 size_t dma_sz, rx_fis_sz; 2333 2334 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 2335 if (!pp) 2336 return -ENOMEM; 2337 2338 if (ap->host->n_ports > 1) { 2339 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL); 2340 if (!pp->irq_desc) { 2341 devm_kfree(dev, pp); 2342 return -ENOMEM; 2343 } 2344 snprintf(pp->irq_desc, 8, 2345 "%s%d", dev_driver_string(dev), ap->port_no); 2346 } 2347 2348 /* check FBS capability */ 2349 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) { 2350 void __iomem *port_mmio = ahci_port_base(ap); 2351 u32 cmd = readl(port_mmio + PORT_CMD); 2352 if (cmd & PORT_CMD_FBSCP) 2353 pp->fbs_supported = true; 2354 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) { 2355 dev_info(dev, "port %d can do FBS, forcing FBSCP\n", 2356 ap->port_no); 2357 pp->fbs_supported = true; 2358 } else 2359 dev_warn(dev, "port %d is not capable of FBS\n", 2360 ap->port_no); 2361 } 2362 2363 if (pp->fbs_supported) { 2364 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ; 2365 rx_fis_sz = AHCI_RX_FIS_SZ * 16; 2366 } else { 2367 dma_sz = AHCI_PORT_PRIV_DMA_SZ; 2368 rx_fis_sz = AHCI_RX_FIS_SZ; 2369 } 2370 2371 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL); 2372 if (!mem) 2373 return -ENOMEM; 2374 memset(mem, 0, dma_sz); 2375 2376 /* 2377 * First item in chunk of DMA memory: 32-slot command table, 2378 * 32 bytes each in size 2379 */ 2380 pp->cmd_slot = mem; 2381 pp->cmd_slot_dma = mem_dma; 2382 2383 mem += AHCI_CMD_SLOT_SZ; 2384 mem_dma += AHCI_CMD_SLOT_SZ; 2385 2386 /* 2387 * Second item: Received-FIS area 2388 */ 2389 pp->rx_fis = mem; 2390 pp->rx_fis_dma = mem_dma; 2391 2392 mem += rx_fis_sz; 2393 mem_dma += rx_fis_sz; 2394 2395 /* 2396 * Third item: data area for storing a single command 2397 * and its scatter-gather table 2398 */ 2399 pp->cmd_tbl = mem; 2400 pp->cmd_tbl_dma = mem_dma; 2401 2402 /* 2403 * Save off initial list of interrupts to be enabled. 2404 * This could be changed later 2405 */ 2406 pp->intr_mask = DEF_PORT_IRQ; 2407 2408 /* 2409 * Switch to per-port locking in case each port has its own MSI vector. 2410 */ 2411 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) { 2412 spin_lock_init(&pp->lock); 2413 ap->lock = &pp->lock; 2414 } 2415 2416 ap->private_data = pp; 2417 2418 /* engage engines, captain */ 2419 return ahci_port_resume(ap); 2420 } 2421 2422 static void ahci_port_stop(struct ata_port *ap) 2423 { 2424 const char *emsg = NULL; 2425 struct ahci_host_priv *hpriv = ap->host->private_data; 2426 void __iomem *host_mmio = hpriv->mmio; 2427 int rc; 2428 2429 /* de-initialize port */ 2430 rc = ahci_deinit_port(ap, &emsg); 2431 if (rc) 2432 ata_port_warn(ap, "%s (%d)\n", emsg, rc); 2433 2434 /* 2435 * Clear GHC.IS to prevent stuck INTx after disabling MSI and 2436 * re-enabling INTx. 2437 */ 2438 writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT); 2439 } 2440 2441 void ahci_print_info(struct ata_host *host, const char *scc_s) 2442 { 2443 struct ahci_host_priv *hpriv = host->private_data; 2444 u32 vers, cap, cap2, impl, speed; 2445 const char *speed_s; 2446 2447 vers = hpriv->version; 2448 cap = hpriv->cap; 2449 cap2 = hpriv->cap2; 2450 impl = hpriv->port_map; 2451 2452 speed = (cap >> 20) & 0xf; 2453 if (speed == 1) 2454 speed_s = "1.5"; 2455 else if (speed == 2) 2456 speed_s = "3"; 2457 else if (speed == 3) 2458 speed_s = "6"; 2459 else 2460 speed_s = "?"; 2461 2462 dev_info(host->dev, 2463 "AHCI %02x%02x.%02x%02x " 2464 "%u slots %u ports %s Gbps 0x%x impl %s mode\n" 2465 , 2466 2467 (vers >> 24) & 0xff, 2468 (vers >> 16) & 0xff, 2469 (vers >> 8) & 0xff, 2470 vers & 0xff, 2471 2472 ((cap >> 8) & 0x1f) + 1, 2473 (cap & 0x1f) + 1, 2474 speed_s, 2475 impl, 2476 scc_s); 2477 2478 dev_info(host->dev, 2479 "flags: " 2480 "%s%s%s%s%s%s%s" 2481 "%s%s%s%s%s%s%s" 2482 "%s%s%s%s%s%s%s" 2483 "%s%s\n" 2484 , 2485 2486 cap & HOST_CAP_64 ? "64bit " : "", 2487 cap & HOST_CAP_NCQ ? "ncq " : "", 2488 cap & HOST_CAP_SNTF ? "sntf " : "", 2489 cap & HOST_CAP_MPS ? "ilck " : "", 2490 cap & HOST_CAP_SSS ? "stag " : "", 2491 cap & HOST_CAP_ALPM ? "pm " : "", 2492 cap & HOST_CAP_LED ? "led " : "", 2493 cap & HOST_CAP_CLO ? "clo " : "", 2494 cap & HOST_CAP_ONLY ? "only " : "", 2495 cap & HOST_CAP_PMP ? "pmp " : "", 2496 cap & HOST_CAP_FBS ? "fbs " : "", 2497 cap & HOST_CAP_PIO_MULTI ? "pio " : "", 2498 cap & HOST_CAP_SSC ? "slum " : "", 2499 cap & HOST_CAP_PART ? "part " : "", 2500 cap & HOST_CAP_CCC ? "ccc " : "", 2501 cap & HOST_CAP_EMS ? "ems " : "", 2502 cap & HOST_CAP_SXS ? "sxs " : "", 2503 cap2 & HOST_CAP2_DESO ? "deso " : "", 2504 cap2 & HOST_CAP2_SADM ? "sadm " : "", 2505 cap2 & HOST_CAP2_SDS ? "sds " : "", 2506 cap2 & HOST_CAP2_APST ? "apst " : "", 2507 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "", 2508 cap2 & HOST_CAP2_BOH ? "boh " : "" 2509 ); 2510 } 2511 EXPORT_SYMBOL_GPL(ahci_print_info); 2512 2513 void ahci_set_em_messages(struct ahci_host_priv *hpriv, 2514 struct ata_port_info *pi) 2515 { 2516 u8 messages; 2517 void __iomem *mmio = hpriv->mmio; 2518 u32 em_loc = readl(mmio + HOST_EM_LOC); 2519 u32 em_ctl = readl(mmio + HOST_EM_CTL); 2520 2521 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS)) 2522 return; 2523 2524 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16; 2525 2526 if (messages) { 2527 /* store em_loc */ 2528 hpriv->em_loc = ((em_loc >> 16) * 4); 2529 hpriv->em_buf_sz = ((em_loc & 0xff) * 4); 2530 hpriv->em_msg_type = messages; 2531 pi->flags |= ATA_FLAG_EM; 2532 if (!(em_ctl & EM_CTL_ALHD)) 2533 pi->flags |= ATA_FLAG_SW_ACTIVITY; 2534 } 2535 } 2536 EXPORT_SYMBOL_GPL(ahci_set_em_messages); 2537 2538 static int ahci_host_activate_multi_irqs(struct ata_host *host, 2539 struct scsi_host_template *sht) 2540 { 2541 struct ahci_host_priv *hpriv = host->private_data; 2542 int i, rc; 2543 2544 rc = ata_host_start(host); 2545 if (rc) 2546 return rc; 2547 /* 2548 * Requests IRQs according to AHCI-1.1 when multiple MSIs were 2549 * allocated. That is one MSI per port, starting from @irq. 2550 */ 2551 for (i = 0; i < host->n_ports; i++) { 2552 struct ahci_port_priv *pp = host->ports[i]->private_data; 2553 int irq = hpriv->get_irq_vector(host, i); 2554 2555 /* Do not receive interrupts sent by dummy ports */ 2556 if (!pp) { 2557 disable_irq(irq); 2558 continue; 2559 } 2560 2561 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard, 2562 0, pp->irq_desc, host->ports[i]); 2563 2564 if (rc) 2565 return rc; 2566 ata_port_desc(host->ports[i], "irq %d", irq); 2567 } 2568 2569 return ata_host_register(host, sht); 2570 } 2571 2572 /** 2573 * ahci_host_activate - start AHCI host, request IRQs and register it 2574 * @host: target ATA host 2575 * @sht: scsi_host_template to use when registering the host 2576 * 2577 * LOCKING: 2578 * Inherited from calling layer (may sleep). 2579 * 2580 * RETURNS: 2581 * 0 on success, -errno otherwise. 2582 */ 2583 int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht) 2584 { 2585 struct ahci_host_priv *hpriv = host->private_data; 2586 int irq = hpriv->irq; 2587 int rc; 2588 2589 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) { 2590 if (hpriv->irq_handler) 2591 dev_warn(host->dev, 2592 "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n"); 2593 if (!hpriv->get_irq_vector) { 2594 dev_err(host->dev, 2595 "AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n"); 2596 return -EIO; 2597 } 2598 2599 rc = ahci_host_activate_multi_irqs(host, sht); 2600 } else { 2601 rc = ata_host_activate(host, irq, hpriv->irq_handler, 2602 IRQF_SHARED, sht); 2603 } 2604 2605 2606 return rc; 2607 } 2608 EXPORT_SYMBOL_GPL(ahci_host_activate); 2609 2610 MODULE_AUTHOR("Jeff Garzik"); 2611 MODULE_DESCRIPTION("Common AHCI SATA low-level routines"); 2612 MODULE_LICENSE("GPL"); 2613