1 /* 2 * libahci.c - Common AHCI SATA low-level routines 3 * 4 * Maintained by: Tejun Heo <tj@kernel.org> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2004-2005 Red Hat, Inc. 9 * 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; see the file COPYING. If not, write to 23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * 26 * libata documentation is available via 'make {ps|pdf}docs', 27 * as Documentation/driver-api/libata.rst 28 * 29 * AHCI hardware documentation: 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 32 * 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/gfp.h> 37 #include <linux/module.h> 38 #include <linux/blkdev.h> 39 #include <linux/delay.h> 40 #include <linux/interrupt.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/device.h> 43 #include <scsi/scsi_host.h> 44 #include <scsi/scsi_cmnd.h> 45 #include <linux/libata.h> 46 #include <linux/pci.h> 47 #include "ahci.h" 48 #include "libata.h" 49 50 static int ahci_skip_host_reset; 51 int ahci_ignore_sss; 52 EXPORT_SYMBOL_GPL(ahci_ignore_sss); 53 54 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); 55 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); 56 57 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444); 58 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)"); 59 60 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 61 unsigned hints); 62 static ssize_t ahci_led_show(struct ata_port *ap, char *buf); 63 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 64 size_t size); 65 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 66 ssize_t size); 67 68 69 70 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); 71 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); 72 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc); 73 static int ahci_port_start(struct ata_port *ap); 74 static void ahci_port_stop(struct ata_port *ap); 75 static void ahci_qc_prep(struct ata_queued_cmd *qc); 76 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc); 77 static void ahci_freeze(struct ata_port *ap); 78 static void ahci_thaw(struct ata_port *ap); 79 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep); 80 static void ahci_enable_fbs(struct ata_port *ap); 81 static void ahci_disable_fbs(struct ata_port *ap); 82 static void ahci_pmp_attach(struct ata_port *ap); 83 static void ahci_pmp_detach(struct ata_port *ap); 84 static int ahci_softreset(struct ata_link *link, unsigned int *class, 85 unsigned long deadline); 86 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class, 87 unsigned long deadline); 88 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 89 unsigned long deadline); 90 static void ahci_postreset(struct ata_link *link, unsigned int *class); 91 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); 92 static void ahci_dev_config(struct ata_device *dev); 93 #ifdef CONFIG_PM 94 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); 95 #endif 96 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf); 97 static ssize_t ahci_activity_store(struct ata_device *dev, 98 enum sw_activity val); 99 static void ahci_init_sw_activity(struct ata_link *link); 100 101 static ssize_t ahci_show_host_caps(struct device *dev, 102 struct device_attribute *attr, char *buf); 103 static ssize_t ahci_show_host_cap2(struct device *dev, 104 struct device_attribute *attr, char *buf); 105 static ssize_t ahci_show_host_version(struct device *dev, 106 struct device_attribute *attr, char *buf); 107 static ssize_t ahci_show_port_cmd(struct device *dev, 108 struct device_attribute *attr, char *buf); 109 static ssize_t ahci_read_em_buffer(struct device *dev, 110 struct device_attribute *attr, char *buf); 111 static ssize_t ahci_store_em_buffer(struct device *dev, 112 struct device_attribute *attr, 113 const char *buf, size_t size); 114 static ssize_t ahci_show_em_supported(struct device *dev, 115 struct device_attribute *attr, char *buf); 116 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance); 117 118 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL); 119 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL); 120 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL); 121 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL); 122 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO, 123 ahci_read_em_buffer, ahci_store_em_buffer); 124 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL); 125 126 struct device_attribute *ahci_shost_attrs[] = { 127 &dev_attr_link_power_management_policy, 128 &dev_attr_em_message_type, 129 &dev_attr_em_message, 130 &dev_attr_ahci_host_caps, 131 &dev_attr_ahci_host_cap2, 132 &dev_attr_ahci_host_version, 133 &dev_attr_ahci_port_cmd, 134 &dev_attr_em_buffer, 135 &dev_attr_em_message_supported, 136 NULL 137 }; 138 EXPORT_SYMBOL_GPL(ahci_shost_attrs); 139 140 struct device_attribute *ahci_sdev_attrs[] = { 141 &dev_attr_sw_activity, 142 &dev_attr_unload_heads, 143 &dev_attr_ncq_prio_enable, 144 NULL 145 }; 146 EXPORT_SYMBOL_GPL(ahci_sdev_attrs); 147 148 struct ata_port_operations ahci_ops = { 149 .inherits = &sata_pmp_port_ops, 150 151 .qc_defer = ahci_pmp_qc_defer, 152 .qc_prep = ahci_qc_prep, 153 .qc_issue = ahci_qc_issue, 154 .qc_fill_rtf = ahci_qc_fill_rtf, 155 156 .freeze = ahci_freeze, 157 .thaw = ahci_thaw, 158 .softreset = ahci_softreset, 159 .hardreset = ahci_hardreset, 160 .postreset = ahci_postreset, 161 .pmp_softreset = ahci_softreset, 162 .error_handler = ahci_error_handler, 163 .post_internal_cmd = ahci_post_internal_cmd, 164 .dev_config = ahci_dev_config, 165 166 .scr_read = ahci_scr_read, 167 .scr_write = ahci_scr_write, 168 .pmp_attach = ahci_pmp_attach, 169 .pmp_detach = ahci_pmp_detach, 170 171 .set_lpm = ahci_set_lpm, 172 .em_show = ahci_led_show, 173 .em_store = ahci_led_store, 174 .sw_activity_show = ahci_activity_show, 175 .sw_activity_store = ahci_activity_store, 176 .transmit_led_message = ahci_transmit_led_message, 177 #ifdef CONFIG_PM 178 .port_suspend = ahci_port_suspend, 179 .port_resume = ahci_port_resume, 180 #endif 181 .port_start = ahci_port_start, 182 .port_stop = ahci_port_stop, 183 }; 184 EXPORT_SYMBOL_GPL(ahci_ops); 185 186 struct ata_port_operations ahci_pmp_retry_srst_ops = { 187 .inherits = &ahci_ops, 188 .softreset = ahci_pmp_retry_softreset, 189 }; 190 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops); 191 192 static bool ahci_em_messages __read_mostly = true; 193 EXPORT_SYMBOL_GPL(ahci_em_messages); 194 module_param(ahci_em_messages, bool, 0444); 195 /* add other LED protocol types when they become supported */ 196 MODULE_PARM_DESC(ahci_em_messages, 197 "AHCI Enclosure Management Message control (0 = off, 1 = on)"); 198 199 /* device sleep idle timeout in ms */ 200 static int devslp_idle_timeout __read_mostly = 1000; 201 module_param(devslp_idle_timeout, int, 0644); 202 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout"); 203 204 static void ahci_enable_ahci(void __iomem *mmio) 205 { 206 int i; 207 u32 tmp; 208 209 /* turn on AHCI_EN */ 210 tmp = readl(mmio + HOST_CTL); 211 if (tmp & HOST_AHCI_EN) 212 return; 213 214 /* Some controllers need AHCI_EN to be written multiple times. 215 * Try a few times before giving up. 216 */ 217 for (i = 0; i < 5; i++) { 218 tmp |= HOST_AHCI_EN; 219 writel(tmp, mmio + HOST_CTL); 220 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ 221 if (tmp & HOST_AHCI_EN) 222 return; 223 msleep(10); 224 } 225 226 WARN_ON(1); 227 } 228 229 /** 230 * ahci_rpm_get_port - Make sure the port is powered on 231 * @ap: Port to power on 232 * 233 * Whenever there is need to access the AHCI host registers outside of 234 * normal execution paths, call this function to make sure the host is 235 * actually powered on. 236 */ 237 static int ahci_rpm_get_port(struct ata_port *ap) 238 { 239 return pm_runtime_get_sync(ap->dev); 240 } 241 242 /** 243 * ahci_rpm_put_port - Undoes ahci_rpm_get_port() 244 * @ap: Port to power down 245 * 246 * Undoes ahci_rpm_get_port() and possibly powers down the AHCI host 247 * if it has no more active users. 248 */ 249 static void ahci_rpm_put_port(struct ata_port *ap) 250 { 251 pm_runtime_put(ap->dev); 252 } 253 254 static ssize_t ahci_show_host_caps(struct device *dev, 255 struct device_attribute *attr, char *buf) 256 { 257 struct Scsi_Host *shost = class_to_shost(dev); 258 struct ata_port *ap = ata_shost_to_port(shost); 259 struct ahci_host_priv *hpriv = ap->host->private_data; 260 261 return sprintf(buf, "%x\n", hpriv->cap); 262 } 263 264 static ssize_t ahci_show_host_cap2(struct device *dev, 265 struct device_attribute *attr, char *buf) 266 { 267 struct Scsi_Host *shost = class_to_shost(dev); 268 struct ata_port *ap = ata_shost_to_port(shost); 269 struct ahci_host_priv *hpriv = ap->host->private_data; 270 271 return sprintf(buf, "%x\n", hpriv->cap2); 272 } 273 274 static ssize_t ahci_show_host_version(struct device *dev, 275 struct device_attribute *attr, char *buf) 276 { 277 struct Scsi_Host *shost = class_to_shost(dev); 278 struct ata_port *ap = ata_shost_to_port(shost); 279 struct ahci_host_priv *hpriv = ap->host->private_data; 280 281 return sprintf(buf, "%x\n", hpriv->version); 282 } 283 284 static ssize_t ahci_show_port_cmd(struct device *dev, 285 struct device_attribute *attr, char *buf) 286 { 287 struct Scsi_Host *shost = class_to_shost(dev); 288 struct ata_port *ap = ata_shost_to_port(shost); 289 void __iomem *port_mmio = ahci_port_base(ap); 290 ssize_t ret; 291 292 ahci_rpm_get_port(ap); 293 ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD)); 294 ahci_rpm_put_port(ap); 295 296 return ret; 297 } 298 299 static ssize_t ahci_read_em_buffer(struct device *dev, 300 struct device_attribute *attr, char *buf) 301 { 302 struct Scsi_Host *shost = class_to_shost(dev); 303 struct ata_port *ap = ata_shost_to_port(shost); 304 struct ahci_host_priv *hpriv = ap->host->private_data; 305 void __iomem *mmio = hpriv->mmio; 306 void __iomem *em_mmio = mmio + hpriv->em_loc; 307 u32 em_ctl, msg; 308 unsigned long flags; 309 size_t count; 310 int i; 311 312 ahci_rpm_get_port(ap); 313 spin_lock_irqsave(ap->lock, flags); 314 315 em_ctl = readl(mmio + HOST_EM_CTL); 316 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT || 317 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) { 318 spin_unlock_irqrestore(ap->lock, flags); 319 ahci_rpm_put_port(ap); 320 return -EINVAL; 321 } 322 323 if (!(em_ctl & EM_CTL_MR)) { 324 spin_unlock_irqrestore(ap->lock, flags); 325 ahci_rpm_put_port(ap); 326 return -EAGAIN; 327 } 328 329 if (!(em_ctl & EM_CTL_SMB)) 330 em_mmio += hpriv->em_buf_sz; 331 332 count = hpriv->em_buf_sz; 333 334 /* the count should not be larger than PAGE_SIZE */ 335 if (count > PAGE_SIZE) { 336 if (printk_ratelimit()) 337 ata_port_warn(ap, 338 "EM read buffer size too large: " 339 "buffer size %u, page size %lu\n", 340 hpriv->em_buf_sz, PAGE_SIZE); 341 count = PAGE_SIZE; 342 } 343 344 for (i = 0; i < count; i += 4) { 345 msg = readl(em_mmio + i); 346 buf[i] = msg & 0xff; 347 buf[i + 1] = (msg >> 8) & 0xff; 348 buf[i + 2] = (msg >> 16) & 0xff; 349 buf[i + 3] = (msg >> 24) & 0xff; 350 } 351 352 spin_unlock_irqrestore(ap->lock, flags); 353 ahci_rpm_put_port(ap); 354 355 return i; 356 } 357 358 static ssize_t ahci_store_em_buffer(struct device *dev, 359 struct device_attribute *attr, 360 const char *buf, size_t size) 361 { 362 struct Scsi_Host *shost = class_to_shost(dev); 363 struct ata_port *ap = ata_shost_to_port(shost); 364 struct ahci_host_priv *hpriv = ap->host->private_data; 365 void __iomem *mmio = hpriv->mmio; 366 void __iomem *em_mmio = mmio + hpriv->em_loc; 367 const unsigned char *msg_buf = buf; 368 u32 em_ctl, msg; 369 unsigned long flags; 370 int i; 371 372 /* check size validity */ 373 if (!(ap->flags & ATA_FLAG_EM) || 374 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) || 375 size % 4 || size > hpriv->em_buf_sz) 376 return -EINVAL; 377 378 ahci_rpm_get_port(ap); 379 spin_lock_irqsave(ap->lock, flags); 380 381 em_ctl = readl(mmio + HOST_EM_CTL); 382 if (em_ctl & EM_CTL_TM) { 383 spin_unlock_irqrestore(ap->lock, flags); 384 ahci_rpm_put_port(ap); 385 return -EBUSY; 386 } 387 388 for (i = 0; i < size; i += 4) { 389 msg = msg_buf[i] | msg_buf[i + 1] << 8 | 390 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24; 391 writel(msg, em_mmio + i); 392 } 393 394 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 395 396 spin_unlock_irqrestore(ap->lock, flags); 397 ahci_rpm_put_port(ap); 398 399 return size; 400 } 401 402 static ssize_t ahci_show_em_supported(struct device *dev, 403 struct device_attribute *attr, char *buf) 404 { 405 struct Scsi_Host *shost = class_to_shost(dev); 406 struct ata_port *ap = ata_shost_to_port(shost); 407 struct ahci_host_priv *hpriv = ap->host->private_data; 408 void __iomem *mmio = hpriv->mmio; 409 u32 em_ctl; 410 411 ahci_rpm_get_port(ap); 412 em_ctl = readl(mmio + HOST_EM_CTL); 413 ahci_rpm_put_port(ap); 414 415 return sprintf(buf, "%s%s%s%s\n", 416 em_ctl & EM_CTL_LED ? "led " : "", 417 em_ctl & EM_CTL_SAFTE ? "saf-te " : "", 418 em_ctl & EM_CTL_SES ? "ses-2 " : "", 419 em_ctl & EM_CTL_SGPIO ? "sgpio " : ""); 420 } 421 422 /** 423 * ahci_save_initial_config - Save and fixup initial config values 424 * @dev: target AHCI device 425 * @hpriv: host private area to store config values 426 * 427 * Some registers containing configuration info might be setup by 428 * BIOS and might be cleared on reset. This function saves the 429 * initial values of those registers into @hpriv such that they 430 * can be restored after controller reset. 431 * 432 * If inconsistent, config values are fixed up by this function. 433 * 434 * If it is not set already this function sets hpriv->start_engine to 435 * ahci_start_engine. 436 * 437 * LOCKING: 438 * None. 439 */ 440 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv) 441 { 442 void __iomem *mmio = hpriv->mmio; 443 u32 cap, cap2, vers, port_map; 444 int i; 445 446 /* make sure AHCI mode is enabled before accessing CAP */ 447 ahci_enable_ahci(mmio); 448 449 /* Values prefixed with saved_ are written back to host after 450 * reset. Values without are used for driver operation. 451 */ 452 hpriv->saved_cap = cap = readl(mmio + HOST_CAP); 453 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); 454 455 /* CAP2 register is only defined for AHCI 1.2 and later */ 456 vers = readl(mmio + HOST_VERSION); 457 if ((vers >> 16) > 1 || 458 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200)) 459 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2); 460 else 461 hpriv->saved_cap2 = cap2 = 0; 462 463 /* some chips have errata preventing 64bit use */ 464 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { 465 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n"); 466 cap &= ~HOST_CAP_64; 467 } 468 469 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { 470 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n"); 471 cap &= ~HOST_CAP_NCQ; 472 } 473 474 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) { 475 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n"); 476 cap |= HOST_CAP_NCQ; 477 } 478 479 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { 480 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n"); 481 cap &= ~HOST_CAP_PMP; 482 } 483 484 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) { 485 dev_info(dev, 486 "controller can't do SNTF, turning off CAP_SNTF\n"); 487 cap &= ~HOST_CAP_SNTF; 488 } 489 490 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) { 491 dev_info(dev, 492 "controller can't do DEVSLP, turning off\n"); 493 cap2 &= ~HOST_CAP2_SDS; 494 cap2 &= ~HOST_CAP2_SADM; 495 } 496 497 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) { 498 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n"); 499 cap |= HOST_CAP_FBS; 500 } 501 502 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) { 503 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n"); 504 cap &= ~HOST_CAP_FBS; 505 } 506 507 if (!(cap & HOST_CAP_ALPM) && (hpriv->flags & AHCI_HFLAG_YES_ALPM)) { 508 dev_info(dev, "controller can do ALPM, turning on CAP_ALPM\n"); 509 cap |= HOST_CAP_ALPM; 510 } 511 512 if (hpriv->force_port_map && port_map != hpriv->force_port_map) { 513 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n", 514 port_map, hpriv->force_port_map); 515 port_map = hpriv->force_port_map; 516 hpriv->saved_port_map = port_map; 517 } 518 519 if (hpriv->mask_port_map) { 520 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n", 521 port_map, 522 port_map & hpriv->mask_port_map); 523 port_map &= hpriv->mask_port_map; 524 } 525 526 /* cross check port_map and cap.n_ports */ 527 if (port_map) { 528 int map_ports = 0; 529 530 for (i = 0; i < AHCI_MAX_PORTS; i++) 531 if (port_map & (1 << i)) 532 map_ports++; 533 534 /* If PI has more ports than n_ports, whine, clear 535 * port_map and let it be generated from n_ports. 536 */ 537 if (map_ports > ahci_nr_ports(cap)) { 538 dev_warn(dev, 539 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n", 540 port_map, ahci_nr_ports(cap)); 541 port_map = 0; 542 } 543 } 544 545 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */ 546 if (!port_map && vers < 0x10300) { 547 port_map = (1 << ahci_nr_ports(cap)) - 1; 548 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map); 549 550 /* write the fixed up value to the PI register */ 551 hpriv->saved_port_map = port_map; 552 } 553 554 /* record values to use during operation */ 555 hpriv->cap = cap; 556 hpriv->cap2 = cap2; 557 hpriv->version = readl(mmio + HOST_VERSION); 558 hpriv->port_map = port_map; 559 560 if (!hpriv->start_engine) 561 hpriv->start_engine = ahci_start_engine; 562 563 if (!hpriv->irq_handler) 564 hpriv->irq_handler = ahci_single_level_irq_intr; 565 } 566 EXPORT_SYMBOL_GPL(ahci_save_initial_config); 567 568 /** 569 * ahci_restore_initial_config - Restore initial config 570 * @host: target ATA host 571 * 572 * Restore initial config stored by ahci_save_initial_config(). 573 * 574 * LOCKING: 575 * None. 576 */ 577 static void ahci_restore_initial_config(struct ata_host *host) 578 { 579 struct ahci_host_priv *hpriv = host->private_data; 580 void __iomem *mmio = hpriv->mmio; 581 582 writel(hpriv->saved_cap, mmio + HOST_CAP); 583 if (hpriv->saved_cap2) 584 writel(hpriv->saved_cap2, mmio + HOST_CAP2); 585 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); 586 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ 587 } 588 589 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) 590 { 591 static const int offset[] = { 592 [SCR_STATUS] = PORT_SCR_STAT, 593 [SCR_CONTROL] = PORT_SCR_CTL, 594 [SCR_ERROR] = PORT_SCR_ERR, 595 [SCR_ACTIVE] = PORT_SCR_ACT, 596 [SCR_NOTIFICATION] = PORT_SCR_NTF, 597 }; 598 struct ahci_host_priv *hpriv = ap->host->private_data; 599 600 if (sc_reg < ARRAY_SIZE(offset) && 601 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) 602 return offset[sc_reg]; 603 return 0; 604 } 605 606 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) 607 { 608 void __iomem *port_mmio = ahci_port_base(link->ap); 609 int offset = ahci_scr_offset(link->ap, sc_reg); 610 611 if (offset) { 612 *val = readl(port_mmio + offset); 613 return 0; 614 } 615 return -EINVAL; 616 } 617 618 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) 619 { 620 void __iomem *port_mmio = ahci_port_base(link->ap); 621 int offset = ahci_scr_offset(link->ap, sc_reg); 622 623 if (offset) { 624 writel(val, port_mmio + offset); 625 return 0; 626 } 627 return -EINVAL; 628 } 629 630 void ahci_start_engine(struct ata_port *ap) 631 { 632 void __iomem *port_mmio = ahci_port_base(ap); 633 u32 tmp; 634 635 /* start DMA */ 636 tmp = readl(port_mmio + PORT_CMD); 637 tmp |= PORT_CMD_START; 638 writel(tmp, port_mmio + PORT_CMD); 639 readl(port_mmio + PORT_CMD); /* flush */ 640 } 641 EXPORT_SYMBOL_GPL(ahci_start_engine); 642 643 int ahci_stop_engine(struct ata_port *ap) 644 { 645 void __iomem *port_mmio = ahci_port_base(ap); 646 struct ahci_host_priv *hpriv = ap->host->private_data; 647 u32 tmp; 648 649 /* 650 * On some controllers, stopping a port's DMA engine while the port 651 * is in ALPM state (partial or slumber) results in failures on 652 * subsequent DMA engine starts. For those controllers, put the 653 * port back in active state before stopping its DMA engine. 654 */ 655 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) && 656 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) && 657 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) { 658 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n"); 659 return -EIO; 660 } 661 662 tmp = readl(port_mmio + PORT_CMD); 663 664 /* check if the HBA is idle */ 665 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) 666 return 0; 667 668 /* setting HBA to idle */ 669 tmp &= ~PORT_CMD_START; 670 writel(tmp, port_mmio + PORT_CMD); 671 672 /* wait for engine to stop. This could be as long as 500 msec */ 673 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 674 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); 675 if (tmp & PORT_CMD_LIST_ON) 676 return -EIO; 677 678 return 0; 679 } 680 EXPORT_SYMBOL_GPL(ahci_stop_engine); 681 682 void ahci_start_fis_rx(struct ata_port *ap) 683 { 684 void __iomem *port_mmio = ahci_port_base(ap); 685 struct ahci_host_priv *hpriv = ap->host->private_data; 686 struct ahci_port_priv *pp = ap->private_data; 687 u32 tmp; 688 689 /* set FIS registers */ 690 if (hpriv->cap & HOST_CAP_64) 691 writel((pp->cmd_slot_dma >> 16) >> 16, 692 port_mmio + PORT_LST_ADDR_HI); 693 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); 694 695 if (hpriv->cap & HOST_CAP_64) 696 writel((pp->rx_fis_dma >> 16) >> 16, 697 port_mmio + PORT_FIS_ADDR_HI); 698 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); 699 700 /* enable FIS reception */ 701 tmp = readl(port_mmio + PORT_CMD); 702 tmp |= PORT_CMD_FIS_RX; 703 writel(tmp, port_mmio + PORT_CMD); 704 705 /* flush */ 706 readl(port_mmio + PORT_CMD); 707 } 708 EXPORT_SYMBOL_GPL(ahci_start_fis_rx); 709 710 static int ahci_stop_fis_rx(struct ata_port *ap) 711 { 712 void __iomem *port_mmio = ahci_port_base(ap); 713 u32 tmp; 714 715 /* disable FIS reception */ 716 tmp = readl(port_mmio + PORT_CMD); 717 tmp &= ~PORT_CMD_FIS_RX; 718 writel(tmp, port_mmio + PORT_CMD); 719 720 /* wait for completion, spec says 500ms, give it 1000 */ 721 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON, 722 PORT_CMD_FIS_ON, 10, 1000); 723 if (tmp & PORT_CMD_FIS_ON) 724 return -EBUSY; 725 726 return 0; 727 } 728 729 static void ahci_power_up(struct ata_port *ap) 730 { 731 struct ahci_host_priv *hpriv = ap->host->private_data; 732 void __iomem *port_mmio = ahci_port_base(ap); 733 u32 cmd; 734 735 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 736 737 /* spin up device */ 738 if (hpriv->cap & HOST_CAP_SSS) { 739 cmd |= PORT_CMD_SPIN_UP; 740 writel(cmd, port_mmio + PORT_CMD); 741 } 742 743 /* wake up link */ 744 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); 745 } 746 747 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 748 unsigned int hints) 749 { 750 struct ata_port *ap = link->ap; 751 struct ahci_host_priv *hpriv = ap->host->private_data; 752 struct ahci_port_priv *pp = ap->private_data; 753 void __iomem *port_mmio = ahci_port_base(ap); 754 755 if (policy != ATA_LPM_MAX_POWER) { 756 /* wakeup flag only applies to the max power policy */ 757 hints &= ~ATA_LPM_WAKE_ONLY; 758 759 /* 760 * Disable interrupts on Phy Ready. This keeps us from 761 * getting woken up due to spurious phy ready 762 * interrupts. 763 */ 764 pp->intr_mask &= ~PORT_IRQ_PHYRDY; 765 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 766 767 sata_link_scr_lpm(link, policy, false); 768 } 769 770 if (hpriv->cap & HOST_CAP_ALPM) { 771 u32 cmd = readl(port_mmio + PORT_CMD); 772 773 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) { 774 if (!(hints & ATA_LPM_WAKE_ONLY)) 775 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE); 776 cmd |= PORT_CMD_ICC_ACTIVE; 777 778 writel(cmd, port_mmio + PORT_CMD); 779 readl(port_mmio + PORT_CMD); 780 781 /* wait 10ms to be sure we've come out of LPM state */ 782 ata_msleep(ap, 10); 783 784 if (hints & ATA_LPM_WAKE_ONLY) 785 return 0; 786 } else { 787 cmd |= PORT_CMD_ALPE; 788 if (policy == ATA_LPM_MIN_POWER) 789 cmd |= PORT_CMD_ASP; 790 791 /* write out new cmd value */ 792 writel(cmd, port_mmio + PORT_CMD); 793 } 794 } 795 796 /* set aggressive device sleep */ 797 if ((hpriv->cap2 & HOST_CAP2_SDS) && 798 (hpriv->cap2 & HOST_CAP2_SADM) && 799 (link->device->flags & ATA_DFLAG_DEVSLP)) { 800 if (policy == ATA_LPM_MIN_POWER) 801 ahci_set_aggressive_devslp(ap, true); 802 else 803 ahci_set_aggressive_devslp(ap, false); 804 } 805 806 if (policy == ATA_LPM_MAX_POWER) { 807 sata_link_scr_lpm(link, policy, false); 808 809 /* turn PHYRDY IRQ back on */ 810 pp->intr_mask |= PORT_IRQ_PHYRDY; 811 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 812 } 813 814 return 0; 815 } 816 817 #ifdef CONFIG_PM 818 static void ahci_power_down(struct ata_port *ap) 819 { 820 struct ahci_host_priv *hpriv = ap->host->private_data; 821 void __iomem *port_mmio = ahci_port_base(ap); 822 u32 cmd, scontrol; 823 824 if (!(hpriv->cap & HOST_CAP_SSS)) 825 return; 826 827 /* put device into listen mode, first set PxSCTL.DET to 0 */ 828 scontrol = readl(port_mmio + PORT_SCR_CTL); 829 scontrol &= ~0xf; 830 writel(scontrol, port_mmio + PORT_SCR_CTL); 831 832 /* then set PxCMD.SUD to 0 */ 833 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 834 cmd &= ~PORT_CMD_SPIN_UP; 835 writel(cmd, port_mmio + PORT_CMD); 836 } 837 #endif 838 839 static void ahci_start_port(struct ata_port *ap) 840 { 841 struct ahci_host_priv *hpriv = ap->host->private_data; 842 struct ahci_port_priv *pp = ap->private_data; 843 struct ata_link *link; 844 struct ahci_em_priv *emp; 845 ssize_t rc; 846 int i; 847 848 /* enable FIS reception */ 849 ahci_start_fis_rx(ap); 850 851 /* enable DMA */ 852 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE)) 853 hpriv->start_engine(ap); 854 855 /* turn on LEDs */ 856 if (ap->flags & ATA_FLAG_EM) { 857 ata_for_each_link(link, ap, EDGE) { 858 emp = &pp->em_priv[link->pmp]; 859 860 /* EM Transmit bit maybe busy during init */ 861 for (i = 0; i < EM_MAX_RETRY; i++) { 862 rc = ap->ops->transmit_led_message(ap, 863 emp->led_state, 864 4); 865 /* 866 * If busy, give a breather but do not 867 * release EH ownership by using msleep() 868 * instead of ata_msleep(). EM Transmit 869 * bit is busy for the whole host and 870 * releasing ownership will cause other 871 * ports to fail the same way. 872 */ 873 if (rc == -EBUSY) 874 msleep(1); 875 else 876 break; 877 } 878 } 879 } 880 881 if (ap->flags & ATA_FLAG_SW_ACTIVITY) 882 ata_for_each_link(link, ap, EDGE) 883 ahci_init_sw_activity(link); 884 885 } 886 887 static int ahci_deinit_port(struct ata_port *ap, const char **emsg) 888 { 889 int rc; 890 891 /* disable DMA */ 892 rc = ahci_stop_engine(ap); 893 if (rc) { 894 *emsg = "failed to stop engine"; 895 return rc; 896 } 897 898 /* disable FIS reception */ 899 rc = ahci_stop_fis_rx(ap); 900 if (rc) { 901 *emsg = "failed stop FIS RX"; 902 return rc; 903 } 904 905 return 0; 906 } 907 908 int ahci_reset_controller(struct ata_host *host) 909 { 910 struct ahci_host_priv *hpriv = host->private_data; 911 void __iomem *mmio = hpriv->mmio; 912 u32 tmp; 913 914 /* we must be in AHCI mode, before using anything 915 * AHCI-specific, such as HOST_RESET. 916 */ 917 ahci_enable_ahci(mmio); 918 919 /* global controller reset */ 920 if (!ahci_skip_host_reset) { 921 tmp = readl(mmio + HOST_CTL); 922 if ((tmp & HOST_RESET) == 0) { 923 writel(tmp | HOST_RESET, mmio + HOST_CTL); 924 readl(mmio + HOST_CTL); /* flush */ 925 } 926 927 /* 928 * to perform host reset, OS should set HOST_RESET 929 * and poll until this bit is read to be "0". 930 * reset must complete within 1 second, or 931 * the hardware should be considered fried. 932 */ 933 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET, 934 HOST_RESET, 10, 1000); 935 936 if (tmp & HOST_RESET) { 937 dev_err(host->dev, "controller reset failed (0x%x)\n", 938 tmp); 939 return -EIO; 940 } 941 942 /* turn on AHCI mode */ 943 ahci_enable_ahci(mmio); 944 945 /* Some registers might be cleared on reset. Restore 946 * initial values. 947 */ 948 if (!(hpriv->flags & AHCI_HFLAG_NO_WRITE_TO_RO)) 949 ahci_restore_initial_config(host); 950 } else 951 dev_info(host->dev, "skipping global host reset\n"); 952 953 return 0; 954 } 955 EXPORT_SYMBOL_GPL(ahci_reset_controller); 956 957 static void ahci_sw_activity(struct ata_link *link) 958 { 959 struct ata_port *ap = link->ap; 960 struct ahci_port_priv *pp = ap->private_data; 961 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 962 963 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY)) 964 return; 965 966 emp->activity++; 967 if (!timer_pending(&emp->timer)) 968 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10)); 969 } 970 971 static void ahci_sw_activity_blink(unsigned long arg) 972 { 973 struct ata_link *link = (struct ata_link *)arg; 974 struct ata_port *ap = link->ap; 975 struct ahci_port_priv *pp = ap->private_data; 976 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 977 unsigned long led_message = emp->led_state; 978 u32 activity_led_state; 979 unsigned long flags; 980 981 led_message &= EM_MSG_LED_VALUE; 982 led_message |= ap->port_no | (link->pmp << 8); 983 984 /* check to see if we've had activity. If so, 985 * toggle state of LED and reset timer. If not, 986 * turn LED to desired idle state. 987 */ 988 spin_lock_irqsave(ap->lock, flags); 989 if (emp->saved_activity != emp->activity) { 990 emp->saved_activity = emp->activity; 991 /* get the current LED state */ 992 activity_led_state = led_message & EM_MSG_LED_VALUE_ON; 993 994 if (activity_led_state) 995 activity_led_state = 0; 996 else 997 activity_led_state = 1; 998 999 /* clear old state */ 1000 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 1001 1002 /* toggle state */ 1003 led_message |= (activity_led_state << 16); 1004 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100)); 1005 } else { 1006 /* switch to idle */ 1007 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 1008 if (emp->blink_policy == BLINK_OFF) 1009 led_message |= (1 << 16); 1010 } 1011 spin_unlock_irqrestore(ap->lock, flags); 1012 ap->ops->transmit_led_message(ap, led_message, 4); 1013 } 1014 1015 static void ahci_init_sw_activity(struct ata_link *link) 1016 { 1017 struct ata_port *ap = link->ap; 1018 struct ahci_port_priv *pp = ap->private_data; 1019 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1020 1021 /* init activity stats, setup timer */ 1022 emp->saved_activity = emp->activity = 0; 1023 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link); 1024 1025 /* check our blink policy and set flag for link if it's enabled */ 1026 if (emp->blink_policy) 1027 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1028 } 1029 1030 int ahci_reset_em(struct ata_host *host) 1031 { 1032 struct ahci_host_priv *hpriv = host->private_data; 1033 void __iomem *mmio = hpriv->mmio; 1034 u32 em_ctl; 1035 1036 em_ctl = readl(mmio + HOST_EM_CTL); 1037 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST)) 1038 return -EINVAL; 1039 1040 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL); 1041 return 0; 1042 } 1043 EXPORT_SYMBOL_GPL(ahci_reset_em); 1044 1045 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 1046 ssize_t size) 1047 { 1048 struct ahci_host_priv *hpriv = ap->host->private_data; 1049 struct ahci_port_priv *pp = ap->private_data; 1050 void __iomem *mmio = hpriv->mmio; 1051 u32 em_ctl; 1052 u32 message[] = {0, 0}; 1053 unsigned long flags; 1054 int pmp; 1055 struct ahci_em_priv *emp; 1056 1057 /* get the slot number from the message */ 1058 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1059 if (pmp < EM_MAX_SLOTS) 1060 emp = &pp->em_priv[pmp]; 1061 else 1062 return -EINVAL; 1063 1064 ahci_rpm_get_port(ap); 1065 spin_lock_irqsave(ap->lock, flags); 1066 1067 /* 1068 * if we are still busy transmitting a previous message, 1069 * do not allow 1070 */ 1071 em_ctl = readl(mmio + HOST_EM_CTL); 1072 if (em_ctl & EM_CTL_TM) { 1073 spin_unlock_irqrestore(ap->lock, flags); 1074 ahci_rpm_put_port(ap); 1075 return -EBUSY; 1076 } 1077 1078 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) { 1079 /* 1080 * create message header - this is all zero except for 1081 * the message size, which is 4 bytes. 1082 */ 1083 message[0] |= (4 << 8); 1084 1085 /* ignore 0:4 of byte zero, fill in port info yourself */ 1086 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no); 1087 1088 /* write message to EM_LOC */ 1089 writel(message[0], mmio + hpriv->em_loc); 1090 writel(message[1], mmio + hpriv->em_loc+4); 1091 1092 /* 1093 * tell hardware to transmit the message 1094 */ 1095 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 1096 } 1097 1098 /* save off new led state for port/slot */ 1099 emp->led_state = state; 1100 1101 spin_unlock_irqrestore(ap->lock, flags); 1102 ahci_rpm_put_port(ap); 1103 1104 return size; 1105 } 1106 1107 static ssize_t ahci_led_show(struct ata_port *ap, char *buf) 1108 { 1109 struct ahci_port_priv *pp = ap->private_data; 1110 struct ata_link *link; 1111 struct ahci_em_priv *emp; 1112 int rc = 0; 1113 1114 ata_for_each_link(link, ap, EDGE) { 1115 emp = &pp->em_priv[link->pmp]; 1116 rc += sprintf(buf, "%lx\n", emp->led_state); 1117 } 1118 return rc; 1119 } 1120 1121 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 1122 size_t size) 1123 { 1124 unsigned int state; 1125 int pmp; 1126 struct ahci_port_priv *pp = ap->private_data; 1127 struct ahci_em_priv *emp; 1128 1129 if (kstrtouint(buf, 0, &state) < 0) 1130 return -EINVAL; 1131 1132 /* get the slot number from the message */ 1133 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1134 if (pmp < EM_MAX_SLOTS) 1135 emp = &pp->em_priv[pmp]; 1136 else 1137 return -EINVAL; 1138 1139 /* mask off the activity bits if we are in sw_activity 1140 * mode, user should turn off sw_activity before setting 1141 * activity led through em_message 1142 */ 1143 if (emp->blink_policy) 1144 state &= ~EM_MSG_LED_VALUE_ACTIVITY; 1145 1146 return ap->ops->transmit_led_message(ap, state, size); 1147 } 1148 1149 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val) 1150 { 1151 struct ata_link *link = dev->link; 1152 struct ata_port *ap = link->ap; 1153 struct ahci_port_priv *pp = ap->private_data; 1154 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1155 u32 port_led_state = emp->led_state; 1156 1157 /* save the desired Activity LED behavior */ 1158 if (val == OFF) { 1159 /* clear LFLAG */ 1160 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY); 1161 1162 /* set the LED to OFF */ 1163 port_led_state &= EM_MSG_LED_VALUE_OFF; 1164 port_led_state |= (ap->port_no | (link->pmp << 8)); 1165 ap->ops->transmit_led_message(ap, port_led_state, 4); 1166 } else { 1167 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1168 if (val == BLINK_OFF) { 1169 /* set LED to ON for idle */ 1170 port_led_state &= EM_MSG_LED_VALUE_OFF; 1171 port_led_state |= (ap->port_no | (link->pmp << 8)); 1172 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */ 1173 ap->ops->transmit_led_message(ap, port_led_state, 4); 1174 } 1175 } 1176 emp->blink_policy = val; 1177 return 0; 1178 } 1179 1180 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf) 1181 { 1182 struct ata_link *link = dev->link; 1183 struct ata_port *ap = link->ap; 1184 struct ahci_port_priv *pp = ap->private_data; 1185 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1186 1187 /* display the saved value of activity behavior for this 1188 * disk. 1189 */ 1190 return sprintf(buf, "%d\n", emp->blink_policy); 1191 } 1192 1193 static void ahci_port_init(struct device *dev, struct ata_port *ap, 1194 int port_no, void __iomem *mmio, 1195 void __iomem *port_mmio) 1196 { 1197 struct ahci_host_priv *hpriv = ap->host->private_data; 1198 const char *emsg = NULL; 1199 int rc; 1200 u32 tmp; 1201 1202 /* make sure port is not active */ 1203 rc = ahci_deinit_port(ap, &emsg); 1204 if (rc) 1205 dev_warn(dev, "%s (%d)\n", emsg, rc); 1206 1207 /* clear SError */ 1208 tmp = readl(port_mmio + PORT_SCR_ERR); 1209 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); 1210 writel(tmp, port_mmio + PORT_SCR_ERR); 1211 1212 /* clear port IRQ */ 1213 tmp = readl(port_mmio + PORT_IRQ_STAT); 1214 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 1215 if (tmp) 1216 writel(tmp, port_mmio + PORT_IRQ_STAT); 1217 1218 writel(1 << port_no, mmio + HOST_IRQ_STAT); 1219 1220 /* mark esata ports */ 1221 tmp = readl(port_mmio + PORT_CMD); 1222 if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS)) 1223 ap->pflags |= ATA_PFLAG_EXTERNAL; 1224 } 1225 1226 void ahci_init_controller(struct ata_host *host) 1227 { 1228 struct ahci_host_priv *hpriv = host->private_data; 1229 void __iomem *mmio = hpriv->mmio; 1230 int i; 1231 void __iomem *port_mmio; 1232 u32 tmp; 1233 1234 for (i = 0; i < host->n_ports; i++) { 1235 struct ata_port *ap = host->ports[i]; 1236 1237 port_mmio = ahci_port_base(ap); 1238 if (ata_port_is_dummy(ap)) 1239 continue; 1240 1241 ahci_port_init(host->dev, ap, i, mmio, port_mmio); 1242 } 1243 1244 tmp = readl(mmio + HOST_CTL); 1245 VPRINTK("HOST_CTL 0x%x\n", tmp); 1246 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); 1247 tmp = readl(mmio + HOST_CTL); 1248 VPRINTK("HOST_CTL 0x%x\n", tmp); 1249 } 1250 EXPORT_SYMBOL_GPL(ahci_init_controller); 1251 1252 static void ahci_dev_config(struct ata_device *dev) 1253 { 1254 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data; 1255 1256 if (hpriv->flags & AHCI_HFLAG_SECT255) { 1257 dev->max_sectors = 255; 1258 ata_dev_info(dev, 1259 "SB600 AHCI: limiting to 255 sectors per cmd\n"); 1260 } 1261 } 1262 1263 unsigned int ahci_dev_classify(struct ata_port *ap) 1264 { 1265 void __iomem *port_mmio = ahci_port_base(ap); 1266 struct ata_taskfile tf; 1267 u32 tmp; 1268 1269 tmp = readl(port_mmio + PORT_SIG); 1270 tf.lbah = (tmp >> 24) & 0xff; 1271 tf.lbam = (tmp >> 16) & 0xff; 1272 tf.lbal = (tmp >> 8) & 0xff; 1273 tf.nsect = (tmp) & 0xff; 1274 1275 return ata_dev_classify(&tf); 1276 } 1277 EXPORT_SYMBOL_GPL(ahci_dev_classify); 1278 1279 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 1280 u32 opts) 1281 { 1282 dma_addr_t cmd_tbl_dma; 1283 1284 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; 1285 1286 pp->cmd_slot[tag].opts = cpu_to_le32(opts); 1287 pp->cmd_slot[tag].status = 0; 1288 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); 1289 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); 1290 } 1291 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot); 1292 1293 int ahci_kick_engine(struct ata_port *ap) 1294 { 1295 void __iomem *port_mmio = ahci_port_base(ap); 1296 struct ahci_host_priv *hpriv = ap->host->private_data; 1297 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1298 u32 tmp; 1299 int busy, rc; 1300 1301 /* stop engine */ 1302 rc = ahci_stop_engine(ap); 1303 if (rc) 1304 goto out_restart; 1305 1306 /* need to do CLO? 1307 * always do CLO if PMP is attached (AHCI-1.3 9.2) 1308 */ 1309 busy = status & (ATA_BUSY | ATA_DRQ); 1310 if (!busy && !sata_pmp_attached(ap)) { 1311 rc = 0; 1312 goto out_restart; 1313 } 1314 1315 if (!(hpriv->cap & HOST_CAP_CLO)) { 1316 rc = -EOPNOTSUPP; 1317 goto out_restart; 1318 } 1319 1320 /* perform CLO */ 1321 tmp = readl(port_mmio + PORT_CMD); 1322 tmp |= PORT_CMD_CLO; 1323 writel(tmp, port_mmio + PORT_CMD); 1324 1325 rc = 0; 1326 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 1327 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); 1328 if (tmp & PORT_CMD_CLO) 1329 rc = -EIO; 1330 1331 /* restart engine */ 1332 out_restart: 1333 hpriv->start_engine(ap); 1334 return rc; 1335 } 1336 EXPORT_SYMBOL_GPL(ahci_kick_engine); 1337 1338 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, 1339 struct ata_taskfile *tf, int is_cmd, u16 flags, 1340 unsigned long timeout_msec) 1341 { 1342 const u32 cmd_fis_len = 5; /* five dwords */ 1343 struct ahci_port_priv *pp = ap->private_data; 1344 void __iomem *port_mmio = ahci_port_base(ap); 1345 u8 *fis = pp->cmd_tbl; 1346 u32 tmp; 1347 1348 /* prep the command */ 1349 ata_tf_to_fis(tf, pmp, is_cmd, fis); 1350 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); 1351 1352 /* set port value for softreset of Port Multiplier */ 1353 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) { 1354 tmp = readl(port_mmio + PORT_FBS); 1355 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); 1356 tmp |= pmp << PORT_FBS_DEV_OFFSET; 1357 writel(tmp, port_mmio + PORT_FBS); 1358 pp->fbs_last_dev = pmp; 1359 } 1360 1361 /* issue & wait */ 1362 writel(1, port_mmio + PORT_CMD_ISSUE); 1363 1364 if (timeout_msec) { 1365 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE, 1366 0x1, 0x1, 1, timeout_msec); 1367 if (tmp & 0x1) { 1368 ahci_kick_engine(ap); 1369 return -EBUSY; 1370 } 1371 } else 1372 readl(port_mmio + PORT_CMD_ISSUE); /* flush */ 1373 1374 return 0; 1375 } 1376 1377 int ahci_do_softreset(struct ata_link *link, unsigned int *class, 1378 int pmp, unsigned long deadline, 1379 int (*check_ready)(struct ata_link *link)) 1380 { 1381 struct ata_port *ap = link->ap; 1382 struct ahci_host_priv *hpriv = ap->host->private_data; 1383 struct ahci_port_priv *pp = ap->private_data; 1384 const char *reason = NULL; 1385 unsigned long now, msecs; 1386 struct ata_taskfile tf; 1387 bool fbs_disabled = false; 1388 int rc; 1389 1390 DPRINTK("ENTER\n"); 1391 1392 /* prepare for SRST (AHCI-1.1 10.4.1) */ 1393 rc = ahci_kick_engine(ap); 1394 if (rc && rc != -EOPNOTSUPP) 1395 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc); 1396 1397 /* 1398 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall 1399 * clear PxFBS.EN to '0' prior to issuing software reset to devices 1400 * that is attached to port multiplier. 1401 */ 1402 if (!ata_is_host_link(link) && pp->fbs_enabled) { 1403 ahci_disable_fbs(ap); 1404 fbs_disabled = true; 1405 } 1406 1407 ata_tf_init(link->device, &tf); 1408 1409 /* issue the first H2D Register FIS */ 1410 msecs = 0; 1411 now = jiffies; 1412 if (time_after(deadline, now)) 1413 msecs = jiffies_to_msecs(deadline - now); 1414 1415 tf.ctl |= ATA_SRST; 1416 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, 1417 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { 1418 rc = -EIO; 1419 reason = "1st FIS failed"; 1420 goto fail; 1421 } 1422 1423 /* spec says at least 5us, but be generous and sleep for 1ms */ 1424 ata_msleep(ap, 1); 1425 1426 /* issue the second H2D Register FIS */ 1427 tf.ctl &= ~ATA_SRST; 1428 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); 1429 1430 /* wait for link to become ready */ 1431 rc = ata_wait_after_reset(link, deadline, check_ready); 1432 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) { 1433 /* 1434 * Workaround for cases where link online status can't 1435 * be trusted. Treat device readiness timeout as link 1436 * offline. 1437 */ 1438 ata_link_info(link, "device not ready, treating as offline\n"); 1439 *class = ATA_DEV_NONE; 1440 } else if (rc) { 1441 /* link occupied, -ENODEV too is an error */ 1442 reason = "device not ready"; 1443 goto fail; 1444 } else 1445 *class = ahci_dev_classify(ap); 1446 1447 /* re-enable FBS if disabled before */ 1448 if (fbs_disabled) 1449 ahci_enable_fbs(ap); 1450 1451 DPRINTK("EXIT, class=%u\n", *class); 1452 return 0; 1453 1454 fail: 1455 ata_link_err(link, "softreset failed (%s)\n", reason); 1456 return rc; 1457 } 1458 1459 int ahci_check_ready(struct ata_link *link) 1460 { 1461 void __iomem *port_mmio = ahci_port_base(link->ap); 1462 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1463 1464 return ata_check_ready(status); 1465 } 1466 EXPORT_SYMBOL_GPL(ahci_check_ready); 1467 1468 static int ahci_softreset(struct ata_link *link, unsigned int *class, 1469 unsigned long deadline) 1470 { 1471 int pmp = sata_srst_pmp(link); 1472 1473 DPRINTK("ENTER\n"); 1474 1475 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready); 1476 } 1477 EXPORT_SYMBOL_GPL(ahci_do_softreset); 1478 1479 static int ahci_bad_pmp_check_ready(struct ata_link *link) 1480 { 1481 void __iomem *port_mmio = ahci_port_base(link->ap); 1482 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1483 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT); 1484 1485 /* 1486 * There is no need to check TFDATA if BAD PMP is found due to HW bug, 1487 * which can save timeout delay. 1488 */ 1489 if (irq_status & PORT_IRQ_BAD_PMP) 1490 return -EIO; 1491 1492 return ata_check_ready(status); 1493 } 1494 1495 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class, 1496 unsigned long deadline) 1497 { 1498 struct ata_port *ap = link->ap; 1499 void __iomem *port_mmio = ahci_port_base(ap); 1500 int pmp = sata_srst_pmp(link); 1501 int rc; 1502 u32 irq_sts; 1503 1504 DPRINTK("ENTER\n"); 1505 1506 rc = ahci_do_softreset(link, class, pmp, deadline, 1507 ahci_bad_pmp_check_ready); 1508 1509 /* 1510 * Soft reset fails with IPMS set when PMP is enabled but 1511 * SATA HDD/ODD is connected to SATA port, do soft reset 1512 * again to port 0. 1513 */ 1514 if (rc == -EIO) { 1515 irq_sts = readl(port_mmio + PORT_IRQ_STAT); 1516 if (irq_sts & PORT_IRQ_BAD_PMP) { 1517 ata_link_warn(link, 1518 "applying PMP SRST workaround " 1519 "and retrying\n"); 1520 rc = ahci_do_softreset(link, class, 0, deadline, 1521 ahci_check_ready); 1522 } 1523 } 1524 1525 return rc; 1526 } 1527 1528 int ahci_do_hardreset(struct ata_link *link, unsigned int *class, 1529 unsigned long deadline, bool *online) 1530 { 1531 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 1532 struct ata_port *ap = link->ap; 1533 struct ahci_port_priv *pp = ap->private_data; 1534 struct ahci_host_priv *hpriv = ap->host->private_data; 1535 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 1536 struct ata_taskfile tf; 1537 int rc; 1538 1539 DPRINTK("ENTER\n"); 1540 1541 ahci_stop_engine(ap); 1542 1543 /* clear D2H reception area to properly wait for D2H FIS */ 1544 ata_tf_init(link->device, &tf); 1545 tf.command = ATA_BUSY; 1546 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 1547 1548 rc = sata_link_hardreset(link, timing, deadline, online, 1549 ahci_check_ready); 1550 1551 hpriv->start_engine(ap); 1552 1553 if (*online) 1554 *class = ahci_dev_classify(ap); 1555 1556 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 1557 return rc; 1558 } 1559 EXPORT_SYMBOL_GPL(ahci_do_hardreset); 1560 1561 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 1562 unsigned long deadline) 1563 { 1564 bool online; 1565 1566 return ahci_do_hardreset(link, class, deadline, &online); 1567 } 1568 1569 static void ahci_postreset(struct ata_link *link, unsigned int *class) 1570 { 1571 struct ata_port *ap = link->ap; 1572 void __iomem *port_mmio = ahci_port_base(ap); 1573 u32 new_tmp, tmp; 1574 1575 ata_std_postreset(link, class); 1576 1577 /* Make sure port's ATAPI bit is set appropriately */ 1578 new_tmp = tmp = readl(port_mmio + PORT_CMD); 1579 if (*class == ATA_DEV_ATAPI) 1580 new_tmp |= PORT_CMD_ATAPI; 1581 else 1582 new_tmp &= ~PORT_CMD_ATAPI; 1583 if (new_tmp != tmp) { 1584 writel(new_tmp, port_mmio + PORT_CMD); 1585 readl(port_mmio + PORT_CMD); /* flush */ 1586 } 1587 } 1588 1589 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) 1590 { 1591 struct scatterlist *sg; 1592 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; 1593 unsigned int si; 1594 1595 VPRINTK("ENTER\n"); 1596 1597 /* 1598 * Next, the S/G list. 1599 */ 1600 for_each_sg(qc->sg, sg, qc->n_elem, si) { 1601 dma_addr_t addr = sg_dma_address(sg); 1602 u32 sg_len = sg_dma_len(sg); 1603 1604 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); 1605 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); 1606 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); 1607 } 1608 1609 return si; 1610 } 1611 1612 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc) 1613 { 1614 struct ata_port *ap = qc->ap; 1615 struct ahci_port_priv *pp = ap->private_data; 1616 1617 if (!sata_pmp_attached(ap) || pp->fbs_enabled) 1618 return ata_std_qc_defer(qc); 1619 else 1620 return sata_pmp_qc_defer_cmd_switch(qc); 1621 } 1622 1623 static void ahci_qc_prep(struct ata_queued_cmd *qc) 1624 { 1625 struct ata_port *ap = qc->ap; 1626 struct ahci_port_priv *pp = ap->private_data; 1627 int is_atapi = ata_is_atapi(qc->tf.protocol); 1628 void *cmd_tbl; 1629 u32 opts; 1630 const u32 cmd_fis_len = 5; /* five dwords */ 1631 unsigned int n_elem; 1632 1633 /* 1634 * Fill in command table information. First, the header, 1635 * a SATA Register - Host to Device command FIS. 1636 */ 1637 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; 1638 1639 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); 1640 if (is_atapi) { 1641 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); 1642 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); 1643 } 1644 1645 n_elem = 0; 1646 if (qc->flags & ATA_QCFLAG_DMAMAP) 1647 n_elem = ahci_fill_sg(qc, cmd_tbl); 1648 1649 /* 1650 * Fill in command slot information. 1651 */ 1652 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); 1653 if (qc->tf.flags & ATA_TFLAG_WRITE) 1654 opts |= AHCI_CMD_WRITE; 1655 if (is_atapi) 1656 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; 1657 1658 ahci_fill_cmd_slot(pp, qc->tag, opts); 1659 } 1660 1661 static void ahci_fbs_dec_intr(struct ata_port *ap) 1662 { 1663 struct ahci_port_priv *pp = ap->private_data; 1664 void __iomem *port_mmio = ahci_port_base(ap); 1665 u32 fbs = readl(port_mmio + PORT_FBS); 1666 int retries = 3; 1667 1668 DPRINTK("ENTER\n"); 1669 BUG_ON(!pp->fbs_enabled); 1670 1671 /* time to wait for DEC is not specified by AHCI spec, 1672 * add a retry loop for safety. 1673 */ 1674 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS); 1675 fbs = readl(port_mmio + PORT_FBS); 1676 while ((fbs & PORT_FBS_DEC) && retries--) { 1677 udelay(1); 1678 fbs = readl(port_mmio + PORT_FBS); 1679 } 1680 1681 if (fbs & PORT_FBS_DEC) 1682 dev_err(ap->host->dev, "failed to clear device error\n"); 1683 } 1684 1685 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) 1686 { 1687 struct ahci_host_priv *hpriv = ap->host->private_data; 1688 struct ahci_port_priv *pp = ap->private_data; 1689 struct ata_eh_info *host_ehi = &ap->link.eh_info; 1690 struct ata_link *link = NULL; 1691 struct ata_queued_cmd *active_qc; 1692 struct ata_eh_info *active_ehi; 1693 bool fbs_need_dec = false; 1694 u32 serror; 1695 1696 /* determine active link with error */ 1697 if (pp->fbs_enabled) { 1698 void __iomem *port_mmio = ahci_port_base(ap); 1699 u32 fbs = readl(port_mmio + PORT_FBS); 1700 int pmp = fbs >> PORT_FBS_DWE_OFFSET; 1701 1702 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) { 1703 link = &ap->pmp_link[pmp]; 1704 fbs_need_dec = true; 1705 } 1706 1707 } else 1708 ata_for_each_link(link, ap, EDGE) 1709 if (ata_link_active(link)) 1710 break; 1711 1712 if (!link) 1713 link = &ap->link; 1714 1715 active_qc = ata_qc_from_tag(ap, link->active_tag); 1716 active_ehi = &link->eh_info; 1717 1718 /* record irq stat */ 1719 ata_ehi_clear_desc(host_ehi); 1720 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); 1721 1722 /* AHCI needs SError cleared; otherwise, it might lock up */ 1723 ahci_scr_read(&ap->link, SCR_ERROR, &serror); 1724 ahci_scr_write(&ap->link, SCR_ERROR, serror); 1725 host_ehi->serror |= serror; 1726 1727 /* some controllers set IRQ_IF_ERR on device errors, ignore it */ 1728 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) 1729 irq_stat &= ~PORT_IRQ_IF_ERR; 1730 1731 if (irq_stat & PORT_IRQ_TF_ERR) { 1732 /* If qc is active, charge it; otherwise, the active 1733 * link. There's no active qc on NCQ errors. It will 1734 * be determined by EH by reading log page 10h. 1735 */ 1736 if (active_qc) 1737 active_qc->err_mask |= AC_ERR_DEV; 1738 else 1739 active_ehi->err_mask |= AC_ERR_DEV; 1740 1741 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) 1742 host_ehi->serror &= ~SERR_INTERNAL; 1743 } 1744 1745 if (irq_stat & PORT_IRQ_UNK_FIS) { 1746 u32 *unk = pp->rx_fis + RX_FIS_UNK; 1747 1748 active_ehi->err_mask |= AC_ERR_HSM; 1749 active_ehi->action |= ATA_EH_RESET; 1750 ata_ehi_push_desc(active_ehi, 1751 "unknown FIS %08x %08x %08x %08x" , 1752 unk[0], unk[1], unk[2], unk[3]); 1753 } 1754 1755 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) { 1756 active_ehi->err_mask |= AC_ERR_HSM; 1757 active_ehi->action |= ATA_EH_RESET; 1758 ata_ehi_push_desc(active_ehi, "incorrect PMP"); 1759 } 1760 1761 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { 1762 host_ehi->err_mask |= AC_ERR_HOST_BUS; 1763 host_ehi->action |= ATA_EH_RESET; 1764 ata_ehi_push_desc(host_ehi, "host bus error"); 1765 } 1766 1767 if (irq_stat & PORT_IRQ_IF_ERR) { 1768 if (fbs_need_dec) 1769 active_ehi->err_mask |= AC_ERR_DEV; 1770 else { 1771 host_ehi->err_mask |= AC_ERR_ATA_BUS; 1772 host_ehi->action |= ATA_EH_RESET; 1773 } 1774 1775 ata_ehi_push_desc(host_ehi, "interface fatal error"); 1776 } 1777 1778 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { 1779 ata_ehi_hotplugged(host_ehi); 1780 ata_ehi_push_desc(host_ehi, "%s", 1781 irq_stat & PORT_IRQ_CONNECT ? 1782 "connection status changed" : "PHY RDY changed"); 1783 } 1784 1785 /* okay, let's hand over to EH */ 1786 1787 if (irq_stat & PORT_IRQ_FREEZE) 1788 ata_port_freeze(ap); 1789 else if (fbs_need_dec) { 1790 ata_link_abort(link); 1791 ahci_fbs_dec_intr(ap); 1792 } else 1793 ata_port_abort(ap); 1794 } 1795 1796 static void ahci_handle_port_interrupt(struct ata_port *ap, 1797 void __iomem *port_mmio, u32 status) 1798 { 1799 struct ata_eh_info *ehi = &ap->link.eh_info; 1800 struct ahci_port_priv *pp = ap->private_data; 1801 struct ahci_host_priv *hpriv = ap->host->private_data; 1802 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING); 1803 u32 qc_active = 0; 1804 int rc; 1805 1806 /* ignore BAD_PMP while resetting */ 1807 if (unlikely(resetting)) 1808 status &= ~PORT_IRQ_BAD_PMP; 1809 1810 if (sata_lpm_ignore_phy_events(&ap->link)) { 1811 status &= ~PORT_IRQ_PHYRDY; 1812 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG); 1813 } 1814 1815 if (unlikely(status & PORT_IRQ_ERROR)) { 1816 ahci_error_intr(ap, status); 1817 return; 1818 } 1819 1820 if (status & PORT_IRQ_SDB_FIS) { 1821 /* If SNotification is available, leave notification 1822 * handling to sata_async_notification(). If not, 1823 * emulate it by snooping SDB FIS RX area. 1824 * 1825 * Snooping FIS RX area is probably cheaper than 1826 * poking SNotification but some constrollers which 1827 * implement SNotification, ICH9 for example, don't 1828 * store AN SDB FIS into receive area. 1829 */ 1830 if (hpriv->cap & HOST_CAP_SNTF) 1831 sata_async_notification(ap); 1832 else { 1833 /* If the 'N' bit in word 0 of the FIS is set, 1834 * we just received asynchronous notification. 1835 * Tell libata about it. 1836 * 1837 * Lack of SNotification should not appear in 1838 * ahci 1.2, so the workaround is unnecessary 1839 * when FBS is enabled. 1840 */ 1841 if (pp->fbs_enabled) 1842 WARN_ON_ONCE(1); 1843 else { 1844 const __le32 *f = pp->rx_fis + RX_FIS_SDB; 1845 u32 f0 = le32_to_cpu(f[0]); 1846 if (f0 & (1 << 15)) 1847 sata_async_notification(ap); 1848 } 1849 } 1850 } 1851 1852 /* pp->active_link is not reliable once FBS is enabled, both 1853 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because 1854 * NCQ and non-NCQ commands may be in flight at the same time. 1855 */ 1856 if (pp->fbs_enabled) { 1857 if (ap->qc_active) { 1858 qc_active = readl(port_mmio + PORT_SCR_ACT); 1859 qc_active |= readl(port_mmio + PORT_CMD_ISSUE); 1860 } 1861 } else { 1862 /* pp->active_link is valid iff any command is in flight */ 1863 if (ap->qc_active && pp->active_link->sactive) 1864 qc_active = readl(port_mmio + PORT_SCR_ACT); 1865 else 1866 qc_active = readl(port_mmio + PORT_CMD_ISSUE); 1867 } 1868 1869 1870 rc = ata_qc_complete_multiple(ap, qc_active); 1871 1872 /* while resetting, invalid completions are expected */ 1873 if (unlikely(rc < 0 && !resetting)) { 1874 ehi->err_mask |= AC_ERR_HSM; 1875 ehi->action |= ATA_EH_RESET; 1876 ata_port_freeze(ap); 1877 } 1878 } 1879 1880 static void ahci_port_intr(struct ata_port *ap) 1881 { 1882 void __iomem *port_mmio = ahci_port_base(ap); 1883 u32 status; 1884 1885 status = readl(port_mmio + PORT_IRQ_STAT); 1886 writel(status, port_mmio + PORT_IRQ_STAT); 1887 1888 ahci_handle_port_interrupt(ap, port_mmio, status); 1889 } 1890 1891 static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance) 1892 { 1893 struct ata_port *ap = dev_instance; 1894 void __iomem *port_mmio = ahci_port_base(ap); 1895 u32 status; 1896 1897 VPRINTK("ENTER\n"); 1898 1899 status = readl(port_mmio + PORT_IRQ_STAT); 1900 writel(status, port_mmio + PORT_IRQ_STAT); 1901 1902 spin_lock(ap->lock); 1903 ahci_handle_port_interrupt(ap, port_mmio, status); 1904 spin_unlock(ap->lock); 1905 1906 VPRINTK("EXIT\n"); 1907 1908 return IRQ_HANDLED; 1909 } 1910 1911 u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked) 1912 { 1913 unsigned int i, handled = 0; 1914 1915 for (i = 0; i < host->n_ports; i++) { 1916 struct ata_port *ap; 1917 1918 if (!(irq_masked & (1 << i))) 1919 continue; 1920 1921 ap = host->ports[i]; 1922 if (ap) { 1923 ahci_port_intr(ap); 1924 VPRINTK("port %u\n", i); 1925 } else { 1926 VPRINTK("port %u (no irq)\n", i); 1927 if (ata_ratelimit()) 1928 dev_warn(host->dev, 1929 "interrupt on disabled port %u\n", i); 1930 } 1931 1932 handled = 1; 1933 } 1934 1935 return handled; 1936 } 1937 EXPORT_SYMBOL_GPL(ahci_handle_port_intr); 1938 1939 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance) 1940 { 1941 struct ata_host *host = dev_instance; 1942 struct ahci_host_priv *hpriv; 1943 unsigned int rc = 0; 1944 void __iomem *mmio; 1945 u32 irq_stat, irq_masked; 1946 1947 VPRINTK("ENTER\n"); 1948 1949 hpriv = host->private_data; 1950 mmio = hpriv->mmio; 1951 1952 /* sigh. 0xffffffff is a valid return from h/w */ 1953 irq_stat = readl(mmio + HOST_IRQ_STAT); 1954 if (!irq_stat) 1955 return IRQ_NONE; 1956 1957 irq_masked = irq_stat & hpriv->port_map; 1958 1959 spin_lock(&host->lock); 1960 1961 rc = ahci_handle_port_intr(host, irq_masked); 1962 1963 /* HOST_IRQ_STAT behaves as level triggered latch meaning that 1964 * it should be cleared after all the port events are cleared; 1965 * otherwise, it will raise a spurious interrupt after each 1966 * valid one. Please read section 10.6.2 of ahci 1.1 for more 1967 * information. 1968 * 1969 * Also, use the unmasked value to clear interrupt as spurious 1970 * pending event on a dummy port might cause screaming IRQ. 1971 */ 1972 writel(irq_stat, mmio + HOST_IRQ_STAT); 1973 1974 spin_unlock(&host->lock); 1975 1976 VPRINTK("EXIT\n"); 1977 1978 return IRQ_RETVAL(rc); 1979 } 1980 1981 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) 1982 { 1983 struct ata_port *ap = qc->ap; 1984 void __iomem *port_mmio = ahci_port_base(ap); 1985 struct ahci_port_priv *pp = ap->private_data; 1986 1987 /* Keep track of the currently active link. It will be used 1988 * in completion path to determine whether NCQ phase is in 1989 * progress. 1990 */ 1991 pp->active_link = qc->dev->link; 1992 1993 if (ata_is_ncq(qc->tf.protocol)) 1994 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); 1995 1996 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) { 1997 u32 fbs = readl(port_mmio + PORT_FBS); 1998 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); 1999 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET; 2000 writel(fbs, port_mmio + PORT_FBS); 2001 pp->fbs_last_dev = qc->dev->link->pmp; 2002 } 2003 2004 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); 2005 2006 ahci_sw_activity(qc->dev->link); 2007 2008 return 0; 2009 } 2010 EXPORT_SYMBOL_GPL(ahci_qc_issue); 2011 2012 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc) 2013 { 2014 struct ahci_port_priv *pp = qc->ap->private_data; 2015 u8 *rx_fis = pp->rx_fis; 2016 2017 if (pp->fbs_enabled) 2018 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ; 2019 2020 /* 2021 * After a successful execution of an ATA PIO data-in command, 2022 * the device doesn't send D2H Reg FIS to update the TF and 2023 * the host should take TF and E_Status from the preceding PIO 2024 * Setup FIS. 2025 */ 2026 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE && 2027 !(qc->flags & ATA_QCFLAG_FAILED)) { 2028 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf); 2029 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15]; 2030 } else 2031 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf); 2032 2033 return true; 2034 } 2035 2036 static void ahci_freeze(struct ata_port *ap) 2037 { 2038 void __iomem *port_mmio = ahci_port_base(ap); 2039 2040 /* turn IRQ off */ 2041 writel(0, port_mmio + PORT_IRQ_MASK); 2042 } 2043 2044 static void ahci_thaw(struct ata_port *ap) 2045 { 2046 struct ahci_host_priv *hpriv = ap->host->private_data; 2047 void __iomem *mmio = hpriv->mmio; 2048 void __iomem *port_mmio = ahci_port_base(ap); 2049 u32 tmp; 2050 struct ahci_port_priv *pp = ap->private_data; 2051 2052 /* clear IRQ */ 2053 tmp = readl(port_mmio + PORT_IRQ_STAT); 2054 writel(tmp, port_mmio + PORT_IRQ_STAT); 2055 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); 2056 2057 /* turn IRQ back on */ 2058 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2059 } 2060 2061 void ahci_error_handler(struct ata_port *ap) 2062 { 2063 struct ahci_host_priv *hpriv = ap->host->private_data; 2064 2065 if (!(ap->pflags & ATA_PFLAG_FROZEN)) { 2066 /* restart engine */ 2067 ahci_stop_engine(ap); 2068 hpriv->start_engine(ap); 2069 } 2070 2071 sata_pmp_error_handler(ap); 2072 2073 if (!ata_dev_enabled(ap->link.device)) 2074 ahci_stop_engine(ap); 2075 } 2076 EXPORT_SYMBOL_GPL(ahci_error_handler); 2077 2078 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) 2079 { 2080 struct ata_port *ap = qc->ap; 2081 2082 /* make DMA engine forget about the failed command */ 2083 if (qc->flags & ATA_QCFLAG_FAILED) 2084 ahci_kick_engine(ap); 2085 } 2086 2087 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep) 2088 { 2089 struct ahci_host_priv *hpriv = ap->host->private_data; 2090 void __iomem *port_mmio = ahci_port_base(ap); 2091 struct ata_device *dev = ap->link.device; 2092 u32 devslp, dm, dito, mdat, deto; 2093 int rc; 2094 unsigned int err_mask; 2095 2096 devslp = readl(port_mmio + PORT_DEVSLP); 2097 if (!(devslp & PORT_DEVSLP_DSP)) { 2098 dev_info(ap->host->dev, "port does not support device sleep\n"); 2099 return; 2100 } 2101 2102 /* disable device sleep */ 2103 if (!sleep) { 2104 if (devslp & PORT_DEVSLP_ADSE) { 2105 writel(devslp & ~PORT_DEVSLP_ADSE, 2106 port_mmio + PORT_DEVSLP); 2107 err_mask = ata_dev_set_feature(dev, 2108 SETFEATURES_SATA_DISABLE, 2109 SATA_DEVSLP); 2110 if (err_mask && err_mask != AC_ERR_DEV) 2111 ata_dev_warn(dev, "failed to disable DEVSLP\n"); 2112 } 2113 return; 2114 } 2115 2116 /* device sleep was already enabled */ 2117 if (devslp & PORT_DEVSLP_ADSE) 2118 return; 2119 2120 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */ 2121 rc = ahci_stop_engine(ap); 2122 if (rc) 2123 return; 2124 2125 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET; 2126 dito = devslp_idle_timeout / (dm + 1); 2127 if (dito > 0x3ff) 2128 dito = 0x3ff; 2129 2130 /* Use the nominal value 10 ms if the read MDAT is zero, 2131 * the nominal value of DETO is 20 ms. 2132 */ 2133 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] & 2134 ATA_LOG_DEVSLP_VALID_MASK) { 2135 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] & 2136 ATA_LOG_DEVSLP_MDAT_MASK; 2137 if (!mdat) 2138 mdat = 10; 2139 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO]; 2140 if (!deto) 2141 deto = 20; 2142 } else { 2143 mdat = 10; 2144 deto = 20; 2145 } 2146 2147 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) | 2148 (mdat << PORT_DEVSLP_MDAT_OFFSET) | 2149 (deto << PORT_DEVSLP_DETO_OFFSET) | 2150 PORT_DEVSLP_ADSE); 2151 writel(devslp, port_mmio + PORT_DEVSLP); 2152 2153 hpriv->start_engine(ap); 2154 2155 /* enable device sleep feature for the drive */ 2156 err_mask = ata_dev_set_feature(dev, 2157 SETFEATURES_SATA_ENABLE, 2158 SATA_DEVSLP); 2159 if (err_mask && err_mask != AC_ERR_DEV) 2160 ata_dev_warn(dev, "failed to enable DEVSLP\n"); 2161 } 2162 2163 static void ahci_enable_fbs(struct ata_port *ap) 2164 { 2165 struct ahci_host_priv *hpriv = ap->host->private_data; 2166 struct ahci_port_priv *pp = ap->private_data; 2167 void __iomem *port_mmio = ahci_port_base(ap); 2168 u32 fbs; 2169 int rc; 2170 2171 if (!pp->fbs_supported) 2172 return; 2173 2174 fbs = readl(port_mmio + PORT_FBS); 2175 if (fbs & PORT_FBS_EN) { 2176 pp->fbs_enabled = true; 2177 pp->fbs_last_dev = -1; /* initialization */ 2178 return; 2179 } 2180 2181 rc = ahci_stop_engine(ap); 2182 if (rc) 2183 return; 2184 2185 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS); 2186 fbs = readl(port_mmio + PORT_FBS); 2187 if (fbs & PORT_FBS_EN) { 2188 dev_info(ap->host->dev, "FBS is enabled\n"); 2189 pp->fbs_enabled = true; 2190 pp->fbs_last_dev = -1; /* initialization */ 2191 } else 2192 dev_err(ap->host->dev, "Failed to enable FBS\n"); 2193 2194 hpriv->start_engine(ap); 2195 } 2196 2197 static void ahci_disable_fbs(struct ata_port *ap) 2198 { 2199 struct ahci_host_priv *hpriv = ap->host->private_data; 2200 struct ahci_port_priv *pp = ap->private_data; 2201 void __iomem *port_mmio = ahci_port_base(ap); 2202 u32 fbs; 2203 int rc; 2204 2205 if (!pp->fbs_supported) 2206 return; 2207 2208 fbs = readl(port_mmio + PORT_FBS); 2209 if ((fbs & PORT_FBS_EN) == 0) { 2210 pp->fbs_enabled = false; 2211 return; 2212 } 2213 2214 rc = ahci_stop_engine(ap); 2215 if (rc) 2216 return; 2217 2218 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS); 2219 fbs = readl(port_mmio + PORT_FBS); 2220 if (fbs & PORT_FBS_EN) 2221 dev_err(ap->host->dev, "Failed to disable FBS\n"); 2222 else { 2223 dev_info(ap->host->dev, "FBS is disabled\n"); 2224 pp->fbs_enabled = false; 2225 } 2226 2227 hpriv->start_engine(ap); 2228 } 2229 2230 static void ahci_pmp_attach(struct ata_port *ap) 2231 { 2232 void __iomem *port_mmio = ahci_port_base(ap); 2233 struct ahci_port_priv *pp = ap->private_data; 2234 u32 cmd; 2235 2236 cmd = readl(port_mmio + PORT_CMD); 2237 cmd |= PORT_CMD_PMP; 2238 writel(cmd, port_mmio + PORT_CMD); 2239 2240 ahci_enable_fbs(ap); 2241 2242 pp->intr_mask |= PORT_IRQ_BAD_PMP; 2243 2244 /* 2245 * We must not change the port interrupt mask register if the 2246 * port is marked frozen, the value in pp->intr_mask will be 2247 * restored later when the port is thawed. 2248 * 2249 * Note that during initialization, the port is marked as 2250 * frozen since the irq handler is not yet registered. 2251 */ 2252 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 2253 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2254 } 2255 2256 static void ahci_pmp_detach(struct ata_port *ap) 2257 { 2258 void __iomem *port_mmio = ahci_port_base(ap); 2259 struct ahci_port_priv *pp = ap->private_data; 2260 u32 cmd; 2261 2262 ahci_disable_fbs(ap); 2263 2264 cmd = readl(port_mmio + PORT_CMD); 2265 cmd &= ~PORT_CMD_PMP; 2266 writel(cmd, port_mmio + PORT_CMD); 2267 2268 pp->intr_mask &= ~PORT_IRQ_BAD_PMP; 2269 2270 /* see comment above in ahci_pmp_attach() */ 2271 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 2272 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2273 } 2274 2275 int ahci_port_resume(struct ata_port *ap) 2276 { 2277 ahci_rpm_get_port(ap); 2278 2279 ahci_power_up(ap); 2280 ahci_start_port(ap); 2281 2282 if (sata_pmp_attached(ap)) 2283 ahci_pmp_attach(ap); 2284 else 2285 ahci_pmp_detach(ap); 2286 2287 return 0; 2288 } 2289 EXPORT_SYMBOL_GPL(ahci_port_resume); 2290 2291 #ifdef CONFIG_PM 2292 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) 2293 { 2294 const char *emsg = NULL; 2295 int rc; 2296 2297 rc = ahci_deinit_port(ap, &emsg); 2298 if (rc == 0) 2299 ahci_power_down(ap); 2300 else { 2301 ata_port_err(ap, "%s (%d)\n", emsg, rc); 2302 ata_port_freeze(ap); 2303 } 2304 2305 ahci_rpm_put_port(ap); 2306 return rc; 2307 } 2308 #endif 2309 2310 static int ahci_port_start(struct ata_port *ap) 2311 { 2312 struct ahci_host_priv *hpriv = ap->host->private_data; 2313 struct device *dev = ap->host->dev; 2314 struct ahci_port_priv *pp; 2315 void *mem; 2316 dma_addr_t mem_dma; 2317 size_t dma_sz, rx_fis_sz; 2318 2319 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 2320 if (!pp) 2321 return -ENOMEM; 2322 2323 if (ap->host->n_ports > 1) { 2324 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL); 2325 if (!pp->irq_desc) { 2326 devm_kfree(dev, pp); 2327 return -ENOMEM; 2328 } 2329 snprintf(pp->irq_desc, 8, 2330 "%s%d", dev_driver_string(dev), ap->port_no); 2331 } 2332 2333 /* check FBS capability */ 2334 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) { 2335 void __iomem *port_mmio = ahci_port_base(ap); 2336 u32 cmd = readl(port_mmio + PORT_CMD); 2337 if (cmd & PORT_CMD_FBSCP) 2338 pp->fbs_supported = true; 2339 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) { 2340 dev_info(dev, "port %d can do FBS, forcing FBSCP\n", 2341 ap->port_no); 2342 pp->fbs_supported = true; 2343 } else 2344 dev_warn(dev, "port %d is not capable of FBS\n", 2345 ap->port_no); 2346 } 2347 2348 if (pp->fbs_supported) { 2349 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ; 2350 rx_fis_sz = AHCI_RX_FIS_SZ * 16; 2351 } else { 2352 dma_sz = AHCI_PORT_PRIV_DMA_SZ; 2353 rx_fis_sz = AHCI_RX_FIS_SZ; 2354 } 2355 2356 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL); 2357 if (!mem) 2358 return -ENOMEM; 2359 memset(mem, 0, dma_sz); 2360 2361 /* 2362 * First item in chunk of DMA memory: 32-slot command table, 2363 * 32 bytes each in size 2364 */ 2365 pp->cmd_slot = mem; 2366 pp->cmd_slot_dma = mem_dma; 2367 2368 mem += AHCI_CMD_SLOT_SZ; 2369 mem_dma += AHCI_CMD_SLOT_SZ; 2370 2371 /* 2372 * Second item: Received-FIS area 2373 */ 2374 pp->rx_fis = mem; 2375 pp->rx_fis_dma = mem_dma; 2376 2377 mem += rx_fis_sz; 2378 mem_dma += rx_fis_sz; 2379 2380 /* 2381 * Third item: data area for storing a single command 2382 * and its scatter-gather table 2383 */ 2384 pp->cmd_tbl = mem; 2385 pp->cmd_tbl_dma = mem_dma; 2386 2387 /* 2388 * Save off initial list of interrupts to be enabled. 2389 * This could be changed later 2390 */ 2391 pp->intr_mask = DEF_PORT_IRQ; 2392 2393 /* 2394 * Switch to per-port locking in case each port has its own MSI vector. 2395 */ 2396 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) { 2397 spin_lock_init(&pp->lock); 2398 ap->lock = &pp->lock; 2399 } 2400 2401 ap->private_data = pp; 2402 2403 /* engage engines, captain */ 2404 return ahci_port_resume(ap); 2405 } 2406 2407 static void ahci_port_stop(struct ata_port *ap) 2408 { 2409 const char *emsg = NULL; 2410 struct ahci_host_priv *hpriv = ap->host->private_data; 2411 void __iomem *host_mmio = hpriv->mmio; 2412 int rc; 2413 2414 /* de-initialize port */ 2415 rc = ahci_deinit_port(ap, &emsg); 2416 if (rc) 2417 ata_port_warn(ap, "%s (%d)\n", emsg, rc); 2418 2419 /* 2420 * Clear GHC.IS to prevent stuck INTx after disabling MSI and 2421 * re-enabling INTx. 2422 */ 2423 writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT); 2424 } 2425 2426 void ahci_print_info(struct ata_host *host, const char *scc_s) 2427 { 2428 struct ahci_host_priv *hpriv = host->private_data; 2429 u32 vers, cap, cap2, impl, speed; 2430 const char *speed_s; 2431 2432 vers = hpriv->version; 2433 cap = hpriv->cap; 2434 cap2 = hpriv->cap2; 2435 impl = hpriv->port_map; 2436 2437 speed = (cap >> 20) & 0xf; 2438 if (speed == 1) 2439 speed_s = "1.5"; 2440 else if (speed == 2) 2441 speed_s = "3"; 2442 else if (speed == 3) 2443 speed_s = "6"; 2444 else 2445 speed_s = "?"; 2446 2447 dev_info(host->dev, 2448 "AHCI %02x%02x.%02x%02x " 2449 "%u slots %u ports %s Gbps 0x%x impl %s mode\n" 2450 , 2451 2452 (vers >> 24) & 0xff, 2453 (vers >> 16) & 0xff, 2454 (vers >> 8) & 0xff, 2455 vers & 0xff, 2456 2457 ((cap >> 8) & 0x1f) + 1, 2458 (cap & 0x1f) + 1, 2459 speed_s, 2460 impl, 2461 scc_s); 2462 2463 dev_info(host->dev, 2464 "flags: " 2465 "%s%s%s%s%s%s%s" 2466 "%s%s%s%s%s%s%s" 2467 "%s%s%s%s%s%s%s" 2468 "%s%s\n" 2469 , 2470 2471 cap & HOST_CAP_64 ? "64bit " : "", 2472 cap & HOST_CAP_NCQ ? "ncq " : "", 2473 cap & HOST_CAP_SNTF ? "sntf " : "", 2474 cap & HOST_CAP_MPS ? "ilck " : "", 2475 cap & HOST_CAP_SSS ? "stag " : "", 2476 cap & HOST_CAP_ALPM ? "pm " : "", 2477 cap & HOST_CAP_LED ? "led " : "", 2478 cap & HOST_CAP_CLO ? "clo " : "", 2479 cap & HOST_CAP_ONLY ? "only " : "", 2480 cap & HOST_CAP_PMP ? "pmp " : "", 2481 cap & HOST_CAP_FBS ? "fbs " : "", 2482 cap & HOST_CAP_PIO_MULTI ? "pio " : "", 2483 cap & HOST_CAP_SSC ? "slum " : "", 2484 cap & HOST_CAP_PART ? "part " : "", 2485 cap & HOST_CAP_CCC ? "ccc " : "", 2486 cap & HOST_CAP_EMS ? "ems " : "", 2487 cap & HOST_CAP_SXS ? "sxs " : "", 2488 cap2 & HOST_CAP2_DESO ? "deso " : "", 2489 cap2 & HOST_CAP2_SADM ? "sadm " : "", 2490 cap2 & HOST_CAP2_SDS ? "sds " : "", 2491 cap2 & HOST_CAP2_APST ? "apst " : "", 2492 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "", 2493 cap2 & HOST_CAP2_BOH ? "boh " : "" 2494 ); 2495 } 2496 EXPORT_SYMBOL_GPL(ahci_print_info); 2497 2498 void ahci_set_em_messages(struct ahci_host_priv *hpriv, 2499 struct ata_port_info *pi) 2500 { 2501 u8 messages; 2502 void __iomem *mmio = hpriv->mmio; 2503 u32 em_loc = readl(mmio + HOST_EM_LOC); 2504 u32 em_ctl = readl(mmio + HOST_EM_CTL); 2505 2506 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS)) 2507 return; 2508 2509 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16; 2510 2511 if (messages) { 2512 /* store em_loc */ 2513 hpriv->em_loc = ((em_loc >> 16) * 4); 2514 hpriv->em_buf_sz = ((em_loc & 0xff) * 4); 2515 hpriv->em_msg_type = messages; 2516 pi->flags |= ATA_FLAG_EM; 2517 if (!(em_ctl & EM_CTL_ALHD)) 2518 pi->flags |= ATA_FLAG_SW_ACTIVITY; 2519 } 2520 } 2521 EXPORT_SYMBOL_GPL(ahci_set_em_messages); 2522 2523 static int ahci_host_activate_multi_irqs(struct ata_host *host, 2524 struct scsi_host_template *sht) 2525 { 2526 struct ahci_host_priv *hpriv = host->private_data; 2527 int i, rc; 2528 2529 rc = ata_host_start(host); 2530 if (rc) 2531 return rc; 2532 /* 2533 * Requests IRQs according to AHCI-1.1 when multiple MSIs were 2534 * allocated. That is one MSI per port, starting from @irq. 2535 */ 2536 for (i = 0; i < host->n_ports; i++) { 2537 struct ahci_port_priv *pp = host->ports[i]->private_data; 2538 int irq = hpriv->get_irq_vector(host, i); 2539 2540 /* Do not receive interrupts sent by dummy ports */ 2541 if (!pp) { 2542 disable_irq(irq); 2543 continue; 2544 } 2545 2546 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard, 2547 0, pp->irq_desc, host->ports[i]); 2548 2549 if (rc) 2550 return rc; 2551 ata_port_desc(host->ports[i], "irq %d", irq); 2552 } 2553 2554 return ata_host_register(host, sht); 2555 } 2556 2557 /** 2558 * ahci_host_activate - start AHCI host, request IRQs and register it 2559 * @host: target ATA host 2560 * @sht: scsi_host_template to use when registering the host 2561 * 2562 * LOCKING: 2563 * Inherited from calling layer (may sleep). 2564 * 2565 * RETURNS: 2566 * 0 on success, -errno otherwise. 2567 */ 2568 int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht) 2569 { 2570 struct ahci_host_priv *hpriv = host->private_data; 2571 int irq = hpriv->irq; 2572 int rc; 2573 2574 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) { 2575 if (hpriv->irq_handler) 2576 dev_warn(host->dev, 2577 "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n"); 2578 if (!hpriv->get_irq_vector) { 2579 dev_err(host->dev, 2580 "AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n"); 2581 return -EIO; 2582 } 2583 2584 rc = ahci_host_activate_multi_irqs(host, sht); 2585 } else { 2586 rc = ata_host_activate(host, irq, hpriv->irq_handler, 2587 IRQF_SHARED, sht); 2588 } 2589 2590 2591 return rc; 2592 } 2593 EXPORT_SYMBOL_GPL(ahci_host_activate); 2594 2595 MODULE_AUTHOR("Jeff Garzik"); 2596 MODULE_DESCRIPTION("Common AHCI SATA low-level routines"); 2597 MODULE_LICENSE("GPL"); 2598