1 /* 2 * libahci.c - Common AHCI SATA low-level routines 3 * 4 * Maintained by: Tejun Heo <tj@kernel.org> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2004-2005 Red Hat, Inc. 9 * 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; see the file COPYING. If not, write to 23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * 26 * libata documentation is available via 'make {ps|pdf}docs', 27 * as Documentation/driver-api/libata.rst 28 * 29 * AHCI hardware documentation: 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 32 * 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/gfp.h> 37 #include <linux/module.h> 38 #include <linux/blkdev.h> 39 #include <linux/delay.h> 40 #include <linux/interrupt.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/device.h> 43 #include <scsi/scsi_host.h> 44 #include <scsi/scsi_cmnd.h> 45 #include <linux/libata.h> 46 #include <linux/pci.h> 47 #include "ahci.h" 48 #include "libata.h" 49 50 static int ahci_skip_host_reset; 51 int ahci_ignore_sss; 52 EXPORT_SYMBOL_GPL(ahci_ignore_sss); 53 54 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); 55 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); 56 57 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444); 58 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)"); 59 60 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 61 unsigned hints); 62 static ssize_t ahci_led_show(struct ata_port *ap, char *buf); 63 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 64 size_t size); 65 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 66 ssize_t size); 67 68 69 70 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); 71 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); 72 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc); 73 static int ahci_port_start(struct ata_port *ap); 74 static void ahci_port_stop(struct ata_port *ap); 75 static void ahci_qc_prep(struct ata_queued_cmd *qc); 76 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc); 77 static void ahci_freeze(struct ata_port *ap); 78 static void ahci_thaw(struct ata_port *ap); 79 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep); 80 static void ahci_enable_fbs(struct ata_port *ap); 81 static void ahci_disable_fbs(struct ata_port *ap); 82 static void ahci_pmp_attach(struct ata_port *ap); 83 static void ahci_pmp_detach(struct ata_port *ap); 84 static int ahci_softreset(struct ata_link *link, unsigned int *class, 85 unsigned long deadline); 86 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class, 87 unsigned long deadline); 88 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 89 unsigned long deadline); 90 static void ahci_postreset(struct ata_link *link, unsigned int *class); 91 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); 92 static void ahci_dev_config(struct ata_device *dev); 93 #ifdef CONFIG_PM 94 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); 95 #endif 96 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf); 97 static ssize_t ahci_activity_store(struct ata_device *dev, 98 enum sw_activity val); 99 static void ahci_init_sw_activity(struct ata_link *link); 100 101 static ssize_t ahci_show_host_caps(struct device *dev, 102 struct device_attribute *attr, char *buf); 103 static ssize_t ahci_show_host_cap2(struct device *dev, 104 struct device_attribute *attr, char *buf); 105 static ssize_t ahci_show_host_version(struct device *dev, 106 struct device_attribute *attr, char *buf); 107 static ssize_t ahci_show_port_cmd(struct device *dev, 108 struct device_attribute *attr, char *buf); 109 static ssize_t ahci_read_em_buffer(struct device *dev, 110 struct device_attribute *attr, char *buf); 111 static ssize_t ahci_store_em_buffer(struct device *dev, 112 struct device_attribute *attr, 113 const char *buf, size_t size); 114 static ssize_t ahci_show_em_supported(struct device *dev, 115 struct device_attribute *attr, char *buf); 116 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance); 117 118 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL); 119 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL); 120 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL); 121 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL); 122 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO, 123 ahci_read_em_buffer, ahci_store_em_buffer); 124 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL); 125 126 struct device_attribute *ahci_shost_attrs[] = { 127 &dev_attr_link_power_management_policy, 128 &dev_attr_em_message_type, 129 &dev_attr_em_message, 130 &dev_attr_ahci_host_caps, 131 &dev_attr_ahci_host_cap2, 132 &dev_attr_ahci_host_version, 133 &dev_attr_ahci_port_cmd, 134 &dev_attr_em_buffer, 135 &dev_attr_em_message_supported, 136 NULL 137 }; 138 EXPORT_SYMBOL_GPL(ahci_shost_attrs); 139 140 struct device_attribute *ahci_sdev_attrs[] = { 141 &dev_attr_sw_activity, 142 &dev_attr_unload_heads, 143 &dev_attr_ncq_prio_enable, 144 NULL 145 }; 146 EXPORT_SYMBOL_GPL(ahci_sdev_attrs); 147 148 struct ata_port_operations ahci_ops = { 149 .inherits = &sata_pmp_port_ops, 150 151 .qc_defer = ahci_pmp_qc_defer, 152 .qc_prep = ahci_qc_prep, 153 .qc_issue = ahci_qc_issue, 154 .qc_fill_rtf = ahci_qc_fill_rtf, 155 156 .freeze = ahci_freeze, 157 .thaw = ahci_thaw, 158 .softreset = ahci_softreset, 159 .hardreset = ahci_hardreset, 160 .postreset = ahci_postreset, 161 .pmp_softreset = ahci_softreset, 162 .error_handler = ahci_error_handler, 163 .post_internal_cmd = ahci_post_internal_cmd, 164 .dev_config = ahci_dev_config, 165 166 .scr_read = ahci_scr_read, 167 .scr_write = ahci_scr_write, 168 .pmp_attach = ahci_pmp_attach, 169 .pmp_detach = ahci_pmp_detach, 170 171 .set_lpm = ahci_set_lpm, 172 .em_show = ahci_led_show, 173 .em_store = ahci_led_store, 174 .sw_activity_show = ahci_activity_show, 175 .sw_activity_store = ahci_activity_store, 176 .transmit_led_message = ahci_transmit_led_message, 177 #ifdef CONFIG_PM 178 .port_suspend = ahci_port_suspend, 179 .port_resume = ahci_port_resume, 180 #endif 181 .port_start = ahci_port_start, 182 .port_stop = ahci_port_stop, 183 }; 184 EXPORT_SYMBOL_GPL(ahci_ops); 185 186 struct ata_port_operations ahci_pmp_retry_srst_ops = { 187 .inherits = &ahci_ops, 188 .softreset = ahci_pmp_retry_softreset, 189 }; 190 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops); 191 192 static bool ahci_em_messages __read_mostly = true; 193 EXPORT_SYMBOL_GPL(ahci_em_messages); 194 module_param(ahci_em_messages, bool, 0444); 195 /* add other LED protocol types when they become supported */ 196 MODULE_PARM_DESC(ahci_em_messages, 197 "AHCI Enclosure Management Message control (0 = off, 1 = on)"); 198 199 /* device sleep idle timeout in ms */ 200 static int devslp_idle_timeout __read_mostly = 1000; 201 module_param(devslp_idle_timeout, int, 0644); 202 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout"); 203 204 static void ahci_enable_ahci(void __iomem *mmio) 205 { 206 int i; 207 u32 tmp; 208 209 /* turn on AHCI_EN */ 210 tmp = readl(mmio + HOST_CTL); 211 if (tmp & HOST_AHCI_EN) 212 return; 213 214 /* Some controllers need AHCI_EN to be written multiple times. 215 * Try a few times before giving up. 216 */ 217 for (i = 0; i < 5; i++) { 218 tmp |= HOST_AHCI_EN; 219 writel(tmp, mmio + HOST_CTL); 220 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ 221 if (tmp & HOST_AHCI_EN) 222 return; 223 msleep(10); 224 } 225 226 WARN_ON(1); 227 } 228 229 /** 230 * ahci_rpm_get_port - Make sure the port is powered on 231 * @ap: Port to power on 232 * 233 * Whenever there is need to access the AHCI host registers outside of 234 * normal execution paths, call this function to make sure the host is 235 * actually powered on. 236 */ 237 static int ahci_rpm_get_port(struct ata_port *ap) 238 { 239 return pm_runtime_get_sync(ap->dev); 240 } 241 242 /** 243 * ahci_rpm_put_port - Undoes ahci_rpm_get_port() 244 * @ap: Port to power down 245 * 246 * Undoes ahci_rpm_get_port() and possibly powers down the AHCI host 247 * if it has no more active users. 248 */ 249 static void ahci_rpm_put_port(struct ata_port *ap) 250 { 251 pm_runtime_put(ap->dev); 252 } 253 254 static ssize_t ahci_show_host_caps(struct device *dev, 255 struct device_attribute *attr, char *buf) 256 { 257 struct Scsi_Host *shost = class_to_shost(dev); 258 struct ata_port *ap = ata_shost_to_port(shost); 259 struct ahci_host_priv *hpriv = ap->host->private_data; 260 261 return sprintf(buf, "%x\n", hpriv->cap); 262 } 263 264 static ssize_t ahci_show_host_cap2(struct device *dev, 265 struct device_attribute *attr, char *buf) 266 { 267 struct Scsi_Host *shost = class_to_shost(dev); 268 struct ata_port *ap = ata_shost_to_port(shost); 269 struct ahci_host_priv *hpriv = ap->host->private_data; 270 271 return sprintf(buf, "%x\n", hpriv->cap2); 272 } 273 274 static ssize_t ahci_show_host_version(struct device *dev, 275 struct device_attribute *attr, char *buf) 276 { 277 struct Scsi_Host *shost = class_to_shost(dev); 278 struct ata_port *ap = ata_shost_to_port(shost); 279 struct ahci_host_priv *hpriv = ap->host->private_data; 280 281 return sprintf(buf, "%x\n", hpriv->version); 282 } 283 284 static ssize_t ahci_show_port_cmd(struct device *dev, 285 struct device_attribute *attr, char *buf) 286 { 287 struct Scsi_Host *shost = class_to_shost(dev); 288 struct ata_port *ap = ata_shost_to_port(shost); 289 void __iomem *port_mmio = ahci_port_base(ap); 290 ssize_t ret; 291 292 ahci_rpm_get_port(ap); 293 ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD)); 294 ahci_rpm_put_port(ap); 295 296 return ret; 297 } 298 299 static ssize_t ahci_read_em_buffer(struct device *dev, 300 struct device_attribute *attr, char *buf) 301 { 302 struct Scsi_Host *shost = class_to_shost(dev); 303 struct ata_port *ap = ata_shost_to_port(shost); 304 struct ahci_host_priv *hpriv = ap->host->private_data; 305 void __iomem *mmio = hpriv->mmio; 306 void __iomem *em_mmio = mmio + hpriv->em_loc; 307 u32 em_ctl, msg; 308 unsigned long flags; 309 size_t count; 310 int i; 311 312 ahci_rpm_get_port(ap); 313 spin_lock_irqsave(ap->lock, flags); 314 315 em_ctl = readl(mmio + HOST_EM_CTL); 316 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT || 317 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) { 318 spin_unlock_irqrestore(ap->lock, flags); 319 ahci_rpm_put_port(ap); 320 return -EINVAL; 321 } 322 323 if (!(em_ctl & EM_CTL_MR)) { 324 spin_unlock_irqrestore(ap->lock, flags); 325 ahci_rpm_put_port(ap); 326 return -EAGAIN; 327 } 328 329 if (!(em_ctl & EM_CTL_SMB)) 330 em_mmio += hpriv->em_buf_sz; 331 332 count = hpriv->em_buf_sz; 333 334 /* the count should not be larger than PAGE_SIZE */ 335 if (count > PAGE_SIZE) { 336 if (printk_ratelimit()) 337 ata_port_warn(ap, 338 "EM read buffer size too large: " 339 "buffer size %u, page size %lu\n", 340 hpriv->em_buf_sz, PAGE_SIZE); 341 count = PAGE_SIZE; 342 } 343 344 for (i = 0; i < count; i += 4) { 345 msg = readl(em_mmio + i); 346 buf[i] = msg & 0xff; 347 buf[i + 1] = (msg >> 8) & 0xff; 348 buf[i + 2] = (msg >> 16) & 0xff; 349 buf[i + 3] = (msg >> 24) & 0xff; 350 } 351 352 spin_unlock_irqrestore(ap->lock, flags); 353 ahci_rpm_put_port(ap); 354 355 return i; 356 } 357 358 static ssize_t ahci_store_em_buffer(struct device *dev, 359 struct device_attribute *attr, 360 const char *buf, size_t size) 361 { 362 struct Scsi_Host *shost = class_to_shost(dev); 363 struct ata_port *ap = ata_shost_to_port(shost); 364 struct ahci_host_priv *hpriv = ap->host->private_data; 365 void __iomem *mmio = hpriv->mmio; 366 void __iomem *em_mmio = mmio + hpriv->em_loc; 367 const unsigned char *msg_buf = buf; 368 u32 em_ctl, msg; 369 unsigned long flags; 370 int i; 371 372 /* check size validity */ 373 if (!(ap->flags & ATA_FLAG_EM) || 374 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) || 375 size % 4 || size > hpriv->em_buf_sz) 376 return -EINVAL; 377 378 ahci_rpm_get_port(ap); 379 spin_lock_irqsave(ap->lock, flags); 380 381 em_ctl = readl(mmio + HOST_EM_CTL); 382 if (em_ctl & EM_CTL_TM) { 383 spin_unlock_irqrestore(ap->lock, flags); 384 ahci_rpm_put_port(ap); 385 return -EBUSY; 386 } 387 388 for (i = 0; i < size; i += 4) { 389 msg = msg_buf[i] | msg_buf[i + 1] << 8 | 390 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24; 391 writel(msg, em_mmio + i); 392 } 393 394 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 395 396 spin_unlock_irqrestore(ap->lock, flags); 397 ahci_rpm_put_port(ap); 398 399 return size; 400 } 401 402 static ssize_t ahci_show_em_supported(struct device *dev, 403 struct device_attribute *attr, char *buf) 404 { 405 struct Scsi_Host *shost = class_to_shost(dev); 406 struct ata_port *ap = ata_shost_to_port(shost); 407 struct ahci_host_priv *hpriv = ap->host->private_data; 408 void __iomem *mmio = hpriv->mmio; 409 u32 em_ctl; 410 411 ahci_rpm_get_port(ap); 412 em_ctl = readl(mmio + HOST_EM_CTL); 413 ahci_rpm_put_port(ap); 414 415 return sprintf(buf, "%s%s%s%s\n", 416 em_ctl & EM_CTL_LED ? "led " : "", 417 em_ctl & EM_CTL_SAFTE ? "saf-te " : "", 418 em_ctl & EM_CTL_SES ? "ses-2 " : "", 419 em_ctl & EM_CTL_SGPIO ? "sgpio " : ""); 420 } 421 422 /** 423 * ahci_save_initial_config - Save and fixup initial config values 424 * @dev: target AHCI device 425 * @hpriv: host private area to store config values 426 * 427 * Some registers containing configuration info might be setup by 428 * BIOS and might be cleared on reset. This function saves the 429 * initial values of those registers into @hpriv such that they 430 * can be restored after controller reset. 431 * 432 * If inconsistent, config values are fixed up by this function. 433 * 434 * If it is not set already this function sets hpriv->start_engine to 435 * ahci_start_engine. 436 * 437 * LOCKING: 438 * None. 439 */ 440 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv) 441 { 442 void __iomem *mmio = hpriv->mmio; 443 u32 cap, cap2, vers, port_map; 444 int i; 445 446 /* make sure AHCI mode is enabled before accessing CAP */ 447 ahci_enable_ahci(mmio); 448 449 /* Values prefixed with saved_ are written back to host after 450 * reset. Values without are used for driver operation. 451 */ 452 hpriv->saved_cap = cap = readl(mmio + HOST_CAP); 453 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); 454 455 /* CAP2 register is only defined for AHCI 1.2 and later */ 456 vers = readl(mmio + HOST_VERSION); 457 if ((vers >> 16) > 1 || 458 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200)) 459 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2); 460 else 461 hpriv->saved_cap2 = cap2 = 0; 462 463 /* some chips have errata preventing 64bit use */ 464 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { 465 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n"); 466 cap &= ~HOST_CAP_64; 467 } 468 469 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { 470 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n"); 471 cap &= ~HOST_CAP_NCQ; 472 } 473 474 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) { 475 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n"); 476 cap |= HOST_CAP_NCQ; 477 } 478 479 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { 480 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n"); 481 cap &= ~HOST_CAP_PMP; 482 } 483 484 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) { 485 dev_info(dev, 486 "controller can't do SNTF, turning off CAP_SNTF\n"); 487 cap &= ~HOST_CAP_SNTF; 488 } 489 490 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) { 491 dev_info(dev, 492 "controller can't do DEVSLP, turning off\n"); 493 cap2 &= ~HOST_CAP2_SDS; 494 cap2 &= ~HOST_CAP2_SADM; 495 } 496 497 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) { 498 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n"); 499 cap |= HOST_CAP_FBS; 500 } 501 502 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) { 503 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n"); 504 cap &= ~HOST_CAP_FBS; 505 } 506 507 if (!(cap & HOST_CAP_ALPM) && (hpriv->flags & AHCI_HFLAG_YES_ALPM)) { 508 dev_info(dev, "controller can do ALPM, turning on CAP_ALPM\n"); 509 cap |= HOST_CAP_ALPM; 510 } 511 512 if (hpriv->force_port_map && port_map != hpriv->force_port_map) { 513 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n", 514 port_map, hpriv->force_port_map); 515 port_map = hpriv->force_port_map; 516 hpriv->saved_port_map = port_map; 517 } 518 519 if (hpriv->mask_port_map) { 520 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n", 521 port_map, 522 port_map & hpriv->mask_port_map); 523 port_map &= hpriv->mask_port_map; 524 } 525 526 /* cross check port_map and cap.n_ports */ 527 if (port_map) { 528 int map_ports = 0; 529 530 for (i = 0; i < AHCI_MAX_PORTS; i++) 531 if (port_map & (1 << i)) 532 map_ports++; 533 534 /* If PI has more ports than n_ports, whine, clear 535 * port_map and let it be generated from n_ports. 536 */ 537 if (map_ports > ahci_nr_ports(cap)) { 538 dev_warn(dev, 539 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n", 540 port_map, ahci_nr_ports(cap)); 541 port_map = 0; 542 } 543 } 544 545 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */ 546 if (!port_map && vers < 0x10300) { 547 port_map = (1 << ahci_nr_ports(cap)) - 1; 548 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map); 549 550 /* write the fixed up value to the PI register */ 551 hpriv->saved_port_map = port_map; 552 } 553 554 /* record values to use during operation */ 555 hpriv->cap = cap; 556 hpriv->cap2 = cap2; 557 hpriv->version = readl(mmio + HOST_VERSION); 558 hpriv->port_map = port_map; 559 560 if (!hpriv->start_engine) 561 hpriv->start_engine = ahci_start_engine; 562 563 if (!hpriv->irq_handler) 564 hpriv->irq_handler = ahci_single_level_irq_intr; 565 } 566 EXPORT_SYMBOL_GPL(ahci_save_initial_config); 567 568 /** 569 * ahci_restore_initial_config - Restore initial config 570 * @host: target ATA host 571 * 572 * Restore initial config stored by ahci_save_initial_config(). 573 * 574 * LOCKING: 575 * None. 576 */ 577 static void ahci_restore_initial_config(struct ata_host *host) 578 { 579 struct ahci_host_priv *hpriv = host->private_data; 580 void __iomem *mmio = hpriv->mmio; 581 582 writel(hpriv->saved_cap, mmio + HOST_CAP); 583 if (hpriv->saved_cap2) 584 writel(hpriv->saved_cap2, mmio + HOST_CAP2); 585 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); 586 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ 587 } 588 589 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) 590 { 591 static const int offset[] = { 592 [SCR_STATUS] = PORT_SCR_STAT, 593 [SCR_CONTROL] = PORT_SCR_CTL, 594 [SCR_ERROR] = PORT_SCR_ERR, 595 [SCR_ACTIVE] = PORT_SCR_ACT, 596 [SCR_NOTIFICATION] = PORT_SCR_NTF, 597 }; 598 struct ahci_host_priv *hpriv = ap->host->private_data; 599 600 if (sc_reg < ARRAY_SIZE(offset) && 601 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) 602 return offset[sc_reg]; 603 return 0; 604 } 605 606 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) 607 { 608 void __iomem *port_mmio = ahci_port_base(link->ap); 609 int offset = ahci_scr_offset(link->ap, sc_reg); 610 611 if (offset) { 612 *val = readl(port_mmio + offset); 613 return 0; 614 } 615 return -EINVAL; 616 } 617 618 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) 619 { 620 void __iomem *port_mmio = ahci_port_base(link->ap); 621 int offset = ahci_scr_offset(link->ap, sc_reg); 622 623 if (offset) { 624 writel(val, port_mmio + offset); 625 return 0; 626 } 627 return -EINVAL; 628 } 629 630 void ahci_start_engine(struct ata_port *ap) 631 { 632 void __iomem *port_mmio = ahci_port_base(ap); 633 u32 tmp; 634 635 /* start DMA */ 636 tmp = readl(port_mmio + PORT_CMD); 637 tmp |= PORT_CMD_START; 638 writel(tmp, port_mmio + PORT_CMD); 639 readl(port_mmio + PORT_CMD); /* flush */ 640 } 641 EXPORT_SYMBOL_GPL(ahci_start_engine); 642 643 int ahci_stop_engine(struct ata_port *ap) 644 { 645 void __iomem *port_mmio = ahci_port_base(ap); 646 struct ahci_host_priv *hpriv = ap->host->private_data; 647 u32 tmp; 648 649 /* 650 * On some controllers, stopping a port's DMA engine while the port 651 * is in ALPM state (partial or slumber) results in failures on 652 * subsequent DMA engine starts. For those controllers, put the 653 * port back in active state before stopping its DMA engine. 654 */ 655 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) && 656 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) && 657 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) { 658 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n"); 659 return -EIO; 660 } 661 662 tmp = readl(port_mmio + PORT_CMD); 663 664 /* check if the HBA is idle */ 665 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) 666 return 0; 667 668 /* 669 * Don't try to issue commands but return with ENODEV if the 670 * AHCI controller not available anymore (e.g. due to PCIe hot 671 * unplugging). Otherwise a 500ms delay for each port is added. 672 */ 673 if (tmp == 0xffffffff) { 674 dev_err(ap->host->dev, "AHCI controller unavailable!\n"); 675 return -ENODEV; 676 } 677 678 /* setting HBA to idle */ 679 tmp &= ~PORT_CMD_START; 680 writel(tmp, port_mmio + PORT_CMD); 681 682 /* wait for engine to stop. This could be as long as 500 msec */ 683 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 684 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); 685 if (tmp & PORT_CMD_LIST_ON) 686 return -EIO; 687 688 return 0; 689 } 690 EXPORT_SYMBOL_GPL(ahci_stop_engine); 691 692 void ahci_start_fis_rx(struct ata_port *ap) 693 { 694 void __iomem *port_mmio = ahci_port_base(ap); 695 struct ahci_host_priv *hpriv = ap->host->private_data; 696 struct ahci_port_priv *pp = ap->private_data; 697 u32 tmp; 698 699 /* set FIS registers */ 700 if (hpriv->cap & HOST_CAP_64) 701 writel((pp->cmd_slot_dma >> 16) >> 16, 702 port_mmio + PORT_LST_ADDR_HI); 703 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); 704 705 if (hpriv->cap & HOST_CAP_64) 706 writel((pp->rx_fis_dma >> 16) >> 16, 707 port_mmio + PORT_FIS_ADDR_HI); 708 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); 709 710 /* enable FIS reception */ 711 tmp = readl(port_mmio + PORT_CMD); 712 tmp |= PORT_CMD_FIS_RX; 713 writel(tmp, port_mmio + PORT_CMD); 714 715 /* flush */ 716 readl(port_mmio + PORT_CMD); 717 } 718 EXPORT_SYMBOL_GPL(ahci_start_fis_rx); 719 720 static int ahci_stop_fis_rx(struct ata_port *ap) 721 { 722 void __iomem *port_mmio = ahci_port_base(ap); 723 u32 tmp; 724 725 /* disable FIS reception */ 726 tmp = readl(port_mmio + PORT_CMD); 727 tmp &= ~PORT_CMD_FIS_RX; 728 writel(tmp, port_mmio + PORT_CMD); 729 730 /* wait for completion, spec says 500ms, give it 1000 */ 731 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON, 732 PORT_CMD_FIS_ON, 10, 1000); 733 if (tmp & PORT_CMD_FIS_ON) 734 return -EBUSY; 735 736 return 0; 737 } 738 739 static void ahci_power_up(struct ata_port *ap) 740 { 741 struct ahci_host_priv *hpriv = ap->host->private_data; 742 void __iomem *port_mmio = ahci_port_base(ap); 743 u32 cmd; 744 745 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 746 747 /* spin up device */ 748 if (hpriv->cap & HOST_CAP_SSS) { 749 cmd |= PORT_CMD_SPIN_UP; 750 writel(cmd, port_mmio + PORT_CMD); 751 } 752 753 /* wake up link */ 754 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); 755 } 756 757 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 758 unsigned int hints) 759 { 760 struct ata_port *ap = link->ap; 761 struct ahci_host_priv *hpriv = ap->host->private_data; 762 struct ahci_port_priv *pp = ap->private_data; 763 void __iomem *port_mmio = ahci_port_base(ap); 764 765 if (policy != ATA_LPM_MAX_POWER) { 766 /* wakeup flag only applies to the max power policy */ 767 hints &= ~ATA_LPM_WAKE_ONLY; 768 769 /* 770 * Disable interrupts on Phy Ready. This keeps us from 771 * getting woken up due to spurious phy ready 772 * interrupts. 773 */ 774 pp->intr_mask &= ~PORT_IRQ_PHYRDY; 775 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 776 777 sata_link_scr_lpm(link, policy, false); 778 } 779 780 if (hpriv->cap & HOST_CAP_ALPM) { 781 u32 cmd = readl(port_mmio + PORT_CMD); 782 783 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) { 784 if (!(hints & ATA_LPM_WAKE_ONLY)) 785 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE); 786 cmd |= PORT_CMD_ICC_ACTIVE; 787 788 writel(cmd, port_mmio + PORT_CMD); 789 readl(port_mmio + PORT_CMD); 790 791 /* wait 10ms to be sure we've come out of LPM state */ 792 ata_msleep(ap, 10); 793 794 if (hints & ATA_LPM_WAKE_ONLY) 795 return 0; 796 } else { 797 cmd |= PORT_CMD_ALPE; 798 if (policy == ATA_LPM_MIN_POWER) 799 cmd |= PORT_CMD_ASP; 800 801 /* write out new cmd value */ 802 writel(cmd, port_mmio + PORT_CMD); 803 } 804 } 805 806 /* set aggressive device sleep */ 807 if ((hpriv->cap2 & HOST_CAP2_SDS) && 808 (hpriv->cap2 & HOST_CAP2_SADM) && 809 (link->device->flags & ATA_DFLAG_DEVSLP)) { 810 if (policy == ATA_LPM_MIN_POWER) 811 ahci_set_aggressive_devslp(ap, true); 812 else 813 ahci_set_aggressive_devslp(ap, false); 814 } 815 816 if (policy == ATA_LPM_MAX_POWER) { 817 sata_link_scr_lpm(link, policy, false); 818 819 /* turn PHYRDY IRQ back on */ 820 pp->intr_mask |= PORT_IRQ_PHYRDY; 821 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 822 } 823 824 return 0; 825 } 826 827 #ifdef CONFIG_PM 828 static void ahci_power_down(struct ata_port *ap) 829 { 830 struct ahci_host_priv *hpriv = ap->host->private_data; 831 void __iomem *port_mmio = ahci_port_base(ap); 832 u32 cmd, scontrol; 833 834 if (!(hpriv->cap & HOST_CAP_SSS)) 835 return; 836 837 /* put device into listen mode, first set PxSCTL.DET to 0 */ 838 scontrol = readl(port_mmio + PORT_SCR_CTL); 839 scontrol &= ~0xf; 840 writel(scontrol, port_mmio + PORT_SCR_CTL); 841 842 /* then set PxCMD.SUD to 0 */ 843 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 844 cmd &= ~PORT_CMD_SPIN_UP; 845 writel(cmd, port_mmio + PORT_CMD); 846 } 847 #endif 848 849 static void ahci_start_port(struct ata_port *ap) 850 { 851 struct ahci_host_priv *hpriv = ap->host->private_data; 852 struct ahci_port_priv *pp = ap->private_data; 853 struct ata_link *link; 854 struct ahci_em_priv *emp; 855 ssize_t rc; 856 int i; 857 858 /* enable FIS reception */ 859 ahci_start_fis_rx(ap); 860 861 /* enable DMA */ 862 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE)) 863 hpriv->start_engine(ap); 864 865 /* turn on LEDs */ 866 if (ap->flags & ATA_FLAG_EM) { 867 ata_for_each_link(link, ap, EDGE) { 868 emp = &pp->em_priv[link->pmp]; 869 870 /* EM Transmit bit maybe busy during init */ 871 for (i = 0; i < EM_MAX_RETRY; i++) { 872 rc = ap->ops->transmit_led_message(ap, 873 emp->led_state, 874 4); 875 /* 876 * If busy, give a breather but do not 877 * release EH ownership by using msleep() 878 * instead of ata_msleep(). EM Transmit 879 * bit is busy for the whole host and 880 * releasing ownership will cause other 881 * ports to fail the same way. 882 */ 883 if (rc == -EBUSY) 884 msleep(1); 885 else 886 break; 887 } 888 } 889 } 890 891 if (ap->flags & ATA_FLAG_SW_ACTIVITY) 892 ata_for_each_link(link, ap, EDGE) 893 ahci_init_sw_activity(link); 894 895 } 896 897 static int ahci_deinit_port(struct ata_port *ap, const char **emsg) 898 { 899 int rc; 900 901 /* disable DMA */ 902 rc = ahci_stop_engine(ap); 903 if (rc) { 904 *emsg = "failed to stop engine"; 905 return rc; 906 } 907 908 /* disable FIS reception */ 909 rc = ahci_stop_fis_rx(ap); 910 if (rc) { 911 *emsg = "failed stop FIS RX"; 912 return rc; 913 } 914 915 return 0; 916 } 917 918 int ahci_reset_controller(struct ata_host *host) 919 { 920 struct ahci_host_priv *hpriv = host->private_data; 921 void __iomem *mmio = hpriv->mmio; 922 u32 tmp; 923 924 /* we must be in AHCI mode, before using anything 925 * AHCI-specific, such as HOST_RESET. 926 */ 927 ahci_enable_ahci(mmio); 928 929 /* global controller reset */ 930 if (!ahci_skip_host_reset) { 931 tmp = readl(mmio + HOST_CTL); 932 if ((tmp & HOST_RESET) == 0) { 933 writel(tmp | HOST_RESET, mmio + HOST_CTL); 934 readl(mmio + HOST_CTL); /* flush */ 935 } 936 937 /* 938 * to perform host reset, OS should set HOST_RESET 939 * and poll until this bit is read to be "0". 940 * reset must complete within 1 second, or 941 * the hardware should be considered fried. 942 */ 943 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET, 944 HOST_RESET, 10, 1000); 945 946 if (tmp & HOST_RESET) { 947 dev_err(host->dev, "controller reset failed (0x%x)\n", 948 tmp); 949 return -EIO; 950 } 951 952 /* turn on AHCI mode */ 953 ahci_enable_ahci(mmio); 954 955 /* Some registers might be cleared on reset. Restore 956 * initial values. 957 */ 958 if (!(hpriv->flags & AHCI_HFLAG_NO_WRITE_TO_RO)) 959 ahci_restore_initial_config(host); 960 } else 961 dev_info(host->dev, "skipping global host reset\n"); 962 963 return 0; 964 } 965 EXPORT_SYMBOL_GPL(ahci_reset_controller); 966 967 static void ahci_sw_activity(struct ata_link *link) 968 { 969 struct ata_port *ap = link->ap; 970 struct ahci_port_priv *pp = ap->private_data; 971 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 972 973 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY)) 974 return; 975 976 emp->activity++; 977 if (!timer_pending(&emp->timer)) 978 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10)); 979 } 980 981 static void ahci_sw_activity_blink(struct timer_list *t) 982 { 983 struct ahci_em_priv *emp = from_timer(emp, t, timer); 984 struct ata_link *link = emp->link; 985 struct ata_port *ap = link->ap; 986 987 unsigned long led_message = emp->led_state; 988 u32 activity_led_state; 989 unsigned long flags; 990 991 led_message &= EM_MSG_LED_VALUE; 992 led_message |= ap->port_no | (link->pmp << 8); 993 994 /* check to see if we've had activity. If so, 995 * toggle state of LED and reset timer. If not, 996 * turn LED to desired idle state. 997 */ 998 spin_lock_irqsave(ap->lock, flags); 999 if (emp->saved_activity != emp->activity) { 1000 emp->saved_activity = emp->activity; 1001 /* get the current LED state */ 1002 activity_led_state = led_message & EM_MSG_LED_VALUE_ON; 1003 1004 if (activity_led_state) 1005 activity_led_state = 0; 1006 else 1007 activity_led_state = 1; 1008 1009 /* clear old state */ 1010 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 1011 1012 /* toggle state */ 1013 led_message |= (activity_led_state << 16); 1014 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100)); 1015 } else { 1016 /* switch to idle */ 1017 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 1018 if (emp->blink_policy == BLINK_OFF) 1019 led_message |= (1 << 16); 1020 } 1021 spin_unlock_irqrestore(ap->lock, flags); 1022 ap->ops->transmit_led_message(ap, led_message, 4); 1023 } 1024 1025 static void ahci_init_sw_activity(struct ata_link *link) 1026 { 1027 struct ata_port *ap = link->ap; 1028 struct ahci_port_priv *pp = ap->private_data; 1029 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1030 1031 /* init activity stats, setup timer */ 1032 emp->saved_activity = emp->activity = 0; 1033 emp->link = link; 1034 timer_setup(&emp->timer, ahci_sw_activity_blink, 0); 1035 1036 /* check our blink policy and set flag for link if it's enabled */ 1037 if (emp->blink_policy) 1038 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1039 } 1040 1041 int ahci_reset_em(struct ata_host *host) 1042 { 1043 struct ahci_host_priv *hpriv = host->private_data; 1044 void __iomem *mmio = hpriv->mmio; 1045 u32 em_ctl; 1046 1047 em_ctl = readl(mmio + HOST_EM_CTL); 1048 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST)) 1049 return -EINVAL; 1050 1051 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL); 1052 return 0; 1053 } 1054 EXPORT_SYMBOL_GPL(ahci_reset_em); 1055 1056 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 1057 ssize_t size) 1058 { 1059 struct ahci_host_priv *hpriv = ap->host->private_data; 1060 struct ahci_port_priv *pp = ap->private_data; 1061 void __iomem *mmio = hpriv->mmio; 1062 u32 em_ctl; 1063 u32 message[] = {0, 0}; 1064 unsigned long flags; 1065 int pmp; 1066 struct ahci_em_priv *emp; 1067 1068 /* get the slot number from the message */ 1069 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1070 if (pmp < EM_MAX_SLOTS) 1071 emp = &pp->em_priv[pmp]; 1072 else 1073 return -EINVAL; 1074 1075 ahci_rpm_get_port(ap); 1076 spin_lock_irqsave(ap->lock, flags); 1077 1078 /* 1079 * if we are still busy transmitting a previous message, 1080 * do not allow 1081 */ 1082 em_ctl = readl(mmio + HOST_EM_CTL); 1083 if (em_ctl & EM_CTL_TM) { 1084 spin_unlock_irqrestore(ap->lock, flags); 1085 ahci_rpm_put_port(ap); 1086 return -EBUSY; 1087 } 1088 1089 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) { 1090 /* 1091 * create message header - this is all zero except for 1092 * the message size, which is 4 bytes. 1093 */ 1094 message[0] |= (4 << 8); 1095 1096 /* ignore 0:4 of byte zero, fill in port info yourself */ 1097 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no); 1098 1099 /* write message to EM_LOC */ 1100 writel(message[0], mmio + hpriv->em_loc); 1101 writel(message[1], mmio + hpriv->em_loc+4); 1102 1103 /* 1104 * tell hardware to transmit the message 1105 */ 1106 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 1107 } 1108 1109 /* save off new led state for port/slot */ 1110 emp->led_state = state; 1111 1112 spin_unlock_irqrestore(ap->lock, flags); 1113 ahci_rpm_put_port(ap); 1114 1115 return size; 1116 } 1117 1118 static ssize_t ahci_led_show(struct ata_port *ap, char *buf) 1119 { 1120 struct ahci_port_priv *pp = ap->private_data; 1121 struct ata_link *link; 1122 struct ahci_em_priv *emp; 1123 int rc = 0; 1124 1125 ata_for_each_link(link, ap, EDGE) { 1126 emp = &pp->em_priv[link->pmp]; 1127 rc += sprintf(buf, "%lx\n", emp->led_state); 1128 } 1129 return rc; 1130 } 1131 1132 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 1133 size_t size) 1134 { 1135 unsigned int state; 1136 int pmp; 1137 struct ahci_port_priv *pp = ap->private_data; 1138 struct ahci_em_priv *emp; 1139 1140 if (kstrtouint(buf, 0, &state) < 0) 1141 return -EINVAL; 1142 1143 /* get the slot number from the message */ 1144 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1145 if (pmp < EM_MAX_SLOTS) 1146 emp = &pp->em_priv[pmp]; 1147 else 1148 return -EINVAL; 1149 1150 /* mask off the activity bits if we are in sw_activity 1151 * mode, user should turn off sw_activity before setting 1152 * activity led through em_message 1153 */ 1154 if (emp->blink_policy) 1155 state &= ~EM_MSG_LED_VALUE_ACTIVITY; 1156 1157 return ap->ops->transmit_led_message(ap, state, size); 1158 } 1159 1160 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val) 1161 { 1162 struct ata_link *link = dev->link; 1163 struct ata_port *ap = link->ap; 1164 struct ahci_port_priv *pp = ap->private_data; 1165 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1166 u32 port_led_state = emp->led_state; 1167 1168 /* save the desired Activity LED behavior */ 1169 if (val == OFF) { 1170 /* clear LFLAG */ 1171 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY); 1172 1173 /* set the LED to OFF */ 1174 port_led_state &= EM_MSG_LED_VALUE_OFF; 1175 port_led_state |= (ap->port_no | (link->pmp << 8)); 1176 ap->ops->transmit_led_message(ap, port_led_state, 4); 1177 } else { 1178 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1179 if (val == BLINK_OFF) { 1180 /* set LED to ON for idle */ 1181 port_led_state &= EM_MSG_LED_VALUE_OFF; 1182 port_led_state |= (ap->port_no | (link->pmp << 8)); 1183 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */ 1184 ap->ops->transmit_led_message(ap, port_led_state, 4); 1185 } 1186 } 1187 emp->blink_policy = val; 1188 return 0; 1189 } 1190 1191 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf) 1192 { 1193 struct ata_link *link = dev->link; 1194 struct ata_port *ap = link->ap; 1195 struct ahci_port_priv *pp = ap->private_data; 1196 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1197 1198 /* display the saved value of activity behavior for this 1199 * disk. 1200 */ 1201 return sprintf(buf, "%d\n", emp->blink_policy); 1202 } 1203 1204 static void ahci_port_init(struct device *dev, struct ata_port *ap, 1205 int port_no, void __iomem *mmio, 1206 void __iomem *port_mmio) 1207 { 1208 struct ahci_host_priv *hpriv = ap->host->private_data; 1209 const char *emsg = NULL; 1210 int rc; 1211 u32 tmp; 1212 1213 /* make sure port is not active */ 1214 rc = ahci_deinit_port(ap, &emsg); 1215 if (rc) 1216 dev_warn(dev, "%s (%d)\n", emsg, rc); 1217 1218 /* clear SError */ 1219 tmp = readl(port_mmio + PORT_SCR_ERR); 1220 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); 1221 writel(tmp, port_mmio + PORT_SCR_ERR); 1222 1223 /* clear port IRQ */ 1224 tmp = readl(port_mmio + PORT_IRQ_STAT); 1225 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 1226 if (tmp) 1227 writel(tmp, port_mmio + PORT_IRQ_STAT); 1228 1229 writel(1 << port_no, mmio + HOST_IRQ_STAT); 1230 1231 /* mark esata ports */ 1232 tmp = readl(port_mmio + PORT_CMD); 1233 if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS)) 1234 ap->pflags |= ATA_PFLAG_EXTERNAL; 1235 } 1236 1237 void ahci_init_controller(struct ata_host *host) 1238 { 1239 struct ahci_host_priv *hpriv = host->private_data; 1240 void __iomem *mmio = hpriv->mmio; 1241 int i; 1242 void __iomem *port_mmio; 1243 u32 tmp; 1244 1245 for (i = 0; i < host->n_ports; i++) { 1246 struct ata_port *ap = host->ports[i]; 1247 1248 port_mmio = ahci_port_base(ap); 1249 if (ata_port_is_dummy(ap)) 1250 continue; 1251 1252 ahci_port_init(host->dev, ap, i, mmio, port_mmio); 1253 } 1254 1255 tmp = readl(mmio + HOST_CTL); 1256 VPRINTK("HOST_CTL 0x%x\n", tmp); 1257 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); 1258 tmp = readl(mmio + HOST_CTL); 1259 VPRINTK("HOST_CTL 0x%x\n", tmp); 1260 } 1261 EXPORT_SYMBOL_GPL(ahci_init_controller); 1262 1263 static void ahci_dev_config(struct ata_device *dev) 1264 { 1265 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data; 1266 1267 if (hpriv->flags & AHCI_HFLAG_SECT255) { 1268 dev->max_sectors = 255; 1269 ata_dev_info(dev, 1270 "SB600 AHCI: limiting to 255 sectors per cmd\n"); 1271 } 1272 } 1273 1274 unsigned int ahci_dev_classify(struct ata_port *ap) 1275 { 1276 void __iomem *port_mmio = ahci_port_base(ap); 1277 struct ata_taskfile tf; 1278 u32 tmp; 1279 1280 tmp = readl(port_mmio + PORT_SIG); 1281 tf.lbah = (tmp >> 24) & 0xff; 1282 tf.lbam = (tmp >> 16) & 0xff; 1283 tf.lbal = (tmp >> 8) & 0xff; 1284 tf.nsect = (tmp) & 0xff; 1285 1286 return ata_dev_classify(&tf); 1287 } 1288 EXPORT_SYMBOL_GPL(ahci_dev_classify); 1289 1290 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 1291 u32 opts) 1292 { 1293 dma_addr_t cmd_tbl_dma; 1294 1295 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; 1296 1297 pp->cmd_slot[tag].opts = cpu_to_le32(opts); 1298 pp->cmd_slot[tag].status = 0; 1299 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); 1300 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); 1301 } 1302 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot); 1303 1304 int ahci_kick_engine(struct ata_port *ap) 1305 { 1306 void __iomem *port_mmio = ahci_port_base(ap); 1307 struct ahci_host_priv *hpriv = ap->host->private_data; 1308 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1309 u32 tmp; 1310 int busy, rc; 1311 1312 /* stop engine */ 1313 rc = ahci_stop_engine(ap); 1314 if (rc) 1315 goto out_restart; 1316 1317 /* need to do CLO? 1318 * always do CLO if PMP is attached (AHCI-1.3 9.2) 1319 */ 1320 busy = status & (ATA_BUSY | ATA_DRQ); 1321 if (!busy && !sata_pmp_attached(ap)) { 1322 rc = 0; 1323 goto out_restart; 1324 } 1325 1326 if (!(hpriv->cap & HOST_CAP_CLO)) { 1327 rc = -EOPNOTSUPP; 1328 goto out_restart; 1329 } 1330 1331 /* perform CLO */ 1332 tmp = readl(port_mmio + PORT_CMD); 1333 tmp |= PORT_CMD_CLO; 1334 writel(tmp, port_mmio + PORT_CMD); 1335 1336 rc = 0; 1337 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 1338 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); 1339 if (tmp & PORT_CMD_CLO) 1340 rc = -EIO; 1341 1342 /* restart engine */ 1343 out_restart: 1344 hpriv->start_engine(ap); 1345 return rc; 1346 } 1347 EXPORT_SYMBOL_GPL(ahci_kick_engine); 1348 1349 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, 1350 struct ata_taskfile *tf, int is_cmd, u16 flags, 1351 unsigned long timeout_msec) 1352 { 1353 const u32 cmd_fis_len = 5; /* five dwords */ 1354 struct ahci_port_priv *pp = ap->private_data; 1355 void __iomem *port_mmio = ahci_port_base(ap); 1356 u8 *fis = pp->cmd_tbl; 1357 u32 tmp; 1358 1359 /* prep the command */ 1360 ata_tf_to_fis(tf, pmp, is_cmd, fis); 1361 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); 1362 1363 /* set port value for softreset of Port Multiplier */ 1364 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) { 1365 tmp = readl(port_mmio + PORT_FBS); 1366 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); 1367 tmp |= pmp << PORT_FBS_DEV_OFFSET; 1368 writel(tmp, port_mmio + PORT_FBS); 1369 pp->fbs_last_dev = pmp; 1370 } 1371 1372 /* issue & wait */ 1373 writel(1, port_mmio + PORT_CMD_ISSUE); 1374 1375 if (timeout_msec) { 1376 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE, 1377 0x1, 0x1, 1, timeout_msec); 1378 if (tmp & 0x1) { 1379 ahci_kick_engine(ap); 1380 return -EBUSY; 1381 } 1382 } else 1383 readl(port_mmio + PORT_CMD_ISSUE); /* flush */ 1384 1385 return 0; 1386 } 1387 1388 int ahci_do_softreset(struct ata_link *link, unsigned int *class, 1389 int pmp, unsigned long deadline, 1390 int (*check_ready)(struct ata_link *link)) 1391 { 1392 struct ata_port *ap = link->ap; 1393 struct ahci_host_priv *hpriv = ap->host->private_data; 1394 struct ahci_port_priv *pp = ap->private_data; 1395 const char *reason = NULL; 1396 unsigned long now, msecs; 1397 struct ata_taskfile tf; 1398 bool fbs_disabled = false; 1399 int rc; 1400 1401 DPRINTK("ENTER\n"); 1402 1403 /* prepare for SRST (AHCI-1.1 10.4.1) */ 1404 rc = ahci_kick_engine(ap); 1405 if (rc && rc != -EOPNOTSUPP) 1406 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc); 1407 1408 /* 1409 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall 1410 * clear PxFBS.EN to '0' prior to issuing software reset to devices 1411 * that is attached to port multiplier. 1412 */ 1413 if (!ata_is_host_link(link) && pp->fbs_enabled) { 1414 ahci_disable_fbs(ap); 1415 fbs_disabled = true; 1416 } 1417 1418 ata_tf_init(link->device, &tf); 1419 1420 /* issue the first H2D Register FIS */ 1421 msecs = 0; 1422 now = jiffies; 1423 if (time_after(deadline, now)) 1424 msecs = jiffies_to_msecs(deadline - now); 1425 1426 tf.ctl |= ATA_SRST; 1427 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, 1428 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { 1429 rc = -EIO; 1430 reason = "1st FIS failed"; 1431 goto fail; 1432 } 1433 1434 /* spec says at least 5us, but be generous and sleep for 1ms */ 1435 ata_msleep(ap, 1); 1436 1437 /* issue the second H2D Register FIS */ 1438 tf.ctl &= ~ATA_SRST; 1439 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); 1440 1441 /* wait for link to become ready */ 1442 rc = ata_wait_after_reset(link, deadline, check_ready); 1443 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) { 1444 /* 1445 * Workaround for cases where link online status can't 1446 * be trusted. Treat device readiness timeout as link 1447 * offline. 1448 */ 1449 ata_link_info(link, "device not ready, treating as offline\n"); 1450 *class = ATA_DEV_NONE; 1451 } else if (rc) { 1452 /* link occupied, -ENODEV too is an error */ 1453 reason = "device not ready"; 1454 goto fail; 1455 } else 1456 *class = ahci_dev_classify(ap); 1457 1458 /* re-enable FBS if disabled before */ 1459 if (fbs_disabled) 1460 ahci_enable_fbs(ap); 1461 1462 DPRINTK("EXIT, class=%u\n", *class); 1463 return 0; 1464 1465 fail: 1466 ata_link_err(link, "softreset failed (%s)\n", reason); 1467 return rc; 1468 } 1469 1470 int ahci_check_ready(struct ata_link *link) 1471 { 1472 void __iomem *port_mmio = ahci_port_base(link->ap); 1473 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1474 1475 return ata_check_ready(status); 1476 } 1477 EXPORT_SYMBOL_GPL(ahci_check_ready); 1478 1479 static int ahci_softreset(struct ata_link *link, unsigned int *class, 1480 unsigned long deadline) 1481 { 1482 int pmp = sata_srst_pmp(link); 1483 1484 DPRINTK("ENTER\n"); 1485 1486 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready); 1487 } 1488 EXPORT_SYMBOL_GPL(ahci_do_softreset); 1489 1490 static int ahci_bad_pmp_check_ready(struct ata_link *link) 1491 { 1492 void __iomem *port_mmio = ahci_port_base(link->ap); 1493 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1494 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT); 1495 1496 /* 1497 * There is no need to check TFDATA if BAD PMP is found due to HW bug, 1498 * which can save timeout delay. 1499 */ 1500 if (irq_status & PORT_IRQ_BAD_PMP) 1501 return -EIO; 1502 1503 return ata_check_ready(status); 1504 } 1505 1506 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class, 1507 unsigned long deadline) 1508 { 1509 struct ata_port *ap = link->ap; 1510 void __iomem *port_mmio = ahci_port_base(ap); 1511 int pmp = sata_srst_pmp(link); 1512 int rc; 1513 u32 irq_sts; 1514 1515 DPRINTK("ENTER\n"); 1516 1517 rc = ahci_do_softreset(link, class, pmp, deadline, 1518 ahci_bad_pmp_check_ready); 1519 1520 /* 1521 * Soft reset fails with IPMS set when PMP is enabled but 1522 * SATA HDD/ODD is connected to SATA port, do soft reset 1523 * again to port 0. 1524 */ 1525 if (rc == -EIO) { 1526 irq_sts = readl(port_mmio + PORT_IRQ_STAT); 1527 if (irq_sts & PORT_IRQ_BAD_PMP) { 1528 ata_link_warn(link, 1529 "applying PMP SRST workaround " 1530 "and retrying\n"); 1531 rc = ahci_do_softreset(link, class, 0, deadline, 1532 ahci_check_ready); 1533 } 1534 } 1535 1536 return rc; 1537 } 1538 1539 int ahci_do_hardreset(struct ata_link *link, unsigned int *class, 1540 unsigned long deadline, bool *online) 1541 { 1542 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 1543 struct ata_port *ap = link->ap; 1544 struct ahci_port_priv *pp = ap->private_data; 1545 struct ahci_host_priv *hpriv = ap->host->private_data; 1546 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 1547 struct ata_taskfile tf; 1548 int rc; 1549 1550 DPRINTK("ENTER\n"); 1551 1552 ahci_stop_engine(ap); 1553 1554 /* clear D2H reception area to properly wait for D2H FIS */ 1555 ata_tf_init(link->device, &tf); 1556 tf.command = ATA_BUSY; 1557 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 1558 1559 rc = sata_link_hardreset(link, timing, deadline, online, 1560 ahci_check_ready); 1561 1562 hpriv->start_engine(ap); 1563 1564 if (*online) 1565 *class = ahci_dev_classify(ap); 1566 1567 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 1568 return rc; 1569 } 1570 EXPORT_SYMBOL_GPL(ahci_do_hardreset); 1571 1572 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 1573 unsigned long deadline) 1574 { 1575 bool online; 1576 1577 return ahci_do_hardreset(link, class, deadline, &online); 1578 } 1579 1580 static void ahci_postreset(struct ata_link *link, unsigned int *class) 1581 { 1582 struct ata_port *ap = link->ap; 1583 void __iomem *port_mmio = ahci_port_base(ap); 1584 u32 new_tmp, tmp; 1585 1586 ata_std_postreset(link, class); 1587 1588 /* Make sure port's ATAPI bit is set appropriately */ 1589 new_tmp = tmp = readl(port_mmio + PORT_CMD); 1590 if (*class == ATA_DEV_ATAPI) 1591 new_tmp |= PORT_CMD_ATAPI; 1592 else 1593 new_tmp &= ~PORT_CMD_ATAPI; 1594 if (new_tmp != tmp) { 1595 writel(new_tmp, port_mmio + PORT_CMD); 1596 readl(port_mmio + PORT_CMD); /* flush */ 1597 } 1598 } 1599 1600 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) 1601 { 1602 struct scatterlist *sg; 1603 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; 1604 unsigned int si; 1605 1606 VPRINTK("ENTER\n"); 1607 1608 /* 1609 * Next, the S/G list. 1610 */ 1611 for_each_sg(qc->sg, sg, qc->n_elem, si) { 1612 dma_addr_t addr = sg_dma_address(sg); 1613 u32 sg_len = sg_dma_len(sg); 1614 1615 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); 1616 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); 1617 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); 1618 } 1619 1620 return si; 1621 } 1622 1623 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc) 1624 { 1625 struct ata_port *ap = qc->ap; 1626 struct ahci_port_priv *pp = ap->private_data; 1627 1628 if (!sata_pmp_attached(ap) || pp->fbs_enabled) 1629 return ata_std_qc_defer(qc); 1630 else 1631 return sata_pmp_qc_defer_cmd_switch(qc); 1632 } 1633 1634 static void ahci_qc_prep(struct ata_queued_cmd *qc) 1635 { 1636 struct ata_port *ap = qc->ap; 1637 struct ahci_port_priv *pp = ap->private_data; 1638 int is_atapi = ata_is_atapi(qc->tf.protocol); 1639 void *cmd_tbl; 1640 u32 opts; 1641 const u32 cmd_fis_len = 5; /* five dwords */ 1642 unsigned int n_elem; 1643 1644 /* 1645 * Fill in command table information. First, the header, 1646 * a SATA Register - Host to Device command FIS. 1647 */ 1648 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; 1649 1650 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); 1651 if (is_atapi) { 1652 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); 1653 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); 1654 } 1655 1656 n_elem = 0; 1657 if (qc->flags & ATA_QCFLAG_DMAMAP) 1658 n_elem = ahci_fill_sg(qc, cmd_tbl); 1659 1660 /* 1661 * Fill in command slot information. 1662 */ 1663 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); 1664 if (qc->tf.flags & ATA_TFLAG_WRITE) 1665 opts |= AHCI_CMD_WRITE; 1666 if (is_atapi) 1667 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; 1668 1669 ahci_fill_cmd_slot(pp, qc->tag, opts); 1670 } 1671 1672 static void ahci_fbs_dec_intr(struct ata_port *ap) 1673 { 1674 struct ahci_port_priv *pp = ap->private_data; 1675 void __iomem *port_mmio = ahci_port_base(ap); 1676 u32 fbs = readl(port_mmio + PORT_FBS); 1677 int retries = 3; 1678 1679 DPRINTK("ENTER\n"); 1680 BUG_ON(!pp->fbs_enabled); 1681 1682 /* time to wait for DEC is not specified by AHCI spec, 1683 * add a retry loop for safety. 1684 */ 1685 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS); 1686 fbs = readl(port_mmio + PORT_FBS); 1687 while ((fbs & PORT_FBS_DEC) && retries--) { 1688 udelay(1); 1689 fbs = readl(port_mmio + PORT_FBS); 1690 } 1691 1692 if (fbs & PORT_FBS_DEC) 1693 dev_err(ap->host->dev, "failed to clear device error\n"); 1694 } 1695 1696 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) 1697 { 1698 struct ahci_host_priv *hpriv = ap->host->private_data; 1699 struct ahci_port_priv *pp = ap->private_data; 1700 struct ata_eh_info *host_ehi = &ap->link.eh_info; 1701 struct ata_link *link = NULL; 1702 struct ata_queued_cmd *active_qc; 1703 struct ata_eh_info *active_ehi; 1704 bool fbs_need_dec = false; 1705 u32 serror; 1706 1707 /* determine active link with error */ 1708 if (pp->fbs_enabled) { 1709 void __iomem *port_mmio = ahci_port_base(ap); 1710 u32 fbs = readl(port_mmio + PORT_FBS); 1711 int pmp = fbs >> PORT_FBS_DWE_OFFSET; 1712 1713 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) { 1714 link = &ap->pmp_link[pmp]; 1715 fbs_need_dec = true; 1716 } 1717 1718 } else 1719 ata_for_each_link(link, ap, EDGE) 1720 if (ata_link_active(link)) 1721 break; 1722 1723 if (!link) 1724 link = &ap->link; 1725 1726 active_qc = ata_qc_from_tag(ap, link->active_tag); 1727 active_ehi = &link->eh_info; 1728 1729 /* record irq stat */ 1730 ata_ehi_clear_desc(host_ehi); 1731 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); 1732 1733 /* AHCI needs SError cleared; otherwise, it might lock up */ 1734 ahci_scr_read(&ap->link, SCR_ERROR, &serror); 1735 ahci_scr_write(&ap->link, SCR_ERROR, serror); 1736 host_ehi->serror |= serror; 1737 1738 /* some controllers set IRQ_IF_ERR on device errors, ignore it */ 1739 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) 1740 irq_stat &= ~PORT_IRQ_IF_ERR; 1741 1742 if (irq_stat & PORT_IRQ_TF_ERR) { 1743 /* If qc is active, charge it; otherwise, the active 1744 * link. There's no active qc on NCQ errors. It will 1745 * be determined by EH by reading log page 10h. 1746 */ 1747 if (active_qc) 1748 active_qc->err_mask |= AC_ERR_DEV; 1749 else 1750 active_ehi->err_mask |= AC_ERR_DEV; 1751 1752 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) 1753 host_ehi->serror &= ~SERR_INTERNAL; 1754 } 1755 1756 if (irq_stat & PORT_IRQ_UNK_FIS) { 1757 u32 *unk = pp->rx_fis + RX_FIS_UNK; 1758 1759 active_ehi->err_mask |= AC_ERR_HSM; 1760 active_ehi->action |= ATA_EH_RESET; 1761 ata_ehi_push_desc(active_ehi, 1762 "unknown FIS %08x %08x %08x %08x" , 1763 unk[0], unk[1], unk[2], unk[3]); 1764 } 1765 1766 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) { 1767 active_ehi->err_mask |= AC_ERR_HSM; 1768 active_ehi->action |= ATA_EH_RESET; 1769 ata_ehi_push_desc(active_ehi, "incorrect PMP"); 1770 } 1771 1772 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { 1773 host_ehi->err_mask |= AC_ERR_HOST_BUS; 1774 host_ehi->action |= ATA_EH_RESET; 1775 ata_ehi_push_desc(host_ehi, "host bus error"); 1776 } 1777 1778 if (irq_stat & PORT_IRQ_IF_ERR) { 1779 if (fbs_need_dec) 1780 active_ehi->err_mask |= AC_ERR_DEV; 1781 else { 1782 host_ehi->err_mask |= AC_ERR_ATA_BUS; 1783 host_ehi->action |= ATA_EH_RESET; 1784 } 1785 1786 ata_ehi_push_desc(host_ehi, "interface fatal error"); 1787 } 1788 1789 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { 1790 ata_ehi_hotplugged(host_ehi); 1791 ata_ehi_push_desc(host_ehi, "%s", 1792 irq_stat & PORT_IRQ_CONNECT ? 1793 "connection status changed" : "PHY RDY changed"); 1794 } 1795 1796 /* okay, let's hand over to EH */ 1797 1798 if (irq_stat & PORT_IRQ_FREEZE) 1799 ata_port_freeze(ap); 1800 else if (fbs_need_dec) { 1801 ata_link_abort(link); 1802 ahci_fbs_dec_intr(ap); 1803 } else 1804 ata_port_abort(ap); 1805 } 1806 1807 static void ahci_handle_port_interrupt(struct ata_port *ap, 1808 void __iomem *port_mmio, u32 status) 1809 { 1810 struct ata_eh_info *ehi = &ap->link.eh_info; 1811 struct ahci_port_priv *pp = ap->private_data; 1812 struct ahci_host_priv *hpriv = ap->host->private_data; 1813 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING); 1814 u32 qc_active = 0; 1815 int rc; 1816 1817 /* ignore BAD_PMP while resetting */ 1818 if (unlikely(resetting)) 1819 status &= ~PORT_IRQ_BAD_PMP; 1820 1821 if (sata_lpm_ignore_phy_events(&ap->link)) { 1822 status &= ~PORT_IRQ_PHYRDY; 1823 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG); 1824 } 1825 1826 if (unlikely(status & PORT_IRQ_ERROR)) { 1827 ahci_error_intr(ap, status); 1828 return; 1829 } 1830 1831 if (status & PORT_IRQ_SDB_FIS) { 1832 /* If SNotification is available, leave notification 1833 * handling to sata_async_notification(). If not, 1834 * emulate it by snooping SDB FIS RX area. 1835 * 1836 * Snooping FIS RX area is probably cheaper than 1837 * poking SNotification but some constrollers which 1838 * implement SNotification, ICH9 for example, don't 1839 * store AN SDB FIS into receive area. 1840 */ 1841 if (hpriv->cap & HOST_CAP_SNTF) 1842 sata_async_notification(ap); 1843 else { 1844 /* If the 'N' bit in word 0 of the FIS is set, 1845 * we just received asynchronous notification. 1846 * Tell libata about it. 1847 * 1848 * Lack of SNotification should not appear in 1849 * ahci 1.2, so the workaround is unnecessary 1850 * when FBS is enabled. 1851 */ 1852 if (pp->fbs_enabled) 1853 WARN_ON_ONCE(1); 1854 else { 1855 const __le32 *f = pp->rx_fis + RX_FIS_SDB; 1856 u32 f0 = le32_to_cpu(f[0]); 1857 if (f0 & (1 << 15)) 1858 sata_async_notification(ap); 1859 } 1860 } 1861 } 1862 1863 /* pp->active_link is not reliable once FBS is enabled, both 1864 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because 1865 * NCQ and non-NCQ commands may be in flight at the same time. 1866 */ 1867 if (pp->fbs_enabled) { 1868 if (ap->qc_active) { 1869 qc_active = readl(port_mmio + PORT_SCR_ACT); 1870 qc_active |= readl(port_mmio + PORT_CMD_ISSUE); 1871 } 1872 } else { 1873 /* pp->active_link is valid iff any command is in flight */ 1874 if (ap->qc_active && pp->active_link->sactive) 1875 qc_active = readl(port_mmio + PORT_SCR_ACT); 1876 else 1877 qc_active = readl(port_mmio + PORT_CMD_ISSUE); 1878 } 1879 1880 1881 rc = ata_qc_complete_multiple(ap, qc_active); 1882 1883 /* while resetting, invalid completions are expected */ 1884 if (unlikely(rc < 0 && !resetting)) { 1885 ehi->err_mask |= AC_ERR_HSM; 1886 ehi->action |= ATA_EH_RESET; 1887 ata_port_freeze(ap); 1888 } 1889 } 1890 1891 static void ahci_port_intr(struct ata_port *ap) 1892 { 1893 void __iomem *port_mmio = ahci_port_base(ap); 1894 u32 status; 1895 1896 status = readl(port_mmio + PORT_IRQ_STAT); 1897 writel(status, port_mmio + PORT_IRQ_STAT); 1898 1899 ahci_handle_port_interrupt(ap, port_mmio, status); 1900 } 1901 1902 static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance) 1903 { 1904 struct ata_port *ap = dev_instance; 1905 void __iomem *port_mmio = ahci_port_base(ap); 1906 u32 status; 1907 1908 VPRINTK("ENTER\n"); 1909 1910 status = readl(port_mmio + PORT_IRQ_STAT); 1911 writel(status, port_mmio + PORT_IRQ_STAT); 1912 1913 spin_lock(ap->lock); 1914 ahci_handle_port_interrupt(ap, port_mmio, status); 1915 spin_unlock(ap->lock); 1916 1917 VPRINTK("EXIT\n"); 1918 1919 return IRQ_HANDLED; 1920 } 1921 1922 u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked) 1923 { 1924 unsigned int i, handled = 0; 1925 1926 for (i = 0; i < host->n_ports; i++) { 1927 struct ata_port *ap; 1928 1929 if (!(irq_masked & (1 << i))) 1930 continue; 1931 1932 ap = host->ports[i]; 1933 if (ap) { 1934 ahci_port_intr(ap); 1935 VPRINTK("port %u\n", i); 1936 } else { 1937 VPRINTK("port %u (no irq)\n", i); 1938 if (ata_ratelimit()) 1939 dev_warn(host->dev, 1940 "interrupt on disabled port %u\n", i); 1941 } 1942 1943 handled = 1; 1944 } 1945 1946 return handled; 1947 } 1948 EXPORT_SYMBOL_GPL(ahci_handle_port_intr); 1949 1950 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance) 1951 { 1952 struct ata_host *host = dev_instance; 1953 struct ahci_host_priv *hpriv; 1954 unsigned int rc = 0; 1955 void __iomem *mmio; 1956 u32 irq_stat, irq_masked; 1957 1958 VPRINTK("ENTER\n"); 1959 1960 hpriv = host->private_data; 1961 mmio = hpriv->mmio; 1962 1963 /* sigh. 0xffffffff is a valid return from h/w */ 1964 irq_stat = readl(mmio + HOST_IRQ_STAT); 1965 if (!irq_stat) 1966 return IRQ_NONE; 1967 1968 irq_masked = irq_stat & hpriv->port_map; 1969 1970 spin_lock(&host->lock); 1971 1972 rc = ahci_handle_port_intr(host, irq_masked); 1973 1974 /* HOST_IRQ_STAT behaves as level triggered latch meaning that 1975 * it should be cleared after all the port events are cleared; 1976 * otherwise, it will raise a spurious interrupt after each 1977 * valid one. Please read section 10.6.2 of ahci 1.1 for more 1978 * information. 1979 * 1980 * Also, use the unmasked value to clear interrupt as spurious 1981 * pending event on a dummy port might cause screaming IRQ. 1982 */ 1983 writel(irq_stat, mmio + HOST_IRQ_STAT); 1984 1985 spin_unlock(&host->lock); 1986 1987 VPRINTK("EXIT\n"); 1988 1989 return IRQ_RETVAL(rc); 1990 } 1991 1992 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) 1993 { 1994 struct ata_port *ap = qc->ap; 1995 void __iomem *port_mmio = ahci_port_base(ap); 1996 struct ahci_port_priv *pp = ap->private_data; 1997 1998 /* Keep track of the currently active link. It will be used 1999 * in completion path to determine whether NCQ phase is in 2000 * progress. 2001 */ 2002 pp->active_link = qc->dev->link; 2003 2004 if (ata_is_ncq(qc->tf.protocol)) 2005 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); 2006 2007 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) { 2008 u32 fbs = readl(port_mmio + PORT_FBS); 2009 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); 2010 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET; 2011 writel(fbs, port_mmio + PORT_FBS); 2012 pp->fbs_last_dev = qc->dev->link->pmp; 2013 } 2014 2015 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); 2016 2017 ahci_sw_activity(qc->dev->link); 2018 2019 return 0; 2020 } 2021 EXPORT_SYMBOL_GPL(ahci_qc_issue); 2022 2023 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc) 2024 { 2025 struct ahci_port_priv *pp = qc->ap->private_data; 2026 u8 *rx_fis = pp->rx_fis; 2027 2028 if (pp->fbs_enabled) 2029 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ; 2030 2031 /* 2032 * After a successful execution of an ATA PIO data-in command, 2033 * the device doesn't send D2H Reg FIS to update the TF and 2034 * the host should take TF and E_Status from the preceding PIO 2035 * Setup FIS. 2036 */ 2037 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE && 2038 !(qc->flags & ATA_QCFLAG_FAILED)) { 2039 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf); 2040 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15]; 2041 } else 2042 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf); 2043 2044 return true; 2045 } 2046 2047 static void ahci_freeze(struct ata_port *ap) 2048 { 2049 void __iomem *port_mmio = ahci_port_base(ap); 2050 2051 /* turn IRQ off */ 2052 writel(0, port_mmio + PORT_IRQ_MASK); 2053 } 2054 2055 static void ahci_thaw(struct ata_port *ap) 2056 { 2057 struct ahci_host_priv *hpriv = ap->host->private_data; 2058 void __iomem *mmio = hpriv->mmio; 2059 void __iomem *port_mmio = ahci_port_base(ap); 2060 u32 tmp; 2061 struct ahci_port_priv *pp = ap->private_data; 2062 2063 /* clear IRQ */ 2064 tmp = readl(port_mmio + PORT_IRQ_STAT); 2065 writel(tmp, port_mmio + PORT_IRQ_STAT); 2066 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); 2067 2068 /* turn IRQ back on */ 2069 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2070 } 2071 2072 void ahci_error_handler(struct ata_port *ap) 2073 { 2074 struct ahci_host_priv *hpriv = ap->host->private_data; 2075 2076 if (!(ap->pflags & ATA_PFLAG_FROZEN)) { 2077 /* restart engine */ 2078 ahci_stop_engine(ap); 2079 hpriv->start_engine(ap); 2080 } 2081 2082 sata_pmp_error_handler(ap); 2083 2084 if (!ata_dev_enabled(ap->link.device)) 2085 ahci_stop_engine(ap); 2086 } 2087 EXPORT_SYMBOL_GPL(ahci_error_handler); 2088 2089 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) 2090 { 2091 struct ata_port *ap = qc->ap; 2092 2093 /* make DMA engine forget about the failed command */ 2094 if (qc->flags & ATA_QCFLAG_FAILED) 2095 ahci_kick_engine(ap); 2096 } 2097 2098 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep) 2099 { 2100 struct ahci_host_priv *hpriv = ap->host->private_data; 2101 void __iomem *port_mmio = ahci_port_base(ap); 2102 struct ata_device *dev = ap->link.device; 2103 u32 devslp, dm, dito, mdat, deto; 2104 int rc; 2105 unsigned int err_mask; 2106 2107 devslp = readl(port_mmio + PORT_DEVSLP); 2108 if (!(devslp & PORT_DEVSLP_DSP)) { 2109 dev_info(ap->host->dev, "port does not support device sleep\n"); 2110 return; 2111 } 2112 2113 /* disable device sleep */ 2114 if (!sleep) { 2115 if (devslp & PORT_DEVSLP_ADSE) { 2116 writel(devslp & ~PORT_DEVSLP_ADSE, 2117 port_mmio + PORT_DEVSLP); 2118 err_mask = ata_dev_set_feature(dev, 2119 SETFEATURES_SATA_DISABLE, 2120 SATA_DEVSLP); 2121 if (err_mask && err_mask != AC_ERR_DEV) 2122 ata_dev_warn(dev, "failed to disable DEVSLP\n"); 2123 } 2124 return; 2125 } 2126 2127 /* device sleep was already enabled */ 2128 if (devslp & PORT_DEVSLP_ADSE) 2129 return; 2130 2131 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */ 2132 rc = ahci_stop_engine(ap); 2133 if (rc) 2134 return; 2135 2136 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET; 2137 dito = devslp_idle_timeout / (dm + 1); 2138 if (dito > 0x3ff) 2139 dito = 0x3ff; 2140 2141 /* Use the nominal value 10 ms if the read MDAT is zero, 2142 * the nominal value of DETO is 20 ms. 2143 */ 2144 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] & 2145 ATA_LOG_DEVSLP_VALID_MASK) { 2146 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] & 2147 ATA_LOG_DEVSLP_MDAT_MASK; 2148 if (!mdat) 2149 mdat = 10; 2150 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO]; 2151 if (!deto) 2152 deto = 20; 2153 } else { 2154 mdat = 10; 2155 deto = 20; 2156 } 2157 2158 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) | 2159 (mdat << PORT_DEVSLP_MDAT_OFFSET) | 2160 (deto << PORT_DEVSLP_DETO_OFFSET) | 2161 PORT_DEVSLP_ADSE); 2162 writel(devslp, port_mmio + PORT_DEVSLP); 2163 2164 hpriv->start_engine(ap); 2165 2166 /* enable device sleep feature for the drive */ 2167 err_mask = ata_dev_set_feature(dev, 2168 SETFEATURES_SATA_ENABLE, 2169 SATA_DEVSLP); 2170 if (err_mask && err_mask != AC_ERR_DEV) 2171 ata_dev_warn(dev, "failed to enable DEVSLP\n"); 2172 } 2173 2174 static void ahci_enable_fbs(struct ata_port *ap) 2175 { 2176 struct ahci_host_priv *hpriv = ap->host->private_data; 2177 struct ahci_port_priv *pp = ap->private_data; 2178 void __iomem *port_mmio = ahci_port_base(ap); 2179 u32 fbs; 2180 int rc; 2181 2182 if (!pp->fbs_supported) 2183 return; 2184 2185 fbs = readl(port_mmio + PORT_FBS); 2186 if (fbs & PORT_FBS_EN) { 2187 pp->fbs_enabled = true; 2188 pp->fbs_last_dev = -1; /* initialization */ 2189 return; 2190 } 2191 2192 rc = ahci_stop_engine(ap); 2193 if (rc) 2194 return; 2195 2196 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS); 2197 fbs = readl(port_mmio + PORT_FBS); 2198 if (fbs & PORT_FBS_EN) { 2199 dev_info(ap->host->dev, "FBS is enabled\n"); 2200 pp->fbs_enabled = true; 2201 pp->fbs_last_dev = -1; /* initialization */ 2202 } else 2203 dev_err(ap->host->dev, "Failed to enable FBS\n"); 2204 2205 hpriv->start_engine(ap); 2206 } 2207 2208 static void ahci_disable_fbs(struct ata_port *ap) 2209 { 2210 struct ahci_host_priv *hpriv = ap->host->private_data; 2211 struct ahci_port_priv *pp = ap->private_data; 2212 void __iomem *port_mmio = ahci_port_base(ap); 2213 u32 fbs; 2214 int rc; 2215 2216 if (!pp->fbs_supported) 2217 return; 2218 2219 fbs = readl(port_mmio + PORT_FBS); 2220 if ((fbs & PORT_FBS_EN) == 0) { 2221 pp->fbs_enabled = false; 2222 return; 2223 } 2224 2225 rc = ahci_stop_engine(ap); 2226 if (rc) 2227 return; 2228 2229 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS); 2230 fbs = readl(port_mmio + PORT_FBS); 2231 if (fbs & PORT_FBS_EN) 2232 dev_err(ap->host->dev, "Failed to disable FBS\n"); 2233 else { 2234 dev_info(ap->host->dev, "FBS is disabled\n"); 2235 pp->fbs_enabled = false; 2236 } 2237 2238 hpriv->start_engine(ap); 2239 } 2240 2241 static void ahci_pmp_attach(struct ata_port *ap) 2242 { 2243 void __iomem *port_mmio = ahci_port_base(ap); 2244 struct ahci_port_priv *pp = ap->private_data; 2245 u32 cmd; 2246 2247 cmd = readl(port_mmio + PORT_CMD); 2248 cmd |= PORT_CMD_PMP; 2249 writel(cmd, port_mmio + PORT_CMD); 2250 2251 ahci_enable_fbs(ap); 2252 2253 pp->intr_mask |= PORT_IRQ_BAD_PMP; 2254 2255 /* 2256 * We must not change the port interrupt mask register if the 2257 * port is marked frozen, the value in pp->intr_mask will be 2258 * restored later when the port is thawed. 2259 * 2260 * Note that during initialization, the port is marked as 2261 * frozen since the irq handler is not yet registered. 2262 */ 2263 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 2264 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2265 } 2266 2267 static void ahci_pmp_detach(struct ata_port *ap) 2268 { 2269 void __iomem *port_mmio = ahci_port_base(ap); 2270 struct ahci_port_priv *pp = ap->private_data; 2271 u32 cmd; 2272 2273 ahci_disable_fbs(ap); 2274 2275 cmd = readl(port_mmio + PORT_CMD); 2276 cmd &= ~PORT_CMD_PMP; 2277 writel(cmd, port_mmio + PORT_CMD); 2278 2279 pp->intr_mask &= ~PORT_IRQ_BAD_PMP; 2280 2281 /* see comment above in ahci_pmp_attach() */ 2282 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 2283 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2284 } 2285 2286 int ahci_port_resume(struct ata_port *ap) 2287 { 2288 ahci_rpm_get_port(ap); 2289 2290 ahci_power_up(ap); 2291 ahci_start_port(ap); 2292 2293 if (sata_pmp_attached(ap)) 2294 ahci_pmp_attach(ap); 2295 else 2296 ahci_pmp_detach(ap); 2297 2298 return 0; 2299 } 2300 EXPORT_SYMBOL_GPL(ahci_port_resume); 2301 2302 #ifdef CONFIG_PM 2303 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) 2304 { 2305 const char *emsg = NULL; 2306 int rc; 2307 2308 rc = ahci_deinit_port(ap, &emsg); 2309 if (rc == 0) 2310 ahci_power_down(ap); 2311 else { 2312 ata_port_err(ap, "%s (%d)\n", emsg, rc); 2313 ata_port_freeze(ap); 2314 } 2315 2316 ahci_rpm_put_port(ap); 2317 return rc; 2318 } 2319 #endif 2320 2321 static int ahci_port_start(struct ata_port *ap) 2322 { 2323 struct ahci_host_priv *hpriv = ap->host->private_data; 2324 struct device *dev = ap->host->dev; 2325 struct ahci_port_priv *pp; 2326 void *mem; 2327 dma_addr_t mem_dma; 2328 size_t dma_sz, rx_fis_sz; 2329 2330 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 2331 if (!pp) 2332 return -ENOMEM; 2333 2334 if (ap->host->n_ports > 1) { 2335 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL); 2336 if (!pp->irq_desc) { 2337 devm_kfree(dev, pp); 2338 return -ENOMEM; 2339 } 2340 snprintf(pp->irq_desc, 8, 2341 "%s%d", dev_driver_string(dev), ap->port_no); 2342 } 2343 2344 /* check FBS capability */ 2345 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) { 2346 void __iomem *port_mmio = ahci_port_base(ap); 2347 u32 cmd = readl(port_mmio + PORT_CMD); 2348 if (cmd & PORT_CMD_FBSCP) 2349 pp->fbs_supported = true; 2350 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) { 2351 dev_info(dev, "port %d can do FBS, forcing FBSCP\n", 2352 ap->port_no); 2353 pp->fbs_supported = true; 2354 } else 2355 dev_warn(dev, "port %d is not capable of FBS\n", 2356 ap->port_no); 2357 } 2358 2359 if (pp->fbs_supported) { 2360 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ; 2361 rx_fis_sz = AHCI_RX_FIS_SZ * 16; 2362 } else { 2363 dma_sz = AHCI_PORT_PRIV_DMA_SZ; 2364 rx_fis_sz = AHCI_RX_FIS_SZ; 2365 } 2366 2367 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL); 2368 if (!mem) 2369 return -ENOMEM; 2370 memset(mem, 0, dma_sz); 2371 2372 /* 2373 * First item in chunk of DMA memory: 32-slot command table, 2374 * 32 bytes each in size 2375 */ 2376 pp->cmd_slot = mem; 2377 pp->cmd_slot_dma = mem_dma; 2378 2379 mem += AHCI_CMD_SLOT_SZ; 2380 mem_dma += AHCI_CMD_SLOT_SZ; 2381 2382 /* 2383 * Second item: Received-FIS area 2384 */ 2385 pp->rx_fis = mem; 2386 pp->rx_fis_dma = mem_dma; 2387 2388 mem += rx_fis_sz; 2389 mem_dma += rx_fis_sz; 2390 2391 /* 2392 * Third item: data area for storing a single command 2393 * and its scatter-gather table 2394 */ 2395 pp->cmd_tbl = mem; 2396 pp->cmd_tbl_dma = mem_dma; 2397 2398 /* 2399 * Save off initial list of interrupts to be enabled. 2400 * This could be changed later 2401 */ 2402 pp->intr_mask = DEF_PORT_IRQ; 2403 2404 /* 2405 * Switch to per-port locking in case each port has its own MSI vector. 2406 */ 2407 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) { 2408 spin_lock_init(&pp->lock); 2409 ap->lock = &pp->lock; 2410 } 2411 2412 ap->private_data = pp; 2413 2414 /* engage engines, captain */ 2415 return ahci_port_resume(ap); 2416 } 2417 2418 static void ahci_port_stop(struct ata_port *ap) 2419 { 2420 const char *emsg = NULL; 2421 struct ahci_host_priv *hpriv = ap->host->private_data; 2422 void __iomem *host_mmio = hpriv->mmio; 2423 int rc; 2424 2425 /* de-initialize port */ 2426 rc = ahci_deinit_port(ap, &emsg); 2427 if (rc) 2428 ata_port_warn(ap, "%s (%d)\n", emsg, rc); 2429 2430 /* 2431 * Clear GHC.IS to prevent stuck INTx after disabling MSI and 2432 * re-enabling INTx. 2433 */ 2434 writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT); 2435 } 2436 2437 void ahci_print_info(struct ata_host *host, const char *scc_s) 2438 { 2439 struct ahci_host_priv *hpriv = host->private_data; 2440 u32 vers, cap, cap2, impl, speed; 2441 const char *speed_s; 2442 2443 vers = hpriv->version; 2444 cap = hpriv->cap; 2445 cap2 = hpriv->cap2; 2446 impl = hpriv->port_map; 2447 2448 speed = (cap >> 20) & 0xf; 2449 if (speed == 1) 2450 speed_s = "1.5"; 2451 else if (speed == 2) 2452 speed_s = "3"; 2453 else if (speed == 3) 2454 speed_s = "6"; 2455 else 2456 speed_s = "?"; 2457 2458 dev_info(host->dev, 2459 "AHCI %02x%02x.%02x%02x " 2460 "%u slots %u ports %s Gbps 0x%x impl %s mode\n" 2461 , 2462 2463 (vers >> 24) & 0xff, 2464 (vers >> 16) & 0xff, 2465 (vers >> 8) & 0xff, 2466 vers & 0xff, 2467 2468 ((cap >> 8) & 0x1f) + 1, 2469 (cap & 0x1f) + 1, 2470 speed_s, 2471 impl, 2472 scc_s); 2473 2474 dev_info(host->dev, 2475 "flags: " 2476 "%s%s%s%s%s%s%s" 2477 "%s%s%s%s%s%s%s" 2478 "%s%s%s%s%s%s%s" 2479 "%s%s\n" 2480 , 2481 2482 cap & HOST_CAP_64 ? "64bit " : "", 2483 cap & HOST_CAP_NCQ ? "ncq " : "", 2484 cap & HOST_CAP_SNTF ? "sntf " : "", 2485 cap & HOST_CAP_MPS ? "ilck " : "", 2486 cap & HOST_CAP_SSS ? "stag " : "", 2487 cap & HOST_CAP_ALPM ? "pm " : "", 2488 cap & HOST_CAP_LED ? "led " : "", 2489 cap & HOST_CAP_CLO ? "clo " : "", 2490 cap & HOST_CAP_ONLY ? "only " : "", 2491 cap & HOST_CAP_PMP ? "pmp " : "", 2492 cap & HOST_CAP_FBS ? "fbs " : "", 2493 cap & HOST_CAP_PIO_MULTI ? "pio " : "", 2494 cap & HOST_CAP_SSC ? "slum " : "", 2495 cap & HOST_CAP_PART ? "part " : "", 2496 cap & HOST_CAP_CCC ? "ccc " : "", 2497 cap & HOST_CAP_EMS ? "ems " : "", 2498 cap & HOST_CAP_SXS ? "sxs " : "", 2499 cap2 & HOST_CAP2_DESO ? "deso " : "", 2500 cap2 & HOST_CAP2_SADM ? "sadm " : "", 2501 cap2 & HOST_CAP2_SDS ? "sds " : "", 2502 cap2 & HOST_CAP2_APST ? "apst " : "", 2503 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "", 2504 cap2 & HOST_CAP2_BOH ? "boh " : "" 2505 ); 2506 } 2507 EXPORT_SYMBOL_GPL(ahci_print_info); 2508 2509 void ahci_set_em_messages(struct ahci_host_priv *hpriv, 2510 struct ata_port_info *pi) 2511 { 2512 u8 messages; 2513 void __iomem *mmio = hpriv->mmio; 2514 u32 em_loc = readl(mmio + HOST_EM_LOC); 2515 u32 em_ctl = readl(mmio + HOST_EM_CTL); 2516 2517 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS)) 2518 return; 2519 2520 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16; 2521 2522 if (messages) { 2523 /* store em_loc */ 2524 hpriv->em_loc = ((em_loc >> 16) * 4); 2525 hpriv->em_buf_sz = ((em_loc & 0xff) * 4); 2526 hpriv->em_msg_type = messages; 2527 pi->flags |= ATA_FLAG_EM; 2528 if (!(em_ctl & EM_CTL_ALHD)) 2529 pi->flags |= ATA_FLAG_SW_ACTIVITY; 2530 } 2531 } 2532 EXPORT_SYMBOL_GPL(ahci_set_em_messages); 2533 2534 static int ahci_host_activate_multi_irqs(struct ata_host *host, 2535 struct scsi_host_template *sht) 2536 { 2537 struct ahci_host_priv *hpriv = host->private_data; 2538 int i, rc; 2539 2540 rc = ata_host_start(host); 2541 if (rc) 2542 return rc; 2543 /* 2544 * Requests IRQs according to AHCI-1.1 when multiple MSIs were 2545 * allocated. That is one MSI per port, starting from @irq. 2546 */ 2547 for (i = 0; i < host->n_ports; i++) { 2548 struct ahci_port_priv *pp = host->ports[i]->private_data; 2549 int irq = hpriv->get_irq_vector(host, i); 2550 2551 /* Do not receive interrupts sent by dummy ports */ 2552 if (!pp) { 2553 disable_irq(irq); 2554 continue; 2555 } 2556 2557 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard, 2558 0, pp->irq_desc, host->ports[i]); 2559 2560 if (rc) 2561 return rc; 2562 ata_port_desc(host->ports[i], "irq %d", irq); 2563 } 2564 2565 return ata_host_register(host, sht); 2566 } 2567 2568 /** 2569 * ahci_host_activate - start AHCI host, request IRQs and register it 2570 * @host: target ATA host 2571 * @sht: scsi_host_template to use when registering the host 2572 * 2573 * LOCKING: 2574 * Inherited from calling layer (may sleep). 2575 * 2576 * RETURNS: 2577 * 0 on success, -errno otherwise. 2578 */ 2579 int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht) 2580 { 2581 struct ahci_host_priv *hpriv = host->private_data; 2582 int irq = hpriv->irq; 2583 int rc; 2584 2585 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) { 2586 if (hpriv->irq_handler) 2587 dev_warn(host->dev, 2588 "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n"); 2589 if (!hpriv->get_irq_vector) { 2590 dev_err(host->dev, 2591 "AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n"); 2592 return -EIO; 2593 } 2594 2595 rc = ahci_host_activate_multi_irqs(host, sht); 2596 } else { 2597 rc = ata_host_activate(host, irq, hpriv->irq_handler, 2598 IRQF_SHARED, sht); 2599 } 2600 2601 2602 return rc; 2603 } 2604 EXPORT_SYMBOL_GPL(ahci_host_activate); 2605 2606 MODULE_AUTHOR("Jeff Garzik"); 2607 MODULE_DESCRIPTION("Common AHCI SATA low-level routines"); 2608 MODULE_LICENSE("GPL"); 2609