1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * libahci.c - Common AHCI SATA low-level routines 4 * 5 * Maintained by: Tejun Heo <tj@kernel.org> 6 * Please ALWAYS copy linux-ide@vger.kernel.org 7 * on emails. 8 * 9 * Copyright 2004-2005 Red Hat, Inc. 10 * 11 * libata documentation is available via 'make {ps|pdf}docs', 12 * as Documentation/driver-api/libata.rst 13 * 14 * AHCI hardware documentation: 15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/gfp.h> 21 #include <linux/module.h> 22 #include <linux/nospec.h> 23 #include <linux/blkdev.h> 24 #include <linux/delay.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/device.h> 28 #include <scsi/scsi_host.h> 29 #include <scsi/scsi_cmnd.h> 30 #include <linux/libata.h> 31 #include <linux/pci.h> 32 #include "ahci.h" 33 #include "libata.h" 34 35 static int ahci_skip_host_reset; 36 int ahci_ignore_sss; 37 EXPORT_SYMBOL_GPL(ahci_ignore_sss); 38 39 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); 40 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); 41 42 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444); 43 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)"); 44 45 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 46 unsigned hints); 47 static ssize_t ahci_led_show(struct ata_port *ap, char *buf); 48 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 49 size_t size); 50 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 51 ssize_t size); 52 53 54 55 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); 56 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); 57 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc); 58 static int ahci_port_start(struct ata_port *ap); 59 static void ahci_port_stop(struct ata_port *ap); 60 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc); 61 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc); 62 static void ahci_freeze(struct ata_port *ap); 63 static void ahci_thaw(struct ata_port *ap); 64 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep); 65 static void ahci_enable_fbs(struct ata_port *ap); 66 static void ahci_disable_fbs(struct ata_port *ap); 67 static void ahci_pmp_attach(struct ata_port *ap); 68 static void ahci_pmp_detach(struct ata_port *ap); 69 static int ahci_softreset(struct ata_link *link, unsigned int *class, 70 unsigned long deadline); 71 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class, 72 unsigned long deadline); 73 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 74 unsigned long deadline); 75 static void ahci_postreset(struct ata_link *link, unsigned int *class); 76 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); 77 static void ahci_dev_config(struct ata_device *dev); 78 #ifdef CONFIG_PM 79 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); 80 #endif 81 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf); 82 static ssize_t ahci_activity_store(struct ata_device *dev, 83 enum sw_activity val); 84 static void ahci_init_sw_activity(struct ata_link *link); 85 86 static ssize_t ahci_show_host_caps(struct device *dev, 87 struct device_attribute *attr, char *buf); 88 static ssize_t ahci_show_host_cap2(struct device *dev, 89 struct device_attribute *attr, char *buf); 90 static ssize_t ahci_show_host_version(struct device *dev, 91 struct device_attribute *attr, char *buf); 92 static ssize_t ahci_show_port_cmd(struct device *dev, 93 struct device_attribute *attr, char *buf); 94 static ssize_t ahci_read_em_buffer(struct device *dev, 95 struct device_attribute *attr, char *buf); 96 static ssize_t ahci_store_em_buffer(struct device *dev, 97 struct device_attribute *attr, 98 const char *buf, size_t size); 99 static ssize_t ahci_show_em_supported(struct device *dev, 100 struct device_attribute *attr, char *buf); 101 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance); 102 103 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL); 104 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL); 105 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL); 106 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL); 107 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO, 108 ahci_read_em_buffer, ahci_store_em_buffer); 109 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL); 110 111 struct device_attribute *ahci_shost_attrs[] = { 112 &dev_attr_link_power_management_policy, 113 &dev_attr_em_message_type, 114 &dev_attr_em_message, 115 &dev_attr_ahci_host_caps, 116 &dev_attr_ahci_host_cap2, 117 &dev_attr_ahci_host_version, 118 &dev_attr_ahci_port_cmd, 119 &dev_attr_em_buffer, 120 &dev_attr_em_message_supported, 121 NULL 122 }; 123 EXPORT_SYMBOL_GPL(ahci_shost_attrs); 124 125 struct device_attribute *ahci_sdev_attrs[] = { 126 &dev_attr_sw_activity, 127 &dev_attr_unload_heads, 128 &dev_attr_ncq_prio_enable, 129 NULL 130 }; 131 EXPORT_SYMBOL_GPL(ahci_sdev_attrs); 132 133 struct ata_port_operations ahci_ops = { 134 .inherits = &sata_pmp_port_ops, 135 136 .qc_defer = ahci_pmp_qc_defer, 137 .qc_prep = ahci_qc_prep, 138 .qc_issue = ahci_qc_issue, 139 .qc_fill_rtf = ahci_qc_fill_rtf, 140 141 .freeze = ahci_freeze, 142 .thaw = ahci_thaw, 143 .softreset = ahci_softreset, 144 .hardreset = ahci_hardreset, 145 .postreset = ahci_postreset, 146 .pmp_softreset = ahci_softreset, 147 .error_handler = ahci_error_handler, 148 .post_internal_cmd = ahci_post_internal_cmd, 149 .dev_config = ahci_dev_config, 150 151 .scr_read = ahci_scr_read, 152 .scr_write = ahci_scr_write, 153 .pmp_attach = ahci_pmp_attach, 154 .pmp_detach = ahci_pmp_detach, 155 156 .set_lpm = ahci_set_lpm, 157 .em_show = ahci_led_show, 158 .em_store = ahci_led_store, 159 .sw_activity_show = ahci_activity_show, 160 .sw_activity_store = ahci_activity_store, 161 .transmit_led_message = ahci_transmit_led_message, 162 #ifdef CONFIG_PM 163 .port_suspend = ahci_port_suspend, 164 .port_resume = ahci_port_resume, 165 #endif 166 .port_start = ahci_port_start, 167 .port_stop = ahci_port_stop, 168 }; 169 EXPORT_SYMBOL_GPL(ahci_ops); 170 171 struct ata_port_operations ahci_pmp_retry_srst_ops = { 172 .inherits = &ahci_ops, 173 .softreset = ahci_pmp_retry_softreset, 174 }; 175 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops); 176 177 static bool ahci_em_messages __read_mostly = true; 178 module_param(ahci_em_messages, bool, 0444); 179 /* add other LED protocol types when they become supported */ 180 MODULE_PARM_DESC(ahci_em_messages, 181 "AHCI Enclosure Management Message control (0 = off, 1 = on)"); 182 183 /* device sleep idle timeout in ms */ 184 static int devslp_idle_timeout __read_mostly = 1000; 185 module_param(devslp_idle_timeout, int, 0644); 186 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout"); 187 188 static void ahci_enable_ahci(void __iomem *mmio) 189 { 190 int i; 191 u32 tmp; 192 193 /* turn on AHCI_EN */ 194 tmp = readl(mmio + HOST_CTL); 195 if (tmp & HOST_AHCI_EN) 196 return; 197 198 /* Some controllers need AHCI_EN to be written multiple times. 199 * Try a few times before giving up. 200 */ 201 for (i = 0; i < 5; i++) { 202 tmp |= HOST_AHCI_EN; 203 writel(tmp, mmio + HOST_CTL); 204 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ 205 if (tmp & HOST_AHCI_EN) 206 return; 207 msleep(10); 208 } 209 210 WARN_ON(1); 211 } 212 213 /** 214 * ahci_rpm_get_port - Make sure the port is powered on 215 * @ap: Port to power on 216 * 217 * Whenever there is need to access the AHCI host registers outside of 218 * normal execution paths, call this function to make sure the host is 219 * actually powered on. 220 */ 221 static int ahci_rpm_get_port(struct ata_port *ap) 222 { 223 return pm_runtime_get_sync(ap->dev); 224 } 225 226 /** 227 * ahci_rpm_put_port - Undoes ahci_rpm_get_port() 228 * @ap: Port to power down 229 * 230 * Undoes ahci_rpm_get_port() and possibly powers down the AHCI host 231 * if it has no more active users. 232 */ 233 static void ahci_rpm_put_port(struct ata_port *ap) 234 { 235 pm_runtime_put(ap->dev); 236 } 237 238 static ssize_t ahci_show_host_caps(struct device *dev, 239 struct device_attribute *attr, char *buf) 240 { 241 struct Scsi_Host *shost = class_to_shost(dev); 242 struct ata_port *ap = ata_shost_to_port(shost); 243 struct ahci_host_priv *hpriv = ap->host->private_data; 244 245 return sprintf(buf, "%x\n", hpriv->cap); 246 } 247 248 static ssize_t ahci_show_host_cap2(struct device *dev, 249 struct device_attribute *attr, char *buf) 250 { 251 struct Scsi_Host *shost = class_to_shost(dev); 252 struct ata_port *ap = ata_shost_to_port(shost); 253 struct ahci_host_priv *hpriv = ap->host->private_data; 254 255 return sprintf(buf, "%x\n", hpriv->cap2); 256 } 257 258 static ssize_t ahci_show_host_version(struct device *dev, 259 struct device_attribute *attr, char *buf) 260 { 261 struct Scsi_Host *shost = class_to_shost(dev); 262 struct ata_port *ap = ata_shost_to_port(shost); 263 struct ahci_host_priv *hpriv = ap->host->private_data; 264 265 return sprintf(buf, "%x\n", hpriv->version); 266 } 267 268 static ssize_t ahci_show_port_cmd(struct device *dev, 269 struct device_attribute *attr, char *buf) 270 { 271 struct Scsi_Host *shost = class_to_shost(dev); 272 struct ata_port *ap = ata_shost_to_port(shost); 273 void __iomem *port_mmio = ahci_port_base(ap); 274 ssize_t ret; 275 276 ahci_rpm_get_port(ap); 277 ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD)); 278 ahci_rpm_put_port(ap); 279 280 return ret; 281 } 282 283 static ssize_t ahci_read_em_buffer(struct device *dev, 284 struct device_attribute *attr, char *buf) 285 { 286 struct Scsi_Host *shost = class_to_shost(dev); 287 struct ata_port *ap = ata_shost_to_port(shost); 288 struct ahci_host_priv *hpriv = ap->host->private_data; 289 void __iomem *mmio = hpriv->mmio; 290 void __iomem *em_mmio = mmio + hpriv->em_loc; 291 u32 em_ctl, msg; 292 unsigned long flags; 293 size_t count; 294 int i; 295 296 ahci_rpm_get_port(ap); 297 spin_lock_irqsave(ap->lock, flags); 298 299 em_ctl = readl(mmio + HOST_EM_CTL); 300 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT || 301 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) { 302 spin_unlock_irqrestore(ap->lock, flags); 303 ahci_rpm_put_port(ap); 304 return -EINVAL; 305 } 306 307 if (!(em_ctl & EM_CTL_MR)) { 308 spin_unlock_irqrestore(ap->lock, flags); 309 ahci_rpm_put_port(ap); 310 return -EAGAIN; 311 } 312 313 if (!(em_ctl & EM_CTL_SMB)) 314 em_mmio += hpriv->em_buf_sz; 315 316 count = hpriv->em_buf_sz; 317 318 /* the count should not be larger than PAGE_SIZE */ 319 if (count > PAGE_SIZE) { 320 if (printk_ratelimit()) 321 ata_port_warn(ap, 322 "EM read buffer size too large: " 323 "buffer size %u, page size %lu\n", 324 hpriv->em_buf_sz, PAGE_SIZE); 325 count = PAGE_SIZE; 326 } 327 328 for (i = 0; i < count; i += 4) { 329 msg = readl(em_mmio + i); 330 buf[i] = msg & 0xff; 331 buf[i + 1] = (msg >> 8) & 0xff; 332 buf[i + 2] = (msg >> 16) & 0xff; 333 buf[i + 3] = (msg >> 24) & 0xff; 334 } 335 336 spin_unlock_irqrestore(ap->lock, flags); 337 ahci_rpm_put_port(ap); 338 339 return i; 340 } 341 342 static ssize_t ahci_store_em_buffer(struct device *dev, 343 struct device_attribute *attr, 344 const char *buf, size_t size) 345 { 346 struct Scsi_Host *shost = class_to_shost(dev); 347 struct ata_port *ap = ata_shost_to_port(shost); 348 struct ahci_host_priv *hpriv = ap->host->private_data; 349 void __iomem *mmio = hpriv->mmio; 350 void __iomem *em_mmio = mmio + hpriv->em_loc; 351 const unsigned char *msg_buf = buf; 352 u32 em_ctl, msg; 353 unsigned long flags; 354 int i; 355 356 /* check size validity */ 357 if (!(ap->flags & ATA_FLAG_EM) || 358 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) || 359 size % 4 || size > hpriv->em_buf_sz) 360 return -EINVAL; 361 362 ahci_rpm_get_port(ap); 363 spin_lock_irqsave(ap->lock, flags); 364 365 em_ctl = readl(mmio + HOST_EM_CTL); 366 if (em_ctl & EM_CTL_TM) { 367 spin_unlock_irqrestore(ap->lock, flags); 368 ahci_rpm_put_port(ap); 369 return -EBUSY; 370 } 371 372 for (i = 0; i < size; i += 4) { 373 msg = msg_buf[i] | msg_buf[i + 1] << 8 | 374 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24; 375 writel(msg, em_mmio + i); 376 } 377 378 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 379 380 spin_unlock_irqrestore(ap->lock, flags); 381 ahci_rpm_put_port(ap); 382 383 return size; 384 } 385 386 static ssize_t ahci_show_em_supported(struct device *dev, 387 struct device_attribute *attr, char *buf) 388 { 389 struct Scsi_Host *shost = class_to_shost(dev); 390 struct ata_port *ap = ata_shost_to_port(shost); 391 struct ahci_host_priv *hpriv = ap->host->private_data; 392 void __iomem *mmio = hpriv->mmio; 393 u32 em_ctl; 394 395 ahci_rpm_get_port(ap); 396 em_ctl = readl(mmio + HOST_EM_CTL); 397 ahci_rpm_put_port(ap); 398 399 return sprintf(buf, "%s%s%s%s\n", 400 em_ctl & EM_CTL_LED ? "led " : "", 401 em_ctl & EM_CTL_SAFTE ? "saf-te " : "", 402 em_ctl & EM_CTL_SES ? "ses-2 " : "", 403 em_ctl & EM_CTL_SGPIO ? "sgpio " : ""); 404 } 405 406 /** 407 * ahci_save_initial_config - Save and fixup initial config values 408 * @dev: target AHCI device 409 * @hpriv: host private area to store config values 410 * 411 * Some registers containing configuration info might be setup by 412 * BIOS and might be cleared on reset. This function saves the 413 * initial values of those registers into @hpriv such that they 414 * can be restored after controller reset. 415 * 416 * If inconsistent, config values are fixed up by this function. 417 * 418 * If it is not set already this function sets hpriv->start_engine to 419 * ahci_start_engine. 420 * 421 * LOCKING: 422 * None. 423 */ 424 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv) 425 { 426 void __iomem *mmio = hpriv->mmio; 427 u32 cap, cap2, vers, port_map; 428 int i; 429 430 /* make sure AHCI mode is enabled before accessing CAP */ 431 ahci_enable_ahci(mmio); 432 433 /* Values prefixed with saved_ are written back to host after 434 * reset. Values without are used for driver operation. 435 */ 436 hpriv->saved_cap = cap = readl(mmio + HOST_CAP); 437 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); 438 439 /* CAP2 register is only defined for AHCI 1.2 and later */ 440 vers = readl(mmio + HOST_VERSION); 441 if ((vers >> 16) > 1 || 442 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200)) 443 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2); 444 else 445 hpriv->saved_cap2 = cap2 = 0; 446 447 /* some chips have errata preventing 64bit use */ 448 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { 449 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n"); 450 cap &= ~HOST_CAP_64; 451 } 452 453 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { 454 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n"); 455 cap &= ~HOST_CAP_NCQ; 456 } 457 458 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) { 459 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n"); 460 cap |= HOST_CAP_NCQ; 461 } 462 463 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { 464 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n"); 465 cap &= ~HOST_CAP_PMP; 466 } 467 468 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) { 469 dev_info(dev, 470 "controller can't do SNTF, turning off CAP_SNTF\n"); 471 cap &= ~HOST_CAP_SNTF; 472 } 473 474 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) { 475 dev_info(dev, 476 "controller can't do DEVSLP, turning off\n"); 477 cap2 &= ~HOST_CAP2_SDS; 478 cap2 &= ~HOST_CAP2_SADM; 479 } 480 481 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) { 482 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n"); 483 cap |= HOST_CAP_FBS; 484 } 485 486 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) { 487 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n"); 488 cap &= ~HOST_CAP_FBS; 489 } 490 491 if (!(cap & HOST_CAP_ALPM) && (hpriv->flags & AHCI_HFLAG_YES_ALPM)) { 492 dev_info(dev, "controller can do ALPM, turning on CAP_ALPM\n"); 493 cap |= HOST_CAP_ALPM; 494 } 495 496 if ((cap & HOST_CAP_SXS) && (hpriv->flags & AHCI_HFLAG_NO_SXS)) { 497 dev_info(dev, "controller does not support SXS, disabling CAP_SXS\n"); 498 cap &= ~HOST_CAP_SXS; 499 } 500 501 if (hpriv->force_port_map && port_map != hpriv->force_port_map) { 502 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n", 503 port_map, hpriv->force_port_map); 504 port_map = hpriv->force_port_map; 505 hpriv->saved_port_map = port_map; 506 } 507 508 if (hpriv->mask_port_map) { 509 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n", 510 port_map, 511 port_map & hpriv->mask_port_map); 512 port_map &= hpriv->mask_port_map; 513 } 514 515 /* cross check port_map and cap.n_ports */ 516 if (port_map) { 517 int map_ports = 0; 518 519 for (i = 0; i < AHCI_MAX_PORTS; i++) 520 if (port_map & (1 << i)) 521 map_ports++; 522 523 /* If PI has more ports than n_ports, whine, clear 524 * port_map and let it be generated from n_ports. 525 */ 526 if (map_ports > ahci_nr_ports(cap)) { 527 dev_warn(dev, 528 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n", 529 port_map, ahci_nr_ports(cap)); 530 port_map = 0; 531 } 532 } 533 534 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */ 535 if (!port_map && vers < 0x10300) { 536 port_map = (1 << ahci_nr_ports(cap)) - 1; 537 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map); 538 539 /* write the fixed up value to the PI register */ 540 hpriv->saved_port_map = port_map; 541 } 542 543 /* record values to use during operation */ 544 hpriv->cap = cap; 545 hpriv->cap2 = cap2; 546 hpriv->version = readl(mmio + HOST_VERSION); 547 hpriv->port_map = port_map; 548 549 if (!hpriv->start_engine) 550 hpriv->start_engine = ahci_start_engine; 551 552 if (!hpriv->stop_engine) 553 hpriv->stop_engine = ahci_stop_engine; 554 555 if (!hpriv->irq_handler) 556 hpriv->irq_handler = ahci_single_level_irq_intr; 557 } 558 EXPORT_SYMBOL_GPL(ahci_save_initial_config); 559 560 /** 561 * ahci_restore_initial_config - Restore initial config 562 * @host: target ATA host 563 * 564 * Restore initial config stored by ahci_save_initial_config(). 565 * 566 * LOCKING: 567 * None. 568 */ 569 static void ahci_restore_initial_config(struct ata_host *host) 570 { 571 struct ahci_host_priv *hpriv = host->private_data; 572 void __iomem *mmio = hpriv->mmio; 573 574 writel(hpriv->saved_cap, mmio + HOST_CAP); 575 if (hpriv->saved_cap2) 576 writel(hpriv->saved_cap2, mmio + HOST_CAP2); 577 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); 578 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ 579 } 580 581 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) 582 { 583 static const int offset[] = { 584 [SCR_STATUS] = PORT_SCR_STAT, 585 [SCR_CONTROL] = PORT_SCR_CTL, 586 [SCR_ERROR] = PORT_SCR_ERR, 587 [SCR_ACTIVE] = PORT_SCR_ACT, 588 [SCR_NOTIFICATION] = PORT_SCR_NTF, 589 }; 590 struct ahci_host_priv *hpriv = ap->host->private_data; 591 592 if (sc_reg < ARRAY_SIZE(offset) && 593 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) 594 return offset[sc_reg]; 595 return 0; 596 } 597 598 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) 599 { 600 void __iomem *port_mmio = ahci_port_base(link->ap); 601 int offset = ahci_scr_offset(link->ap, sc_reg); 602 603 if (offset) { 604 *val = readl(port_mmio + offset); 605 return 0; 606 } 607 return -EINVAL; 608 } 609 610 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) 611 { 612 void __iomem *port_mmio = ahci_port_base(link->ap); 613 int offset = ahci_scr_offset(link->ap, sc_reg); 614 615 if (offset) { 616 writel(val, port_mmio + offset); 617 return 0; 618 } 619 return -EINVAL; 620 } 621 622 void ahci_start_engine(struct ata_port *ap) 623 { 624 void __iomem *port_mmio = ahci_port_base(ap); 625 u32 tmp; 626 627 /* start DMA */ 628 tmp = readl(port_mmio + PORT_CMD); 629 tmp |= PORT_CMD_START; 630 writel(tmp, port_mmio + PORT_CMD); 631 readl(port_mmio + PORT_CMD); /* flush */ 632 } 633 EXPORT_SYMBOL_GPL(ahci_start_engine); 634 635 int ahci_stop_engine(struct ata_port *ap) 636 { 637 void __iomem *port_mmio = ahci_port_base(ap); 638 struct ahci_host_priv *hpriv = ap->host->private_data; 639 u32 tmp; 640 641 /* 642 * On some controllers, stopping a port's DMA engine while the port 643 * is in ALPM state (partial or slumber) results in failures on 644 * subsequent DMA engine starts. For those controllers, put the 645 * port back in active state before stopping its DMA engine. 646 */ 647 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) && 648 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) && 649 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) { 650 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n"); 651 return -EIO; 652 } 653 654 tmp = readl(port_mmio + PORT_CMD); 655 656 /* check if the HBA is idle */ 657 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) 658 return 0; 659 660 /* 661 * Don't try to issue commands but return with ENODEV if the 662 * AHCI controller not available anymore (e.g. due to PCIe hot 663 * unplugging). Otherwise a 500ms delay for each port is added. 664 */ 665 if (tmp == 0xffffffff) { 666 dev_err(ap->host->dev, "AHCI controller unavailable!\n"); 667 return -ENODEV; 668 } 669 670 /* setting HBA to idle */ 671 tmp &= ~PORT_CMD_START; 672 writel(tmp, port_mmio + PORT_CMD); 673 674 /* wait for engine to stop. This could be as long as 500 msec */ 675 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 676 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); 677 if (tmp & PORT_CMD_LIST_ON) 678 return -EIO; 679 680 return 0; 681 } 682 EXPORT_SYMBOL_GPL(ahci_stop_engine); 683 684 void ahci_start_fis_rx(struct ata_port *ap) 685 { 686 void __iomem *port_mmio = ahci_port_base(ap); 687 struct ahci_host_priv *hpriv = ap->host->private_data; 688 struct ahci_port_priv *pp = ap->private_data; 689 u32 tmp; 690 691 /* set FIS registers */ 692 if (hpriv->cap & HOST_CAP_64) 693 writel((pp->cmd_slot_dma >> 16) >> 16, 694 port_mmio + PORT_LST_ADDR_HI); 695 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); 696 697 if (hpriv->cap & HOST_CAP_64) 698 writel((pp->rx_fis_dma >> 16) >> 16, 699 port_mmio + PORT_FIS_ADDR_HI); 700 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); 701 702 /* enable FIS reception */ 703 tmp = readl(port_mmio + PORT_CMD); 704 tmp |= PORT_CMD_FIS_RX; 705 writel(tmp, port_mmio + PORT_CMD); 706 707 /* flush */ 708 readl(port_mmio + PORT_CMD); 709 } 710 EXPORT_SYMBOL_GPL(ahci_start_fis_rx); 711 712 static int ahci_stop_fis_rx(struct ata_port *ap) 713 { 714 void __iomem *port_mmio = ahci_port_base(ap); 715 u32 tmp; 716 717 /* disable FIS reception */ 718 tmp = readl(port_mmio + PORT_CMD); 719 tmp &= ~PORT_CMD_FIS_RX; 720 writel(tmp, port_mmio + PORT_CMD); 721 722 /* wait for completion, spec says 500ms, give it 1000 */ 723 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON, 724 PORT_CMD_FIS_ON, 10, 1000); 725 if (tmp & PORT_CMD_FIS_ON) 726 return -EBUSY; 727 728 return 0; 729 } 730 731 static void ahci_power_up(struct ata_port *ap) 732 { 733 struct ahci_host_priv *hpriv = ap->host->private_data; 734 void __iomem *port_mmio = ahci_port_base(ap); 735 u32 cmd; 736 737 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 738 739 /* spin up device */ 740 if (hpriv->cap & HOST_CAP_SSS) { 741 cmd |= PORT_CMD_SPIN_UP; 742 writel(cmd, port_mmio + PORT_CMD); 743 } 744 745 /* wake up link */ 746 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); 747 } 748 749 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 750 unsigned int hints) 751 { 752 struct ata_port *ap = link->ap; 753 struct ahci_host_priv *hpriv = ap->host->private_data; 754 struct ahci_port_priv *pp = ap->private_data; 755 void __iomem *port_mmio = ahci_port_base(ap); 756 757 if (policy != ATA_LPM_MAX_POWER) { 758 /* wakeup flag only applies to the max power policy */ 759 hints &= ~ATA_LPM_WAKE_ONLY; 760 761 /* 762 * Disable interrupts on Phy Ready. This keeps us from 763 * getting woken up due to spurious phy ready 764 * interrupts. 765 */ 766 pp->intr_mask &= ~PORT_IRQ_PHYRDY; 767 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 768 769 sata_link_scr_lpm(link, policy, false); 770 } 771 772 if (hpriv->cap & HOST_CAP_ALPM) { 773 u32 cmd = readl(port_mmio + PORT_CMD); 774 775 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) { 776 if (!(hints & ATA_LPM_WAKE_ONLY)) 777 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE); 778 cmd |= PORT_CMD_ICC_ACTIVE; 779 780 writel(cmd, port_mmio + PORT_CMD); 781 readl(port_mmio + PORT_CMD); 782 783 /* wait 10ms to be sure we've come out of LPM state */ 784 ata_msleep(ap, 10); 785 786 if (hints & ATA_LPM_WAKE_ONLY) 787 return 0; 788 } else { 789 cmd |= PORT_CMD_ALPE; 790 if (policy == ATA_LPM_MIN_POWER) 791 cmd |= PORT_CMD_ASP; 792 else if (policy == ATA_LPM_MIN_POWER_WITH_PARTIAL) 793 cmd &= ~PORT_CMD_ASP; 794 795 /* write out new cmd value */ 796 writel(cmd, port_mmio + PORT_CMD); 797 } 798 } 799 800 /* set aggressive device sleep */ 801 if ((hpriv->cap2 & HOST_CAP2_SDS) && 802 (hpriv->cap2 & HOST_CAP2_SADM) && 803 (link->device->flags & ATA_DFLAG_DEVSLP)) { 804 if (policy == ATA_LPM_MIN_POWER || 805 policy == ATA_LPM_MIN_POWER_WITH_PARTIAL) 806 ahci_set_aggressive_devslp(ap, true); 807 else 808 ahci_set_aggressive_devslp(ap, false); 809 } 810 811 if (policy == ATA_LPM_MAX_POWER) { 812 sata_link_scr_lpm(link, policy, false); 813 814 /* turn PHYRDY IRQ back on */ 815 pp->intr_mask |= PORT_IRQ_PHYRDY; 816 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 817 } 818 819 return 0; 820 } 821 822 #ifdef CONFIG_PM 823 static void ahci_power_down(struct ata_port *ap) 824 { 825 struct ahci_host_priv *hpriv = ap->host->private_data; 826 void __iomem *port_mmio = ahci_port_base(ap); 827 u32 cmd, scontrol; 828 829 if (!(hpriv->cap & HOST_CAP_SSS)) 830 return; 831 832 /* put device into listen mode, first set PxSCTL.DET to 0 */ 833 scontrol = readl(port_mmio + PORT_SCR_CTL); 834 scontrol &= ~0xf; 835 writel(scontrol, port_mmio + PORT_SCR_CTL); 836 837 /* then set PxCMD.SUD to 0 */ 838 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 839 cmd &= ~PORT_CMD_SPIN_UP; 840 writel(cmd, port_mmio + PORT_CMD); 841 } 842 #endif 843 844 static void ahci_start_port(struct ata_port *ap) 845 { 846 struct ahci_host_priv *hpriv = ap->host->private_data; 847 struct ahci_port_priv *pp = ap->private_data; 848 struct ata_link *link; 849 struct ahci_em_priv *emp; 850 ssize_t rc; 851 int i; 852 853 /* enable FIS reception */ 854 ahci_start_fis_rx(ap); 855 856 /* enable DMA */ 857 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE)) 858 hpriv->start_engine(ap); 859 860 /* turn on LEDs */ 861 if (ap->flags & ATA_FLAG_EM) { 862 ata_for_each_link(link, ap, EDGE) { 863 emp = &pp->em_priv[link->pmp]; 864 865 /* EM Transmit bit maybe busy during init */ 866 for (i = 0; i < EM_MAX_RETRY; i++) { 867 rc = ap->ops->transmit_led_message(ap, 868 emp->led_state, 869 4); 870 /* 871 * If busy, give a breather but do not 872 * release EH ownership by using msleep() 873 * instead of ata_msleep(). EM Transmit 874 * bit is busy for the whole host and 875 * releasing ownership will cause other 876 * ports to fail the same way. 877 */ 878 if (rc == -EBUSY) 879 msleep(1); 880 else 881 break; 882 } 883 } 884 } 885 886 if (ap->flags & ATA_FLAG_SW_ACTIVITY) 887 ata_for_each_link(link, ap, EDGE) 888 ahci_init_sw_activity(link); 889 890 } 891 892 static int ahci_deinit_port(struct ata_port *ap, const char **emsg) 893 { 894 int rc; 895 struct ahci_host_priv *hpriv = ap->host->private_data; 896 897 /* disable DMA */ 898 rc = hpriv->stop_engine(ap); 899 if (rc) { 900 *emsg = "failed to stop engine"; 901 return rc; 902 } 903 904 /* disable FIS reception */ 905 rc = ahci_stop_fis_rx(ap); 906 if (rc) { 907 *emsg = "failed stop FIS RX"; 908 return rc; 909 } 910 911 return 0; 912 } 913 914 int ahci_reset_controller(struct ata_host *host) 915 { 916 struct ahci_host_priv *hpriv = host->private_data; 917 void __iomem *mmio = hpriv->mmio; 918 u32 tmp; 919 920 /* we must be in AHCI mode, before using anything 921 * AHCI-specific, such as HOST_RESET. 922 */ 923 ahci_enable_ahci(mmio); 924 925 /* global controller reset */ 926 if (!ahci_skip_host_reset) { 927 tmp = readl(mmio + HOST_CTL); 928 if ((tmp & HOST_RESET) == 0) { 929 writel(tmp | HOST_RESET, mmio + HOST_CTL); 930 readl(mmio + HOST_CTL); /* flush */ 931 } 932 933 /* 934 * to perform host reset, OS should set HOST_RESET 935 * and poll until this bit is read to be "0". 936 * reset must complete within 1 second, or 937 * the hardware should be considered fried. 938 */ 939 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET, 940 HOST_RESET, 10, 1000); 941 942 if (tmp & HOST_RESET) { 943 dev_err(host->dev, "controller reset failed (0x%x)\n", 944 tmp); 945 return -EIO; 946 } 947 948 /* turn on AHCI mode */ 949 ahci_enable_ahci(mmio); 950 951 /* Some registers might be cleared on reset. Restore 952 * initial values. 953 */ 954 if (!(hpriv->flags & AHCI_HFLAG_NO_WRITE_TO_RO)) 955 ahci_restore_initial_config(host); 956 } else 957 dev_info(host->dev, "skipping global host reset\n"); 958 959 return 0; 960 } 961 EXPORT_SYMBOL_GPL(ahci_reset_controller); 962 963 static void ahci_sw_activity(struct ata_link *link) 964 { 965 struct ata_port *ap = link->ap; 966 struct ahci_port_priv *pp = ap->private_data; 967 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 968 969 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY)) 970 return; 971 972 emp->activity++; 973 if (!timer_pending(&emp->timer)) 974 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10)); 975 } 976 977 static void ahci_sw_activity_blink(struct timer_list *t) 978 { 979 struct ahci_em_priv *emp = from_timer(emp, t, timer); 980 struct ata_link *link = emp->link; 981 struct ata_port *ap = link->ap; 982 983 unsigned long led_message = emp->led_state; 984 u32 activity_led_state; 985 unsigned long flags; 986 987 led_message &= EM_MSG_LED_VALUE; 988 led_message |= ap->port_no | (link->pmp << 8); 989 990 /* check to see if we've had activity. If so, 991 * toggle state of LED and reset timer. If not, 992 * turn LED to desired idle state. 993 */ 994 spin_lock_irqsave(ap->lock, flags); 995 if (emp->saved_activity != emp->activity) { 996 emp->saved_activity = emp->activity; 997 /* get the current LED state */ 998 activity_led_state = led_message & EM_MSG_LED_VALUE_ON; 999 1000 if (activity_led_state) 1001 activity_led_state = 0; 1002 else 1003 activity_led_state = 1; 1004 1005 /* clear old state */ 1006 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 1007 1008 /* toggle state */ 1009 led_message |= (activity_led_state << 16); 1010 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100)); 1011 } else { 1012 /* switch to idle */ 1013 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 1014 if (emp->blink_policy == BLINK_OFF) 1015 led_message |= (1 << 16); 1016 } 1017 spin_unlock_irqrestore(ap->lock, flags); 1018 ap->ops->transmit_led_message(ap, led_message, 4); 1019 } 1020 1021 static void ahci_init_sw_activity(struct ata_link *link) 1022 { 1023 struct ata_port *ap = link->ap; 1024 struct ahci_port_priv *pp = ap->private_data; 1025 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1026 1027 /* init activity stats, setup timer */ 1028 emp->saved_activity = emp->activity = 0; 1029 emp->link = link; 1030 timer_setup(&emp->timer, ahci_sw_activity_blink, 0); 1031 1032 /* check our blink policy and set flag for link if it's enabled */ 1033 if (emp->blink_policy) 1034 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1035 } 1036 1037 int ahci_reset_em(struct ata_host *host) 1038 { 1039 struct ahci_host_priv *hpriv = host->private_data; 1040 void __iomem *mmio = hpriv->mmio; 1041 u32 em_ctl; 1042 1043 em_ctl = readl(mmio + HOST_EM_CTL); 1044 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST)) 1045 return -EINVAL; 1046 1047 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL); 1048 return 0; 1049 } 1050 EXPORT_SYMBOL_GPL(ahci_reset_em); 1051 1052 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 1053 ssize_t size) 1054 { 1055 struct ahci_host_priv *hpriv = ap->host->private_data; 1056 struct ahci_port_priv *pp = ap->private_data; 1057 void __iomem *mmio = hpriv->mmio; 1058 u32 em_ctl; 1059 u32 message[] = {0, 0}; 1060 unsigned long flags; 1061 int pmp; 1062 struct ahci_em_priv *emp; 1063 1064 /* get the slot number from the message */ 1065 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1066 if (pmp < EM_MAX_SLOTS) 1067 emp = &pp->em_priv[pmp]; 1068 else 1069 return -EINVAL; 1070 1071 ahci_rpm_get_port(ap); 1072 spin_lock_irqsave(ap->lock, flags); 1073 1074 /* 1075 * if we are still busy transmitting a previous message, 1076 * do not allow 1077 */ 1078 em_ctl = readl(mmio + HOST_EM_CTL); 1079 if (em_ctl & EM_CTL_TM) { 1080 spin_unlock_irqrestore(ap->lock, flags); 1081 ahci_rpm_put_port(ap); 1082 return -EBUSY; 1083 } 1084 1085 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) { 1086 /* 1087 * create message header - this is all zero except for 1088 * the message size, which is 4 bytes. 1089 */ 1090 message[0] |= (4 << 8); 1091 1092 /* ignore 0:4 of byte zero, fill in port info yourself */ 1093 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no); 1094 1095 /* write message to EM_LOC */ 1096 writel(message[0], mmio + hpriv->em_loc); 1097 writel(message[1], mmio + hpriv->em_loc+4); 1098 1099 /* 1100 * tell hardware to transmit the message 1101 */ 1102 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 1103 } 1104 1105 /* save off new led state for port/slot */ 1106 emp->led_state = state; 1107 1108 spin_unlock_irqrestore(ap->lock, flags); 1109 ahci_rpm_put_port(ap); 1110 1111 return size; 1112 } 1113 1114 static ssize_t ahci_led_show(struct ata_port *ap, char *buf) 1115 { 1116 struct ahci_port_priv *pp = ap->private_data; 1117 struct ata_link *link; 1118 struct ahci_em_priv *emp; 1119 int rc = 0; 1120 1121 ata_for_each_link(link, ap, EDGE) { 1122 emp = &pp->em_priv[link->pmp]; 1123 rc += sprintf(buf, "%lx\n", emp->led_state); 1124 } 1125 return rc; 1126 } 1127 1128 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 1129 size_t size) 1130 { 1131 unsigned int state; 1132 int pmp; 1133 struct ahci_port_priv *pp = ap->private_data; 1134 struct ahci_em_priv *emp; 1135 1136 if (kstrtouint(buf, 0, &state) < 0) 1137 return -EINVAL; 1138 1139 /* get the slot number from the message */ 1140 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1141 if (pmp < EM_MAX_SLOTS) { 1142 pmp = array_index_nospec(pmp, EM_MAX_SLOTS); 1143 emp = &pp->em_priv[pmp]; 1144 } else { 1145 return -EINVAL; 1146 } 1147 1148 /* mask off the activity bits if we are in sw_activity 1149 * mode, user should turn off sw_activity before setting 1150 * activity led through em_message 1151 */ 1152 if (emp->blink_policy) 1153 state &= ~EM_MSG_LED_VALUE_ACTIVITY; 1154 1155 return ap->ops->transmit_led_message(ap, state, size); 1156 } 1157 1158 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val) 1159 { 1160 struct ata_link *link = dev->link; 1161 struct ata_port *ap = link->ap; 1162 struct ahci_port_priv *pp = ap->private_data; 1163 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1164 u32 port_led_state = emp->led_state; 1165 1166 /* save the desired Activity LED behavior */ 1167 if (val == OFF) { 1168 /* clear LFLAG */ 1169 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY); 1170 1171 /* set the LED to OFF */ 1172 port_led_state &= EM_MSG_LED_VALUE_OFF; 1173 port_led_state |= (ap->port_no | (link->pmp << 8)); 1174 ap->ops->transmit_led_message(ap, port_led_state, 4); 1175 } else { 1176 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1177 if (val == BLINK_OFF) { 1178 /* set LED to ON for idle */ 1179 port_led_state &= EM_MSG_LED_VALUE_OFF; 1180 port_led_state |= (ap->port_no | (link->pmp << 8)); 1181 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */ 1182 ap->ops->transmit_led_message(ap, port_led_state, 4); 1183 } 1184 } 1185 emp->blink_policy = val; 1186 return 0; 1187 } 1188 1189 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf) 1190 { 1191 struct ata_link *link = dev->link; 1192 struct ata_port *ap = link->ap; 1193 struct ahci_port_priv *pp = ap->private_data; 1194 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1195 1196 /* display the saved value of activity behavior for this 1197 * disk. 1198 */ 1199 return sprintf(buf, "%d\n", emp->blink_policy); 1200 } 1201 1202 static void ahci_port_init(struct device *dev, struct ata_port *ap, 1203 int port_no, void __iomem *mmio, 1204 void __iomem *port_mmio) 1205 { 1206 struct ahci_host_priv *hpriv = ap->host->private_data; 1207 const char *emsg = NULL; 1208 int rc; 1209 u32 tmp; 1210 1211 /* make sure port is not active */ 1212 rc = ahci_deinit_port(ap, &emsg); 1213 if (rc) 1214 dev_warn(dev, "%s (%d)\n", emsg, rc); 1215 1216 /* clear SError */ 1217 tmp = readl(port_mmio + PORT_SCR_ERR); 1218 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); 1219 writel(tmp, port_mmio + PORT_SCR_ERR); 1220 1221 /* clear port IRQ */ 1222 tmp = readl(port_mmio + PORT_IRQ_STAT); 1223 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 1224 if (tmp) 1225 writel(tmp, port_mmio + PORT_IRQ_STAT); 1226 1227 writel(1 << port_no, mmio + HOST_IRQ_STAT); 1228 1229 /* mark esata ports */ 1230 tmp = readl(port_mmio + PORT_CMD); 1231 if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS)) 1232 ap->pflags |= ATA_PFLAG_EXTERNAL; 1233 } 1234 1235 void ahci_init_controller(struct ata_host *host) 1236 { 1237 struct ahci_host_priv *hpriv = host->private_data; 1238 void __iomem *mmio = hpriv->mmio; 1239 int i; 1240 void __iomem *port_mmio; 1241 u32 tmp; 1242 1243 for (i = 0; i < host->n_ports; i++) { 1244 struct ata_port *ap = host->ports[i]; 1245 1246 port_mmio = ahci_port_base(ap); 1247 if (ata_port_is_dummy(ap)) 1248 continue; 1249 1250 ahci_port_init(host->dev, ap, i, mmio, port_mmio); 1251 } 1252 1253 tmp = readl(mmio + HOST_CTL); 1254 VPRINTK("HOST_CTL 0x%x\n", tmp); 1255 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); 1256 tmp = readl(mmio + HOST_CTL); 1257 VPRINTK("HOST_CTL 0x%x\n", tmp); 1258 } 1259 EXPORT_SYMBOL_GPL(ahci_init_controller); 1260 1261 static void ahci_dev_config(struct ata_device *dev) 1262 { 1263 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data; 1264 1265 if (hpriv->flags & AHCI_HFLAG_SECT255) { 1266 dev->max_sectors = 255; 1267 ata_dev_info(dev, 1268 "SB600 AHCI: limiting to 255 sectors per cmd\n"); 1269 } 1270 } 1271 1272 unsigned int ahci_dev_classify(struct ata_port *ap) 1273 { 1274 void __iomem *port_mmio = ahci_port_base(ap); 1275 struct ata_taskfile tf; 1276 u32 tmp; 1277 1278 tmp = readl(port_mmio + PORT_SIG); 1279 tf.lbah = (tmp >> 24) & 0xff; 1280 tf.lbam = (tmp >> 16) & 0xff; 1281 tf.lbal = (tmp >> 8) & 0xff; 1282 tf.nsect = (tmp) & 0xff; 1283 1284 return ata_dev_classify(&tf); 1285 } 1286 EXPORT_SYMBOL_GPL(ahci_dev_classify); 1287 1288 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 1289 u32 opts) 1290 { 1291 dma_addr_t cmd_tbl_dma; 1292 1293 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; 1294 1295 pp->cmd_slot[tag].opts = cpu_to_le32(opts); 1296 pp->cmd_slot[tag].status = 0; 1297 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); 1298 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); 1299 } 1300 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot); 1301 1302 int ahci_kick_engine(struct ata_port *ap) 1303 { 1304 void __iomem *port_mmio = ahci_port_base(ap); 1305 struct ahci_host_priv *hpriv = ap->host->private_data; 1306 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1307 u32 tmp; 1308 int busy, rc; 1309 1310 /* stop engine */ 1311 rc = hpriv->stop_engine(ap); 1312 if (rc) 1313 goto out_restart; 1314 1315 /* need to do CLO? 1316 * always do CLO if PMP is attached (AHCI-1.3 9.2) 1317 */ 1318 busy = status & (ATA_BUSY | ATA_DRQ); 1319 if (!busy && !sata_pmp_attached(ap)) { 1320 rc = 0; 1321 goto out_restart; 1322 } 1323 1324 if (!(hpriv->cap & HOST_CAP_CLO)) { 1325 rc = -EOPNOTSUPP; 1326 goto out_restart; 1327 } 1328 1329 /* perform CLO */ 1330 tmp = readl(port_mmio + PORT_CMD); 1331 tmp |= PORT_CMD_CLO; 1332 writel(tmp, port_mmio + PORT_CMD); 1333 1334 rc = 0; 1335 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 1336 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); 1337 if (tmp & PORT_CMD_CLO) 1338 rc = -EIO; 1339 1340 /* restart engine */ 1341 out_restart: 1342 hpriv->start_engine(ap); 1343 return rc; 1344 } 1345 EXPORT_SYMBOL_GPL(ahci_kick_engine); 1346 1347 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, 1348 struct ata_taskfile *tf, int is_cmd, u16 flags, 1349 unsigned long timeout_msec) 1350 { 1351 const u32 cmd_fis_len = 5; /* five dwords */ 1352 struct ahci_port_priv *pp = ap->private_data; 1353 void __iomem *port_mmio = ahci_port_base(ap); 1354 u8 *fis = pp->cmd_tbl; 1355 u32 tmp; 1356 1357 /* prep the command */ 1358 ata_tf_to_fis(tf, pmp, is_cmd, fis); 1359 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); 1360 1361 /* set port value for softreset of Port Multiplier */ 1362 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) { 1363 tmp = readl(port_mmio + PORT_FBS); 1364 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); 1365 tmp |= pmp << PORT_FBS_DEV_OFFSET; 1366 writel(tmp, port_mmio + PORT_FBS); 1367 pp->fbs_last_dev = pmp; 1368 } 1369 1370 /* issue & wait */ 1371 writel(1, port_mmio + PORT_CMD_ISSUE); 1372 1373 if (timeout_msec) { 1374 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE, 1375 0x1, 0x1, 1, timeout_msec); 1376 if (tmp & 0x1) { 1377 ahci_kick_engine(ap); 1378 return -EBUSY; 1379 } 1380 } else 1381 readl(port_mmio + PORT_CMD_ISSUE); /* flush */ 1382 1383 return 0; 1384 } 1385 1386 int ahci_do_softreset(struct ata_link *link, unsigned int *class, 1387 int pmp, unsigned long deadline, 1388 int (*check_ready)(struct ata_link *link)) 1389 { 1390 struct ata_port *ap = link->ap; 1391 struct ahci_host_priv *hpriv = ap->host->private_data; 1392 struct ahci_port_priv *pp = ap->private_data; 1393 const char *reason = NULL; 1394 unsigned long now, msecs; 1395 struct ata_taskfile tf; 1396 bool fbs_disabled = false; 1397 int rc; 1398 1399 DPRINTK("ENTER\n"); 1400 1401 /* prepare for SRST (AHCI-1.1 10.4.1) */ 1402 rc = ahci_kick_engine(ap); 1403 if (rc && rc != -EOPNOTSUPP) 1404 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc); 1405 1406 /* 1407 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall 1408 * clear PxFBS.EN to '0' prior to issuing software reset to devices 1409 * that is attached to port multiplier. 1410 */ 1411 if (!ata_is_host_link(link) && pp->fbs_enabled) { 1412 ahci_disable_fbs(ap); 1413 fbs_disabled = true; 1414 } 1415 1416 ata_tf_init(link->device, &tf); 1417 1418 /* issue the first H2D Register FIS */ 1419 msecs = 0; 1420 now = jiffies; 1421 if (time_after(deadline, now)) 1422 msecs = jiffies_to_msecs(deadline - now); 1423 1424 tf.ctl |= ATA_SRST; 1425 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, 1426 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { 1427 rc = -EIO; 1428 reason = "1st FIS failed"; 1429 goto fail; 1430 } 1431 1432 /* spec says at least 5us, but be generous and sleep for 1ms */ 1433 ata_msleep(ap, 1); 1434 1435 /* issue the second H2D Register FIS */ 1436 tf.ctl &= ~ATA_SRST; 1437 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); 1438 1439 /* wait for link to become ready */ 1440 rc = ata_wait_after_reset(link, deadline, check_ready); 1441 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) { 1442 /* 1443 * Workaround for cases where link online status can't 1444 * be trusted. Treat device readiness timeout as link 1445 * offline. 1446 */ 1447 ata_link_info(link, "device not ready, treating as offline\n"); 1448 *class = ATA_DEV_NONE; 1449 } else if (rc) { 1450 /* link occupied, -ENODEV too is an error */ 1451 reason = "device not ready"; 1452 goto fail; 1453 } else 1454 *class = ahci_dev_classify(ap); 1455 1456 /* re-enable FBS if disabled before */ 1457 if (fbs_disabled) 1458 ahci_enable_fbs(ap); 1459 1460 DPRINTK("EXIT, class=%u\n", *class); 1461 return 0; 1462 1463 fail: 1464 ata_link_err(link, "softreset failed (%s)\n", reason); 1465 return rc; 1466 } 1467 1468 int ahci_check_ready(struct ata_link *link) 1469 { 1470 void __iomem *port_mmio = ahci_port_base(link->ap); 1471 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1472 1473 return ata_check_ready(status); 1474 } 1475 EXPORT_SYMBOL_GPL(ahci_check_ready); 1476 1477 static int ahci_softreset(struct ata_link *link, unsigned int *class, 1478 unsigned long deadline) 1479 { 1480 int pmp = sata_srst_pmp(link); 1481 1482 DPRINTK("ENTER\n"); 1483 1484 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready); 1485 } 1486 EXPORT_SYMBOL_GPL(ahci_do_softreset); 1487 1488 static int ahci_bad_pmp_check_ready(struct ata_link *link) 1489 { 1490 void __iomem *port_mmio = ahci_port_base(link->ap); 1491 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1492 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT); 1493 1494 /* 1495 * There is no need to check TFDATA if BAD PMP is found due to HW bug, 1496 * which can save timeout delay. 1497 */ 1498 if (irq_status & PORT_IRQ_BAD_PMP) 1499 return -EIO; 1500 1501 return ata_check_ready(status); 1502 } 1503 1504 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class, 1505 unsigned long deadline) 1506 { 1507 struct ata_port *ap = link->ap; 1508 void __iomem *port_mmio = ahci_port_base(ap); 1509 int pmp = sata_srst_pmp(link); 1510 int rc; 1511 u32 irq_sts; 1512 1513 DPRINTK("ENTER\n"); 1514 1515 rc = ahci_do_softreset(link, class, pmp, deadline, 1516 ahci_bad_pmp_check_ready); 1517 1518 /* 1519 * Soft reset fails with IPMS set when PMP is enabled but 1520 * SATA HDD/ODD is connected to SATA port, do soft reset 1521 * again to port 0. 1522 */ 1523 if (rc == -EIO) { 1524 irq_sts = readl(port_mmio + PORT_IRQ_STAT); 1525 if (irq_sts & PORT_IRQ_BAD_PMP) { 1526 ata_link_warn(link, 1527 "applying PMP SRST workaround " 1528 "and retrying\n"); 1529 rc = ahci_do_softreset(link, class, 0, deadline, 1530 ahci_check_ready); 1531 } 1532 } 1533 1534 return rc; 1535 } 1536 1537 int ahci_do_hardreset(struct ata_link *link, unsigned int *class, 1538 unsigned long deadline, bool *online) 1539 { 1540 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 1541 struct ata_port *ap = link->ap; 1542 struct ahci_port_priv *pp = ap->private_data; 1543 struct ahci_host_priv *hpriv = ap->host->private_data; 1544 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 1545 struct ata_taskfile tf; 1546 int rc; 1547 1548 DPRINTK("ENTER\n"); 1549 1550 hpriv->stop_engine(ap); 1551 1552 /* clear D2H reception area to properly wait for D2H FIS */ 1553 ata_tf_init(link->device, &tf); 1554 tf.command = ATA_BUSY; 1555 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 1556 1557 rc = sata_link_hardreset(link, timing, deadline, online, 1558 ahci_check_ready); 1559 1560 hpriv->start_engine(ap); 1561 1562 if (*online) 1563 *class = ahci_dev_classify(ap); 1564 1565 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 1566 return rc; 1567 } 1568 EXPORT_SYMBOL_GPL(ahci_do_hardreset); 1569 1570 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 1571 unsigned long deadline) 1572 { 1573 bool online; 1574 1575 return ahci_do_hardreset(link, class, deadline, &online); 1576 } 1577 1578 static void ahci_postreset(struct ata_link *link, unsigned int *class) 1579 { 1580 struct ata_port *ap = link->ap; 1581 void __iomem *port_mmio = ahci_port_base(ap); 1582 u32 new_tmp, tmp; 1583 1584 ata_std_postreset(link, class); 1585 1586 /* Make sure port's ATAPI bit is set appropriately */ 1587 new_tmp = tmp = readl(port_mmio + PORT_CMD); 1588 if (*class == ATA_DEV_ATAPI) 1589 new_tmp |= PORT_CMD_ATAPI; 1590 else 1591 new_tmp &= ~PORT_CMD_ATAPI; 1592 if (new_tmp != tmp) { 1593 writel(new_tmp, port_mmio + PORT_CMD); 1594 readl(port_mmio + PORT_CMD); /* flush */ 1595 } 1596 } 1597 1598 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) 1599 { 1600 struct scatterlist *sg; 1601 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; 1602 unsigned int si; 1603 1604 VPRINTK("ENTER\n"); 1605 1606 /* 1607 * Next, the S/G list. 1608 */ 1609 for_each_sg(qc->sg, sg, qc->n_elem, si) { 1610 dma_addr_t addr = sg_dma_address(sg); 1611 u32 sg_len = sg_dma_len(sg); 1612 1613 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); 1614 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); 1615 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); 1616 } 1617 1618 return si; 1619 } 1620 1621 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc) 1622 { 1623 struct ata_port *ap = qc->ap; 1624 struct ahci_port_priv *pp = ap->private_data; 1625 1626 if (!sata_pmp_attached(ap) || pp->fbs_enabled) 1627 return ata_std_qc_defer(qc); 1628 else 1629 return sata_pmp_qc_defer_cmd_switch(qc); 1630 } 1631 1632 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc) 1633 { 1634 struct ata_port *ap = qc->ap; 1635 struct ahci_port_priv *pp = ap->private_data; 1636 int is_atapi = ata_is_atapi(qc->tf.protocol); 1637 void *cmd_tbl; 1638 u32 opts; 1639 const u32 cmd_fis_len = 5; /* five dwords */ 1640 unsigned int n_elem; 1641 1642 /* 1643 * Fill in command table information. First, the header, 1644 * a SATA Register - Host to Device command FIS. 1645 */ 1646 cmd_tbl = pp->cmd_tbl + qc->hw_tag * AHCI_CMD_TBL_SZ; 1647 1648 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); 1649 if (is_atapi) { 1650 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); 1651 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); 1652 } 1653 1654 n_elem = 0; 1655 if (qc->flags & ATA_QCFLAG_DMAMAP) 1656 n_elem = ahci_fill_sg(qc, cmd_tbl); 1657 1658 /* 1659 * Fill in command slot information. 1660 */ 1661 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); 1662 if (qc->tf.flags & ATA_TFLAG_WRITE) 1663 opts |= AHCI_CMD_WRITE; 1664 if (is_atapi) 1665 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; 1666 1667 ahci_fill_cmd_slot(pp, qc->hw_tag, opts); 1668 1669 return AC_ERR_OK; 1670 } 1671 1672 static void ahci_fbs_dec_intr(struct ata_port *ap) 1673 { 1674 struct ahci_port_priv *pp = ap->private_data; 1675 void __iomem *port_mmio = ahci_port_base(ap); 1676 u32 fbs = readl(port_mmio + PORT_FBS); 1677 int retries = 3; 1678 1679 DPRINTK("ENTER\n"); 1680 BUG_ON(!pp->fbs_enabled); 1681 1682 /* time to wait for DEC is not specified by AHCI spec, 1683 * add a retry loop for safety. 1684 */ 1685 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS); 1686 fbs = readl(port_mmio + PORT_FBS); 1687 while ((fbs & PORT_FBS_DEC) && retries--) { 1688 udelay(1); 1689 fbs = readl(port_mmio + PORT_FBS); 1690 } 1691 1692 if (fbs & PORT_FBS_DEC) 1693 dev_err(ap->host->dev, "failed to clear device error\n"); 1694 } 1695 1696 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) 1697 { 1698 struct ahci_host_priv *hpriv = ap->host->private_data; 1699 struct ahci_port_priv *pp = ap->private_data; 1700 struct ata_eh_info *host_ehi = &ap->link.eh_info; 1701 struct ata_link *link = NULL; 1702 struct ata_queued_cmd *active_qc; 1703 struct ata_eh_info *active_ehi; 1704 bool fbs_need_dec = false; 1705 u32 serror; 1706 1707 /* determine active link with error */ 1708 if (pp->fbs_enabled) { 1709 void __iomem *port_mmio = ahci_port_base(ap); 1710 u32 fbs = readl(port_mmio + PORT_FBS); 1711 int pmp = fbs >> PORT_FBS_DWE_OFFSET; 1712 1713 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) { 1714 link = &ap->pmp_link[pmp]; 1715 fbs_need_dec = true; 1716 } 1717 1718 } else 1719 ata_for_each_link(link, ap, EDGE) 1720 if (ata_link_active(link)) 1721 break; 1722 1723 if (!link) 1724 link = &ap->link; 1725 1726 active_qc = ata_qc_from_tag(ap, link->active_tag); 1727 active_ehi = &link->eh_info; 1728 1729 /* record irq stat */ 1730 ata_ehi_clear_desc(host_ehi); 1731 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); 1732 1733 /* AHCI needs SError cleared; otherwise, it might lock up */ 1734 ahci_scr_read(&ap->link, SCR_ERROR, &serror); 1735 ahci_scr_write(&ap->link, SCR_ERROR, serror); 1736 host_ehi->serror |= serror; 1737 1738 /* some controllers set IRQ_IF_ERR on device errors, ignore it */ 1739 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) 1740 irq_stat &= ~PORT_IRQ_IF_ERR; 1741 1742 if (irq_stat & PORT_IRQ_TF_ERR) { 1743 /* If qc is active, charge it; otherwise, the active 1744 * link. There's no active qc on NCQ errors. It will 1745 * be determined by EH by reading log page 10h. 1746 */ 1747 if (active_qc) 1748 active_qc->err_mask |= AC_ERR_DEV; 1749 else 1750 active_ehi->err_mask |= AC_ERR_DEV; 1751 1752 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) 1753 host_ehi->serror &= ~SERR_INTERNAL; 1754 } 1755 1756 if (irq_stat & PORT_IRQ_UNK_FIS) { 1757 u32 *unk = pp->rx_fis + RX_FIS_UNK; 1758 1759 active_ehi->err_mask |= AC_ERR_HSM; 1760 active_ehi->action |= ATA_EH_RESET; 1761 ata_ehi_push_desc(active_ehi, 1762 "unknown FIS %08x %08x %08x %08x" , 1763 unk[0], unk[1], unk[2], unk[3]); 1764 } 1765 1766 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) { 1767 active_ehi->err_mask |= AC_ERR_HSM; 1768 active_ehi->action |= ATA_EH_RESET; 1769 ata_ehi_push_desc(active_ehi, "incorrect PMP"); 1770 } 1771 1772 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { 1773 host_ehi->err_mask |= AC_ERR_HOST_BUS; 1774 host_ehi->action |= ATA_EH_RESET; 1775 ata_ehi_push_desc(host_ehi, "host bus error"); 1776 } 1777 1778 if (irq_stat & PORT_IRQ_IF_ERR) { 1779 if (fbs_need_dec) 1780 active_ehi->err_mask |= AC_ERR_DEV; 1781 else { 1782 host_ehi->err_mask |= AC_ERR_ATA_BUS; 1783 host_ehi->action |= ATA_EH_RESET; 1784 } 1785 1786 ata_ehi_push_desc(host_ehi, "interface fatal error"); 1787 } 1788 1789 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { 1790 ata_ehi_hotplugged(host_ehi); 1791 ata_ehi_push_desc(host_ehi, "%s", 1792 irq_stat & PORT_IRQ_CONNECT ? 1793 "connection status changed" : "PHY RDY changed"); 1794 } 1795 1796 /* okay, let's hand over to EH */ 1797 1798 if (irq_stat & PORT_IRQ_FREEZE) 1799 ata_port_freeze(ap); 1800 else if (fbs_need_dec) { 1801 ata_link_abort(link); 1802 ahci_fbs_dec_intr(ap); 1803 } else 1804 ata_port_abort(ap); 1805 } 1806 1807 static void ahci_handle_port_interrupt(struct ata_port *ap, 1808 void __iomem *port_mmio, u32 status) 1809 { 1810 struct ata_eh_info *ehi = &ap->link.eh_info; 1811 struct ahci_port_priv *pp = ap->private_data; 1812 struct ahci_host_priv *hpriv = ap->host->private_data; 1813 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING); 1814 u32 qc_active = 0; 1815 int rc; 1816 1817 /* ignore BAD_PMP while resetting */ 1818 if (unlikely(resetting)) 1819 status &= ~PORT_IRQ_BAD_PMP; 1820 1821 if (sata_lpm_ignore_phy_events(&ap->link)) { 1822 status &= ~PORT_IRQ_PHYRDY; 1823 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG); 1824 } 1825 1826 if (unlikely(status & PORT_IRQ_ERROR)) { 1827 ahci_error_intr(ap, status); 1828 return; 1829 } 1830 1831 if (status & PORT_IRQ_SDB_FIS) { 1832 /* If SNotification is available, leave notification 1833 * handling to sata_async_notification(). If not, 1834 * emulate it by snooping SDB FIS RX area. 1835 * 1836 * Snooping FIS RX area is probably cheaper than 1837 * poking SNotification but some constrollers which 1838 * implement SNotification, ICH9 for example, don't 1839 * store AN SDB FIS into receive area. 1840 */ 1841 if (hpriv->cap & HOST_CAP_SNTF) 1842 sata_async_notification(ap); 1843 else { 1844 /* If the 'N' bit in word 0 of the FIS is set, 1845 * we just received asynchronous notification. 1846 * Tell libata about it. 1847 * 1848 * Lack of SNotification should not appear in 1849 * ahci 1.2, so the workaround is unnecessary 1850 * when FBS is enabled. 1851 */ 1852 if (pp->fbs_enabled) 1853 WARN_ON_ONCE(1); 1854 else { 1855 const __le32 *f = pp->rx_fis + RX_FIS_SDB; 1856 u32 f0 = le32_to_cpu(f[0]); 1857 if (f0 & (1 << 15)) 1858 sata_async_notification(ap); 1859 } 1860 } 1861 } 1862 1863 /* pp->active_link is not reliable once FBS is enabled, both 1864 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because 1865 * NCQ and non-NCQ commands may be in flight at the same time. 1866 */ 1867 if (pp->fbs_enabled) { 1868 if (ap->qc_active) { 1869 qc_active = readl(port_mmio + PORT_SCR_ACT); 1870 qc_active |= readl(port_mmio + PORT_CMD_ISSUE); 1871 } 1872 } else { 1873 /* pp->active_link is valid iff any command is in flight */ 1874 if (ap->qc_active && pp->active_link->sactive) 1875 qc_active = readl(port_mmio + PORT_SCR_ACT); 1876 else 1877 qc_active = readl(port_mmio + PORT_CMD_ISSUE); 1878 } 1879 1880 1881 rc = ata_qc_complete_multiple(ap, qc_active); 1882 1883 /* while resetting, invalid completions are expected */ 1884 if (unlikely(rc < 0 && !resetting)) { 1885 ehi->err_mask |= AC_ERR_HSM; 1886 ehi->action |= ATA_EH_RESET; 1887 ata_port_freeze(ap); 1888 } 1889 } 1890 1891 static void ahci_port_intr(struct ata_port *ap) 1892 { 1893 void __iomem *port_mmio = ahci_port_base(ap); 1894 u32 status; 1895 1896 status = readl(port_mmio + PORT_IRQ_STAT); 1897 writel(status, port_mmio + PORT_IRQ_STAT); 1898 1899 ahci_handle_port_interrupt(ap, port_mmio, status); 1900 } 1901 1902 static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance) 1903 { 1904 struct ata_port *ap = dev_instance; 1905 void __iomem *port_mmio = ahci_port_base(ap); 1906 u32 status; 1907 1908 VPRINTK("ENTER\n"); 1909 1910 status = readl(port_mmio + PORT_IRQ_STAT); 1911 writel(status, port_mmio + PORT_IRQ_STAT); 1912 1913 spin_lock(ap->lock); 1914 ahci_handle_port_interrupt(ap, port_mmio, status); 1915 spin_unlock(ap->lock); 1916 1917 VPRINTK("EXIT\n"); 1918 1919 return IRQ_HANDLED; 1920 } 1921 1922 u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked) 1923 { 1924 unsigned int i, handled = 0; 1925 1926 for (i = 0; i < host->n_ports; i++) { 1927 struct ata_port *ap; 1928 1929 if (!(irq_masked & (1 << i))) 1930 continue; 1931 1932 ap = host->ports[i]; 1933 if (ap) { 1934 ahci_port_intr(ap); 1935 VPRINTK("port %u\n", i); 1936 } else { 1937 VPRINTK("port %u (no irq)\n", i); 1938 if (ata_ratelimit()) 1939 dev_warn(host->dev, 1940 "interrupt on disabled port %u\n", i); 1941 } 1942 1943 handled = 1; 1944 } 1945 1946 return handled; 1947 } 1948 EXPORT_SYMBOL_GPL(ahci_handle_port_intr); 1949 1950 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance) 1951 { 1952 struct ata_host *host = dev_instance; 1953 struct ahci_host_priv *hpriv; 1954 unsigned int rc = 0; 1955 void __iomem *mmio; 1956 u32 irq_stat, irq_masked; 1957 1958 VPRINTK("ENTER\n"); 1959 1960 hpriv = host->private_data; 1961 mmio = hpriv->mmio; 1962 1963 /* sigh. 0xffffffff is a valid return from h/w */ 1964 irq_stat = readl(mmio + HOST_IRQ_STAT); 1965 if (!irq_stat) 1966 return IRQ_NONE; 1967 1968 irq_masked = irq_stat & hpriv->port_map; 1969 1970 spin_lock(&host->lock); 1971 1972 rc = ahci_handle_port_intr(host, irq_masked); 1973 1974 /* HOST_IRQ_STAT behaves as level triggered latch meaning that 1975 * it should be cleared after all the port events are cleared; 1976 * otherwise, it will raise a spurious interrupt after each 1977 * valid one. Please read section 10.6.2 of ahci 1.1 for more 1978 * information. 1979 * 1980 * Also, use the unmasked value to clear interrupt as spurious 1981 * pending event on a dummy port might cause screaming IRQ. 1982 */ 1983 writel(irq_stat, mmio + HOST_IRQ_STAT); 1984 1985 spin_unlock(&host->lock); 1986 1987 VPRINTK("EXIT\n"); 1988 1989 return IRQ_RETVAL(rc); 1990 } 1991 1992 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) 1993 { 1994 struct ata_port *ap = qc->ap; 1995 void __iomem *port_mmio = ahci_port_base(ap); 1996 struct ahci_port_priv *pp = ap->private_data; 1997 1998 /* Keep track of the currently active link. It will be used 1999 * in completion path to determine whether NCQ phase is in 2000 * progress. 2001 */ 2002 pp->active_link = qc->dev->link; 2003 2004 if (ata_is_ncq(qc->tf.protocol)) 2005 writel(1 << qc->hw_tag, port_mmio + PORT_SCR_ACT); 2006 2007 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) { 2008 u32 fbs = readl(port_mmio + PORT_FBS); 2009 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); 2010 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET; 2011 writel(fbs, port_mmio + PORT_FBS); 2012 pp->fbs_last_dev = qc->dev->link->pmp; 2013 } 2014 2015 writel(1 << qc->hw_tag, port_mmio + PORT_CMD_ISSUE); 2016 2017 ahci_sw_activity(qc->dev->link); 2018 2019 return 0; 2020 } 2021 EXPORT_SYMBOL_GPL(ahci_qc_issue); 2022 2023 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc) 2024 { 2025 struct ahci_port_priv *pp = qc->ap->private_data; 2026 u8 *rx_fis = pp->rx_fis; 2027 2028 if (pp->fbs_enabled) 2029 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ; 2030 2031 /* 2032 * After a successful execution of an ATA PIO data-in command, 2033 * the device doesn't send D2H Reg FIS to update the TF and 2034 * the host should take TF and E_Status from the preceding PIO 2035 * Setup FIS. 2036 */ 2037 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE && 2038 !(qc->flags & ATA_QCFLAG_FAILED)) { 2039 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf); 2040 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15]; 2041 } else 2042 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf); 2043 2044 return true; 2045 } 2046 2047 static void ahci_freeze(struct ata_port *ap) 2048 { 2049 void __iomem *port_mmio = ahci_port_base(ap); 2050 2051 /* turn IRQ off */ 2052 writel(0, port_mmio + PORT_IRQ_MASK); 2053 } 2054 2055 static void ahci_thaw(struct ata_port *ap) 2056 { 2057 struct ahci_host_priv *hpriv = ap->host->private_data; 2058 void __iomem *mmio = hpriv->mmio; 2059 void __iomem *port_mmio = ahci_port_base(ap); 2060 u32 tmp; 2061 struct ahci_port_priv *pp = ap->private_data; 2062 2063 /* clear IRQ */ 2064 tmp = readl(port_mmio + PORT_IRQ_STAT); 2065 writel(tmp, port_mmio + PORT_IRQ_STAT); 2066 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); 2067 2068 /* turn IRQ back on */ 2069 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2070 } 2071 2072 void ahci_error_handler(struct ata_port *ap) 2073 { 2074 struct ahci_host_priv *hpriv = ap->host->private_data; 2075 2076 if (!(ap->pflags & ATA_PFLAG_FROZEN)) { 2077 /* restart engine */ 2078 hpriv->stop_engine(ap); 2079 hpriv->start_engine(ap); 2080 } 2081 2082 sata_pmp_error_handler(ap); 2083 2084 if (!ata_dev_enabled(ap->link.device)) 2085 hpriv->stop_engine(ap); 2086 } 2087 EXPORT_SYMBOL_GPL(ahci_error_handler); 2088 2089 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) 2090 { 2091 struct ata_port *ap = qc->ap; 2092 2093 /* make DMA engine forget about the failed command */ 2094 if (qc->flags & ATA_QCFLAG_FAILED) 2095 ahci_kick_engine(ap); 2096 } 2097 2098 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep) 2099 { 2100 struct ahci_host_priv *hpriv = ap->host->private_data; 2101 void __iomem *port_mmio = ahci_port_base(ap); 2102 struct ata_device *dev = ap->link.device; 2103 u32 devslp, dm, dito, mdat, deto, dito_conf; 2104 int rc; 2105 unsigned int err_mask; 2106 2107 devslp = readl(port_mmio + PORT_DEVSLP); 2108 if (!(devslp & PORT_DEVSLP_DSP)) { 2109 dev_info(ap->host->dev, "port does not support device sleep\n"); 2110 return; 2111 } 2112 2113 /* disable device sleep */ 2114 if (!sleep) { 2115 if (devslp & PORT_DEVSLP_ADSE) { 2116 writel(devslp & ~PORT_DEVSLP_ADSE, 2117 port_mmio + PORT_DEVSLP); 2118 err_mask = ata_dev_set_feature(dev, 2119 SETFEATURES_SATA_DISABLE, 2120 SATA_DEVSLP); 2121 if (err_mask && err_mask != AC_ERR_DEV) 2122 ata_dev_warn(dev, "failed to disable DEVSLP\n"); 2123 } 2124 return; 2125 } 2126 2127 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET; 2128 dito = devslp_idle_timeout / (dm + 1); 2129 if (dito > 0x3ff) 2130 dito = 0x3ff; 2131 2132 dito_conf = (devslp >> PORT_DEVSLP_DITO_OFFSET) & 0x3FF; 2133 2134 /* device sleep was already enabled and same dito */ 2135 if ((devslp & PORT_DEVSLP_ADSE) && (dito_conf == dito)) 2136 return; 2137 2138 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */ 2139 rc = hpriv->stop_engine(ap); 2140 if (rc) 2141 return; 2142 2143 /* Use the nominal value 10 ms if the read MDAT is zero, 2144 * the nominal value of DETO is 20 ms. 2145 */ 2146 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] & 2147 ATA_LOG_DEVSLP_VALID_MASK) { 2148 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] & 2149 ATA_LOG_DEVSLP_MDAT_MASK; 2150 if (!mdat) 2151 mdat = 10; 2152 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO]; 2153 if (!deto) 2154 deto = 20; 2155 } else { 2156 mdat = 10; 2157 deto = 20; 2158 } 2159 2160 /* Make dito, mdat, deto bits to 0s */ 2161 devslp &= ~GENMASK_ULL(24, 2); 2162 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) | 2163 (mdat << PORT_DEVSLP_MDAT_OFFSET) | 2164 (deto << PORT_DEVSLP_DETO_OFFSET) | 2165 PORT_DEVSLP_ADSE); 2166 writel(devslp, port_mmio + PORT_DEVSLP); 2167 2168 hpriv->start_engine(ap); 2169 2170 /* enable device sleep feature for the drive */ 2171 err_mask = ata_dev_set_feature(dev, 2172 SETFEATURES_SATA_ENABLE, 2173 SATA_DEVSLP); 2174 if (err_mask && err_mask != AC_ERR_DEV) 2175 ata_dev_warn(dev, "failed to enable DEVSLP\n"); 2176 } 2177 2178 static void ahci_enable_fbs(struct ata_port *ap) 2179 { 2180 struct ahci_host_priv *hpriv = ap->host->private_data; 2181 struct ahci_port_priv *pp = ap->private_data; 2182 void __iomem *port_mmio = ahci_port_base(ap); 2183 u32 fbs; 2184 int rc; 2185 2186 if (!pp->fbs_supported) 2187 return; 2188 2189 fbs = readl(port_mmio + PORT_FBS); 2190 if (fbs & PORT_FBS_EN) { 2191 pp->fbs_enabled = true; 2192 pp->fbs_last_dev = -1; /* initialization */ 2193 return; 2194 } 2195 2196 rc = hpriv->stop_engine(ap); 2197 if (rc) 2198 return; 2199 2200 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS); 2201 fbs = readl(port_mmio + PORT_FBS); 2202 if (fbs & PORT_FBS_EN) { 2203 dev_info(ap->host->dev, "FBS is enabled\n"); 2204 pp->fbs_enabled = true; 2205 pp->fbs_last_dev = -1; /* initialization */ 2206 } else 2207 dev_err(ap->host->dev, "Failed to enable FBS\n"); 2208 2209 hpriv->start_engine(ap); 2210 } 2211 2212 static void ahci_disable_fbs(struct ata_port *ap) 2213 { 2214 struct ahci_host_priv *hpriv = ap->host->private_data; 2215 struct ahci_port_priv *pp = ap->private_data; 2216 void __iomem *port_mmio = ahci_port_base(ap); 2217 u32 fbs; 2218 int rc; 2219 2220 if (!pp->fbs_supported) 2221 return; 2222 2223 fbs = readl(port_mmio + PORT_FBS); 2224 if ((fbs & PORT_FBS_EN) == 0) { 2225 pp->fbs_enabled = false; 2226 return; 2227 } 2228 2229 rc = hpriv->stop_engine(ap); 2230 if (rc) 2231 return; 2232 2233 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS); 2234 fbs = readl(port_mmio + PORT_FBS); 2235 if (fbs & PORT_FBS_EN) 2236 dev_err(ap->host->dev, "Failed to disable FBS\n"); 2237 else { 2238 dev_info(ap->host->dev, "FBS is disabled\n"); 2239 pp->fbs_enabled = false; 2240 } 2241 2242 hpriv->start_engine(ap); 2243 } 2244 2245 static void ahci_pmp_attach(struct ata_port *ap) 2246 { 2247 void __iomem *port_mmio = ahci_port_base(ap); 2248 struct ahci_port_priv *pp = ap->private_data; 2249 u32 cmd; 2250 2251 cmd = readl(port_mmio + PORT_CMD); 2252 cmd |= PORT_CMD_PMP; 2253 writel(cmd, port_mmio + PORT_CMD); 2254 2255 ahci_enable_fbs(ap); 2256 2257 pp->intr_mask |= PORT_IRQ_BAD_PMP; 2258 2259 /* 2260 * We must not change the port interrupt mask register if the 2261 * port is marked frozen, the value in pp->intr_mask will be 2262 * restored later when the port is thawed. 2263 * 2264 * Note that during initialization, the port is marked as 2265 * frozen since the irq handler is not yet registered. 2266 */ 2267 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 2268 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2269 } 2270 2271 static void ahci_pmp_detach(struct ata_port *ap) 2272 { 2273 void __iomem *port_mmio = ahci_port_base(ap); 2274 struct ahci_port_priv *pp = ap->private_data; 2275 u32 cmd; 2276 2277 ahci_disable_fbs(ap); 2278 2279 cmd = readl(port_mmio + PORT_CMD); 2280 cmd &= ~PORT_CMD_PMP; 2281 writel(cmd, port_mmio + PORT_CMD); 2282 2283 pp->intr_mask &= ~PORT_IRQ_BAD_PMP; 2284 2285 /* see comment above in ahci_pmp_attach() */ 2286 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 2287 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2288 } 2289 2290 int ahci_port_resume(struct ata_port *ap) 2291 { 2292 ahci_rpm_get_port(ap); 2293 2294 ahci_power_up(ap); 2295 ahci_start_port(ap); 2296 2297 if (sata_pmp_attached(ap)) 2298 ahci_pmp_attach(ap); 2299 else 2300 ahci_pmp_detach(ap); 2301 2302 return 0; 2303 } 2304 EXPORT_SYMBOL_GPL(ahci_port_resume); 2305 2306 #ifdef CONFIG_PM 2307 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) 2308 { 2309 const char *emsg = NULL; 2310 int rc; 2311 2312 rc = ahci_deinit_port(ap, &emsg); 2313 if (rc == 0) 2314 ahci_power_down(ap); 2315 else { 2316 ata_port_err(ap, "%s (%d)\n", emsg, rc); 2317 ata_port_freeze(ap); 2318 } 2319 2320 ahci_rpm_put_port(ap); 2321 return rc; 2322 } 2323 #endif 2324 2325 static int ahci_port_start(struct ata_port *ap) 2326 { 2327 struct ahci_host_priv *hpriv = ap->host->private_data; 2328 struct device *dev = ap->host->dev; 2329 struct ahci_port_priv *pp; 2330 void *mem; 2331 dma_addr_t mem_dma; 2332 size_t dma_sz, rx_fis_sz; 2333 2334 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 2335 if (!pp) 2336 return -ENOMEM; 2337 2338 if (ap->host->n_ports > 1) { 2339 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL); 2340 if (!pp->irq_desc) { 2341 devm_kfree(dev, pp); 2342 return -ENOMEM; 2343 } 2344 snprintf(pp->irq_desc, 8, 2345 "%s%d", dev_driver_string(dev), ap->port_no); 2346 } 2347 2348 /* check FBS capability */ 2349 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) { 2350 void __iomem *port_mmio = ahci_port_base(ap); 2351 u32 cmd = readl(port_mmio + PORT_CMD); 2352 if (cmd & PORT_CMD_FBSCP) 2353 pp->fbs_supported = true; 2354 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) { 2355 dev_info(dev, "port %d can do FBS, forcing FBSCP\n", 2356 ap->port_no); 2357 pp->fbs_supported = true; 2358 } else 2359 dev_warn(dev, "port %d is not capable of FBS\n", 2360 ap->port_no); 2361 } 2362 2363 if (pp->fbs_supported) { 2364 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ; 2365 rx_fis_sz = AHCI_RX_FIS_SZ * 16; 2366 } else { 2367 dma_sz = AHCI_PORT_PRIV_DMA_SZ; 2368 rx_fis_sz = AHCI_RX_FIS_SZ; 2369 } 2370 2371 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL); 2372 if (!mem) 2373 return -ENOMEM; 2374 2375 /* 2376 * First item in chunk of DMA memory: 32-slot command table, 2377 * 32 bytes each in size 2378 */ 2379 pp->cmd_slot = mem; 2380 pp->cmd_slot_dma = mem_dma; 2381 2382 mem += AHCI_CMD_SLOT_SZ; 2383 mem_dma += AHCI_CMD_SLOT_SZ; 2384 2385 /* 2386 * Second item: Received-FIS area 2387 */ 2388 pp->rx_fis = mem; 2389 pp->rx_fis_dma = mem_dma; 2390 2391 mem += rx_fis_sz; 2392 mem_dma += rx_fis_sz; 2393 2394 /* 2395 * Third item: data area for storing a single command 2396 * and its scatter-gather table 2397 */ 2398 pp->cmd_tbl = mem; 2399 pp->cmd_tbl_dma = mem_dma; 2400 2401 /* 2402 * Save off initial list of interrupts to be enabled. 2403 * This could be changed later 2404 */ 2405 pp->intr_mask = DEF_PORT_IRQ; 2406 2407 /* 2408 * Switch to per-port locking in case each port has its own MSI vector. 2409 */ 2410 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) { 2411 spin_lock_init(&pp->lock); 2412 ap->lock = &pp->lock; 2413 } 2414 2415 ap->private_data = pp; 2416 2417 /* engage engines, captain */ 2418 return ahci_port_resume(ap); 2419 } 2420 2421 static void ahci_port_stop(struct ata_port *ap) 2422 { 2423 const char *emsg = NULL; 2424 struct ahci_host_priv *hpriv = ap->host->private_data; 2425 void __iomem *host_mmio = hpriv->mmio; 2426 int rc; 2427 2428 /* de-initialize port */ 2429 rc = ahci_deinit_port(ap, &emsg); 2430 if (rc) 2431 ata_port_warn(ap, "%s (%d)\n", emsg, rc); 2432 2433 /* 2434 * Clear GHC.IS to prevent stuck INTx after disabling MSI and 2435 * re-enabling INTx. 2436 */ 2437 writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT); 2438 2439 ahci_rpm_put_port(ap); 2440 } 2441 2442 void ahci_print_info(struct ata_host *host, const char *scc_s) 2443 { 2444 struct ahci_host_priv *hpriv = host->private_data; 2445 u32 vers, cap, cap2, impl, speed; 2446 const char *speed_s; 2447 2448 vers = hpriv->version; 2449 cap = hpriv->cap; 2450 cap2 = hpriv->cap2; 2451 impl = hpriv->port_map; 2452 2453 speed = (cap >> 20) & 0xf; 2454 if (speed == 1) 2455 speed_s = "1.5"; 2456 else if (speed == 2) 2457 speed_s = "3"; 2458 else if (speed == 3) 2459 speed_s = "6"; 2460 else 2461 speed_s = "?"; 2462 2463 dev_info(host->dev, 2464 "AHCI %02x%02x.%02x%02x " 2465 "%u slots %u ports %s Gbps 0x%x impl %s mode\n" 2466 , 2467 2468 (vers >> 24) & 0xff, 2469 (vers >> 16) & 0xff, 2470 (vers >> 8) & 0xff, 2471 vers & 0xff, 2472 2473 ((cap >> 8) & 0x1f) + 1, 2474 (cap & 0x1f) + 1, 2475 speed_s, 2476 impl, 2477 scc_s); 2478 2479 dev_info(host->dev, 2480 "flags: " 2481 "%s%s%s%s%s%s%s" 2482 "%s%s%s%s%s%s%s" 2483 "%s%s%s%s%s%s%s" 2484 "%s%s\n" 2485 , 2486 2487 cap & HOST_CAP_64 ? "64bit " : "", 2488 cap & HOST_CAP_NCQ ? "ncq " : "", 2489 cap & HOST_CAP_SNTF ? "sntf " : "", 2490 cap & HOST_CAP_MPS ? "ilck " : "", 2491 cap & HOST_CAP_SSS ? "stag " : "", 2492 cap & HOST_CAP_ALPM ? "pm " : "", 2493 cap & HOST_CAP_LED ? "led " : "", 2494 cap & HOST_CAP_CLO ? "clo " : "", 2495 cap & HOST_CAP_ONLY ? "only " : "", 2496 cap & HOST_CAP_PMP ? "pmp " : "", 2497 cap & HOST_CAP_FBS ? "fbs " : "", 2498 cap & HOST_CAP_PIO_MULTI ? "pio " : "", 2499 cap & HOST_CAP_SSC ? "slum " : "", 2500 cap & HOST_CAP_PART ? "part " : "", 2501 cap & HOST_CAP_CCC ? "ccc " : "", 2502 cap & HOST_CAP_EMS ? "ems " : "", 2503 cap & HOST_CAP_SXS ? "sxs " : "", 2504 cap2 & HOST_CAP2_DESO ? "deso " : "", 2505 cap2 & HOST_CAP2_SADM ? "sadm " : "", 2506 cap2 & HOST_CAP2_SDS ? "sds " : "", 2507 cap2 & HOST_CAP2_APST ? "apst " : "", 2508 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "", 2509 cap2 & HOST_CAP2_BOH ? "boh " : "" 2510 ); 2511 } 2512 EXPORT_SYMBOL_GPL(ahci_print_info); 2513 2514 void ahci_set_em_messages(struct ahci_host_priv *hpriv, 2515 struct ata_port_info *pi) 2516 { 2517 u8 messages; 2518 void __iomem *mmio = hpriv->mmio; 2519 u32 em_loc = readl(mmio + HOST_EM_LOC); 2520 u32 em_ctl = readl(mmio + HOST_EM_CTL); 2521 2522 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS)) 2523 return; 2524 2525 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16; 2526 2527 if (messages) { 2528 /* store em_loc */ 2529 hpriv->em_loc = ((em_loc >> 16) * 4); 2530 hpriv->em_buf_sz = ((em_loc & 0xff) * 4); 2531 hpriv->em_msg_type = messages; 2532 pi->flags |= ATA_FLAG_EM; 2533 if (!(em_ctl & EM_CTL_ALHD)) 2534 pi->flags |= ATA_FLAG_SW_ACTIVITY; 2535 } 2536 } 2537 EXPORT_SYMBOL_GPL(ahci_set_em_messages); 2538 2539 static int ahci_host_activate_multi_irqs(struct ata_host *host, 2540 struct scsi_host_template *sht) 2541 { 2542 struct ahci_host_priv *hpriv = host->private_data; 2543 int i, rc; 2544 2545 rc = ata_host_start(host); 2546 if (rc) 2547 return rc; 2548 /* 2549 * Requests IRQs according to AHCI-1.1 when multiple MSIs were 2550 * allocated. That is one MSI per port, starting from @irq. 2551 */ 2552 for (i = 0; i < host->n_ports; i++) { 2553 struct ahci_port_priv *pp = host->ports[i]->private_data; 2554 int irq = hpriv->get_irq_vector(host, i); 2555 2556 /* Do not receive interrupts sent by dummy ports */ 2557 if (!pp) { 2558 disable_irq(irq); 2559 continue; 2560 } 2561 2562 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard, 2563 0, pp->irq_desc, host->ports[i]); 2564 2565 if (rc) 2566 return rc; 2567 ata_port_desc(host->ports[i], "irq %d", irq); 2568 } 2569 2570 return ata_host_register(host, sht); 2571 } 2572 2573 /** 2574 * ahci_host_activate - start AHCI host, request IRQs and register it 2575 * @host: target ATA host 2576 * @sht: scsi_host_template to use when registering the host 2577 * 2578 * LOCKING: 2579 * Inherited from calling layer (may sleep). 2580 * 2581 * RETURNS: 2582 * 0 on success, -errno otherwise. 2583 */ 2584 int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht) 2585 { 2586 struct ahci_host_priv *hpriv = host->private_data; 2587 int irq = hpriv->irq; 2588 int rc; 2589 2590 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) { 2591 if (hpriv->irq_handler && 2592 hpriv->irq_handler != ahci_single_level_irq_intr) 2593 dev_warn(host->dev, 2594 "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n"); 2595 if (!hpriv->get_irq_vector) { 2596 dev_err(host->dev, 2597 "AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n"); 2598 return -EIO; 2599 } 2600 2601 rc = ahci_host_activate_multi_irqs(host, sht); 2602 } else { 2603 rc = ata_host_activate(host, irq, hpriv->irq_handler, 2604 IRQF_SHARED, sht); 2605 } 2606 2607 2608 return rc; 2609 } 2610 EXPORT_SYMBOL_GPL(ahci_host_activate); 2611 2612 MODULE_AUTHOR("Jeff Garzik"); 2613 MODULE_DESCRIPTION("Common AHCI SATA low-level routines"); 2614 MODULE_LICENSE("GPL"); 2615