1 /* 2 * libahci.c - Common AHCI SATA low-level routines 3 * 4 * Maintained by: Tejun Heo <tj@kernel.org> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2004-2005 Red Hat, Inc. 9 * 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; see the file COPYING. If not, write to 23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * 26 * libata documentation is available via 'make {ps|pdf}docs', 27 * as Documentation/DocBook/libata.* 28 * 29 * AHCI hardware documentation: 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 32 * 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/gfp.h> 37 #include <linux/module.h> 38 #include <linux/blkdev.h> 39 #include <linux/delay.h> 40 #include <linux/interrupt.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/device.h> 43 #include <scsi/scsi_host.h> 44 #include <scsi/scsi_cmnd.h> 45 #include <linux/libata.h> 46 #include <linux/pci.h> 47 #include "ahci.h" 48 #include "libata.h" 49 50 static int ahci_skip_host_reset; 51 int ahci_ignore_sss; 52 EXPORT_SYMBOL_GPL(ahci_ignore_sss); 53 54 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); 55 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); 56 57 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444); 58 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)"); 59 60 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 61 unsigned hints); 62 static ssize_t ahci_led_show(struct ata_port *ap, char *buf); 63 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 64 size_t size); 65 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 66 ssize_t size); 67 68 69 70 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); 71 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); 72 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc); 73 static int ahci_port_start(struct ata_port *ap); 74 static void ahci_port_stop(struct ata_port *ap); 75 static void ahci_qc_prep(struct ata_queued_cmd *qc); 76 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc); 77 static void ahci_freeze(struct ata_port *ap); 78 static void ahci_thaw(struct ata_port *ap); 79 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep); 80 static void ahci_enable_fbs(struct ata_port *ap); 81 static void ahci_disable_fbs(struct ata_port *ap); 82 static void ahci_pmp_attach(struct ata_port *ap); 83 static void ahci_pmp_detach(struct ata_port *ap); 84 static int ahci_softreset(struct ata_link *link, unsigned int *class, 85 unsigned long deadline); 86 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class, 87 unsigned long deadline); 88 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 89 unsigned long deadline); 90 static void ahci_postreset(struct ata_link *link, unsigned int *class); 91 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); 92 static void ahci_dev_config(struct ata_device *dev); 93 #ifdef CONFIG_PM 94 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); 95 #endif 96 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf); 97 static ssize_t ahci_activity_store(struct ata_device *dev, 98 enum sw_activity val); 99 static void ahci_init_sw_activity(struct ata_link *link); 100 101 static ssize_t ahci_show_host_caps(struct device *dev, 102 struct device_attribute *attr, char *buf); 103 static ssize_t ahci_show_host_cap2(struct device *dev, 104 struct device_attribute *attr, char *buf); 105 static ssize_t ahci_show_host_version(struct device *dev, 106 struct device_attribute *attr, char *buf); 107 static ssize_t ahci_show_port_cmd(struct device *dev, 108 struct device_attribute *attr, char *buf); 109 static ssize_t ahci_read_em_buffer(struct device *dev, 110 struct device_attribute *attr, char *buf); 111 static ssize_t ahci_store_em_buffer(struct device *dev, 112 struct device_attribute *attr, 113 const char *buf, size_t size); 114 static ssize_t ahci_show_em_supported(struct device *dev, 115 struct device_attribute *attr, char *buf); 116 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance); 117 118 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL); 119 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL); 120 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL); 121 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL); 122 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO, 123 ahci_read_em_buffer, ahci_store_em_buffer); 124 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL); 125 126 struct device_attribute *ahci_shost_attrs[] = { 127 &dev_attr_link_power_management_policy, 128 &dev_attr_em_message_type, 129 &dev_attr_em_message, 130 &dev_attr_ahci_host_caps, 131 &dev_attr_ahci_host_cap2, 132 &dev_attr_ahci_host_version, 133 &dev_attr_ahci_port_cmd, 134 &dev_attr_em_buffer, 135 &dev_attr_em_message_supported, 136 NULL 137 }; 138 EXPORT_SYMBOL_GPL(ahci_shost_attrs); 139 140 struct device_attribute *ahci_sdev_attrs[] = { 141 &dev_attr_sw_activity, 142 &dev_attr_unload_heads, 143 &dev_attr_ncq_prio_enable, 144 NULL 145 }; 146 EXPORT_SYMBOL_GPL(ahci_sdev_attrs); 147 148 struct ata_port_operations ahci_ops = { 149 .inherits = &sata_pmp_port_ops, 150 151 .qc_defer = ahci_pmp_qc_defer, 152 .qc_prep = ahci_qc_prep, 153 .qc_issue = ahci_qc_issue, 154 .qc_fill_rtf = ahci_qc_fill_rtf, 155 156 .freeze = ahci_freeze, 157 .thaw = ahci_thaw, 158 .softreset = ahci_softreset, 159 .hardreset = ahci_hardreset, 160 .postreset = ahci_postreset, 161 .pmp_softreset = ahci_softreset, 162 .error_handler = ahci_error_handler, 163 .post_internal_cmd = ahci_post_internal_cmd, 164 .dev_config = ahci_dev_config, 165 166 .scr_read = ahci_scr_read, 167 .scr_write = ahci_scr_write, 168 .pmp_attach = ahci_pmp_attach, 169 .pmp_detach = ahci_pmp_detach, 170 171 .set_lpm = ahci_set_lpm, 172 .em_show = ahci_led_show, 173 .em_store = ahci_led_store, 174 .sw_activity_show = ahci_activity_show, 175 .sw_activity_store = ahci_activity_store, 176 .transmit_led_message = ahci_transmit_led_message, 177 #ifdef CONFIG_PM 178 .port_suspend = ahci_port_suspend, 179 .port_resume = ahci_port_resume, 180 #endif 181 .port_start = ahci_port_start, 182 .port_stop = ahci_port_stop, 183 }; 184 EXPORT_SYMBOL_GPL(ahci_ops); 185 186 struct ata_port_operations ahci_pmp_retry_srst_ops = { 187 .inherits = &ahci_ops, 188 .softreset = ahci_pmp_retry_softreset, 189 }; 190 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops); 191 192 static bool ahci_em_messages __read_mostly = true; 193 EXPORT_SYMBOL_GPL(ahci_em_messages); 194 module_param(ahci_em_messages, bool, 0444); 195 /* add other LED protocol types when they become supported */ 196 MODULE_PARM_DESC(ahci_em_messages, 197 "AHCI Enclosure Management Message control (0 = off, 1 = on)"); 198 199 /* device sleep idle timeout in ms */ 200 static int devslp_idle_timeout __read_mostly = 1000; 201 module_param(devslp_idle_timeout, int, 0644); 202 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout"); 203 204 static void ahci_enable_ahci(void __iomem *mmio) 205 { 206 int i; 207 u32 tmp; 208 209 /* turn on AHCI_EN */ 210 tmp = readl(mmio + HOST_CTL); 211 if (tmp & HOST_AHCI_EN) 212 return; 213 214 /* Some controllers need AHCI_EN to be written multiple times. 215 * Try a few times before giving up. 216 */ 217 for (i = 0; i < 5; i++) { 218 tmp |= HOST_AHCI_EN; 219 writel(tmp, mmio + HOST_CTL); 220 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ 221 if (tmp & HOST_AHCI_EN) 222 return; 223 msleep(10); 224 } 225 226 WARN_ON(1); 227 } 228 229 /** 230 * ahci_rpm_get_port - Make sure the port is powered on 231 * @ap: Port to power on 232 * 233 * Whenever there is need to access the AHCI host registers outside of 234 * normal execution paths, call this function to make sure the host is 235 * actually powered on. 236 */ 237 static int ahci_rpm_get_port(struct ata_port *ap) 238 { 239 return pm_runtime_get_sync(ap->dev); 240 } 241 242 /** 243 * ahci_rpm_put_port - Undoes ahci_rpm_get_port() 244 * @ap: Port to power down 245 * 246 * Undoes ahci_rpm_get_port() and possibly powers down the AHCI host 247 * if it has no more active users. 248 */ 249 static void ahci_rpm_put_port(struct ata_port *ap) 250 { 251 pm_runtime_put(ap->dev); 252 } 253 254 static ssize_t ahci_show_host_caps(struct device *dev, 255 struct device_attribute *attr, char *buf) 256 { 257 struct Scsi_Host *shost = class_to_shost(dev); 258 struct ata_port *ap = ata_shost_to_port(shost); 259 struct ahci_host_priv *hpriv = ap->host->private_data; 260 261 return sprintf(buf, "%x\n", hpriv->cap); 262 } 263 264 static ssize_t ahci_show_host_cap2(struct device *dev, 265 struct device_attribute *attr, char *buf) 266 { 267 struct Scsi_Host *shost = class_to_shost(dev); 268 struct ata_port *ap = ata_shost_to_port(shost); 269 struct ahci_host_priv *hpriv = ap->host->private_data; 270 271 return sprintf(buf, "%x\n", hpriv->cap2); 272 } 273 274 static ssize_t ahci_show_host_version(struct device *dev, 275 struct device_attribute *attr, char *buf) 276 { 277 struct Scsi_Host *shost = class_to_shost(dev); 278 struct ata_port *ap = ata_shost_to_port(shost); 279 struct ahci_host_priv *hpriv = ap->host->private_data; 280 281 return sprintf(buf, "%x\n", hpriv->version); 282 } 283 284 static ssize_t ahci_show_port_cmd(struct device *dev, 285 struct device_attribute *attr, char *buf) 286 { 287 struct Scsi_Host *shost = class_to_shost(dev); 288 struct ata_port *ap = ata_shost_to_port(shost); 289 void __iomem *port_mmio = ahci_port_base(ap); 290 ssize_t ret; 291 292 ahci_rpm_get_port(ap); 293 ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD)); 294 ahci_rpm_put_port(ap); 295 296 return ret; 297 } 298 299 static ssize_t ahci_read_em_buffer(struct device *dev, 300 struct device_attribute *attr, char *buf) 301 { 302 struct Scsi_Host *shost = class_to_shost(dev); 303 struct ata_port *ap = ata_shost_to_port(shost); 304 struct ahci_host_priv *hpriv = ap->host->private_data; 305 void __iomem *mmio = hpriv->mmio; 306 void __iomem *em_mmio = mmio + hpriv->em_loc; 307 u32 em_ctl, msg; 308 unsigned long flags; 309 size_t count; 310 int i; 311 312 ahci_rpm_get_port(ap); 313 spin_lock_irqsave(ap->lock, flags); 314 315 em_ctl = readl(mmio + HOST_EM_CTL); 316 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT || 317 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) { 318 spin_unlock_irqrestore(ap->lock, flags); 319 ahci_rpm_put_port(ap); 320 return -EINVAL; 321 } 322 323 if (!(em_ctl & EM_CTL_MR)) { 324 spin_unlock_irqrestore(ap->lock, flags); 325 ahci_rpm_put_port(ap); 326 return -EAGAIN; 327 } 328 329 if (!(em_ctl & EM_CTL_SMB)) 330 em_mmio += hpriv->em_buf_sz; 331 332 count = hpriv->em_buf_sz; 333 334 /* the count should not be larger than PAGE_SIZE */ 335 if (count > PAGE_SIZE) { 336 if (printk_ratelimit()) 337 ata_port_warn(ap, 338 "EM read buffer size too large: " 339 "buffer size %u, page size %lu\n", 340 hpriv->em_buf_sz, PAGE_SIZE); 341 count = PAGE_SIZE; 342 } 343 344 for (i = 0; i < count; i += 4) { 345 msg = readl(em_mmio + i); 346 buf[i] = msg & 0xff; 347 buf[i + 1] = (msg >> 8) & 0xff; 348 buf[i + 2] = (msg >> 16) & 0xff; 349 buf[i + 3] = (msg >> 24) & 0xff; 350 } 351 352 spin_unlock_irqrestore(ap->lock, flags); 353 ahci_rpm_put_port(ap); 354 355 return i; 356 } 357 358 static ssize_t ahci_store_em_buffer(struct device *dev, 359 struct device_attribute *attr, 360 const char *buf, size_t size) 361 { 362 struct Scsi_Host *shost = class_to_shost(dev); 363 struct ata_port *ap = ata_shost_to_port(shost); 364 struct ahci_host_priv *hpriv = ap->host->private_data; 365 void __iomem *mmio = hpriv->mmio; 366 void __iomem *em_mmio = mmio + hpriv->em_loc; 367 const unsigned char *msg_buf = buf; 368 u32 em_ctl, msg; 369 unsigned long flags; 370 int i; 371 372 /* check size validity */ 373 if (!(ap->flags & ATA_FLAG_EM) || 374 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) || 375 size % 4 || size > hpriv->em_buf_sz) 376 return -EINVAL; 377 378 ahci_rpm_get_port(ap); 379 spin_lock_irqsave(ap->lock, flags); 380 381 em_ctl = readl(mmio + HOST_EM_CTL); 382 if (em_ctl & EM_CTL_TM) { 383 spin_unlock_irqrestore(ap->lock, flags); 384 ahci_rpm_put_port(ap); 385 return -EBUSY; 386 } 387 388 for (i = 0; i < size; i += 4) { 389 msg = msg_buf[i] | msg_buf[i + 1] << 8 | 390 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24; 391 writel(msg, em_mmio + i); 392 } 393 394 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 395 396 spin_unlock_irqrestore(ap->lock, flags); 397 ahci_rpm_put_port(ap); 398 399 return size; 400 } 401 402 static ssize_t ahci_show_em_supported(struct device *dev, 403 struct device_attribute *attr, char *buf) 404 { 405 struct Scsi_Host *shost = class_to_shost(dev); 406 struct ata_port *ap = ata_shost_to_port(shost); 407 struct ahci_host_priv *hpriv = ap->host->private_data; 408 void __iomem *mmio = hpriv->mmio; 409 u32 em_ctl; 410 411 ahci_rpm_get_port(ap); 412 em_ctl = readl(mmio + HOST_EM_CTL); 413 ahci_rpm_put_port(ap); 414 415 return sprintf(buf, "%s%s%s%s\n", 416 em_ctl & EM_CTL_LED ? "led " : "", 417 em_ctl & EM_CTL_SAFTE ? "saf-te " : "", 418 em_ctl & EM_CTL_SES ? "ses-2 " : "", 419 em_ctl & EM_CTL_SGPIO ? "sgpio " : ""); 420 } 421 422 /** 423 * ahci_save_initial_config - Save and fixup initial config values 424 * @dev: target AHCI device 425 * @hpriv: host private area to store config values 426 * 427 * Some registers containing configuration info might be setup by 428 * BIOS and might be cleared on reset. This function saves the 429 * initial values of those registers into @hpriv such that they 430 * can be restored after controller reset. 431 * 432 * If inconsistent, config values are fixed up by this function. 433 * 434 * If it is not set already this function sets hpriv->start_engine to 435 * ahci_start_engine. 436 * 437 * LOCKING: 438 * None. 439 */ 440 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv) 441 { 442 void __iomem *mmio = hpriv->mmio; 443 u32 cap, cap2, vers, port_map; 444 int i; 445 446 /* make sure AHCI mode is enabled before accessing CAP */ 447 ahci_enable_ahci(mmio); 448 449 /* Values prefixed with saved_ are written back to host after 450 * reset. Values without are used for driver operation. 451 */ 452 hpriv->saved_cap = cap = readl(mmio + HOST_CAP); 453 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); 454 455 /* CAP2 register is only defined for AHCI 1.2 and later */ 456 vers = readl(mmio + HOST_VERSION); 457 if ((vers >> 16) > 1 || 458 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200)) 459 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2); 460 else 461 hpriv->saved_cap2 = cap2 = 0; 462 463 /* some chips have errata preventing 64bit use */ 464 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { 465 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n"); 466 cap &= ~HOST_CAP_64; 467 } 468 469 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { 470 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n"); 471 cap &= ~HOST_CAP_NCQ; 472 } 473 474 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) { 475 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n"); 476 cap |= HOST_CAP_NCQ; 477 } 478 479 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { 480 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n"); 481 cap &= ~HOST_CAP_PMP; 482 } 483 484 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) { 485 dev_info(dev, 486 "controller can't do SNTF, turning off CAP_SNTF\n"); 487 cap &= ~HOST_CAP_SNTF; 488 } 489 490 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) { 491 dev_info(dev, 492 "controller can't do DEVSLP, turning off\n"); 493 cap2 &= ~HOST_CAP2_SDS; 494 cap2 &= ~HOST_CAP2_SADM; 495 } 496 497 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) { 498 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n"); 499 cap |= HOST_CAP_FBS; 500 } 501 502 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) { 503 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n"); 504 cap &= ~HOST_CAP_FBS; 505 } 506 507 if (hpriv->force_port_map && port_map != hpriv->force_port_map) { 508 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n", 509 port_map, hpriv->force_port_map); 510 port_map = hpriv->force_port_map; 511 hpriv->saved_port_map = port_map; 512 } 513 514 if (hpriv->mask_port_map) { 515 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n", 516 port_map, 517 port_map & hpriv->mask_port_map); 518 port_map &= hpriv->mask_port_map; 519 } 520 521 /* cross check port_map and cap.n_ports */ 522 if (port_map) { 523 int map_ports = 0; 524 525 for (i = 0; i < AHCI_MAX_PORTS; i++) 526 if (port_map & (1 << i)) 527 map_ports++; 528 529 /* If PI has more ports than n_ports, whine, clear 530 * port_map and let it be generated from n_ports. 531 */ 532 if (map_ports > ahci_nr_ports(cap)) { 533 dev_warn(dev, 534 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n", 535 port_map, ahci_nr_ports(cap)); 536 port_map = 0; 537 } 538 } 539 540 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */ 541 if (!port_map && vers < 0x10300) { 542 port_map = (1 << ahci_nr_ports(cap)) - 1; 543 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map); 544 545 /* write the fixed up value to the PI register */ 546 hpriv->saved_port_map = port_map; 547 } 548 549 /* record values to use during operation */ 550 hpriv->cap = cap; 551 hpriv->cap2 = cap2; 552 hpriv->version = readl(mmio + HOST_VERSION); 553 hpriv->port_map = port_map; 554 555 if (!hpriv->start_engine) 556 hpriv->start_engine = ahci_start_engine; 557 558 if (!hpriv->irq_handler) 559 hpriv->irq_handler = ahci_single_level_irq_intr; 560 } 561 EXPORT_SYMBOL_GPL(ahci_save_initial_config); 562 563 /** 564 * ahci_restore_initial_config - Restore initial config 565 * @host: target ATA host 566 * 567 * Restore initial config stored by ahci_save_initial_config(). 568 * 569 * LOCKING: 570 * None. 571 */ 572 static void ahci_restore_initial_config(struct ata_host *host) 573 { 574 struct ahci_host_priv *hpriv = host->private_data; 575 void __iomem *mmio = hpriv->mmio; 576 577 writel(hpriv->saved_cap, mmio + HOST_CAP); 578 if (hpriv->saved_cap2) 579 writel(hpriv->saved_cap2, mmio + HOST_CAP2); 580 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); 581 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ 582 } 583 584 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) 585 { 586 static const int offset[] = { 587 [SCR_STATUS] = PORT_SCR_STAT, 588 [SCR_CONTROL] = PORT_SCR_CTL, 589 [SCR_ERROR] = PORT_SCR_ERR, 590 [SCR_ACTIVE] = PORT_SCR_ACT, 591 [SCR_NOTIFICATION] = PORT_SCR_NTF, 592 }; 593 struct ahci_host_priv *hpriv = ap->host->private_data; 594 595 if (sc_reg < ARRAY_SIZE(offset) && 596 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) 597 return offset[sc_reg]; 598 return 0; 599 } 600 601 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) 602 { 603 void __iomem *port_mmio = ahci_port_base(link->ap); 604 int offset = ahci_scr_offset(link->ap, sc_reg); 605 606 if (offset) { 607 *val = readl(port_mmio + offset); 608 return 0; 609 } 610 return -EINVAL; 611 } 612 613 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) 614 { 615 void __iomem *port_mmio = ahci_port_base(link->ap); 616 int offset = ahci_scr_offset(link->ap, sc_reg); 617 618 if (offset) { 619 writel(val, port_mmio + offset); 620 return 0; 621 } 622 return -EINVAL; 623 } 624 625 void ahci_start_engine(struct ata_port *ap) 626 { 627 void __iomem *port_mmio = ahci_port_base(ap); 628 u32 tmp; 629 630 /* start DMA */ 631 tmp = readl(port_mmio + PORT_CMD); 632 tmp |= PORT_CMD_START; 633 writel(tmp, port_mmio + PORT_CMD); 634 readl(port_mmio + PORT_CMD); /* flush */ 635 } 636 EXPORT_SYMBOL_GPL(ahci_start_engine); 637 638 int ahci_stop_engine(struct ata_port *ap) 639 { 640 void __iomem *port_mmio = ahci_port_base(ap); 641 struct ahci_host_priv *hpriv = ap->host->private_data; 642 u32 tmp; 643 644 /* 645 * On some controllers, stopping a port's DMA engine while the port 646 * is in ALPM state (partial or slumber) results in failures on 647 * subsequent DMA engine starts. For those controllers, put the 648 * port back in active state before stopping its DMA engine. 649 */ 650 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) && 651 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) && 652 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) { 653 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n"); 654 return -EIO; 655 } 656 657 tmp = readl(port_mmio + PORT_CMD); 658 659 /* check if the HBA is idle */ 660 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) 661 return 0; 662 663 /* setting HBA to idle */ 664 tmp &= ~PORT_CMD_START; 665 writel(tmp, port_mmio + PORT_CMD); 666 667 /* wait for engine to stop. This could be as long as 500 msec */ 668 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 669 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); 670 if (tmp & PORT_CMD_LIST_ON) 671 return -EIO; 672 673 return 0; 674 } 675 EXPORT_SYMBOL_GPL(ahci_stop_engine); 676 677 void ahci_start_fis_rx(struct ata_port *ap) 678 { 679 void __iomem *port_mmio = ahci_port_base(ap); 680 struct ahci_host_priv *hpriv = ap->host->private_data; 681 struct ahci_port_priv *pp = ap->private_data; 682 u32 tmp; 683 684 /* set FIS registers */ 685 if (hpriv->cap & HOST_CAP_64) 686 writel((pp->cmd_slot_dma >> 16) >> 16, 687 port_mmio + PORT_LST_ADDR_HI); 688 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); 689 690 if (hpriv->cap & HOST_CAP_64) 691 writel((pp->rx_fis_dma >> 16) >> 16, 692 port_mmio + PORT_FIS_ADDR_HI); 693 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); 694 695 /* enable FIS reception */ 696 tmp = readl(port_mmio + PORT_CMD); 697 tmp |= PORT_CMD_FIS_RX; 698 writel(tmp, port_mmio + PORT_CMD); 699 700 /* flush */ 701 readl(port_mmio + PORT_CMD); 702 } 703 EXPORT_SYMBOL_GPL(ahci_start_fis_rx); 704 705 static int ahci_stop_fis_rx(struct ata_port *ap) 706 { 707 void __iomem *port_mmio = ahci_port_base(ap); 708 u32 tmp; 709 710 /* disable FIS reception */ 711 tmp = readl(port_mmio + PORT_CMD); 712 tmp &= ~PORT_CMD_FIS_RX; 713 writel(tmp, port_mmio + PORT_CMD); 714 715 /* wait for completion, spec says 500ms, give it 1000 */ 716 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON, 717 PORT_CMD_FIS_ON, 10, 1000); 718 if (tmp & PORT_CMD_FIS_ON) 719 return -EBUSY; 720 721 return 0; 722 } 723 724 static void ahci_power_up(struct ata_port *ap) 725 { 726 struct ahci_host_priv *hpriv = ap->host->private_data; 727 void __iomem *port_mmio = ahci_port_base(ap); 728 u32 cmd; 729 730 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 731 732 /* spin up device */ 733 if (hpriv->cap & HOST_CAP_SSS) { 734 cmd |= PORT_CMD_SPIN_UP; 735 writel(cmd, port_mmio + PORT_CMD); 736 } 737 738 /* wake up link */ 739 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); 740 } 741 742 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 743 unsigned int hints) 744 { 745 struct ata_port *ap = link->ap; 746 struct ahci_host_priv *hpriv = ap->host->private_data; 747 struct ahci_port_priv *pp = ap->private_data; 748 void __iomem *port_mmio = ahci_port_base(ap); 749 750 if (policy != ATA_LPM_MAX_POWER) { 751 /* wakeup flag only applies to the max power policy */ 752 hints &= ~ATA_LPM_WAKE_ONLY; 753 754 /* 755 * Disable interrupts on Phy Ready. This keeps us from 756 * getting woken up due to spurious phy ready 757 * interrupts. 758 */ 759 pp->intr_mask &= ~PORT_IRQ_PHYRDY; 760 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 761 762 sata_link_scr_lpm(link, policy, false); 763 } 764 765 if (hpriv->cap & HOST_CAP_ALPM) { 766 u32 cmd = readl(port_mmio + PORT_CMD); 767 768 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) { 769 if (!(hints & ATA_LPM_WAKE_ONLY)) 770 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE); 771 cmd |= PORT_CMD_ICC_ACTIVE; 772 773 writel(cmd, port_mmio + PORT_CMD); 774 readl(port_mmio + PORT_CMD); 775 776 /* wait 10ms to be sure we've come out of LPM state */ 777 ata_msleep(ap, 10); 778 779 if (hints & ATA_LPM_WAKE_ONLY) 780 return 0; 781 } else { 782 cmd |= PORT_CMD_ALPE; 783 if (policy == ATA_LPM_MIN_POWER) 784 cmd |= PORT_CMD_ASP; 785 786 /* write out new cmd value */ 787 writel(cmd, port_mmio + PORT_CMD); 788 } 789 } 790 791 /* set aggressive device sleep */ 792 if ((hpriv->cap2 & HOST_CAP2_SDS) && 793 (hpriv->cap2 & HOST_CAP2_SADM) && 794 (link->device->flags & ATA_DFLAG_DEVSLP)) { 795 if (policy == ATA_LPM_MIN_POWER) 796 ahci_set_aggressive_devslp(ap, true); 797 else 798 ahci_set_aggressive_devslp(ap, false); 799 } 800 801 if (policy == ATA_LPM_MAX_POWER) { 802 sata_link_scr_lpm(link, policy, false); 803 804 /* turn PHYRDY IRQ back on */ 805 pp->intr_mask |= PORT_IRQ_PHYRDY; 806 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 807 } 808 809 return 0; 810 } 811 812 #ifdef CONFIG_PM 813 static void ahci_power_down(struct ata_port *ap) 814 { 815 struct ahci_host_priv *hpriv = ap->host->private_data; 816 void __iomem *port_mmio = ahci_port_base(ap); 817 u32 cmd, scontrol; 818 819 if (!(hpriv->cap & HOST_CAP_SSS)) 820 return; 821 822 /* put device into listen mode, first set PxSCTL.DET to 0 */ 823 scontrol = readl(port_mmio + PORT_SCR_CTL); 824 scontrol &= ~0xf; 825 writel(scontrol, port_mmio + PORT_SCR_CTL); 826 827 /* then set PxCMD.SUD to 0 */ 828 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 829 cmd &= ~PORT_CMD_SPIN_UP; 830 writel(cmd, port_mmio + PORT_CMD); 831 } 832 #endif 833 834 static void ahci_start_port(struct ata_port *ap) 835 { 836 struct ahci_host_priv *hpriv = ap->host->private_data; 837 struct ahci_port_priv *pp = ap->private_data; 838 struct ata_link *link; 839 struct ahci_em_priv *emp; 840 ssize_t rc; 841 int i; 842 843 /* enable FIS reception */ 844 ahci_start_fis_rx(ap); 845 846 /* enable DMA */ 847 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE)) 848 hpriv->start_engine(ap); 849 850 /* turn on LEDs */ 851 if (ap->flags & ATA_FLAG_EM) { 852 ata_for_each_link(link, ap, EDGE) { 853 emp = &pp->em_priv[link->pmp]; 854 855 /* EM Transmit bit maybe busy during init */ 856 for (i = 0; i < EM_MAX_RETRY; i++) { 857 rc = ap->ops->transmit_led_message(ap, 858 emp->led_state, 859 4); 860 /* 861 * If busy, give a breather but do not 862 * release EH ownership by using msleep() 863 * instead of ata_msleep(). EM Transmit 864 * bit is busy for the whole host and 865 * releasing ownership will cause other 866 * ports to fail the same way. 867 */ 868 if (rc == -EBUSY) 869 msleep(1); 870 else 871 break; 872 } 873 } 874 } 875 876 if (ap->flags & ATA_FLAG_SW_ACTIVITY) 877 ata_for_each_link(link, ap, EDGE) 878 ahci_init_sw_activity(link); 879 880 } 881 882 static int ahci_deinit_port(struct ata_port *ap, const char **emsg) 883 { 884 int rc; 885 886 /* disable DMA */ 887 rc = ahci_stop_engine(ap); 888 if (rc) { 889 *emsg = "failed to stop engine"; 890 return rc; 891 } 892 893 /* disable FIS reception */ 894 rc = ahci_stop_fis_rx(ap); 895 if (rc) { 896 *emsg = "failed stop FIS RX"; 897 return rc; 898 } 899 900 return 0; 901 } 902 903 int ahci_reset_controller(struct ata_host *host) 904 { 905 struct ahci_host_priv *hpriv = host->private_data; 906 void __iomem *mmio = hpriv->mmio; 907 u32 tmp; 908 909 /* we must be in AHCI mode, before using anything 910 * AHCI-specific, such as HOST_RESET. 911 */ 912 ahci_enable_ahci(mmio); 913 914 /* global controller reset */ 915 if (!ahci_skip_host_reset) { 916 tmp = readl(mmio + HOST_CTL); 917 if ((tmp & HOST_RESET) == 0) { 918 writel(tmp | HOST_RESET, mmio + HOST_CTL); 919 readl(mmio + HOST_CTL); /* flush */ 920 } 921 922 /* 923 * to perform host reset, OS should set HOST_RESET 924 * and poll until this bit is read to be "0". 925 * reset must complete within 1 second, or 926 * the hardware should be considered fried. 927 */ 928 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET, 929 HOST_RESET, 10, 1000); 930 931 if (tmp & HOST_RESET) { 932 dev_err(host->dev, "controller reset failed (0x%x)\n", 933 tmp); 934 return -EIO; 935 } 936 937 /* turn on AHCI mode */ 938 ahci_enable_ahci(mmio); 939 940 /* Some registers might be cleared on reset. Restore 941 * initial values. 942 */ 943 ahci_restore_initial_config(host); 944 } else 945 dev_info(host->dev, "skipping global host reset\n"); 946 947 return 0; 948 } 949 EXPORT_SYMBOL_GPL(ahci_reset_controller); 950 951 static void ahci_sw_activity(struct ata_link *link) 952 { 953 struct ata_port *ap = link->ap; 954 struct ahci_port_priv *pp = ap->private_data; 955 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 956 957 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY)) 958 return; 959 960 emp->activity++; 961 if (!timer_pending(&emp->timer)) 962 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10)); 963 } 964 965 static void ahci_sw_activity_blink(unsigned long arg) 966 { 967 struct ata_link *link = (struct ata_link *)arg; 968 struct ata_port *ap = link->ap; 969 struct ahci_port_priv *pp = ap->private_data; 970 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 971 unsigned long led_message = emp->led_state; 972 u32 activity_led_state; 973 unsigned long flags; 974 975 led_message &= EM_MSG_LED_VALUE; 976 led_message |= ap->port_no | (link->pmp << 8); 977 978 /* check to see if we've had activity. If so, 979 * toggle state of LED and reset timer. If not, 980 * turn LED to desired idle state. 981 */ 982 spin_lock_irqsave(ap->lock, flags); 983 if (emp->saved_activity != emp->activity) { 984 emp->saved_activity = emp->activity; 985 /* get the current LED state */ 986 activity_led_state = led_message & EM_MSG_LED_VALUE_ON; 987 988 if (activity_led_state) 989 activity_led_state = 0; 990 else 991 activity_led_state = 1; 992 993 /* clear old state */ 994 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 995 996 /* toggle state */ 997 led_message |= (activity_led_state << 16); 998 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100)); 999 } else { 1000 /* switch to idle */ 1001 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 1002 if (emp->blink_policy == BLINK_OFF) 1003 led_message |= (1 << 16); 1004 } 1005 spin_unlock_irqrestore(ap->lock, flags); 1006 ap->ops->transmit_led_message(ap, led_message, 4); 1007 } 1008 1009 static void ahci_init_sw_activity(struct ata_link *link) 1010 { 1011 struct ata_port *ap = link->ap; 1012 struct ahci_port_priv *pp = ap->private_data; 1013 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1014 1015 /* init activity stats, setup timer */ 1016 emp->saved_activity = emp->activity = 0; 1017 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link); 1018 1019 /* check our blink policy and set flag for link if it's enabled */ 1020 if (emp->blink_policy) 1021 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1022 } 1023 1024 int ahci_reset_em(struct ata_host *host) 1025 { 1026 struct ahci_host_priv *hpriv = host->private_data; 1027 void __iomem *mmio = hpriv->mmio; 1028 u32 em_ctl; 1029 1030 em_ctl = readl(mmio + HOST_EM_CTL); 1031 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST)) 1032 return -EINVAL; 1033 1034 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL); 1035 return 0; 1036 } 1037 EXPORT_SYMBOL_GPL(ahci_reset_em); 1038 1039 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 1040 ssize_t size) 1041 { 1042 struct ahci_host_priv *hpriv = ap->host->private_data; 1043 struct ahci_port_priv *pp = ap->private_data; 1044 void __iomem *mmio = hpriv->mmio; 1045 u32 em_ctl; 1046 u32 message[] = {0, 0}; 1047 unsigned long flags; 1048 int pmp; 1049 struct ahci_em_priv *emp; 1050 1051 /* get the slot number from the message */ 1052 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1053 if (pmp < EM_MAX_SLOTS) 1054 emp = &pp->em_priv[pmp]; 1055 else 1056 return -EINVAL; 1057 1058 ahci_rpm_get_port(ap); 1059 spin_lock_irqsave(ap->lock, flags); 1060 1061 /* 1062 * if we are still busy transmitting a previous message, 1063 * do not allow 1064 */ 1065 em_ctl = readl(mmio + HOST_EM_CTL); 1066 if (em_ctl & EM_CTL_TM) { 1067 spin_unlock_irqrestore(ap->lock, flags); 1068 ahci_rpm_put_port(ap); 1069 return -EBUSY; 1070 } 1071 1072 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) { 1073 /* 1074 * create message header - this is all zero except for 1075 * the message size, which is 4 bytes. 1076 */ 1077 message[0] |= (4 << 8); 1078 1079 /* ignore 0:4 of byte zero, fill in port info yourself */ 1080 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no); 1081 1082 /* write message to EM_LOC */ 1083 writel(message[0], mmio + hpriv->em_loc); 1084 writel(message[1], mmio + hpriv->em_loc+4); 1085 1086 /* 1087 * tell hardware to transmit the message 1088 */ 1089 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 1090 } 1091 1092 /* save off new led state for port/slot */ 1093 emp->led_state = state; 1094 1095 spin_unlock_irqrestore(ap->lock, flags); 1096 ahci_rpm_put_port(ap); 1097 1098 return size; 1099 } 1100 1101 static ssize_t ahci_led_show(struct ata_port *ap, char *buf) 1102 { 1103 struct ahci_port_priv *pp = ap->private_data; 1104 struct ata_link *link; 1105 struct ahci_em_priv *emp; 1106 int rc = 0; 1107 1108 ata_for_each_link(link, ap, EDGE) { 1109 emp = &pp->em_priv[link->pmp]; 1110 rc += sprintf(buf, "%lx\n", emp->led_state); 1111 } 1112 return rc; 1113 } 1114 1115 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 1116 size_t size) 1117 { 1118 unsigned int state; 1119 int pmp; 1120 struct ahci_port_priv *pp = ap->private_data; 1121 struct ahci_em_priv *emp; 1122 1123 if (kstrtouint(buf, 0, &state) < 0) 1124 return -EINVAL; 1125 1126 /* get the slot number from the message */ 1127 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1128 if (pmp < EM_MAX_SLOTS) 1129 emp = &pp->em_priv[pmp]; 1130 else 1131 return -EINVAL; 1132 1133 /* mask off the activity bits if we are in sw_activity 1134 * mode, user should turn off sw_activity before setting 1135 * activity led through em_message 1136 */ 1137 if (emp->blink_policy) 1138 state &= ~EM_MSG_LED_VALUE_ACTIVITY; 1139 1140 return ap->ops->transmit_led_message(ap, state, size); 1141 } 1142 1143 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val) 1144 { 1145 struct ata_link *link = dev->link; 1146 struct ata_port *ap = link->ap; 1147 struct ahci_port_priv *pp = ap->private_data; 1148 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1149 u32 port_led_state = emp->led_state; 1150 1151 /* save the desired Activity LED behavior */ 1152 if (val == OFF) { 1153 /* clear LFLAG */ 1154 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY); 1155 1156 /* set the LED to OFF */ 1157 port_led_state &= EM_MSG_LED_VALUE_OFF; 1158 port_led_state |= (ap->port_no | (link->pmp << 8)); 1159 ap->ops->transmit_led_message(ap, port_led_state, 4); 1160 } else { 1161 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1162 if (val == BLINK_OFF) { 1163 /* set LED to ON for idle */ 1164 port_led_state &= EM_MSG_LED_VALUE_OFF; 1165 port_led_state |= (ap->port_no | (link->pmp << 8)); 1166 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */ 1167 ap->ops->transmit_led_message(ap, port_led_state, 4); 1168 } 1169 } 1170 emp->blink_policy = val; 1171 return 0; 1172 } 1173 1174 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf) 1175 { 1176 struct ata_link *link = dev->link; 1177 struct ata_port *ap = link->ap; 1178 struct ahci_port_priv *pp = ap->private_data; 1179 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1180 1181 /* display the saved value of activity behavior for this 1182 * disk. 1183 */ 1184 return sprintf(buf, "%d\n", emp->blink_policy); 1185 } 1186 1187 static void ahci_port_init(struct device *dev, struct ata_port *ap, 1188 int port_no, void __iomem *mmio, 1189 void __iomem *port_mmio) 1190 { 1191 struct ahci_host_priv *hpriv = ap->host->private_data; 1192 const char *emsg = NULL; 1193 int rc; 1194 u32 tmp; 1195 1196 /* make sure port is not active */ 1197 rc = ahci_deinit_port(ap, &emsg); 1198 if (rc) 1199 dev_warn(dev, "%s (%d)\n", emsg, rc); 1200 1201 /* clear SError */ 1202 tmp = readl(port_mmio + PORT_SCR_ERR); 1203 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); 1204 writel(tmp, port_mmio + PORT_SCR_ERR); 1205 1206 /* clear port IRQ */ 1207 tmp = readl(port_mmio + PORT_IRQ_STAT); 1208 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 1209 if (tmp) 1210 writel(tmp, port_mmio + PORT_IRQ_STAT); 1211 1212 writel(1 << port_no, mmio + HOST_IRQ_STAT); 1213 1214 /* mark esata ports */ 1215 tmp = readl(port_mmio + PORT_CMD); 1216 if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS)) 1217 ap->pflags |= ATA_PFLAG_EXTERNAL; 1218 } 1219 1220 void ahci_init_controller(struct ata_host *host) 1221 { 1222 struct ahci_host_priv *hpriv = host->private_data; 1223 void __iomem *mmio = hpriv->mmio; 1224 int i; 1225 void __iomem *port_mmio; 1226 u32 tmp; 1227 1228 for (i = 0; i < host->n_ports; i++) { 1229 struct ata_port *ap = host->ports[i]; 1230 1231 port_mmio = ahci_port_base(ap); 1232 if (ata_port_is_dummy(ap)) 1233 continue; 1234 1235 ahci_port_init(host->dev, ap, i, mmio, port_mmio); 1236 } 1237 1238 tmp = readl(mmio + HOST_CTL); 1239 VPRINTK("HOST_CTL 0x%x\n", tmp); 1240 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); 1241 tmp = readl(mmio + HOST_CTL); 1242 VPRINTK("HOST_CTL 0x%x\n", tmp); 1243 } 1244 EXPORT_SYMBOL_GPL(ahci_init_controller); 1245 1246 static void ahci_dev_config(struct ata_device *dev) 1247 { 1248 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data; 1249 1250 if (hpriv->flags & AHCI_HFLAG_SECT255) { 1251 dev->max_sectors = 255; 1252 ata_dev_info(dev, 1253 "SB600 AHCI: limiting to 255 sectors per cmd\n"); 1254 } 1255 } 1256 1257 unsigned int ahci_dev_classify(struct ata_port *ap) 1258 { 1259 void __iomem *port_mmio = ahci_port_base(ap); 1260 struct ata_taskfile tf; 1261 u32 tmp; 1262 1263 tmp = readl(port_mmio + PORT_SIG); 1264 tf.lbah = (tmp >> 24) & 0xff; 1265 tf.lbam = (tmp >> 16) & 0xff; 1266 tf.lbal = (tmp >> 8) & 0xff; 1267 tf.nsect = (tmp) & 0xff; 1268 1269 return ata_dev_classify(&tf); 1270 } 1271 EXPORT_SYMBOL_GPL(ahci_dev_classify); 1272 1273 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 1274 u32 opts) 1275 { 1276 dma_addr_t cmd_tbl_dma; 1277 1278 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; 1279 1280 pp->cmd_slot[tag].opts = cpu_to_le32(opts); 1281 pp->cmd_slot[tag].status = 0; 1282 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); 1283 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); 1284 } 1285 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot); 1286 1287 int ahci_kick_engine(struct ata_port *ap) 1288 { 1289 void __iomem *port_mmio = ahci_port_base(ap); 1290 struct ahci_host_priv *hpriv = ap->host->private_data; 1291 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1292 u32 tmp; 1293 int busy, rc; 1294 1295 /* stop engine */ 1296 rc = ahci_stop_engine(ap); 1297 if (rc) 1298 goto out_restart; 1299 1300 /* need to do CLO? 1301 * always do CLO if PMP is attached (AHCI-1.3 9.2) 1302 */ 1303 busy = status & (ATA_BUSY | ATA_DRQ); 1304 if (!busy && !sata_pmp_attached(ap)) { 1305 rc = 0; 1306 goto out_restart; 1307 } 1308 1309 if (!(hpriv->cap & HOST_CAP_CLO)) { 1310 rc = -EOPNOTSUPP; 1311 goto out_restart; 1312 } 1313 1314 /* perform CLO */ 1315 tmp = readl(port_mmio + PORT_CMD); 1316 tmp |= PORT_CMD_CLO; 1317 writel(tmp, port_mmio + PORT_CMD); 1318 1319 rc = 0; 1320 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 1321 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); 1322 if (tmp & PORT_CMD_CLO) 1323 rc = -EIO; 1324 1325 /* restart engine */ 1326 out_restart: 1327 hpriv->start_engine(ap); 1328 return rc; 1329 } 1330 EXPORT_SYMBOL_GPL(ahci_kick_engine); 1331 1332 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, 1333 struct ata_taskfile *tf, int is_cmd, u16 flags, 1334 unsigned long timeout_msec) 1335 { 1336 const u32 cmd_fis_len = 5; /* five dwords */ 1337 struct ahci_port_priv *pp = ap->private_data; 1338 void __iomem *port_mmio = ahci_port_base(ap); 1339 u8 *fis = pp->cmd_tbl; 1340 u32 tmp; 1341 1342 /* prep the command */ 1343 ata_tf_to_fis(tf, pmp, is_cmd, fis); 1344 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); 1345 1346 /* set port value for softreset of Port Multiplier */ 1347 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) { 1348 tmp = readl(port_mmio + PORT_FBS); 1349 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); 1350 tmp |= pmp << PORT_FBS_DEV_OFFSET; 1351 writel(tmp, port_mmio + PORT_FBS); 1352 pp->fbs_last_dev = pmp; 1353 } 1354 1355 /* issue & wait */ 1356 writel(1, port_mmio + PORT_CMD_ISSUE); 1357 1358 if (timeout_msec) { 1359 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE, 1360 0x1, 0x1, 1, timeout_msec); 1361 if (tmp & 0x1) { 1362 ahci_kick_engine(ap); 1363 return -EBUSY; 1364 } 1365 } else 1366 readl(port_mmio + PORT_CMD_ISSUE); /* flush */ 1367 1368 return 0; 1369 } 1370 1371 int ahci_do_softreset(struct ata_link *link, unsigned int *class, 1372 int pmp, unsigned long deadline, 1373 int (*check_ready)(struct ata_link *link)) 1374 { 1375 struct ata_port *ap = link->ap; 1376 struct ahci_host_priv *hpriv = ap->host->private_data; 1377 struct ahci_port_priv *pp = ap->private_data; 1378 const char *reason = NULL; 1379 unsigned long now, msecs; 1380 struct ata_taskfile tf; 1381 bool fbs_disabled = false; 1382 int rc; 1383 1384 DPRINTK("ENTER\n"); 1385 1386 /* prepare for SRST (AHCI-1.1 10.4.1) */ 1387 rc = ahci_kick_engine(ap); 1388 if (rc && rc != -EOPNOTSUPP) 1389 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc); 1390 1391 /* 1392 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall 1393 * clear PxFBS.EN to '0' prior to issuing software reset to devices 1394 * that is attached to port multiplier. 1395 */ 1396 if (!ata_is_host_link(link) && pp->fbs_enabled) { 1397 ahci_disable_fbs(ap); 1398 fbs_disabled = true; 1399 } 1400 1401 ata_tf_init(link->device, &tf); 1402 1403 /* issue the first D2H Register FIS */ 1404 msecs = 0; 1405 now = jiffies; 1406 if (time_after(deadline, now)) 1407 msecs = jiffies_to_msecs(deadline - now); 1408 1409 tf.ctl |= ATA_SRST; 1410 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, 1411 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { 1412 rc = -EIO; 1413 reason = "1st FIS failed"; 1414 goto fail; 1415 } 1416 1417 /* spec says at least 5us, but be generous and sleep for 1ms */ 1418 ata_msleep(ap, 1); 1419 1420 /* issue the second D2H Register FIS */ 1421 tf.ctl &= ~ATA_SRST; 1422 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); 1423 1424 /* wait for link to become ready */ 1425 rc = ata_wait_after_reset(link, deadline, check_ready); 1426 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) { 1427 /* 1428 * Workaround for cases where link online status can't 1429 * be trusted. Treat device readiness timeout as link 1430 * offline. 1431 */ 1432 ata_link_info(link, "device not ready, treating as offline\n"); 1433 *class = ATA_DEV_NONE; 1434 } else if (rc) { 1435 /* link occupied, -ENODEV too is an error */ 1436 reason = "device not ready"; 1437 goto fail; 1438 } else 1439 *class = ahci_dev_classify(ap); 1440 1441 /* re-enable FBS if disabled before */ 1442 if (fbs_disabled) 1443 ahci_enable_fbs(ap); 1444 1445 DPRINTK("EXIT, class=%u\n", *class); 1446 return 0; 1447 1448 fail: 1449 ata_link_err(link, "softreset failed (%s)\n", reason); 1450 return rc; 1451 } 1452 1453 int ahci_check_ready(struct ata_link *link) 1454 { 1455 void __iomem *port_mmio = ahci_port_base(link->ap); 1456 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1457 1458 return ata_check_ready(status); 1459 } 1460 EXPORT_SYMBOL_GPL(ahci_check_ready); 1461 1462 static int ahci_softreset(struct ata_link *link, unsigned int *class, 1463 unsigned long deadline) 1464 { 1465 int pmp = sata_srst_pmp(link); 1466 1467 DPRINTK("ENTER\n"); 1468 1469 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready); 1470 } 1471 EXPORT_SYMBOL_GPL(ahci_do_softreset); 1472 1473 static int ahci_bad_pmp_check_ready(struct ata_link *link) 1474 { 1475 void __iomem *port_mmio = ahci_port_base(link->ap); 1476 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1477 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT); 1478 1479 /* 1480 * There is no need to check TFDATA if BAD PMP is found due to HW bug, 1481 * which can save timeout delay. 1482 */ 1483 if (irq_status & PORT_IRQ_BAD_PMP) 1484 return -EIO; 1485 1486 return ata_check_ready(status); 1487 } 1488 1489 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class, 1490 unsigned long deadline) 1491 { 1492 struct ata_port *ap = link->ap; 1493 void __iomem *port_mmio = ahci_port_base(ap); 1494 int pmp = sata_srst_pmp(link); 1495 int rc; 1496 u32 irq_sts; 1497 1498 DPRINTK("ENTER\n"); 1499 1500 rc = ahci_do_softreset(link, class, pmp, deadline, 1501 ahci_bad_pmp_check_ready); 1502 1503 /* 1504 * Soft reset fails with IPMS set when PMP is enabled but 1505 * SATA HDD/ODD is connected to SATA port, do soft reset 1506 * again to port 0. 1507 */ 1508 if (rc == -EIO) { 1509 irq_sts = readl(port_mmio + PORT_IRQ_STAT); 1510 if (irq_sts & PORT_IRQ_BAD_PMP) { 1511 ata_link_warn(link, 1512 "applying PMP SRST workaround " 1513 "and retrying\n"); 1514 rc = ahci_do_softreset(link, class, 0, deadline, 1515 ahci_check_ready); 1516 } 1517 } 1518 1519 return rc; 1520 } 1521 1522 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 1523 unsigned long deadline) 1524 { 1525 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 1526 struct ata_port *ap = link->ap; 1527 struct ahci_port_priv *pp = ap->private_data; 1528 struct ahci_host_priv *hpriv = ap->host->private_data; 1529 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 1530 struct ata_taskfile tf; 1531 bool online; 1532 int rc; 1533 1534 DPRINTK("ENTER\n"); 1535 1536 ahci_stop_engine(ap); 1537 1538 /* clear D2H reception area to properly wait for D2H FIS */ 1539 ata_tf_init(link->device, &tf); 1540 tf.command = ATA_BUSY; 1541 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 1542 1543 rc = sata_link_hardreset(link, timing, deadline, &online, 1544 ahci_check_ready); 1545 1546 hpriv->start_engine(ap); 1547 1548 if (online) 1549 *class = ahci_dev_classify(ap); 1550 1551 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 1552 return rc; 1553 } 1554 1555 static void ahci_postreset(struct ata_link *link, unsigned int *class) 1556 { 1557 struct ata_port *ap = link->ap; 1558 void __iomem *port_mmio = ahci_port_base(ap); 1559 u32 new_tmp, tmp; 1560 1561 ata_std_postreset(link, class); 1562 1563 /* Make sure port's ATAPI bit is set appropriately */ 1564 new_tmp = tmp = readl(port_mmio + PORT_CMD); 1565 if (*class == ATA_DEV_ATAPI) 1566 new_tmp |= PORT_CMD_ATAPI; 1567 else 1568 new_tmp &= ~PORT_CMD_ATAPI; 1569 if (new_tmp != tmp) { 1570 writel(new_tmp, port_mmio + PORT_CMD); 1571 readl(port_mmio + PORT_CMD); /* flush */ 1572 } 1573 } 1574 1575 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) 1576 { 1577 struct scatterlist *sg; 1578 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; 1579 unsigned int si; 1580 1581 VPRINTK("ENTER\n"); 1582 1583 /* 1584 * Next, the S/G list. 1585 */ 1586 for_each_sg(qc->sg, sg, qc->n_elem, si) { 1587 dma_addr_t addr = sg_dma_address(sg); 1588 u32 sg_len = sg_dma_len(sg); 1589 1590 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); 1591 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); 1592 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); 1593 } 1594 1595 return si; 1596 } 1597 1598 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc) 1599 { 1600 struct ata_port *ap = qc->ap; 1601 struct ahci_port_priv *pp = ap->private_data; 1602 1603 if (!sata_pmp_attached(ap) || pp->fbs_enabled) 1604 return ata_std_qc_defer(qc); 1605 else 1606 return sata_pmp_qc_defer_cmd_switch(qc); 1607 } 1608 1609 static void ahci_qc_prep(struct ata_queued_cmd *qc) 1610 { 1611 struct ata_port *ap = qc->ap; 1612 struct ahci_port_priv *pp = ap->private_data; 1613 int is_atapi = ata_is_atapi(qc->tf.protocol); 1614 void *cmd_tbl; 1615 u32 opts; 1616 const u32 cmd_fis_len = 5; /* five dwords */ 1617 unsigned int n_elem; 1618 1619 /* 1620 * Fill in command table information. First, the header, 1621 * a SATA Register - Host to Device command FIS. 1622 */ 1623 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; 1624 1625 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); 1626 if (is_atapi) { 1627 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); 1628 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); 1629 } 1630 1631 n_elem = 0; 1632 if (qc->flags & ATA_QCFLAG_DMAMAP) 1633 n_elem = ahci_fill_sg(qc, cmd_tbl); 1634 1635 /* 1636 * Fill in command slot information. 1637 */ 1638 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); 1639 if (qc->tf.flags & ATA_TFLAG_WRITE) 1640 opts |= AHCI_CMD_WRITE; 1641 if (is_atapi) 1642 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; 1643 1644 ahci_fill_cmd_slot(pp, qc->tag, opts); 1645 } 1646 1647 static void ahci_fbs_dec_intr(struct ata_port *ap) 1648 { 1649 struct ahci_port_priv *pp = ap->private_data; 1650 void __iomem *port_mmio = ahci_port_base(ap); 1651 u32 fbs = readl(port_mmio + PORT_FBS); 1652 int retries = 3; 1653 1654 DPRINTK("ENTER\n"); 1655 BUG_ON(!pp->fbs_enabled); 1656 1657 /* time to wait for DEC is not specified by AHCI spec, 1658 * add a retry loop for safety. 1659 */ 1660 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS); 1661 fbs = readl(port_mmio + PORT_FBS); 1662 while ((fbs & PORT_FBS_DEC) && retries--) { 1663 udelay(1); 1664 fbs = readl(port_mmio + PORT_FBS); 1665 } 1666 1667 if (fbs & PORT_FBS_DEC) 1668 dev_err(ap->host->dev, "failed to clear device error\n"); 1669 } 1670 1671 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) 1672 { 1673 struct ahci_host_priv *hpriv = ap->host->private_data; 1674 struct ahci_port_priv *pp = ap->private_data; 1675 struct ata_eh_info *host_ehi = &ap->link.eh_info; 1676 struct ata_link *link = NULL; 1677 struct ata_queued_cmd *active_qc; 1678 struct ata_eh_info *active_ehi; 1679 bool fbs_need_dec = false; 1680 u32 serror; 1681 1682 /* determine active link with error */ 1683 if (pp->fbs_enabled) { 1684 void __iomem *port_mmio = ahci_port_base(ap); 1685 u32 fbs = readl(port_mmio + PORT_FBS); 1686 int pmp = fbs >> PORT_FBS_DWE_OFFSET; 1687 1688 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) { 1689 link = &ap->pmp_link[pmp]; 1690 fbs_need_dec = true; 1691 } 1692 1693 } else 1694 ata_for_each_link(link, ap, EDGE) 1695 if (ata_link_active(link)) 1696 break; 1697 1698 if (!link) 1699 link = &ap->link; 1700 1701 active_qc = ata_qc_from_tag(ap, link->active_tag); 1702 active_ehi = &link->eh_info; 1703 1704 /* record irq stat */ 1705 ata_ehi_clear_desc(host_ehi); 1706 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); 1707 1708 /* AHCI needs SError cleared; otherwise, it might lock up */ 1709 ahci_scr_read(&ap->link, SCR_ERROR, &serror); 1710 ahci_scr_write(&ap->link, SCR_ERROR, serror); 1711 host_ehi->serror |= serror; 1712 1713 /* some controllers set IRQ_IF_ERR on device errors, ignore it */ 1714 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) 1715 irq_stat &= ~PORT_IRQ_IF_ERR; 1716 1717 if (irq_stat & PORT_IRQ_TF_ERR) { 1718 /* If qc is active, charge it; otherwise, the active 1719 * link. There's no active qc on NCQ errors. It will 1720 * be determined by EH by reading log page 10h. 1721 */ 1722 if (active_qc) 1723 active_qc->err_mask |= AC_ERR_DEV; 1724 else 1725 active_ehi->err_mask |= AC_ERR_DEV; 1726 1727 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) 1728 host_ehi->serror &= ~SERR_INTERNAL; 1729 } 1730 1731 if (irq_stat & PORT_IRQ_UNK_FIS) { 1732 u32 *unk = pp->rx_fis + RX_FIS_UNK; 1733 1734 active_ehi->err_mask |= AC_ERR_HSM; 1735 active_ehi->action |= ATA_EH_RESET; 1736 ata_ehi_push_desc(active_ehi, 1737 "unknown FIS %08x %08x %08x %08x" , 1738 unk[0], unk[1], unk[2], unk[3]); 1739 } 1740 1741 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) { 1742 active_ehi->err_mask |= AC_ERR_HSM; 1743 active_ehi->action |= ATA_EH_RESET; 1744 ata_ehi_push_desc(active_ehi, "incorrect PMP"); 1745 } 1746 1747 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { 1748 host_ehi->err_mask |= AC_ERR_HOST_BUS; 1749 host_ehi->action |= ATA_EH_RESET; 1750 ata_ehi_push_desc(host_ehi, "host bus error"); 1751 } 1752 1753 if (irq_stat & PORT_IRQ_IF_ERR) { 1754 if (fbs_need_dec) 1755 active_ehi->err_mask |= AC_ERR_DEV; 1756 else { 1757 host_ehi->err_mask |= AC_ERR_ATA_BUS; 1758 host_ehi->action |= ATA_EH_RESET; 1759 } 1760 1761 ata_ehi_push_desc(host_ehi, "interface fatal error"); 1762 } 1763 1764 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { 1765 ata_ehi_hotplugged(host_ehi); 1766 ata_ehi_push_desc(host_ehi, "%s", 1767 irq_stat & PORT_IRQ_CONNECT ? 1768 "connection status changed" : "PHY RDY changed"); 1769 } 1770 1771 /* okay, let's hand over to EH */ 1772 1773 if (irq_stat & PORT_IRQ_FREEZE) 1774 ata_port_freeze(ap); 1775 else if (fbs_need_dec) { 1776 ata_link_abort(link); 1777 ahci_fbs_dec_intr(ap); 1778 } else 1779 ata_port_abort(ap); 1780 } 1781 1782 static void ahci_handle_port_interrupt(struct ata_port *ap, 1783 void __iomem *port_mmio, u32 status) 1784 { 1785 struct ata_eh_info *ehi = &ap->link.eh_info; 1786 struct ahci_port_priv *pp = ap->private_data; 1787 struct ahci_host_priv *hpriv = ap->host->private_data; 1788 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING); 1789 u32 qc_active = 0; 1790 int rc; 1791 1792 /* ignore BAD_PMP while resetting */ 1793 if (unlikely(resetting)) 1794 status &= ~PORT_IRQ_BAD_PMP; 1795 1796 if (sata_lpm_ignore_phy_events(&ap->link)) { 1797 status &= ~PORT_IRQ_PHYRDY; 1798 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG); 1799 } 1800 1801 if (unlikely(status & PORT_IRQ_ERROR)) { 1802 ahci_error_intr(ap, status); 1803 return; 1804 } 1805 1806 if (status & PORT_IRQ_SDB_FIS) { 1807 /* If SNotification is available, leave notification 1808 * handling to sata_async_notification(). If not, 1809 * emulate it by snooping SDB FIS RX area. 1810 * 1811 * Snooping FIS RX area is probably cheaper than 1812 * poking SNotification but some constrollers which 1813 * implement SNotification, ICH9 for example, don't 1814 * store AN SDB FIS into receive area. 1815 */ 1816 if (hpriv->cap & HOST_CAP_SNTF) 1817 sata_async_notification(ap); 1818 else { 1819 /* If the 'N' bit in word 0 of the FIS is set, 1820 * we just received asynchronous notification. 1821 * Tell libata about it. 1822 * 1823 * Lack of SNotification should not appear in 1824 * ahci 1.2, so the workaround is unnecessary 1825 * when FBS is enabled. 1826 */ 1827 if (pp->fbs_enabled) 1828 WARN_ON_ONCE(1); 1829 else { 1830 const __le32 *f = pp->rx_fis + RX_FIS_SDB; 1831 u32 f0 = le32_to_cpu(f[0]); 1832 if (f0 & (1 << 15)) 1833 sata_async_notification(ap); 1834 } 1835 } 1836 } 1837 1838 /* pp->active_link is not reliable once FBS is enabled, both 1839 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because 1840 * NCQ and non-NCQ commands may be in flight at the same time. 1841 */ 1842 if (pp->fbs_enabled) { 1843 if (ap->qc_active) { 1844 qc_active = readl(port_mmio + PORT_SCR_ACT); 1845 qc_active |= readl(port_mmio + PORT_CMD_ISSUE); 1846 } 1847 } else { 1848 /* pp->active_link is valid iff any command is in flight */ 1849 if (ap->qc_active && pp->active_link->sactive) 1850 qc_active = readl(port_mmio + PORT_SCR_ACT); 1851 else 1852 qc_active = readl(port_mmio + PORT_CMD_ISSUE); 1853 } 1854 1855 1856 rc = ata_qc_complete_multiple(ap, qc_active); 1857 1858 /* while resetting, invalid completions are expected */ 1859 if (unlikely(rc < 0 && !resetting)) { 1860 ehi->err_mask |= AC_ERR_HSM; 1861 ehi->action |= ATA_EH_RESET; 1862 ata_port_freeze(ap); 1863 } 1864 } 1865 1866 static void ahci_port_intr(struct ata_port *ap) 1867 { 1868 void __iomem *port_mmio = ahci_port_base(ap); 1869 u32 status; 1870 1871 status = readl(port_mmio + PORT_IRQ_STAT); 1872 writel(status, port_mmio + PORT_IRQ_STAT); 1873 1874 ahci_handle_port_interrupt(ap, port_mmio, status); 1875 } 1876 1877 static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance) 1878 { 1879 struct ata_port *ap = dev_instance; 1880 void __iomem *port_mmio = ahci_port_base(ap); 1881 u32 status; 1882 1883 VPRINTK("ENTER\n"); 1884 1885 status = readl(port_mmio + PORT_IRQ_STAT); 1886 writel(status, port_mmio + PORT_IRQ_STAT); 1887 1888 spin_lock(ap->lock); 1889 ahci_handle_port_interrupt(ap, port_mmio, status); 1890 spin_unlock(ap->lock); 1891 1892 VPRINTK("EXIT\n"); 1893 1894 return IRQ_HANDLED; 1895 } 1896 1897 u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked) 1898 { 1899 unsigned int i, handled = 0; 1900 1901 for (i = 0; i < host->n_ports; i++) { 1902 struct ata_port *ap; 1903 1904 if (!(irq_masked & (1 << i))) 1905 continue; 1906 1907 ap = host->ports[i]; 1908 if (ap) { 1909 ahci_port_intr(ap); 1910 VPRINTK("port %u\n", i); 1911 } else { 1912 VPRINTK("port %u (no irq)\n", i); 1913 if (ata_ratelimit()) 1914 dev_warn(host->dev, 1915 "interrupt on disabled port %u\n", i); 1916 } 1917 1918 handled = 1; 1919 } 1920 1921 return handled; 1922 } 1923 EXPORT_SYMBOL_GPL(ahci_handle_port_intr); 1924 1925 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance) 1926 { 1927 struct ata_host *host = dev_instance; 1928 struct ahci_host_priv *hpriv; 1929 unsigned int rc = 0; 1930 void __iomem *mmio; 1931 u32 irq_stat, irq_masked; 1932 1933 VPRINTK("ENTER\n"); 1934 1935 hpriv = host->private_data; 1936 mmio = hpriv->mmio; 1937 1938 /* sigh. 0xffffffff is a valid return from h/w */ 1939 irq_stat = readl(mmio + HOST_IRQ_STAT); 1940 if (!irq_stat) 1941 return IRQ_NONE; 1942 1943 irq_masked = irq_stat & hpriv->port_map; 1944 1945 spin_lock(&host->lock); 1946 1947 rc = ahci_handle_port_intr(host, irq_masked); 1948 1949 /* HOST_IRQ_STAT behaves as level triggered latch meaning that 1950 * it should be cleared after all the port events are cleared; 1951 * otherwise, it will raise a spurious interrupt after each 1952 * valid one. Please read section 10.6.2 of ahci 1.1 for more 1953 * information. 1954 * 1955 * Also, use the unmasked value to clear interrupt as spurious 1956 * pending event on a dummy port might cause screaming IRQ. 1957 */ 1958 writel(irq_stat, mmio + HOST_IRQ_STAT); 1959 1960 spin_unlock(&host->lock); 1961 1962 VPRINTK("EXIT\n"); 1963 1964 return IRQ_RETVAL(rc); 1965 } 1966 1967 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) 1968 { 1969 struct ata_port *ap = qc->ap; 1970 void __iomem *port_mmio = ahci_port_base(ap); 1971 struct ahci_port_priv *pp = ap->private_data; 1972 1973 /* Keep track of the currently active link. It will be used 1974 * in completion path to determine whether NCQ phase is in 1975 * progress. 1976 */ 1977 pp->active_link = qc->dev->link; 1978 1979 if (ata_is_ncq(qc->tf.protocol)) 1980 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); 1981 1982 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) { 1983 u32 fbs = readl(port_mmio + PORT_FBS); 1984 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); 1985 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET; 1986 writel(fbs, port_mmio + PORT_FBS); 1987 pp->fbs_last_dev = qc->dev->link->pmp; 1988 } 1989 1990 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); 1991 1992 ahci_sw_activity(qc->dev->link); 1993 1994 return 0; 1995 } 1996 EXPORT_SYMBOL_GPL(ahci_qc_issue); 1997 1998 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc) 1999 { 2000 struct ahci_port_priv *pp = qc->ap->private_data; 2001 u8 *rx_fis = pp->rx_fis; 2002 2003 if (pp->fbs_enabled) 2004 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ; 2005 2006 /* 2007 * After a successful execution of an ATA PIO data-in command, 2008 * the device doesn't send D2H Reg FIS to update the TF and 2009 * the host should take TF and E_Status from the preceding PIO 2010 * Setup FIS. 2011 */ 2012 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE && 2013 !(qc->flags & ATA_QCFLAG_FAILED)) { 2014 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf); 2015 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15]; 2016 } else 2017 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf); 2018 2019 return true; 2020 } 2021 2022 static void ahci_freeze(struct ata_port *ap) 2023 { 2024 void __iomem *port_mmio = ahci_port_base(ap); 2025 2026 /* turn IRQ off */ 2027 writel(0, port_mmio + PORT_IRQ_MASK); 2028 } 2029 2030 static void ahci_thaw(struct ata_port *ap) 2031 { 2032 struct ahci_host_priv *hpriv = ap->host->private_data; 2033 void __iomem *mmio = hpriv->mmio; 2034 void __iomem *port_mmio = ahci_port_base(ap); 2035 u32 tmp; 2036 struct ahci_port_priv *pp = ap->private_data; 2037 2038 /* clear IRQ */ 2039 tmp = readl(port_mmio + PORT_IRQ_STAT); 2040 writel(tmp, port_mmio + PORT_IRQ_STAT); 2041 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); 2042 2043 /* turn IRQ back on */ 2044 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2045 } 2046 2047 void ahci_error_handler(struct ata_port *ap) 2048 { 2049 struct ahci_host_priv *hpriv = ap->host->private_data; 2050 2051 if (!(ap->pflags & ATA_PFLAG_FROZEN)) { 2052 /* restart engine */ 2053 ahci_stop_engine(ap); 2054 hpriv->start_engine(ap); 2055 } 2056 2057 sata_pmp_error_handler(ap); 2058 2059 if (!ata_dev_enabled(ap->link.device)) 2060 ahci_stop_engine(ap); 2061 } 2062 EXPORT_SYMBOL_GPL(ahci_error_handler); 2063 2064 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) 2065 { 2066 struct ata_port *ap = qc->ap; 2067 2068 /* make DMA engine forget about the failed command */ 2069 if (qc->flags & ATA_QCFLAG_FAILED) 2070 ahci_kick_engine(ap); 2071 } 2072 2073 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep) 2074 { 2075 struct ahci_host_priv *hpriv = ap->host->private_data; 2076 void __iomem *port_mmio = ahci_port_base(ap); 2077 struct ata_device *dev = ap->link.device; 2078 u32 devslp, dm, dito, mdat, deto; 2079 int rc; 2080 unsigned int err_mask; 2081 2082 devslp = readl(port_mmio + PORT_DEVSLP); 2083 if (!(devslp & PORT_DEVSLP_DSP)) { 2084 dev_info(ap->host->dev, "port does not support device sleep\n"); 2085 return; 2086 } 2087 2088 /* disable device sleep */ 2089 if (!sleep) { 2090 if (devslp & PORT_DEVSLP_ADSE) { 2091 writel(devslp & ~PORT_DEVSLP_ADSE, 2092 port_mmio + PORT_DEVSLP); 2093 err_mask = ata_dev_set_feature(dev, 2094 SETFEATURES_SATA_DISABLE, 2095 SATA_DEVSLP); 2096 if (err_mask && err_mask != AC_ERR_DEV) 2097 ata_dev_warn(dev, "failed to disable DEVSLP\n"); 2098 } 2099 return; 2100 } 2101 2102 /* device sleep was already enabled */ 2103 if (devslp & PORT_DEVSLP_ADSE) 2104 return; 2105 2106 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */ 2107 rc = ahci_stop_engine(ap); 2108 if (rc) 2109 return; 2110 2111 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET; 2112 dito = devslp_idle_timeout / (dm + 1); 2113 if (dito > 0x3ff) 2114 dito = 0x3ff; 2115 2116 /* Use the nominal value 10 ms if the read MDAT is zero, 2117 * the nominal value of DETO is 20 ms. 2118 */ 2119 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] & 2120 ATA_LOG_DEVSLP_VALID_MASK) { 2121 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] & 2122 ATA_LOG_DEVSLP_MDAT_MASK; 2123 if (!mdat) 2124 mdat = 10; 2125 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO]; 2126 if (!deto) 2127 deto = 20; 2128 } else { 2129 mdat = 10; 2130 deto = 20; 2131 } 2132 2133 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) | 2134 (mdat << PORT_DEVSLP_MDAT_OFFSET) | 2135 (deto << PORT_DEVSLP_DETO_OFFSET) | 2136 PORT_DEVSLP_ADSE); 2137 writel(devslp, port_mmio + PORT_DEVSLP); 2138 2139 hpriv->start_engine(ap); 2140 2141 /* enable device sleep feature for the drive */ 2142 err_mask = ata_dev_set_feature(dev, 2143 SETFEATURES_SATA_ENABLE, 2144 SATA_DEVSLP); 2145 if (err_mask && err_mask != AC_ERR_DEV) 2146 ata_dev_warn(dev, "failed to enable DEVSLP\n"); 2147 } 2148 2149 static void ahci_enable_fbs(struct ata_port *ap) 2150 { 2151 struct ahci_host_priv *hpriv = ap->host->private_data; 2152 struct ahci_port_priv *pp = ap->private_data; 2153 void __iomem *port_mmio = ahci_port_base(ap); 2154 u32 fbs; 2155 int rc; 2156 2157 if (!pp->fbs_supported) 2158 return; 2159 2160 fbs = readl(port_mmio + PORT_FBS); 2161 if (fbs & PORT_FBS_EN) { 2162 pp->fbs_enabled = true; 2163 pp->fbs_last_dev = -1; /* initialization */ 2164 return; 2165 } 2166 2167 rc = ahci_stop_engine(ap); 2168 if (rc) 2169 return; 2170 2171 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS); 2172 fbs = readl(port_mmio + PORT_FBS); 2173 if (fbs & PORT_FBS_EN) { 2174 dev_info(ap->host->dev, "FBS is enabled\n"); 2175 pp->fbs_enabled = true; 2176 pp->fbs_last_dev = -1; /* initialization */ 2177 } else 2178 dev_err(ap->host->dev, "Failed to enable FBS\n"); 2179 2180 hpriv->start_engine(ap); 2181 } 2182 2183 static void ahci_disable_fbs(struct ata_port *ap) 2184 { 2185 struct ahci_host_priv *hpriv = ap->host->private_data; 2186 struct ahci_port_priv *pp = ap->private_data; 2187 void __iomem *port_mmio = ahci_port_base(ap); 2188 u32 fbs; 2189 int rc; 2190 2191 if (!pp->fbs_supported) 2192 return; 2193 2194 fbs = readl(port_mmio + PORT_FBS); 2195 if ((fbs & PORT_FBS_EN) == 0) { 2196 pp->fbs_enabled = false; 2197 return; 2198 } 2199 2200 rc = ahci_stop_engine(ap); 2201 if (rc) 2202 return; 2203 2204 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS); 2205 fbs = readl(port_mmio + PORT_FBS); 2206 if (fbs & PORT_FBS_EN) 2207 dev_err(ap->host->dev, "Failed to disable FBS\n"); 2208 else { 2209 dev_info(ap->host->dev, "FBS is disabled\n"); 2210 pp->fbs_enabled = false; 2211 } 2212 2213 hpriv->start_engine(ap); 2214 } 2215 2216 static void ahci_pmp_attach(struct ata_port *ap) 2217 { 2218 void __iomem *port_mmio = ahci_port_base(ap); 2219 struct ahci_port_priv *pp = ap->private_data; 2220 u32 cmd; 2221 2222 cmd = readl(port_mmio + PORT_CMD); 2223 cmd |= PORT_CMD_PMP; 2224 writel(cmd, port_mmio + PORT_CMD); 2225 2226 ahci_enable_fbs(ap); 2227 2228 pp->intr_mask |= PORT_IRQ_BAD_PMP; 2229 2230 /* 2231 * We must not change the port interrupt mask register if the 2232 * port is marked frozen, the value in pp->intr_mask will be 2233 * restored later when the port is thawed. 2234 * 2235 * Note that during initialization, the port is marked as 2236 * frozen since the irq handler is not yet registered. 2237 */ 2238 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 2239 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2240 } 2241 2242 static void ahci_pmp_detach(struct ata_port *ap) 2243 { 2244 void __iomem *port_mmio = ahci_port_base(ap); 2245 struct ahci_port_priv *pp = ap->private_data; 2246 u32 cmd; 2247 2248 ahci_disable_fbs(ap); 2249 2250 cmd = readl(port_mmio + PORT_CMD); 2251 cmd &= ~PORT_CMD_PMP; 2252 writel(cmd, port_mmio + PORT_CMD); 2253 2254 pp->intr_mask &= ~PORT_IRQ_BAD_PMP; 2255 2256 /* see comment above in ahci_pmp_attach() */ 2257 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 2258 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2259 } 2260 2261 int ahci_port_resume(struct ata_port *ap) 2262 { 2263 ahci_rpm_get_port(ap); 2264 2265 ahci_power_up(ap); 2266 ahci_start_port(ap); 2267 2268 if (sata_pmp_attached(ap)) 2269 ahci_pmp_attach(ap); 2270 else 2271 ahci_pmp_detach(ap); 2272 2273 return 0; 2274 } 2275 EXPORT_SYMBOL_GPL(ahci_port_resume); 2276 2277 #ifdef CONFIG_PM 2278 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) 2279 { 2280 const char *emsg = NULL; 2281 int rc; 2282 2283 rc = ahci_deinit_port(ap, &emsg); 2284 if (rc == 0) 2285 ahci_power_down(ap); 2286 else { 2287 ata_port_err(ap, "%s (%d)\n", emsg, rc); 2288 ata_port_freeze(ap); 2289 } 2290 2291 ahci_rpm_put_port(ap); 2292 return rc; 2293 } 2294 #endif 2295 2296 static int ahci_port_start(struct ata_port *ap) 2297 { 2298 struct ahci_host_priv *hpriv = ap->host->private_data; 2299 struct device *dev = ap->host->dev; 2300 struct ahci_port_priv *pp; 2301 void *mem; 2302 dma_addr_t mem_dma; 2303 size_t dma_sz, rx_fis_sz; 2304 2305 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 2306 if (!pp) 2307 return -ENOMEM; 2308 2309 if (ap->host->n_ports > 1) { 2310 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL); 2311 if (!pp->irq_desc) { 2312 devm_kfree(dev, pp); 2313 return -ENOMEM; 2314 } 2315 snprintf(pp->irq_desc, 8, 2316 "%s%d", dev_driver_string(dev), ap->port_no); 2317 } 2318 2319 /* check FBS capability */ 2320 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) { 2321 void __iomem *port_mmio = ahci_port_base(ap); 2322 u32 cmd = readl(port_mmio + PORT_CMD); 2323 if (cmd & PORT_CMD_FBSCP) 2324 pp->fbs_supported = true; 2325 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) { 2326 dev_info(dev, "port %d can do FBS, forcing FBSCP\n", 2327 ap->port_no); 2328 pp->fbs_supported = true; 2329 } else 2330 dev_warn(dev, "port %d is not capable of FBS\n", 2331 ap->port_no); 2332 } 2333 2334 if (pp->fbs_supported) { 2335 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ; 2336 rx_fis_sz = AHCI_RX_FIS_SZ * 16; 2337 } else { 2338 dma_sz = AHCI_PORT_PRIV_DMA_SZ; 2339 rx_fis_sz = AHCI_RX_FIS_SZ; 2340 } 2341 2342 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL); 2343 if (!mem) 2344 return -ENOMEM; 2345 memset(mem, 0, dma_sz); 2346 2347 /* 2348 * First item in chunk of DMA memory: 32-slot command table, 2349 * 32 bytes each in size 2350 */ 2351 pp->cmd_slot = mem; 2352 pp->cmd_slot_dma = mem_dma; 2353 2354 mem += AHCI_CMD_SLOT_SZ; 2355 mem_dma += AHCI_CMD_SLOT_SZ; 2356 2357 /* 2358 * Second item: Received-FIS area 2359 */ 2360 pp->rx_fis = mem; 2361 pp->rx_fis_dma = mem_dma; 2362 2363 mem += rx_fis_sz; 2364 mem_dma += rx_fis_sz; 2365 2366 /* 2367 * Third item: data area for storing a single command 2368 * and its scatter-gather table 2369 */ 2370 pp->cmd_tbl = mem; 2371 pp->cmd_tbl_dma = mem_dma; 2372 2373 /* 2374 * Save off initial list of interrupts to be enabled. 2375 * This could be changed later 2376 */ 2377 pp->intr_mask = DEF_PORT_IRQ; 2378 2379 /* 2380 * Switch to per-port locking in case each port has its own MSI vector. 2381 */ 2382 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) { 2383 spin_lock_init(&pp->lock); 2384 ap->lock = &pp->lock; 2385 } 2386 2387 ap->private_data = pp; 2388 2389 /* engage engines, captain */ 2390 return ahci_port_resume(ap); 2391 } 2392 2393 static void ahci_port_stop(struct ata_port *ap) 2394 { 2395 const char *emsg = NULL; 2396 struct ahci_host_priv *hpriv = ap->host->private_data; 2397 void __iomem *host_mmio = hpriv->mmio; 2398 int rc; 2399 2400 /* de-initialize port */ 2401 rc = ahci_deinit_port(ap, &emsg); 2402 if (rc) 2403 ata_port_warn(ap, "%s (%d)\n", emsg, rc); 2404 2405 /* 2406 * Clear GHC.IS to prevent stuck INTx after disabling MSI and 2407 * re-enabling INTx. 2408 */ 2409 writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT); 2410 } 2411 2412 void ahci_print_info(struct ata_host *host, const char *scc_s) 2413 { 2414 struct ahci_host_priv *hpriv = host->private_data; 2415 u32 vers, cap, cap2, impl, speed; 2416 const char *speed_s; 2417 2418 vers = hpriv->version; 2419 cap = hpriv->cap; 2420 cap2 = hpriv->cap2; 2421 impl = hpriv->port_map; 2422 2423 speed = (cap >> 20) & 0xf; 2424 if (speed == 1) 2425 speed_s = "1.5"; 2426 else if (speed == 2) 2427 speed_s = "3"; 2428 else if (speed == 3) 2429 speed_s = "6"; 2430 else 2431 speed_s = "?"; 2432 2433 dev_info(host->dev, 2434 "AHCI %02x%02x.%02x%02x " 2435 "%u slots %u ports %s Gbps 0x%x impl %s mode\n" 2436 , 2437 2438 (vers >> 24) & 0xff, 2439 (vers >> 16) & 0xff, 2440 (vers >> 8) & 0xff, 2441 vers & 0xff, 2442 2443 ((cap >> 8) & 0x1f) + 1, 2444 (cap & 0x1f) + 1, 2445 speed_s, 2446 impl, 2447 scc_s); 2448 2449 dev_info(host->dev, 2450 "flags: " 2451 "%s%s%s%s%s%s%s" 2452 "%s%s%s%s%s%s%s" 2453 "%s%s%s%s%s%s%s" 2454 "%s%s\n" 2455 , 2456 2457 cap & HOST_CAP_64 ? "64bit " : "", 2458 cap & HOST_CAP_NCQ ? "ncq " : "", 2459 cap & HOST_CAP_SNTF ? "sntf " : "", 2460 cap & HOST_CAP_MPS ? "ilck " : "", 2461 cap & HOST_CAP_SSS ? "stag " : "", 2462 cap & HOST_CAP_ALPM ? "pm " : "", 2463 cap & HOST_CAP_LED ? "led " : "", 2464 cap & HOST_CAP_CLO ? "clo " : "", 2465 cap & HOST_CAP_ONLY ? "only " : "", 2466 cap & HOST_CAP_PMP ? "pmp " : "", 2467 cap & HOST_CAP_FBS ? "fbs " : "", 2468 cap & HOST_CAP_PIO_MULTI ? "pio " : "", 2469 cap & HOST_CAP_SSC ? "slum " : "", 2470 cap & HOST_CAP_PART ? "part " : "", 2471 cap & HOST_CAP_CCC ? "ccc " : "", 2472 cap & HOST_CAP_EMS ? "ems " : "", 2473 cap & HOST_CAP_SXS ? "sxs " : "", 2474 cap2 & HOST_CAP2_DESO ? "deso " : "", 2475 cap2 & HOST_CAP2_SADM ? "sadm " : "", 2476 cap2 & HOST_CAP2_SDS ? "sds " : "", 2477 cap2 & HOST_CAP2_APST ? "apst " : "", 2478 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "", 2479 cap2 & HOST_CAP2_BOH ? "boh " : "" 2480 ); 2481 } 2482 EXPORT_SYMBOL_GPL(ahci_print_info); 2483 2484 void ahci_set_em_messages(struct ahci_host_priv *hpriv, 2485 struct ata_port_info *pi) 2486 { 2487 u8 messages; 2488 void __iomem *mmio = hpriv->mmio; 2489 u32 em_loc = readl(mmio + HOST_EM_LOC); 2490 u32 em_ctl = readl(mmio + HOST_EM_CTL); 2491 2492 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS)) 2493 return; 2494 2495 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16; 2496 2497 if (messages) { 2498 /* store em_loc */ 2499 hpriv->em_loc = ((em_loc >> 16) * 4); 2500 hpriv->em_buf_sz = ((em_loc & 0xff) * 4); 2501 hpriv->em_msg_type = messages; 2502 pi->flags |= ATA_FLAG_EM; 2503 if (!(em_ctl & EM_CTL_ALHD)) 2504 pi->flags |= ATA_FLAG_SW_ACTIVITY; 2505 } 2506 } 2507 EXPORT_SYMBOL_GPL(ahci_set_em_messages); 2508 2509 static int ahci_host_activate_multi_irqs(struct ata_host *host, 2510 struct scsi_host_template *sht) 2511 { 2512 struct ahci_host_priv *hpriv = host->private_data; 2513 int i, rc; 2514 2515 rc = ata_host_start(host); 2516 if (rc) 2517 return rc; 2518 /* 2519 * Requests IRQs according to AHCI-1.1 when multiple MSIs were 2520 * allocated. That is one MSI per port, starting from @irq. 2521 */ 2522 for (i = 0; i < host->n_ports; i++) { 2523 struct ahci_port_priv *pp = host->ports[i]->private_data; 2524 int irq = hpriv->get_irq_vector(host, i); 2525 2526 /* Do not receive interrupts sent by dummy ports */ 2527 if (!pp) { 2528 disable_irq(irq); 2529 continue; 2530 } 2531 2532 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard, 2533 0, pp->irq_desc, host->ports[i]); 2534 2535 if (rc) 2536 return rc; 2537 ata_port_desc(host->ports[i], "irq %d", irq); 2538 } 2539 2540 return ata_host_register(host, sht); 2541 } 2542 2543 /** 2544 * ahci_host_activate - start AHCI host, request IRQs and register it 2545 * @host: target ATA host 2546 * @sht: scsi_host_template to use when registering the host 2547 * 2548 * LOCKING: 2549 * Inherited from calling layer (may sleep). 2550 * 2551 * RETURNS: 2552 * 0 on success, -errno otherwise. 2553 */ 2554 int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht) 2555 { 2556 struct ahci_host_priv *hpriv = host->private_data; 2557 int irq = hpriv->irq; 2558 int rc; 2559 2560 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) { 2561 if (hpriv->irq_handler) 2562 dev_warn(host->dev, 2563 "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n"); 2564 if (!hpriv->get_irq_vector) { 2565 dev_err(host->dev, 2566 "AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n"); 2567 return -EIO; 2568 } 2569 2570 rc = ahci_host_activate_multi_irqs(host, sht); 2571 } else { 2572 rc = ata_host_activate(host, irq, hpriv->irq_handler, 2573 IRQF_SHARED, sht); 2574 } 2575 2576 2577 return rc; 2578 } 2579 EXPORT_SYMBOL_GPL(ahci_host_activate); 2580 2581 MODULE_AUTHOR("Jeff Garzik"); 2582 MODULE_DESCRIPTION("Common AHCI SATA low-level routines"); 2583 MODULE_LICENSE("GPL"); 2584