1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * libahci.c - Common AHCI SATA low-level routines 4 * 5 * Maintained by: Tejun Heo <tj@kernel.org> 6 * Please ALWAYS copy linux-ide@vger.kernel.org 7 * on emails. 8 * 9 * Copyright 2004-2005 Red Hat, Inc. 10 * 11 * libata documentation is available via 'make {ps|pdf}docs', 12 * as Documentation/driver-api/libata.rst 13 * 14 * AHCI hardware documentation: 15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 17 */ 18 19 #include <linux/bitops.h> 20 #include <linux/kernel.h> 21 #include <linux/gfp.h> 22 #include <linux/module.h> 23 #include <linux/nospec.h> 24 #include <linux/blkdev.h> 25 #include <linux/delay.h> 26 #include <linux/interrupt.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/device.h> 29 #include <scsi/scsi_host.h> 30 #include <scsi/scsi_cmnd.h> 31 #include <linux/libata.h> 32 #include <linux/pci.h> 33 #include "ahci.h" 34 #include "libata.h" 35 36 static int ahci_skip_host_reset; 37 int ahci_ignore_sss; 38 EXPORT_SYMBOL_GPL(ahci_ignore_sss); 39 40 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); 41 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); 42 43 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444); 44 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)"); 45 46 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 47 unsigned hints); 48 static ssize_t ahci_led_show(struct ata_port *ap, char *buf); 49 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 50 size_t size); 51 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 52 ssize_t size); 53 54 55 56 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); 57 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); 58 static void ahci_qc_fill_rtf(struct ata_queued_cmd *qc); 59 static void ahci_qc_ncq_fill_rtf(struct ata_port *ap, u64 done_mask); 60 static int ahci_port_start(struct ata_port *ap); 61 static void ahci_port_stop(struct ata_port *ap); 62 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc); 63 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc); 64 static void ahci_freeze(struct ata_port *ap); 65 static void ahci_thaw(struct ata_port *ap); 66 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep); 67 static void ahci_enable_fbs(struct ata_port *ap); 68 static void ahci_disable_fbs(struct ata_port *ap); 69 static void ahci_pmp_attach(struct ata_port *ap); 70 static void ahci_pmp_detach(struct ata_port *ap); 71 static int ahci_softreset(struct ata_link *link, unsigned int *class, 72 unsigned long deadline); 73 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class, 74 unsigned long deadline); 75 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 76 unsigned long deadline); 77 static void ahci_postreset(struct ata_link *link, unsigned int *class); 78 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); 79 static void ahci_dev_config(struct ata_device *dev); 80 #ifdef CONFIG_PM 81 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); 82 #endif 83 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf); 84 static ssize_t ahci_activity_store(struct ata_device *dev, 85 enum sw_activity val); 86 static void ahci_init_sw_activity(struct ata_link *link); 87 88 static ssize_t ahci_show_host_caps(struct device *dev, 89 struct device_attribute *attr, char *buf); 90 static ssize_t ahci_show_host_cap2(struct device *dev, 91 struct device_attribute *attr, char *buf); 92 static ssize_t ahci_show_host_version(struct device *dev, 93 struct device_attribute *attr, char *buf); 94 static ssize_t ahci_show_port_cmd(struct device *dev, 95 struct device_attribute *attr, char *buf); 96 static ssize_t ahci_read_em_buffer(struct device *dev, 97 struct device_attribute *attr, char *buf); 98 static ssize_t ahci_store_em_buffer(struct device *dev, 99 struct device_attribute *attr, 100 const char *buf, size_t size); 101 static ssize_t ahci_show_em_supported(struct device *dev, 102 struct device_attribute *attr, char *buf); 103 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance); 104 105 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL); 106 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL); 107 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL); 108 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL); 109 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO, 110 ahci_read_em_buffer, ahci_store_em_buffer); 111 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL); 112 113 static struct attribute *ahci_shost_attrs[] = { 114 &dev_attr_link_power_management_policy.attr, 115 &dev_attr_em_message_type.attr, 116 &dev_attr_em_message.attr, 117 &dev_attr_ahci_host_caps.attr, 118 &dev_attr_ahci_host_cap2.attr, 119 &dev_attr_ahci_host_version.attr, 120 &dev_attr_ahci_port_cmd.attr, 121 &dev_attr_em_buffer.attr, 122 &dev_attr_em_message_supported.attr, 123 NULL 124 }; 125 126 static const struct attribute_group ahci_shost_attr_group = { 127 .attrs = ahci_shost_attrs 128 }; 129 130 const struct attribute_group *ahci_shost_groups[] = { 131 &ahci_shost_attr_group, 132 NULL 133 }; 134 EXPORT_SYMBOL_GPL(ahci_shost_groups); 135 136 static struct attribute *ahci_sdev_attrs[] = { 137 &dev_attr_sw_activity.attr, 138 &dev_attr_unload_heads.attr, 139 &dev_attr_ncq_prio_supported.attr, 140 &dev_attr_ncq_prio_enable.attr, 141 NULL 142 }; 143 144 static const struct attribute_group ahci_sdev_attr_group = { 145 .attrs = ahci_sdev_attrs 146 }; 147 148 const struct attribute_group *ahci_sdev_groups[] = { 149 &ahci_sdev_attr_group, 150 NULL 151 }; 152 EXPORT_SYMBOL_GPL(ahci_sdev_groups); 153 154 struct ata_port_operations ahci_ops = { 155 .inherits = &sata_pmp_port_ops, 156 157 .qc_defer = ahci_pmp_qc_defer, 158 .qc_prep = ahci_qc_prep, 159 .qc_issue = ahci_qc_issue, 160 .qc_fill_rtf = ahci_qc_fill_rtf, 161 .qc_ncq_fill_rtf = ahci_qc_ncq_fill_rtf, 162 163 .freeze = ahci_freeze, 164 .thaw = ahci_thaw, 165 .softreset = ahci_softreset, 166 .hardreset = ahci_hardreset, 167 .postreset = ahci_postreset, 168 .pmp_softreset = ahci_softreset, 169 .error_handler = ahci_error_handler, 170 .post_internal_cmd = ahci_post_internal_cmd, 171 .dev_config = ahci_dev_config, 172 173 .scr_read = ahci_scr_read, 174 .scr_write = ahci_scr_write, 175 .pmp_attach = ahci_pmp_attach, 176 .pmp_detach = ahci_pmp_detach, 177 178 .set_lpm = ahci_set_lpm, 179 .em_show = ahci_led_show, 180 .em_store = ahci_led_store, 181 .sw_activity_show = ahci_activity_show, 182 .sw_activity_store = ahci_activity_store, 183 .transmit_led_message = ahci_transmit_led_message, 184 #ifdef CONFIG_PM 185 .port_suspend = ahci_port_suspend, 186 .port_resume = ahci_port_resume, 187 #endif 188 .port_start = ahci_port_start, 189 .port_stop = ahci_port_stop, 190 }; 191 EXPORT_SYMBOL_GPL(ahci_ops); 192 193 struct ata_port_operations ahci_pmp_retry_srst_ops = { 194 .inherits = &ahci_ops, 195 .softreset = ahci_pmp_retry_softreset, 196 }; 197 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops); 198 199 static bool ahci_em_messages __read_mostly = true; 200 module_param(ahci_em_messages, bool, 0444); 201 /* add other LED protocol types when they become supported */ 202 MODULE_PARM_DESC(ahci_em_messages, 203 "AHCI Enclosure Management Message control (0 = off, 1 = on)"); 204 205 /* device sleep idle timeout in ms */ 206 static int devslp_idle_timeout __read_mostly = 1000; 207 module_param(devslp_idle_timeout, int, 0644); 208 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout"); 209 210 static void ahci_enable_ahci(void __iomem *mmio) 211 { 212 int i; 213 u32 tmp; 214 215 /* turn on AHCI_EN */ 216 tmp = readl(mmio + HOST_CTL); 217 if (tmp & HOST_AHCI_EN) 218 return; 219 220 /* Some controllers need AHCI_EN to be written multiple times. 221 * Try a few times before giving up. 222 */ 223 for (i = 0; i < 5; i++) { 224 tmp |= HOST_AHCI_EN; 225 writel(tmp, mmio + HOST_CTL); 226 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ 227 if (tmp & HOST_AHCI_EN) 228 return; 229 msleep(10); 230 } 231 232 WARN_ON(1); 233 } 234 235 /** 236 * ahci_rpm_get_port - Make sure the port is powered on 237 * @ap: Port to power on 238 * 239 * Whenever there is need to access the AHCI host registers outside of 240 * normal execution paths, call this function to make sure the host is 241 * actually powered on. 242 */ 243 static int ahci_rpm_get_port(struct ata_port *ap) 244 { 245 return pm_runtime_get_sync(ap->dev); 246 } 247 248 /** 249 * ahci_rpm_put_port - Undoes ahci_rpm_get_port() 250 * @ap: Port to power down 251 * 252 * Undoes ahci_rpm_get_port() and possibly powers down the AHCI host 253 * if it has no more active users. 254 */ 255 static void ahci_rpm_put_port(struct ata_port *ap) 256 { 257 pm_runtime_put(ap->dev); 258 } 259 260 static ssize_t ahci_show_host_caps(struct device *dev, 261 struct device_attribute *attr, char *buf) 262 { 263 struct Scsi_Host *shost = class_to_shost(dev); 264 struct ata_port *ap = ata_shost_to_port(shost); 265 struct ahci_host_priv *hpriv = ap->host->private_data; 266 267 return sprintf(buf, "%x\n", hpriv->cap); 268 } 269 270 static ssize_t ahci_show_host_cap2(struct device *dev, 271 struct device_attribute *attr, char *buf) 272 { 273 struct Scsi_Host *shost = class_to_shost(dev); 274 struct ata_port *ap = ata_shost_to_port(shost); 275 struct ahci_host_priv *hpriv = ap->host->private_data; 276 277 return sprintf(buf, "%x\n", hpriv->cap2); 278 } 279 280 static ssize_t ahci_show_host_version(struct device *dev, 281 struct device_attribute *attr, char *buf) 282 { 283 struct Scsi_Host *shost = class_to_shost(dev); 284 struct ata_port *ap = ata_shost_to_port(shost); 285 struct ahci_host_priv *hpriv = ap->host->private_data; 286 287 return sprintf(buf, "%x\n", hpriv->version); 288 } 289 290 static ssize_t ahci_show_port_cmd(struct device *dev, 291 struct device_attribute *attr, char *buf) 292 { 293 struct Scsi_Host *shost = class_to_shost(dev); 294 struct ata_port *ap = ata_shost_to_port(shost); 295 void __iomem *port_mmio = ahci_port_base(ap); 296 ssize_t ret; 297 298 ahci_rpm_get_port(ap); 299 ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD)); 300 ahci_rpm_put_port(ap); 301 302 return ret; 303 } 304 305 static ssize_t ahci_read_em_buffer(struct device *dev, 306 struct device_attribute *attr, char *buf) 307 { 308 struct Scsi_Host *shost = class_to_shost(dev); 309 struct ata_port *ap = ata_shost_to_port(shost); 310 struct ahci_host_priv *hpriv = ap->host->private_data; 311 void __iomem *mmio = hpriv->mmio; 312 void __iomem *em_mmio = mmio + hpriv->em_loc; 313 u32 em_ctl, msg; 314 unsigned long flags; 315 size_t count; 316 int i; 317 318 ahci_rpm_get_port(ap); 319 spin_lock_irqsave(ap->lock, flags); 320 321 em_ctl = readl(mmio + HOST_EM_CTL); 322 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT || 323 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) { 324 spin_unlock_irqrestore(ap->lock, flags); 325 ahci_rpm_put_port(ap); 326 return -EINVAL; 327 } 328 329 if (!(em_ctl & EM_CTL_MR)) { 330 spin_unlock_irqrestore(ap->lock, flags); 331 ahci_rpm_put_port(ap); 332 return -EAGAIN; 333 } 334 335 if (!(em_ctl & EM_CTL_SMB)) 336 em_mmio += hpriv->em_buf_sz; 337 338 count = hpriv->em_buf_sz; 339 340 /* the count should not be larger than PAGE_SIZE */ 341 if (count > PAGE_SIZE) { 342 if (printk_ratelimit()) 343 ata_port_warn(ap, 344 "EM read buffer size too large: " 345 "buffer size %u, page size %lu\n", 346 hpriv->em_buf_sz, PAGE_SIZE); 347 count = PAGE_SIZE; 348 } 349 350 for (i = 0; i < count; i += 4) { 351 msg = readl(em_mmio + i); 352 buf[i] = msg & 0xff; 353 buf[i + 1] = (msg >> 8) & 0xff; 354 buf[i + 2] = (msg >> 16) & 0xff; 355 buf[i + 3] = (msg >> 24) & 0xff; 356 } 357 358 spin_unlock_irqrestore(ap->lock, flags); 359 ahci_rpm_put_port(ap); 360 361 return i; 362 } 363 364 static ssize_t ahci_store_em_buffer(struct device *dev, 365 struct device_attribute *attr, 366 const char *buf, size_t size) 367 { 368 struct Scsi_Host *shost = class_to_shost(dev); 369 struct ata_port *ap = ata_shost_to_port(shost); 370 struct ahci_host_priv *hpriv = ap->host->private_data; 371 void __iomem *mmio = hpriv->mmio; 372 void __iomem *em_mmio = mmio + hpriv->em_loc; 373 const unsigned char *msg_buf = buf; 374 u32 em_ctl, msg; 375 unsigned long flags; 376 int i; 377 378 /* check size validity */ 379 if (!(ap->flags & ATA_FLAG_EM) || 380 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) || 381 size % 4 || size > hpriv->em_buf_sz) 382 return -EINVAL; 383 384 ahci_rpm_get_port(ap); 385 spin_lock_irqsave(ap->lock, flags); 386 387 em_ctl = readl(mmio + HOST_EM_CTL); 388 if (em_ctl & EM_CTL_TM) { 389 spin_unlock_irqrestore(ap->lock, flags); 390 ahci_rpm_put_port(ap); 391 return -EBUSY; 392 } 393 394 for (i = 0; i < size; i += 4) { 395 msg = msg_buf[i] | msg_buf[i + 1] << 8 | 396 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24; 397 writel(msg, em_mmio + i); 398 } 399 400 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 401 402 spin_unlock_irqrestore(ap->lock, flags); 403 ahci_rpm_put_port(ap); 404 405 return size; 406 } 407 408 static ssize_t ahci_show_em_supported(struct device *dev, 409 struct device_attribute *attr, char *buf) 410 { 411 struct Scsi_Host *shost = class_to_shost(dev); 412 struct ata_port *ap = ata_shost_to_port(shost); 413 struct ahci_host_priv *hpriv = ap->host->private_data; 414 void __iomem *mmio = hpriv->mmio; 415 u32 em_ctl; 416 417 ahci_rpm_get_port(ap); 418 em_ctl = readl(mmio + HOST_EM_CTL); 419 ahci_rpm_put_port(ap); 420 421 return sprintf(buf, "%s%s%s%s\n", 422 em_ctl & EM_CTL_LED ? "led " : "", 423 em_ctl & EM_CTL_SAFTE ? "saf-te " : "", 424 em_ctl & EM_CTL_SES ? "ses-2 " : "", 425 em_ctl & EM_CTL_SGPIO ? "sgpio " : ""); 426 } 427 428 /** 429 * ahci_save_initial_config - Save and fixup initial config values 430 * @dev: target AHCI device 431 * @hpriv: host private area to store config values 432 * 433 * Some registers containing configuration info might be setup by 434 * BIOS and might be cleared on reset. This function saves the 435 * initial values of those registers into @hpriv such that they 436 * can be restored after controller reset. 437 * 438 * If inconsistent, config values are fixed up by this function. 439 * 440 * If it is not set already this function sets hpriv->start_engine to 441 * ahci_start_engine. 442 * 443 * LOCKING: 444 * None. 445 */ 446 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv) 447 { 448 void __iomem *mmio = hpriv->mmio; 449 void __iomem *port_mmio; 450 unsigned long port_map; 451 u32 cap, cap2, vers; 452 int i; 453 454 /* make sure AHCI mode is enabled before accessing CAP */ 455 ahci_enable_ahci(mmio); 456 457 /* 458 * Values prefixed with saved_ are written back to the HBA and ports 459 * registers after reset. Values without are used for driver operation. 460 */ 461 462 /* 463 * Override HW-init HBA capability fields with the platform-specific 464 * values. The rest of the HBA capabilities are defined as Read-only 465 * and can't be modified in CSR anyway. 466 */ 467 cap = readl(mmio + HOST_CAP); 468 if (hpriv->saved_cap) 469 cap = (cap & ~(HOST_CAP_SSS | HOST_CAP_MPS)) | hpriv->saved_cap; 470 hpriv->saved_cap = cap; 471 472 /* CAP2 register is only defined for AHCI 1.2 and later */ 473 vers = readl(mmio + HOST_VERSION); 474 if ((vers >> 16) > 1 || 475 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200)) 476 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2); 477 else 478 hpriv->saved_cap2 = cap2 = 0; 479 480 /* some chips have errata preventing 64bit use */ 481 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { 482 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n"); 483 cap &= ~HOST_CAP_64; 484 } 485 486 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { 487 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n"); 488 cap &= ~HOST_CAP_NCQ; 489 } 490 491 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) { 492 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n"); 493 cap |= HOST_CAP_NCQ; 494 } 495 496 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { 497 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n"); 498 cap &= ~HOST_CAP_PMP; 499 } 500 501 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) { 502 dev_info(dev, 503 "controller can't do SNTF, turning off CAP_SNTF\n"); 504 cap &= ~HOST_CAP_SNTF; 505 } 506 507 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) { 508 dev_info(dev, 509 "controller can't do DEVSLP, turning off\n"); 510 cap2 &= ~HOST_CAP2_SDS; 511 cap2 &= ~HOST_CAP2_SADM; 512 } 513 514 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) { 515 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n"); 516 cap |= HOST_CAP_FBS; 517 } 518 519 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) { 520 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n"); 521 cap &= ~HOST_CAP_FBS; 522 } 523 524 if (!(cap & HOST_CAP_ALPM) && (hpriv->flags & AHCI_HFLAG_YES_ALPM)) { 525 dev_info(dev, "controller can do ALPM, turning on CAP_ALPM\n"); 526 cap |= HOST_CAP_ALPM; 527 } 528 529 if ((cap & HOST_CAP_SXS) && (hpriv->flags & AHCI_HFLAG_NO_SXS)) { 530 dev_info(dev, "controller does not support SXS, disabling CAP_SXS\n"); 531 cap &= ~HOST_CAP_SXS; 532 } 533 534 /* Override the HBA ports mapping if the platform needs it */ 535 port_map = readl(mmio + HOST_PORTS_IMPL); 536 if (hpriv->saved_port_map && port_map != hpriv->saved_port_map) { 537 dev_info(dev, "forcing port_map 0x%lx -> 0x%x\n", 538 port_map, hpriv->saved_port_map); 539 port_map = hpriv->saved_port_map; 540 } else { 541 hpriv->saved_port_map = port_map; 542 } 543 544 if (hpriv->mask_port_map) { 545 dev_warn(dev, "masking port_map 0x%lx -> 0x%lx\n", 546 port_map, 547 port_map & hpriv->mask_port_map); 548 port_map &= hpriv->mask_port_map; 549 } 550 551 /* cross check port_map and cap.n_ports */ 552 if (port_map) { 553 int map_ports = 0; 554 555 for (i = 0; i < AHCI_MAX_PORTS; i++) 556 if (port_map & (1 << i)) 557 map_ports++; 558 559 /* If PI has more ports than n_ports, whine, clear 560 * port_map and let it be generated from n_ports. 561 */ 562 if (map_ports > ahci_nr_ports(cap)) { 563 dev_warn(dev, 564 "implemented port map (0x%lx) contains more ports than nr_ports (%u), using nr_ports\n", 565 port_map, ahci_nr_ports(cap)); 566 port_map = 0; 567 } 568 } 569 570 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */ 571 if (!port_map && vers < 0x10300) { 572 port_map = (1 << ahci_nr_ports(cap)) - 1; 573 dev_warn(dev, "forcing PORTS_IMPL to 0x%lx\n", port_map); 574 575 /* write the fixed up value to the PI register */ 576 hpriv->saved_port_map = port_map; 577 } 578 579 /* 580 * Preserve the ports capabilities defined by the platform. Note there 581 * is no need in storing the rest of the P#.CMD fields since they are 582 * volatile. 583 */ 584 for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) { 585 if (hpriv->saved_port_cap[i]) 586 continue; 587 588 port_mmio = __ahci_port_base(hpriv, i); 589 hpriv->saved_port_cap[i] = 590 readl(port_mmio + PORT_CMD) & PORT_CMD_CAP; 591 } 592 593 /* record values to use during operation */ 594 hpriv->cap = cap; 595 hpriv->cap2 = cap2; 596 hpriv->version = vers; 597 hpriv->port_map = port_map; 598 599 if (!hpriv->start_engine) 600 hpriv->start_engine = ahci_start_engine; 601 602 if (!hpriv->stop_engine) 603 hpriv->stop_engine = ahci_stop_engine; 604 605 if (!hpriv->irq_handler) 606 hpriv->irq_handler = ahci_single_level_irq_intr; 607 } 608 EXPORT_SYMBOL_GPL(ahci_save_initial_config); 609 610 /** 611 * ahci_restore_initial_config - Restore initial config 612 * @host: target ATA host 613 * 614 * Restore initial config stored by ahci_save_initial_config(). 615 * 616 * LOCKING: 617 * None. 618 */ 619 static void ahci_restore_initial_config(struct ata_host *host) 620 { 621 struct ahci_host_priv *hpriv = host->private_data; 622 unsigned long port_map = hpriv->port_map; 623 void __iomem *mmio = hpriv->mmio; 624 void __iomem *port_mmio; 625 int i; 626 627 writel(hpriv->saved_cap, mmio + HOST_CAP); 628 if (hpriv->saved_cap2) 629 writel(hpriv->saved_cap2, mmio + HOST_CAP2); 630 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); 631 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ 632 633 for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) { 634 port_mmio = __ahci_port_base(hpriv, i); 635 writel(hpriv->saved_port_cap[i], port_mmio + PORT_CMD); 636 } 637 } 638 639 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) 640 { 641 static const int offset[] = { 642 [SCR_STATUS] = PORT_SCR_STAT, 643 [SCR_CONTROL] = PORT_SCR_CTL, 644 [SCR_ERROR] = PORT_SCR_ERR, 645 [SCR_ACTIVE] = PORT_SCR_ACT, 646 [SCR_NOTIFICATION] = PORT_SCR_NTF, 647 }; 648 struct ahci_host_priv *hpriv = ap->host->private_data; 649 650 if (sc_reg < ARRAY_SIZE(offset) && 651 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) 652 return offset[sc_reg]; 653 return 0; 654 } 655 656 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) 657 { 658 void __iomem *port_mmio = ahci_port_base(link->ap); 659 int offset = ahci_scr_offset(link->ap, sc_reg); 660 661 if (offset) { 662 *val = readl(port_mmio + offset); 663 return 0; 664 } 665 return -EINVAL; 666 } 667 668 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) 669 { 670 void __iomem *port_mmio = ahci_port_base(link->ap); 671 int offset = ahci_scr_offset(link->ap, sc_reg); 672 673 if (offset) { 674 writel(val, port_mmio + offset); 675 return 0; 676 } 677 return -EINVAL; 678 } 679 680 void ahci_start_engine(struct ata_port *ap) 681 { 682 void __iomem *port_mmio = ahci_port_base(ap); 683 u32 tmp; 684 685 /* start DMA */ 686 tmp = readl(port_mmio + PORT_CMD); 687 tmp |= PORT_CMD_START; 688 writel(tmp, port_mmio + PORT_CMD); 689 readl(port_mmio + PORT_CMD); /* flush */ 690 } 691 EXPORT_SYMBOL_GPL(ahci_start_engine); 692 693 int ahci_stop_engine(struct ata_port *ap) 694 { 695 void __iomem *port_mmio = ahci_port_base(ap); 696 struct ahci_host_priv *hpriv = ap->host->private_data; 697 u32 tmp; 698 699 /* 700 * On some controllers, stopping a port's DMA engine while the port 701 * is in ALPM state (partial or slumber) results in failures on 702 * subsequent DMA engine starts. For those controllers, put the 703 * port back in active state before stopping its DMA engine. 704 */ 705 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) && 706 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) && 707 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) { 708 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n"); 709 return -EIO; 710 } 711 712 tmp = readl(port_mmio + PORT_CMD); 713 714 /* check if the HBA is idle */ 715 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) 716 return 0; 717 718 /* 719 * Don't try to issue commands but return with ENODEV if the 720 * AHCI controller not available anymore (e.g. due to PCIe hot 721 * unplugging). Otherwise a 500ms delay for each port is added. 722 */ 723 if (tmp == 0xffffffff) { 724 dev_err(ap->host->dev, "AHCI controller unavailable!\n"); 725 return -ENODEV; 726 } 727 728 /* setting HBA to idle */ 729 tmp &= ~PORT_CMD_START; 730 writel(tmp, port_mmio + PORT_CMD); 731 732 /* wait for engine to stop. This could be as long as 500 msec */ 733 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 734 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); 735 if (tmp & PORT_CMD_LIST_ON) 736 return -EIO; 737 738 return 0; 739 } 740 EXPORT_SYMBOL_GPL(ahci_stop_engine); 741 742 void ahci_start_fis_rx(struct ata_port *ap) 743 { 744 void __iomem *port_mmio = ahci_port_base(ap); 745 struct ahci_host_priv *hpriv = ap->host->private_data; 746 struct ahci_port_priv *pp = ap->private_data; 747 u32 tmp; 748 749 /* set FIS registers */ 750 if (hpriv->cap & HOST_CAP_64) 751 writel((pp->cmd_slot_dma >> 16) >> 16, 752 port_mmio + PORT_LST_ADDR_HI); 753 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); 754 755 if (hpriv->cap & HOST_CAP_64) 756 writel((pp->rx_fis_dma >> 16) >> 16, 757 port_mmio + PORT_FIS_ADDR_HI); 758 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); 759 760 /* enable FIS reception */ 761 tmp = readl(port_mmio + PORT_CMD); 762 tmp |= PORT_CMD_FIS_RX; 763 writel(tmp, port_mmio + PORT_CMD); 764 765 /* flush */ 766 readl(port_mmio + PORT_CMD); 767 } 768 EXPORT_SYMBOL_GPL(ahci_start_fis_rx); 769 770 static int ahci_stop_fis_rx(struct ata_port *ap) 771 { 772 void __iomem *port_mmio = ahci_port_base(ap); 773 u32 tmp; 774 775 /* disable FIS reception */ 776 tmp = readl(port_mmio + PORT_CMD); 777 tmp &= ~PORT_CMD_FIS_RX; 778 writel(tmp, port_mmio + PORT_CMD); 779 780 /* wait for completion, spec says 500ms, give it 1000 */ 781 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON, 782 PORT_CMD_FIS_ON, 10, 1000); 783 if (tmp & PORT_CMD_FIS_ON) 784 return -EBUSY; 785 786 return 0; 787 } 788 789 static void ahci_power_up(struct ata_port *ap) 790 { 791 struct ahci_host_priv *hpriv = ap->host->private_data; 792 void __iomem *port_mmio = ahci_port_base(ap); 793 u32 cmd; 794 795 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 796 797 /* spin up device */ 798 if (hpriv->cap & HOST_CAP_SSS) { 799 cmd |= PORT_CMD_SPIN_UP; 800 writel(cmd, port_mmio + PORT_CMD); 801 } 802 803 /* wake up link */ 804 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); 805 } 806 807 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 808 unsigned int hints) 809 { 810 struct ata_port *ap = link->ap; 811 struct ahci_host_priv *hpriv = ap->host->private_data; 812 struct ahci_port_priv *pp = ap->private_data; 813 void __iomem *port_mmio = ahci_port_base(ap); 814 815 if (policy != ATA_LPM_MAX_POWER) { 816 /* wakeup flag only applies to the max power policy */ 817 hints &= ~ATA_LPM_WAKE_ONLY; 818 819 /* 820 * Disable interrupts on Phy Ready. This keeps us from 821 * getting woken up due to spurious phy ready 822 * interrupts. 823 */ 824 pp->intr_mask &= ~PORT_IRQ_PHYRDY; 825 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 826 827 sata_link_scr_lpm(link, policy, false); 828 } 829 830 if (hpriv->cap & HOST_CAP_ALPM) { 831 u32 cmd = readl(port_mmio + PORT_CMD); 832 833 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) { 834 if (!(hints & ATA_LPM_WAKE_ONLY)) 835 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE); 836 cmd |= PORT_CMD_ICC_ACTIVE; 837 838 writel(cmd, port_mmio + PORT_CMD); 839 readl(port_mmio + PORT_CMD); 840 841 /* wait 10ms to be sure we've come out of LPM state */ 842 ata_msleep(ap, 10); 843 844 if (hints & ATA_LPM_WAKE_ONLY) 845 return 0; 846 } else { 847 cmd |= PORT_CMD_ALPE; 848 if (policy == ATA_LPM_MIN_POWER) 849 cmd |= PORT_CMD_ASP; 850 else if (policy == ATA_LPM_MIN_POWER_WITH_PARTIAL) 851 cmd &= ~PORT_CMD_ASP; 852 853 /* write out new cmd value */ 854 writel(cmd, port_mmio + PORT_CMD); 855 } 856 } 857 858 /* set aggressive device sleep */ 859 if ((hpriv->cap2 & HOST_CAP2_SDS) && 860 (hpriv->cap2 & HOST_CAP2_SADM) && 861 (link->device->flags & ATA_DFLAG_DEVSLP)) { 862 if (policy == ATA_LPM_MIN_POWER || 863 policy == ATA_LPM_MIN_POWER_WITH_PARTIAL) 864 ahci_set_aggressive_devslp(ap, true); 865 else 866 ahci_set_aggressive_devslp(ap, false); 867 } 868 869 if (policy == ATA_LPM_MAX_POWER) { 870 sata_link_scr_lpm(link, policy, false); 871 872 /* turn PHYRDY IRQ back on */ 873 pp->intr_mask |= PORT_IRQ_PHYRDY; 874 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 875 } 876 877 return 0; 878 } 879 880 #ifdef CONFIG_PM 881 static void ahci_power_down(struct ata_port *ap) 882 { 883 struct ahci_host_priv *hpriv = ap->host->private_data; 884 void __iomem *port_mmio = ahci_port_base(ap); 885 u32 cmd, scontrol; 886 887 if (!(hpriv->cap & HOST_CAP_SSS)) 888 return; 889 890 /* put device into listen mode, first set PxSCTL.DET to 0 */ 891 scontrol = readl(port_mmio + PORT_SCR_CTL); 892 scontrol &= ~0xf; 893 writel(scontrol, port_mmio + PORT_SCR_CTL); 894 895 /* then set PxCMD.SUD to 0 */ 896 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 897 cmd &= ~PORT_CMD_SPIN_UP; 898 writel(cmd, port_mmio + PORT_CMD); 899 } 900 #endif 901 902 static void ahci_start_port(struct ata_port *ap) 903 { 904 struct ahci_host_priv *hpriv = ap->host->private_data; 905 struct ahci_port_priv *pp = ap->private_data; 906 struct ata_link *link; 907 struct ahci_em_priv *emp; 908 ssize_t rc; 909 int i; 910 911 /* enable FIS reception */ 912 ahci_start_fis_rx(ap); 913 914 /* enable DMA */ 915 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE)) 916 hpriv->start_engine(ap); 917 918 /* turn on LEDs */ 919 if (ap->flags & ATA_FLAG_EM) { 920 ata_for_each_link(link, ap, EDGE) { 921 emp = &pp->em_priv[link->pmp]; 922 923 /* EM Transmit bit maybe busy during init */ 924 for (i = 0; i < EM_MAX_RETRY; i++) { 925 rc = ap->ops->transmit_led_message(ap, 926 emp->led_state, 927 4); 928 /* 929 * If busy, give a breather but do not 930 * release EH ownership by using msleep() 931 * instead of ata_msleep(). EM Transmit 932 * bit is busy for the whole host and 933 * releasing ownership will cause other 934 * ports to fail the same way. 935 */ 936 if (rc == -EBUSY) 937 msleep(1); 938 else 939 break; 940 } 941 } 942 } 943 944 if (ap->flags & ATA_FLAG_SW_ACTIVITY) 945 ata_for_each_link(link, ap, EDGE) 946 ahci_init_sw_activity(link); 947 948 } 949 950 static int ahci_deinit_port(struct ata_port *ap, const char **emsg) 951 { 952 int rc; 953 struct ahci_host_priv *hpriv = ap->host->private_data; 954 955 /* disable DMA */ 956 rc = hpriv->stop_engine(ap); 957 if (rc) { 958 *emsg = "failed to stop engine"; 959 return rc; 960 } 961 962 /* disable FIS reception */ 963 rc = ahci_stop_fis_rx(ap); 964 if (rc) { 965 *emsg = "failed stop FIS RX"; 966 return rc; 967 } 968 969 return 0; 970 } 971 972 int ahci_reset_controller(struct ata_host *host) 973 { 974 struct ahci_host_priv *hpriv = host->private_data; 975 void __iomem *mmio = hpriv->mmio; 976 u32 tmp; 977 978 /* 979 * We must be in AHCI mode, before using anything AHCI-specific, such 980 * as HOST_RESET. 981 */ 982 ahci_enable_ahci(mmio); 983 984 /* Global controller reset */ 985 if (ahci_skip_host_reset) { 986 dev_info(host->dev, "Skipping global host reset\n"); 987 return 0; 988 } 989 990 tmp = readl(mmio + HOST_CTL); 991 if (!(tmp & HOST_RESET)) { 992 writel(tmp | HOST_RESET, mmio + HOST_CTL); 993 readl(mmio + HOST_CTL); /* flush */ 994 } 995 996 /* 997 * To perform host reset, OS should set HOST_RESET and poll until this 998 * bit is read to be "0". Reset must complete within 1 second, or the 999 * hardware should be considered fried. 1000 */ 1001 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET, 1002 HOST_RESET, 10, 1000); 1003 if (tmp & HOST_RESET) { 1004 dev_err(host->dev, "Controller reset failed (0x%x)\n", 1005 tmp); 1006 return -EIO; 1007 } 1008 1009 /* Turn on AHCI mode */ 1010 ahci_enable_ahci(mmio); 1011 1012 /* Some registers might be cleared on reset. Restore initial values. */ 1013 if (!(hpriv->flags & AHCI_HFLAG_NO_WRITE_TO_RO)) 1014 ahci_restore_initial_config(host); 1015 1016 return 0; 1017 } 1018 EXPORT_SYMBOL_GPL(ahci_reset_controller); 1019 1020 static void ahci_sw_activity(struct ata_link *link) 1021 { 1022 struct ata_port *ap = link->ap; 1023 struct ahci_port_priv *pp = ap->private_data; 1024 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1025 1026 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY)) 1027 return; 1028 1029 emp->activity++; 1030 if (!timer_pending(&emp->timer)) 1031 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10)); 1032 } 1033 1034 static void ahci_sw_activity_blink(struct timer_list *t) 1035 { 1036 struct ahci_em_priv *emp = from_timer(emp, t, timer); 1037 struct ata_link *link = emp->link; 1038 struct ata_port *ap = link->ap; 1039 1040 unsigned long led_message = emp->led_state; 1041 u32 activity_led_state; 1042 unsigned long flags; 1043 1044 led_message &= EM_MSG_LED_VALUE; 1045 led_message |= ap->port_no | (link->pmp << 8); 1046 1047 /* check to see if we've had activity. If so, 1048 * toggle state of LED and reset timer. If not, 1049 * turn LED to desired idle state. 1050 */ 1051 spin_lock_irqsave(ap->lock, flags); 1052 if (emp->saved_activity != emp->activity) { 1053 emp->saved_activity = emp->activity; 1054 /* get the current LED state */ 1055 activity_led_state = led_message & EM_MSG_LED_VALUE_ON; 1056 1057 if (activity_led_state) 1058 activity_led_state = 0; 1059 else 1060 activity_led_state = 1; 1061 1062 /* clear old state */ 1063 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 1064 1065 /* toggle state */ 1066 led_message |= (activity_led_state << 16); 1067 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100)); 1068 } else { 1069 /* switch to idle */ 1070 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 1071 if (emp->blink_policy == BLINK_OFF) 1072 led_message |= (1 << 16); 1073 } 1074 spin_unlock_irqrestore(ap->lock, flags); 1075 ap->ops->transmit_led_message(ap, led_message, 4); 1076 } 1077 1078 static void ahci_init_sw_activity(struct ata_link *link) 1079 { 1080 struct ata_port *ap = link->ap; 1081 struct ahci_port_priv *pp = ap->private_data; 1082 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1083 1084 /* init activity stats, setup timer */ 1085 emp->saved_activity = emp->activity = 0; 1086 emp->link = link; 1087 timer_setup(&emp->timer, ahci_sw_activity_blink, 0); 1088 1089 /* check our blink policy and set flag for link if it's enabled */ 1090 if (emp->blink_policy) 1091 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1092 } 1093 1094 int ahci_reset_em(struct ata_host *host) 1095 { 1096 struct ahci_host_priv *hpriv = host->private_data; 1097 void __iomem *mmio = hpriv->mmio; 1098 u32 em_ctl; 1099 1100 em_ctl = readl(mmio + HOST_EM_CTL); 1101 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST)) 1102 return -EINVAL; 1103 1104 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL); 1105 return 0; 1106 } 1107 EXPORT_SYMBOL_GPL(ahci_reset_em); 1108 1109 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 1110 ssize_t size) 1111 { 1112 struct ahci_host_priv *hpriv = ap->host->private_data; 1113 struct ahci_port_priv *pp = ap->private_data; 1114 void __iomem *mmio = hpriv->mmio; 1115 u32 em_ctl; 1116 u32 message[] = {0, 0}; 1117 unsigned long flags; 1118 int pmp; 1119 struct ahci_em_priv *emp; 1120 1121 /* get the slot number from the message */ 1122 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1123 if (pmp < EM_MAX_SLOTS) 1124 emp = &pp->em_priv[pmp]; 1125 else 1126 return -EINVAL; 1127 1128 ahci_rpm_get_port(ap); 1129 spin_lock_irqsave(ap->lock, flags); 1130 1131 /* 1132 * if we are still busy transmitting a previous message, 1133 * do not allow 1134 */ 1135 em_ctl = readl(mmio + HOST_EM_CTL); 1136 if (em_ctl & EM_CTL_TM) { 1137 spin_unlock_irqrestore(ap->lock, flags); 1138 ahci_rpm_put_port(ap); 1139 return -EBUSY; 1140 } 1141 1142 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) { 1143 /* 1144 * create message header - this is all zero except for 1145 * the message size, which is 4 bytes. 1146 */ 1147 message[0] |= (4 << 8); 1148 1149 /* ignore 0:4 of byte zero, fill in port info yourself */ 1150 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no); 1151 1152 /* write message to EM_LOC */ 1153 writel(message[0], mmio + hpriv->em_loc); 1154 writel(message[1], mmio + hpriv->em_loc+4); 1155 1156 /* 1157 * tell hardware to transmit the message 1158 */ 1159 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 1160 } 1161 1162 /* save off new led state for port/slot */ 1163 emp->led_state = state; 1164 1165 spin_unlock_irqrestore(ap->lock, flags); 1166 ahci_rpm_put_port(ap); 1167 1168 return size; 1169 } 1170 1171 static ssize_t ahci_led_show(struct ata_port *ap, char *buf) 1172 { 1173 struct ahci_port_priv *pp = ap->private_data; 1174 struct ata_link *link; 1175 struct ahci_em_priv *emp; 1176 int rc = 0; 1177 1178 ata_for_each_link(link, ap, EDGE) { 1179 emp = &pp->em_priv[link->pmp]; 1180 rc += sprintf(buf, "%lx\n", emp->led_state); 1181 } 1182 return rc; 1183 } 1184 1185 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 1186 size_t size) 1187 { 1188 unsigned int state; 1189 int pmp; 1190 struct ahci_port_priv *pp = ap->private_data; 1191 struct ahci_em_priv *emp; 1192 1193 if (kstrtouint(buf, 0, &state) < 0) 1194 return -EINVAL; 1195 1196 /* get the slot number from the message */ 1197 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1198 if (pmp < EM_MAX_SLOTS) { 1199 pmp = array_index_nospec(pmp, EM_MAX_SLOTS); 1200 emp = &pp->em_priv[pmp]; 1201 } else { 1202 return -EINVAL; 1203 } 1204 1205 /* mask off the activity bits if we are in sw_activity 1206 * mode, user should turn off sw_activity before setting 1207 * activity led through em_message 1208 */ 1209 if (emp->blink_policy) 1210 state &= ~EM_MSG_LED_VALUE_ACTIVITY; 1211 1212 return ap->ops->transmit_led_message(ap, state, size); 1213 } 1214 1215 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val) 1216 { 1217 struct ata_link *link = dev->link; 1218 struct ata_port *ap = link->ap; 1219 struct ahci_port_priv *pp = ap->private_data; 1220 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1221 u32 port_led_state = emp->led_state; 1222 1223 /* save the desired Activity LED behavior */ 1224 if (val == OFF) { 1225 /* clear LFLAG */ 1226 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY); 1227 1228 /* set the LED to OFF */ 1229 port_led_state &= EM_MSG_LED_VALUE_OFF; 1230 port_led_state |= (ap->port_no | (link->pmp << 8)); 1231 ap->ops->transmit_led_message(ap, port_led_state, 4); 1232 } else { 1233 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1234 if (val == BLINK_OFF) { 1235 /* set LED to ON for idle */ 1236 port_led_state &= EM_MSG_LED_VALUE_OFF; 1237 port_led_state |= (ap->port_no | (link->pmp << 8)); 1238 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */ 1239 ap->ops->transmit_led_message(ap, port_led_state, 4); 1240 } 1241 } 1242 emp->blink_policy = val; 1243 return 0; 1244 } 1245 1246 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf) 1247 { 1248 struct ata_link *link = dev->link; 1249 struct ata_port *ap = link->ap; 1250 struct ahci_port_priv *pp = ap->private_data; 1251 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1252 1253 /* display the saved value of activity behavior for this 1254 * disk. 1255 */ 1256 return sprintf(buf, "%d\n", emp->blink_policy); 1257 } 1258 1259 static void ahci_port_init(struct device *dev, struct ata_port *ap, 1260 int port_no, void __iomem *mmio, 1261 void __iomem *port_mmio) 1262 { 1263 struct ahci_host_priv *hpriv = ap->host->private_data; 1264 const char *emsg = NULL; 1265 int rc; 1266 u32 tmp; 1267 1268 /* make sure port is not active */ 1269 rc = ahci_deinit_port(ap, &emsg); 1270 if (rc) 1271 dev_warn(dev, "%s (%d)\n", emsg, rc); 1272 1273 /* clear SError */ 1274 tmp = readl(port_mmio + PORT_SCR_ERR); 1275 dev_dbg(dev, "PORT_SCR_ERR 0x%x\n", tmp); 1276 writel(tmp, port_mmio + PORT_SCR_ERR); 1277 1278 /* clear port IRQ */ 1279 tmp = readl(port_mmio + PORT_IRQ_STAT); 1280 dev_dbg(dev, "PORT_IRQ_STAT 0x%x\n", tmp); 1281 if (tmp) 1282 writel(tmp, port_mmio + PORT_IRQ_STAT); 1283 1284 writel(1 << port_no, mmio + HOST_IRQ_STAT); 1285 1286 /* mark esata ports */ 1287 tmp = readl(port_mmio + PORT_CMD); 1288 if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS)) 1289 ap->pflags |= ATA_PFLAG_EXTERNAL; 1290 } 1291 1292 void ahci_init_controller(struct ata_host *host) 1293 { 1294 struct ahci_host_priv *hpriv = host->private_data; 1295 void __iomem *mmio = hpriv->mmio; 1296 int i; 1297 void __iomem *port_mmio; 1298 u32 tmp; 1299 1300 for (i = 0; i < host->n_ports; i++) { 1301 struct ata_port *ap = host->ports[i]; 1302 1303 port_mmio = ahci_port_base(ap); 1304 if (ata_port_is_dummy(ap)) 1305 continue; 1306 1307 ahci_port_init(host->dev, ap, i, mmio, port_mmio); 1308 } 1309 1310 tmp = readl(mmio + HOST_CTL); 1311 dev_dbg(host->dev, "HOST_CTL 0x%x\n", tmp); 1312 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); 1313 tmp = readl(mmio + HOST_CTL); 1314 dev_dbg(host->dev, "HOST_CTL 0x%x\n", tmp); 1315 } 1316 EXPORT_SYMBOL_GPL(ahci_init_controller); 1317 1318 static void ahci_dev_config(struct ata_device *dev) 1319 { 1320 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data; 1321 1322 if (hpriv->flags & AHCI_HFLAG_SECT255) { 1323 dev->max_sectors = 255; 1324 ata_dev_info(dev, 1325 "SB600 AHCI: limiting to 255 sectors per cmd\n"); 1326 } 1327 } 1328 1329 unsigned int ahci_dev_classify(struct ata_port *ap) 1330 { 1331 void __iomem *port_mmio = ahci_port_base(ap); 1332 struct ata_taskfile tf; 1333 u32 tmp; 1334 1335 tmp = readl(port_mmio + PORT_SIG); 1336 tf.lbah = (tmp >> 24) & 0xff; 1337 tf.lbam = (tmp >> 16) & 0xff; 1338 tf.lbal = (tmp >> 8) & 0xff; 1339 tf.nsect = (tmp) & 0xff; 1340 1341 return ata_port_classify(ap, &tf); 1342 } 1343 EXPORT_SYMBOL_GPL(ahci_dev_classify); 1344 1345 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 1346 u32 opts) 1347 { 1348 dma_addr_t cmd_tbl_dma; 1349 1350 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; 1351 1352 pp->cmd_slot[tag].opts = cpu_to_le32(opts); 1353 pp->cmd_slot[tag].status = 0; 1354 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); 1355 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); 1356 } 1357 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot); 1358 1359 int ahci_kick_engine(struct ata_port *ap) 1360 { 1361 void __iomem *port_mmio = ahci_port_base(ap); 1362 struct ahci_host_priv *hpriv = ap->host->private_data; 1363 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1364 u32 tmp; 1365 int busy, rc; 1366 1367 /* stop engine */ 1368 rc = hpriv->stop_engine(ap); 1369 if (rc) 1370 goto out_restart; 1371 1372 /* need to do CLO? 1373 * always do CLO if PMP is attached (AHCI-1.3 9.2) 1374 */ 1375 busy = status & (ATA_BUSY | ATA_DRQ); 1376 if (!busy && !sata_pmp_attached(ap)) { 1377 rc = 0; 1378 goto out_restart; 1379 } 1380 1381 if (!(hpriv->cap & HOST_CAP_CLO)) { 1382 rc = -EOPNOTSUPP; 1383 goto out_restart; 1384 } 1385 1386 /* perform CLO */ 1387 tmp = readl(port_mmio + PORT_CMD); 1388 tmp |= PORT_CMD_CLO; 1389 writel(tmp, port_mmio + PORT_CMD); 1390 1391 rc = 0; 1392 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 1393 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); 1394 if (tmp & PORT_CMD_CLO) 1395 rc = -EIO; 1396 1397 /* restart engine */ 1398 out_restart: 1399 hpriv->start_engine(ap); 1400 return rc; 1401 } 1402 EXPORT_SYMBOL_GPL(ahci_kick_engine); 1403 1404 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, 1405 struct ata_taskfile *tf, int is_cmd, u16 flags, 1406 unsigned long timeout_msec) 1407 { 1408 const u32 cmd_fis_len = 5; /* five dwords */ 1409 struct ahci_port_priv *pp = ap->private_data; 1410 void __iomem *port_mmio = ahci_port_base(ap); 1411 u8 *fis = pp->cmd_tbl; 1412 u32 tmp; 1413 1414 /* prep the command */ 1415 ata_tf_to_fis(tf, pmp, is_cmd, fis); 1416 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); 1417 1418 /* set port value for softreset of Port Multiplier */ 1419 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) { 1420 tmp = readl(port_mmio + PORT_FBS); 1421 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); 1422 tmp |= pmp << PORT_FBS_DEV_OFFSET; 1423 writel(tmp, port_mmio + PORT_FBS); 1424 pp->fbs_last_dev = pmp; 1425 } 1426 1427 /* issue & wait */ 1428 writel(1, port_mmio + PORT_CMD_ISSUE); 1429 1430 if (timeout_msec) { 1431 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE, 1432 0x1, 0x1, 1, timeout_msec); 1433 if (tmp & 0x1) { 1434 ahci_kick_engine(ap); 1435 return -EBUSY; 1436 } 1437 } else 1438 readl(port_mmio + PORT_CMD_ISSUE); /* flush */ 1439 1440 return 0; 1441 } 1442 1443 int ahci_do_softreset(struct ata_link *link, unsigned int *class, 1444 int pmp, unsigned long deadline, 1445 int (*check_ready)(struct ata_link *link)) 1446 { 1447 struct ata_port *ap = link->ap; 1448 struct ahci_host_priv *hpriv = ap->host->private_data; 1449 struct ahci_port_priv *pp = ap->private_data; 1450 const char *reason = NULL; 1451 unsigned long now, msecs; 1452 struct ata_taskfile tf; 1453 bool fbs_disabled = false; 1454 int rc; 1455 1456 /* prepare for SRST (AHCI-1.1 10.4.1) */ 1457 rc = ahci_kick_engine(ap); 1458 if (rc && rc != -EOPNOTSUPP) 1459 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc); 1460 1461 /* 1462 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall 1463 * clear PxFBS.EN to '0' prior to issuing software reset to devices 1464 * that is attached to port multiplier. 1465 */ 1466 if (!ata_is_host_link(link) && pp->fbs_enabled) { 1467 ahci_disable_fbs(ap); 1468 fbs_disabled = true; 1469 } 1470 1471 ata_tf_init(link->device, &tf); 1472 1473 /* issue the first H2D Register FIS */ 1474 msecs = 0; 1475 now = jiffies; 1476 if (time_after(deadline, now)) 1477 msecs = jiffies_to_msecs(deadline - now); 1478 1479 tf.ctl |= ATA_SRST; 1480 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, 1481 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { 1482 rc = -EIO; 1483 reason = "1st FIS failed"; 1484 goto fail; 1485 } 1486 1487 /* spec says at least 5us, but be generous and sleep for 1ms */ 1488 ata_msleep(ap, 1); 1489 1490 /* issue the second H2D Register FIS */ 1491 tf.ctl &= ~ATA_SRST; 1492 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); 1493 1494 /* wait for link to become ready */ 1495 rc = ata_wait_after_reset(link, deadline, check_ready); 1496 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) { 1497 /* 1498 * Workaround for cases where link online status can't 1499 * be trusted. Treat device readiness timeout as link 1500 * offline. 1501 */ 1502 ata_link_info(link, "device not ready, treating as offline\n"); 1503 *class = ATA_DEV_NONE; 1504 } else if (rc) { 1505 /* link occupied, -ENODEV too is an error */ 1506 reason = "device not ready"; 1507 goto fail; 1508 } else 1509 *class = ahci_dev_classify(ap); 1510 1511 /* re-enable FBS if disabled before */ 1512 if (fbs_disabled) 1513 ahci_enable_fbs(ap); 1514 1515 return 0; 1516 1517 fail: 1518 ata_link_err(link, "softreset failed (%s)\n", reason); 1519 return rc; 1520 } 1521 1522 int ahci_check_ready(struct ata_link *link) 1523 { 1524 void __iomem *port_mmio = ahci_port_base(link->ap); 1525 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1526 1527 return ata_check_ready(status); 1528 } 1529 EXPORT_SYMBOL_GPL(ahci_check_ready); 1530 1531 static int ahci_softreset(struct ata_link *link, unsigned int *class, 1532 unsigned long deadline) 1533 { 1534 int pmp = sata_srst_pmp(link); 1535 1536 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready); 1537 } 1538 EXPORT_SYMBOL_GPL(ahci_do_softreset); 1539 1540 static int ahci_bad_pmp_check_ready(struct ata_link *link) 1541 { 1542 void __iomem *port_mmio = ahci_port_base(link->ap); 1543 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1544 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT); 1545 1546 /* 1547 * There is no need to check TFDATA if BAD PMP is found due to HW bug, 1548 * which can save timeout delay. 1549 */ 1550 if (irq_status & PORT_IRQ_BAD_PMP) 1551 return -EIO; 1552 1553 return ata_check_ready(status); 1554 } 1555 1556 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class, 1557 unsigned long deadline) 1558 { 1559 struct ata_port *ap = link->ap; 1560 void __iomem *port_mmio = ahci_port_base(ap); 1561 int pmp = sata_srst_pmp(link); 1562 int rc; 1563 u32 irq_sts; 1564 1565 rc = ahci_do_softreset(link, class, pmp, deadline, 1566 ahci_bad_pmp_check_ready); 1567 1568 /* 1569 * Soft reset fails with IPMS set when PMP is enabled but 1570 * SATA HDD/ODD is connected to SATA port, do soft reset 1571 * again to port 0. 1572 */ 1573 if (rc == -EIO) { 1574 irq_sts = readl(port_mmio + PORT_IRQ_STAT); 1575 if (irq_sts & PORT_IRQ_BAD_PMP) { 1576 ata_link_warn(link, 1577 "applying PMP SRST workaround " 1578 "and retrying\n"); 1579 rc = ahci_do_softreset(link, class, 0, deadline, 1580 ahci_check_ready); 1581 } 1582 } 1583 1584 return rc; 1585 } 1586 1587 int ahci_do_hardreset(struct ata_link *link, unsigned int *class, 1588 unsigned long deadline, bool *online) 1589 { 1590 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 1591 struct ata_port *ap = link->ap; 1592 struct ahci_port_priv *pp = ap->private_data; 1593 struct ahci_host_priv *hpriv = ap->host->private_data; 1594 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 1595 struct ata_taskfile tf; 1596 int rc; 1597 1598 hpriv->stop_engine(ap); 1599 1600 /* clear D2H reception area to properly wait for D2H FIS */ 1601 ata_tf_init(link->device, &tf); 1602 tf.status = ATA_BUSY; 1603 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 1604 1605 rc = sata_link_hardreset(link, timing, deadline, online, 1606 ahci_check_ready); 1607 1608 hpriv->start_engine(ap); 1609 1610 if (*online) 1611 *class = ahci_dev_classify(ap); 1612 1613 return rc; 1614 } 1615 EXPORT_SYMBOL_GPL(ahci_do_hardreset); 1616 1617 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 1618 unsigned long deadline) 1619 { 1620 bool online; 1621 1622 return ahci_do_hardreset(link, class, deadline, &online); 1623 } 1624 1625 static void ahci_postreset(struct ata_link *link, unsigned int *class) 1626 { 1627 struct ata_port *ap = link->ap; 1628 void __iomem *port_mmio = ahci_port_base(ap); 1629 u32 new_tmp, tmp; 1630 1631 ata_std_postreset(link, class); 1632 1633 /* Make sure port's ATAPI bit is set appropriately */ 1634 new_tmp = tmp = readl(port_mmio + PORT_CMD); 1635 if (*class == ATA_DEV_ATAPI) 1636 new_tmp |= PORT_CMD_ATAPI; 1637 else 1638 new_tmp &= ~PORT_CMD_ATAPI; 1639 if (new_tmp != tmp) { 1640 writel(new_tmp, port_mmio + PORT_CMD); 1641 readl(port_mmio + PORT_CMD); /* flush */ 1642 } 1643 } 1644 1645 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) 1646 { 1647 struct scatterlist *sg; 1648 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; 1649 unsigned int si; 1650 1651 /* 1652 * Next, the S/G list. 1653 */ 1654 for_each_sg(qc->sg, sg, qc->n_elem, si) { 1655 dma_addr_t addr = sg_dma_address(sg); 1656 u32 sg_len = sg_dma_len(sg); 1657 1658 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); 1659 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); 1660 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); 1661 } 1662 1663 return si; 1664 } 1665 1666 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc) 1667 { 1668 struct ata_port *ap = qc->ap; 1669 struct ahci_port_priv *pp = ap->private_data; 1670 1671 if (!sata_pmp_attached(ap) || pp->fbs_enabled) 1672 return ata_std_qc_defer(qc); 1673 else 1674 return sata_pmp_qc_defer_cmd_switch(qc); 1675 } 1676 1677 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc) 1678 { 1679 struct ata_port *ap = qc->ap; 1680 struct ahci_port_priv *pp = ap->private_data; 1681 int is_atapi = ata_is_atapi(qc->tf.protocol); 1682 void *cmd_tbl; 1683 u32 opts; 1684 const u32 cmd_fis_len = 5; /* five dwords */ 1685 unsigned int n_elem; 1686 1687 /* 1688 * Fill in command table information. First, the header, 1689 * a SATA Register - Host to Device command FIS. 1690 */ 1691 cmd_tbl = pp->cmd_tbl + qc->hw_tag * AHCI_CMD_TBL_SZ; 1692 1693 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); 1694 if (is_atapi) { 1695 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); 1696 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); 1697 } 1698 1699 n_elem = 0; 1700 if (qc->flags & ATA_QCFLAG_DMAMAP) 1701 n_elem = ahci_fill_sg(qc, cmd_tbl); 1702 1703 /* 1704 * Fill in command slot information. 1705 */ 1706 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); 1707 if (qc->tf.flags & ATA_TFLAG_WRITE) 1708 opts |= AHCI_CMD_WRITE; 1709 if (is_atapi) 1710 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; 1711 1712 ahci_fill_cmd_slot(pp, qc->hw_tag, opts); 1713 1714 return AC_ERR_OK; 1715 } 1716 1717 static void ahci_fbs_dec_intr(struct ata_port *ap) 1718 { 1719 struct ahci_port_priv *pp = ap->private_data; 1720 void __iomem *port_mmio = ahci_port_base(ap); 1721 u32 fbs = readl(port_mmio + PORT_FBS); 1722 int retries = 3; 1723 1724 BUG_ON(!pp->fbs_enabled); 1725 1726 /* time to wait for DEC is not specified by AHCI spec, 1727 * add a retry loop for safety. 1728 */ 1729 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS); 1730 fbs = readl(port_mmio + PORT_FBS); 1731 while ((fbs & PORT_FBS_DEC) && retries--) { 1732 udelay(1); 1733 fbs = readl(port_mmio + PORT_FBS); 1734 } 1735 1736 if (fbs & PORT_FBS_DEC) 1737 dev_err(ap->host->dev, "failed to clear device error\n"); 1738 } 1739 1740 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) 1741 { 1742 struct ahci_host_priv *hpriv = ap->host->private_data; 1743 struct ahci_port_priv *pp = ap->private_data; 1744 struct ata_eh_info *host_ehi = &ap->link.eh_info; 1745 struct ata_link *link = NULL; 1746 struct ata_queued_cmd *active_qc; 1747 struct ata_eh_info *active_ehi; 1748 bool fbs_need_dec = false; 1749 u32 serror; 1750 1751 /* determine active link with error */ 1752 if (pp->fbs_enabled) { 1753 void __iomem *port_mmio = ahci_port_base(ap); 1754 u32 fbs = readl(port_mmio + PORT_FBS); 1755 int pmp = fbs >> PORT_FBS_DWE_OFFSET; 1756 1757 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) { 1758 link = &ap->pmp_link[pmp]; 1759 fbs_need_dec = true; 1760 } 1761 1762 } else 1763 ata_for_each_link(link, ap, EDGE) 1764 if (ata_link_active(link)) 1765 break; 1766 1767 if (!link) 1768 link = &ap->link; 1769 1770 active_qc = ata_qc_from_tag(ap, link->active_tag); 1771 active_ehi = &link->eh_info; 1772 1773 /* record irq stat */ 1774 ata_ehi_clear_desc(host_ehi); 1775 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); 1776 1777 /* AHCI needs SError cleared; otherwise, it might lock up */ 1778 ahci_scr_read(&ap->link, SCR_ERROR, &serror); 1779 ahci_scr_write(&ap->link, SCR_ERROR, serror); 1780 host_ehi->serror |= serror; 1781 1782 /* some controllers set IRQ_IF_ERR on device errors, ignore it */ 1783 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) 1784 irq_stat &= ~PORT_IRQ_IF_ERR; 1785 1786 if (irq_stat & PORT_IRQ_TF_ERR) { 1787 /* If qc is active, charge it; otherwise, the active 1788 * link. There's no active qc on NCQ errors. It will 1789 * be determined by EH by reading log page 10h. 1790 */ 1791 if (active_qc) 1792 active_qc->err_mask |= AC_ERR_DEV; 1793 else 1794 active_ehi->err_mask |= AC_ERR_DEV; 1795 1796 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) 1797 host_ehi->serror &= ~SERR_INTERNAL; 1798 } 1799 1800 if (irq_stat & PORT_IRQ_UNK_FIS) { 1801 u32 *unk = pp->rx_fis + RX_FIS_UNK; 1802 1803 active_ehi->err_mask |= AC_ERR_HSM; 1804 active_ehi->action |= ATA_EH_RESET; 1805 ata_ehi_push_desc(active_ehi, 1806 "unknown FIS %08x %08x %08x %08x" , 1807 unk[0], unk[1], unk[2], unk[3]); 1808 } 1809 1810 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) { 1811 active_ehi->err_mask |= AC_ERR_HSM; 1812 active_ehi->action |= ATA_EH_RESET; 1813 ata_ehi_push_desc(active_ehi, "incorrect PMP"); 1814 } 1815 1816 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { 1817 host_ehi->err_mask |= AC_ERR_HOST_BUS; 1818 host_ehi->action |= ATA_EH_RESET; 1819 ata_ehi_push_desc(host_ehi, "host bus error"); 1820 } 1821 1822 if (irq_stat & PORT_IRQ_IF_ERR) { 1823 if (fbs_need_dec) 1824 active_ehi->err_mask |= AC_ERR_DEV; 1825 else { 1826 host_ehi->err_mask |= AC_ERR_ATA_BUS; 1827 host_ehi->action |= ATA_EH_RESET; 1828 } 1829 1830 ata_ehi_push_desc(host_ehi, "interface fatal error"); 1831 } 1832 1833 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { 1834 ata_ehi_hotplugged(host_ehi); 1835 ata_ehi_push_desc(host_ehi, "%s", 1836 irq_stat & PORT_IRQ_CONNECT ? 1837 "connection status changed" : "PHY RDY changed"); 1838 } 1839 1840 /* okay, let's hand over to EH */ 1841 1842 if (irq_stat & PORT_IRQ_FREEZE) 1843 ata_port_freeze(ap); 1844 else if (fbs_need_dec) { 1845 ata_link_abort(link); 1846 ahci_fbs_dec_intr(ap); 1847 } else 1848 ata_port_abort(ap); 1849 } 1850 1851 static void ahci_qc_complete(struct ata_port *ap, void __iomem *port_mmio) 1852 { 1853 struct ata_eh_info *ehi = &ap->link.eh_info; 1854 struct ahci_port_priv *pp = ap->private_data; 1855 u32 qc_active = 0; 1856 int rc; 1857 1858 /* 1859 * pp->active_link is not reliable once FBS is enabled, both 1860 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because 1861 * NCQ and non-NCQ commands may be in flight at the same time. 1862 */ 1863 if (pp->fbs_enabled) { 1864 if (ap->qc_active) { 1865 qc_active = readl(port_mmio + PORT_SCR_ACT); 1866 qc_active |= readl(port_mmio + PORT_CMD_ISSUE); 1867 } 1868 } else { 1869 /* pp->active_link is valid iff any command is in flight */ 1870 if (ap->qc_active && pp->active_link->sactive) 1871 qc_active = readl(port_mmio + PORT_SCR_ACT); 1872 else 1873 qc_active = readl(port_mmio + PORT_CMD_ISSUE); 1874 } 1875 1876 rc = ata_qc_complete_multiple(ap, qc_active); 1877 if (unlikely(rc < 0 && !(ap->pflags & ATA_PFLAG_RESETTING))) { 1878 ehi->err_mask |= AC_ERR_HSM; 1879 ehi->action |= ATA_EH_RESET; 1880 ata_port_freeze(ap); 1881 } 1882 } 1883 1884 static void ahci_handle_port_interrupt(struct ata_port *ap, 1885 void __iomem *port_mmio, u32 status) 1886 { 1887 struct ahci_port_priv *pp = ap->private_data; 1888 struct ahci_host_priv *hpriv = ap->host->private_data; 1889 1890 /* ignore BAD_PMP while resetting */ 1891 if (unlikely(ap->pflags & ATA_PFLAG_RESETTING)) 1892 status &= ~PORT_IRQ_BAD_PMP; 1893 1894 if (sata_lpm_ignore_phy_events(&ap->link)) { 1895 status &= ~PORT_IRQ_PHYRDY; 1896 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG); 1897 } 1898 1899 if (unlikely(status & PORT_IRQ_ERROR)) { 1900 /* 1901 * Before getting the error notification, we may have 1902 * received SDB FISes notifying successful completions. 1903 * Handle these first and then handle the error. 1904 */ 1905 ahci_qc_complete(ap, port_mmio); 1906 ahci_error_intr(ap, status); 1907 return; 1908 } 1909 1910 if (status & PORT_IRQ_SDB_FIS) { 1911 /* If SNotification is available, leave notification 1912 * handling to sata_async_notification(). If not, 1913 * emulate it by snooping SDB FIS RX area. 1914 * 1915 * Snooping FIS RX area is probably cheaper than 1916 * poking SNotification but some constrollers which 1917 * implement SNotification, ICH9 for example, don't 1918 * store AN SDB FIS into receive area. 1919 */ 1920 if (hpriv->cap & HOST_CAP_SNTF) 1921 sata_async_notification(ap); 1922 else { 1923 /* If the 'N' bit in word 0 of the FIS is set, 1924 * we just received asynchronous notification. 1925 * Tell libata about it. 1926 * 1927 * Lack of SNotification should not appear in 1928 * ahci 1.2, so the workaround is unnecessary 1929 * when FBS is enabled. 1930 */ 1931 if (pp->fbs_enabled) 1932 WARN_ON_ONCE(1); 1933 else { 1934 const __le32 *f = pp->rx_fis + RX_FIS_SDB; 1935 u32 f0 = le32_to_cpu(f[0]); 1936 if (f0 & (1 << 15)) 1937 sata_async_notification(ap); 1938 } 1939 } 1940 } 1941 1942 /* Handle completed commands */ 1943 ahci_qc_complete(ap, port_mmio); 1944 } 1945 1946 static void ahci_port_intr(struct ata_port *ap) 1947 { 1948 void __iomem *port_mmio = ahci_port_base(ap); 1949 u32 status; 1950 1951 status = readl(port_mmio + PORT_IRQ_STAT); 1952 writel(status, port_mmio + PORT_IRQ_STAT); 1953 1954 ahci_handle_port_interrupt(ap, port_mmio, status); 1955 } 1956 1957 static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance) 1958 { 1959 struct ata_port *ap = dev_instance; 1960 void __iomem *port_mmio = ahci_port_base(ap); 1961 u32 status; 1962 1963 status = readl(port_mmio + PORT_IRQ_STAT); 1964 writel(status, port_mmio + PORT_IRQ_STAT); 1965 1966 spin_lock(ap->lock); 1967 ahci_handle_port_interrupt(ap, port_mmio, status); 1968 spin_unlock(ap->lock); 1969 1970 return IRQ_HANDLED; 1971 } 1972 1973 u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked) 1974 { 1975 unsigned int i, handled = 0; 1976 1977 for (i = 0; i < host->n_ports; i++) { 1978 struct ata_port *ap; 1979 1980 if (!(irq_masked & (1 << i))) 1981 continue; 1982 1983 ap = host->ports[i]; 1984 if (ap) { 1985 ahci_port_intr(ap); 1986 } else { 1987 if (ata_ratelimit()) 1988 dev_warn(host->dev, 1989 "interrupt on disabled port %u\n", i); 1990 } 1991 1992 handled = 1; 1993 } 1994 1995 return handled; 1996 } 1997 EXPORT_SYMBOL_GPL(ahci_handle_port_intr); 1998 1999 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance) 2000 { 2001 struct ata_host *host = dev_instance; 2002 struct ahci_host_priv *hpriv; 2003 unsigned int rc = 0; 2004 void __iomem *mmio; 2005 u32 irq_stat, irq_masked; 2006 2007 hpriv = host->private_data; 2008 mmio = hpriv->mmio; 2009 2010 /* sigh. 0xffffffff is a valid return from h/w */ 2011 irq_stat = readl(mmio + HOST_IRQ_STAT); 2012 if (!irq_stat) 2013 return IRQ_NONE; 2014 2015 irq_masked = irq_stat & hpriv->port_map; 2016 2017 spin_lock(&host->lock); 2018 2019 rc = ahci_handle_port_intr(host, irq_masked); 2020 2021 /* HOST_IRQ_STAT behaves as level triggered latch meaning that 2022 * it should be cleared after all the port events are cleared; 2023 * otherwise, it will raise a spurious interrupt after each 2024 * valid one. Please read section 10.6.2 of ahci 1.1 for more 2025 * information. 2026 * 2027 * Also, use the unmasked value to clear interrupt as spurious 2028 * pending event on a dummy port might cause screaming IRQ. 2029 */ 2030 writel(irq_stat, mmio + HOST_IRQ_STAT); 2031 2032 spin_unlock(&host->lock); 2033 2034 return IRQ_RETVAL(rc); 2035 } 2036 2037 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) 2038 { 2039 struct ata_port *ap = qc->ap; 2040 void __iomem *port_mmio = ahci_port_base(ap); 2041 struct ahci_port_priv *pp = ap->private_data; 2042 2043 /* Keep track of the currently active link. It will be used 2044 * in completion path to determine whether NCQ phase is in 2045 * progress. 2046 */ 2047 pp->active_link = qc->dev->link; 2048 2049 if (ata_is_ncq(qc->tf.protocol)) 2050 writel(1 << qc->hw_tag, port_mmio + PORT_SCR_ACT); 2051 2052 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) { 2053 u32 fbs = readl(port_mmio + PORT_FBS); 2054 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); 2055 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET; 2056 writel(fbs, port_mmio + PORT_FBS); 2057 pp->fbs_last_dev = qc->dev->link->pmp; 2058 } 2059 2060 writel(1 << qc->hw_tag, port_mmio + PORT_CMD_ISSUE); 2061 2062 ahci_sw_activity(qc->dev->link); 2063 2064 return 0; 2065 } 2066 EXPORT_SYMBOL_GPL(ahci_qc_issue); 2067 2068 static void ahci_qc_fill_rtf(struct ata_queued_cmd *qc) 2069 { 2070 struct ahci_port_priv *pp = qc->ap->private_data; 2071 u8 *rx_fis = pp->rx_fis; 2072 2073 /* 2074 * rtf may already be filled (e.g. for successful NCQ commands). 2075 * If that is the case, we have nothing to do. 2076 */ 2077 if (qc->flags & ATA_QCFLAG_RTF_FILLED) 2078 return; 2079 2080 if (pp->fbs_enabled) 2081 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ; 2082 2083 /* 2084 * After a successful execution of an ATA PIO data-in command, 2085 * the device doesn't send D2H Reg FIS to update the TF and 2086 * the host should take TF and E_Status from the preceding PIO 2087 * Setup FIS. 2088 */ 2089 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE && 2090 !(qc->flags & ATA_QCFLAG_EH)) { 2091 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf); 2092 qc->result_tf.status = (rx_fis + RX_FIS_PIO_SETUP)[15]; 2093 qc->flags |= ATA_QCFLAG_RTF_FILLED; 2094 return; 2095 } 2096 2097 /* 2098 * For NCQ commands, we never get a D2H FIS, so reading the D2H Register 2099 * FIS area of the Received FIS Structure (which contains a copy of the 2100 * last D2H FIS received) will contain an outdated status code. 2101 * For NCQ commands, we instead get a SDB FIS, so read the SDB FIS area 2102 * instead. However, the SDB FIS does not contain the LBA, so we can't 2103 * use the ata_tf_from_fis() helper. 2104 */ 2105 if (ata_is_ncq(qc->tf.protocol)) { 2106 const u8 *fis = rx_fis + RX_FIS_SDB; 2107 2108 /* 2109 * Successful NCQ commands have been filled already. 2110 * A failed NCQ command will read the status here. 2111 * (Note that a failed NCQ command will get a more specific 2112 * error when reading the NCQ Command Error log.) 2113 */ 2114 qc->result_tf.status = fis[2]; 2115 qc->result_tf.error = fis[3]; 2116 qc->flags |= ATA_QCFLAG_RTF_FILLED; 2117 return; 2118 } 2119 2120 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf); 2121 qc->flags |= ATA_QCFLAG_RTF_FILLED; 2122 } 2123 2124 static void ahci_qc_ncq_fill_rtf(struct ata_port *ap, u64 done_mask) 2125 { 2126 struct ahci_port_priv *pp = ap->private_data; 2127 const u8 *fis; 2128 2129 /* No outstanding commands. */ 2130 if (!ap->qc_active) 2131 return; 2132 2133 /* 2134 * FBS not enabled, so read status and error once, since they are shared 2135 * for all QCs. 2136 */ 2137 if (!pp->fbs_enabled) { 2138 u8 status, error; 2139 2140 /* No outstanding NCQ commands. */ 2141 if (!pp->active_link->sactive) 2142 return; 2143 2144 fis = pp->rx_fis + RX_FIS_SDB; 2145 status = fis[2]; 2146 error = fis[3]; 2147 2148 while (done_mask) { 2149 struct ata_queued_cmd *qc; 2150 unsigned int tag = __ffs64(done_mask); 2151 2152 qc = ata_qc_from_tag(ap, tag); 2153 if (qc && ata_is_ncq(qc->tf.protocol)) { 2154 qc->result_tf.status = status; 2155 qc->result_tf.error = error; 2156 qc->flags |= ATA_QCFLAG_RTF_FILLED; 2157 } 2158 done_mask &= ~(1ULL << tag); 2159 } 2160 2161 return; 2162 } 2163 2164 /* 2165 * FBS enabled, so read the status and error for each QC, since the QCs 2166 * can belong to different PMP links. (Each PMP link has its own FIS 2167 * Receive Area.) 2168 */ 2169 while (done_mask) { 2170 struct ata_queued_cmd *qc; 2171 unsigned int tag = __ffs64(done_mask); 2172 2173 qc = ata_qc_from_tag(ap, tag); 2174 if (qc && ata_is_ncq(qc->tf.protocol)) { 2175 fis = pp->rx_fis; 2176 fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ; 2177 fis += RX_FIS_SDB; 2178 qc->result_tf.status = fis[2]; 2179 qc->result_tf.error = fis[3]; 2180 qc->flags |= ATA_QCFLAG_RTF_FILLED; 2181 } 2182 done_mask &= ~(1ULL << tag); 2183 } 2184 } 2185 2186 static void ahci_freeze(struct ata_port *ap) 2187 { 2188 void __iomem *port_mmio = ahci_port_base(ap); 2189 2190 /* turn IRQ off */ 2191 writel(0, port_mmio + PORT_IRQ_MASK); 2192 } 2193 2194 static void ahci_thaw(struct ata_port *ap) 2195 { 2196 struct ahci_host_priv *hpriv = ap->host->private_data; 2197 void __iomem *mmio = hpriv->mmio; 2198 void __iomem *port_mmio = ahci_port_base(ap); 2199 u32 tmp; 2200 struct ahci_port_priv *pp = ap->private_data; 2201 2202 /* clear IRQ */ 2203 tmp = readl(port_mmio + PORT_IRQ_STAT); 2204 writel(tmp, port_mmio + PORT_IRQ_STAT); 2205 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); 2206 2207 /* turn IRQ back on */ 2208 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2209 } 2210 2211 void ahci_error_handler(struct ata_port *ap) 2212 { 2213 struct ahci_host_priv *hpriv = ap->host->private_data; 2214 2215 if (!ata_port_is_frozen(ap)) { 2216 /* restart engine */ 2217 hpriv->stop_engine(ap); 2218 hpriv->start_engine(ap); 2219 } 2220 2221 sata_pmp_error_handler(ap); 2222 2223 if (!ata_dev_enabled(ap->link.device)) 2224 hpriv->stop_engine(ap); 2225 } 2226 EXPORT_SYMBOL_GPL(ahci_error_handler); 2227 2228 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) 2229 { 2230 struct ata_port *ap = qc->ap; 2231 2232 /* make DMA engine forget about the failed command */ 2233 if (qc->flags & ATA_QCFLAG_EH) 2234 ahci_kick_engine(ap); 2235 } 2236 2237 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep) 2238 { 2239 struct ahci_host_priv *hpriv = ap->host->private_data; 2240 void __iomem *port_mmio = ahci_port_base(ap); 2241 struct ata_device *dev = ap->link.device; 2242 u32 devslp, dm, dito, mdat, deto, dito_conf; 2243 int rc; 2244 unsigned int err_mask; 2245 2246 devslp = readl(port_mmio + PORT_DEVSLP); 2247 if (!(devslp & PORT_DEVSLP_DSP)) { 2248 dev_info(ap->host->dev, "port does not support device sleep\n"); 2249 return; 2250 } 2251 2252 /* disable device sleep */ 2253 if (!sleep) { 2254 if (devslp & PORT_DEVSLP_ADSE) { 2255 writel(devslp & ~PORT_DEVSLP_ADSE, 2256 port_mmio + PORT_DEVSLP); 2257 err_mask = ata_dev_set_feature(dev, 2258 SETFEATURES_SATA_DISABLE, 2259 SATA_DEVSLP); 2260 if (err_mask && err_mask != AC_ERR_DEV) 2261 ata_dev_warn(dev, "failed to disable DEVSLP\n"); 2262 } 2263 return; 2264 } 2265 2266 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET; 2267 dito = devslp_idle_timeout / (dm + 1); 2268 if (dito > 0x3ff) 2269 dito = 0x3ff; 2270 2271 dito_conf = (devslp >> PORT_DEVSLP_DITO_OFFSET) & 0x3FF; 2272 2273 /* device sleep was already enabled and same dito */ 2274 if ((devslp & PORT_DEVSLP_ADSE) && (dito_conf == dito)) 2275 return; 2276 2277 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */ 2278 rc = hpriv->stop_engine(ap); 2279 if (rc) 2280 return; 2281 2282 /* Use the nominal value 10 ms if the read MDAT is zero, 2283 * the nominal value of DETO is 20 ms. 2284 */ 2285 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] & 2286 ATA_LOG_DEVSLP_VALID_MASK) { 2287 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] & 2288 ATA_LOG_DEVSLP_MDAT_MASK; 2289 if (!mdat) 2290 mdat = 10; 2291 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO]; 2292 if (!deto) 2293 deto = 20; 2294 } else { 2295 mdat = 10; 2296 deto = 20; 2297 } 2298 2299 /* Make dito, mdat, deto bits to 0s */ 2300 devslp &= ~GENMASK_ULL(24, 2); 2301 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) | 2302 (mdat << PORT_DEVSLP_MDAT_OFFSET) | 2303 (deto << PORT_DEVSLP_DETO_OFFSET) | 2304 PORT_DEVSLP_ADSE); 2305 writel(devslp, port_mmio + PORT_DEVSLP); 2306 2307 hpriv->start_engine(ap); 2308 2309 /* enable device sleep feature for the drive */ 2310 err_mask = ata_dev_set_feature(dev, 2311 SETFEATURES_SATA_ENABLE, 2312 SATA_DEVSLP); 2313 if (err_mask && err_mask != AC_ERR_DEV) 2314 ata_dev_warn(dev, "failed to enable DEVSLP\n"); 2315 } 2316 2317 static void ahci_enable_fbs(struct ata_port *ap) 2318 { 2319 struct ahci_host_priv *hpriv = ap->host->private_data; 2320 struct ahci_port_priv *pp = ap->private_data; 2321 void __iomem *port_mmio = ahci_port_base(ap); 2322 u32 fbs; 2323 int rc; 2324 2325 if (!pp->fbs_supported) 2326 return; 2327 2328 fbs = readl(port_mmio + PORT_FBS); 2329 if (fbs & PORT_FBS_EN) { 2330 pp->fbs_enabled = true; 2331 pp->fbs_last_dev = -1; /* initialization */ 2332 return; 2333 } 2334 2335 rc = hpriv->stop_engine(ap); 2336 if (rc) 2337 return; 2338 2339 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS); 2340 fbs = readl(port_mmio + PORT_FBS); 2341 if (fbs & PORT_FBS_EN) { 2342 dev_info(ap->host->dev, "FBS is enabled\n"); 2343 pp->fbs_enabled = true; 2344 pp->fbs_last_dev = -1; /* initialization */ 2345 } else 2346 dev_err(ap->host->dev, "Failed to enable FBS\n"); 2347 2348 hpriv->start_engine(ap); 2349 } 2350 2351 static void ahci_disable_fbs(struct ata_port *ap) 2352 { 2353 struct ahci_host_priv *hpriv = ap->host->private_data; 2354 struct ahci_port_priv *pp = ap->private_data; 2355 void __iomem *port_mmio = ahci_port_base(ap); 2356 u32 fbs; 2357 int rc; 2358 2359 if (!pp->fbs_supported) 2360 return; 2361 2362 fbs = readl(port_mmio + PORT_FBS); 2363 if ((fbs & PORT_FBS_EN) == 0) { 2364 pp->fbs_enabled = false; 2365 return; 2366 } 2367 2368 rc = hpriv->stop_engine(ap); 2369 if (rc) 2370 return; 2371 2372 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS); 2373 fbs = readl(port_mmio + PORT_FBS); 2374 if (fbs & PORT_FBS_EN) 2375 dev_err(ap->host->dev, "Failed to disable FBS\n"); 2376 else { 2377 dev_info(ap->host->dev, "FBS is disabled\n"); 2378 pp->fbs_enabled = false; 2379 } 2380 2381 hpriv->start_engine(ap); 2382 } 2383 2384 static void ahci_pmp_attach(struct ata_port *ap) 2385 { 2386 void __iomem *port_mmio = ahci_port_base(ap); 2387 struct ahci_port_priv *pp = ap->private_data; 2388 u32 cmd; 2389 2390 cmd = readl(port_mmio + PORT_CMD); 2391 cmd |= PORT_CMD_PMP; 2392 writel(cmd, port_mmio + PORT_CMD); 2393 2394 ahci_enable_fbs(ap); 2395 2396 pp->intr_mask |= PORT_IRQ_BAD_PMP; 2397 2398 /* 2399 * We must not change the port interrupt mask register if the 2400 * port is marked frozen, the value in pp->intr_mask will be 2401 * restored later when the port is thawed. 2402 * 2403 * Note that during initialization, the port is marked as 2404 * frozen since the irq handler is not yet registered. 2405 */ 2406 if (!ata_port_is_frozen(ap)) 2407 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2408 } 2409 2410 static void ahci_pmp_detach(struct ata_port *ap) 2411 { 2412 void __iomem *port_mmio = ahci_port_base(ap); 2413 struct ahci_port_priv *pp = ap->private_data; 2414 u32 cmd; 2415 2416 ahci_disable_fbs(ap); 2417 2418 cmd = readl(port_mmio + PORT_CMD); 2419 cmd &= ~PORT_CMD_PMP; 2420 writel(cmd, port_mmio + PORT_CMD); 2421 2422 pp->intr_mask &= ~PORT_IRQ_BAD_PMP; 2423 2424 /* see comment above in ahci_pmp_attach() */ 2425 if (!ata_port_is_frozen(ap)) 2426 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2427 } 2428 2429 int ahci_port_resume(struct ata_port *ap) 2430 { 2431 ahci_rpm_get_port(ap); 2432 2433 ahci_power_up(ap); 2434 ahci_start_port(ap); 2435 2436 if (sata_pmp_attached(ap)) 2437 ahci_pmp_attach(ap); 2438 else 2439 ahci_pmp_detach(ap); 2440 2441 return 0; 2442 } 2443 EXPORT_SYMBOL_GPL(ahci_port_resume); 2444 2445 #ifdef CONFIG_PM 2446 static void ahci_handle_s2idle(struct ata_port *ap) 2447 { 2448 void __iomem *port_mmio = ahci_port_base(ap); 2449 u32 devslp; 2450 2451 if (pm_suspend_via_firmware()) 2452 return; 2453 devslp = readl(port_mmio + PORT_DEVSLP); 2454 if ((devslp & PORT_DEVSLP_ADSE)) 2455 ata_msleep(ap, devslp_idle_timeout); 2456 } 2457 2458 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) 2459 { 2460 const char *emsg = NULL; 2461 int rc; 2462 2463 rc = ahci_deinit_port(ap, &emsg); 2464 if (rc == 0) 2465 ahci_power_down(ap); 2466 else { 2467 ata_port_err(ap, "%s (%d)\n", emsg, rc); 2468 ata_port_freeze(ap); 2469 } 2470 2471 if (acpi_storage_d3(ap->host->dev)) 2472 ahci_handle_s2idle(ap); 2473 2474 ahci_rpm_put_port(ap); 2475 return rc; 2476 } 2477 #endif 2478 2479 static int ahci_port_start(struct ata_port *ap) 2480 { 2481 struct ahci_host_priv *hpriv = ap->host->private_data; 2482 struct device *dev = ap->host->dev; 2483 struct ahci_port_priv *pp; 2484 void *mem; 2485 dma_addr_t mem_dma; 2486 size_t dma_sz, rx_fis_sz; 2487 2488 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 2489 if (!pp) 2490 return -ENOMEM; 2491 2492 if (ap->host->n_ports > 1) { 2493 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL); 2494 if (!pp->irq_desc) { 2495 devm_kfree(dev, pp); 2496 return -ENOMEM; 2497 } 2498 snprintf(pp->irq_desc, 8, 2499 "%s%d", dev_driver_string(dev), ap->port_no); 2500 } 2501 2502 /* check FBS capability */ 2503 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) { 2504 void __iomem *port_mmio = ahci_port_base(ap); 2505 u32 cmd = readl(port_mmio + PORT_CMD); 2506 if (cmd & PORT_CMD_FBSCP) 2507 pp->fbs_supported = true; 2508 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) { 2509 dev_info(dev, "port %d can do FBS, forcing FBSCP\n", 2510 ap->port_no); 2511 pp->fbs_supported = true; 2512 } else 2513 dev_warn(dev, "port %d is not capable of FBS\n", 2514 ap->port_no); 2515 } 2516 2517 if (pp->fbs_supported) { 2518 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ; 2519 rx_fis_sz = AHCI_RX_FIS_SZ * 16; 2520 } else { 2521 dma_sz = AHCI_PORT_PRIV_DMA_SZ; 2522 rx_fis_sz = AHCI_RX_FIS_SZ; 2523 } 2524 2525 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL); 2526 if (!mem) 2527 return -ENOMEM; 2528 2529 /* 2530 * First item in chunk of DMA memory: 32-slot command table, 2531 * 32 bytes each in size 2532 */ 2533 pp->cmd_slot = mem; 2534 pp->cmd_slot_dma = mem_dma; 2535 2536 mem += AHCI_CMD_SLOT_SZ; 2537 mem_dma += AHCI_CMD_SLOT_SZ; 2538 2539 /* 2540 * Second item: Received-FIS area 2541 */ 2542 pp->rx_fis = mem; 2543 pp->rx_fis_dma = mem_dma; 2544 2545 mem += rx_fis_sz; 2546 mem_dma += rx_fis_sz; 2547 2548 /* 2549 * Third item: data area for storing a single command 2550 * and its scatter-gather table 2551 */ 2552 pp->cmd_tbl = mem; 2553 pp->cmd_tbl_dma = mem_dma; 2554 2555 /* 2556 * Save off initial list of interrupts to be enabled. 2557 * This could be changed later 2558 */ 2559 pp->intr_mask = DEF_PORT_IRQ; 2560 2561 /* 2562 * Switch to per-port locking in case each port has its own MSI vector. 2563 */ 2564 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) { 2565 spin_lock_init(&pp->lock); 2566 ap->lock = &pp->lock; 2567 } 2568 2569 ap->private_data = pp; 2570 2571 /* engage engines, captain */ 2572 return ahci_port_resume(ap); 2573 } 2574 2575 static void ahci_port_stop(struct ata_port *ap) 2576 { 2577 const char *emsg = NULL; 2578 struct ahci_host_priv *hpriv = ap->host->private_data; 2579 void __iomem *host_mmio = hpriv->mmio; 2580 int rc; 2581 2582 /* de-initialize port */ 2583 rc = ahci_deinit_port(ap, &emsg); 2584 if (rc) 2585 ata_port_warn(ap, "%s (%d)\n", emsg, rc); 2586 2587 /* 2588 * Clear GHC.IS to prevent stuck INTx after disabling MSI and 2589 * re-enabling INTx. 2590 */ 2591 writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT); 2592 2593 ahci_rpm_put_port(ap); 2594 } 2595 2596 void ahci_print_info(struct ata_host *host, const char *scc_s) 2597 { 2598 struct ahci_host_priv *hpriv = host->private_data; 2599 u32 vers, cap, cap2, impl, speed; 2600 const char *speed_s; 2601 2602 vers = hpriv->version; 2603 cap = hpriv->cap; 2604 cap2 = hpriv->cap2; 2605 impl = hpriv->port_map; 2606 2607 speed = (cap >> 20) & 0xf; 2608 if (speed == 1) 2609 speed_s = "1.5"; 2610 else if (speed == 2) 2611 speed_s = "3"; 2612 else if (speed == 3) 2613 speed_s = "6"; 2614 else 2615 speed_s = "?"; 2616 2617 dev_info(host->dev, 2618 "AHCI %02x%02x.%02x%02x " 2619 "%u slots %u ports %s Gbps 0x%x impl %s mode\n" 2620 , 2621 2622 (vers >> 24) & 0xff, 2623 (vers >> 16) & 0xff, 2624 (vers >> 8) & 0xff, 2625 vers & 0xff, 2626 2627 ((cap >> 8) & 0x1f) + 1, 2628 (cap & 0x1f) + 1, 2629 speed_s, 2630 impl, 2631 scc_s); 2632 2633 dev_info(host->dev, 2634 "flags: " 2635 "%s%s%s%s%s%s%s" 2636 "%s%s%s%s%s%s%s" 2637 "%s%s%s%s%s%s%s" 2638 "%s%s\n" 2639 , 2640 2641 cap & HOST_CAP_64 ? "64bit " : "", 2642 cap & HOST_CAP_NCQ ? "ncq " : "", 2643 cap & HOST_CAP_SNTF ? "sntf " : "", 2644 cap & HOST_CAP_MPS ? "ilck " : "", 2645 cap & HOST_CAP_SSS ? "stag " : "", 2646 cap & HOST_CAP_ALPM ? "pm " : "", 2647 cap & HOST_CAP_LED ? "led " : "", 2648 cap & HOST_CAP_CLO ? "clo " : "", 2649 cap & HOST_CAP_ONLY ? "only " : "", 2650 cap & HOST_CAP_PMP ? "pmp " : "", 2651 cap & HOST_CAP_FBS ? "fbs " : "", 2652 cap & HOST_CAP_PIO_MULTI ? "pio " : "", 2653 cap & HOST_CAP_SSC ? "slum " : "", 2654 cap & HOST_CAP_PART ? "part " : "", 2655 cap & HOST_CAP_CCC ? "ccc " : "", 2656 cap & HOST_CAP_EMS ? "ems " : "", 2657 cap & HOST_CAP_SXS ? "sxs " : "", 2658 cap2 & HOST_CAP2_DESO ? "deso " : "", 2659 cap2 & HOST_CAP2_SADM ? "sadm " : "", 2660 cap2 & HOST_CAP2_SDS ? "sds " : "", 2661 cap2 & HOST_CAP2_APST ? "apst " : "", 2662 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "", 2663 cap2 & HOST_CAP2_BOH ? "boh " : "" 2664 ); 2665 } 2666 EXPORT_SYMBOL_GPL(ahci_print_info); 2667 2668 void ahci_set_em_messages(struct ahci_host_priv *hpriv, 2669 struct ata_port_info *pi) 2670 { 2671 u8 messages; 2672 void __iomem *mmio = hpriv->mmio; 2673 u32 em_loc = readl(mmio + HOST_EM_LOC); 2674 u32 em_ctl = readl(mmio + HOST_EM_CTL); 2675 2676 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS)) 2677 return; 2678 2679 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16; 2680 2681 if (messages) { 2682 /* store em_loc */ 2683 hpriv->em_loc = ((em_loc >> 16) * 4); 2684 hpriv->em_buf_sz = ((em_loc & 0xff) * 4); 2685 hpriv->em_msg_type = messages; 2686 pi->flags |= ATA_FLAG_EM; 2687 if (!(em_ctl & EM_CTL_ALHD)) 2688 pi->flags |= ATA_FLAG_SW_ACTIVITY; 2689 } 2690 } 2691 EXPORT_SYMBOL_GPL(ahci_set_em_messages); 2692 2693 static int ahci_host_activate_multi_irqs(struct ata_host *host, 2694 const struct scsi_host_template *sht) 2695 { 2696 struct ahci_host_priv *hpriv = host->private_data; 2697 int i, rc; 2698 2699 rc = ata_host_start(host); 2700 if (rc) 2701 return rc; 2702 /* 2703 * Requests IRQs according to AHCI-1.1 when multiple MSIs were 2704 * allocated. That is one MSI per port, starting from @irq. 2705 */ 2706 for (i = 0; i < host->n_ports; i++) { 2707 struct ahci_port_priv *pp = host->ports[i]->private_data; 2708 int irq = hpriv->get_irq_vector(host, i); 2709 2710 /* Do not receive interrupts sent by dummy ports */ 2711 if (!pp) { 2712 disable_irq(irq); 2713 continue; 2714 } 2715 2716 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard, 2717 0, pp->irq_desc, host->ports[i]); 2718 2719 if (rc) 2720 return rc; 2721 ata_port_desc(host->ports[i], "irq %d", irq); 2722 } 2723 2724 return ata_host_register(host, sht); 2725 } 2726 2727 /** 2728 * ahci_host_activate - start AHCI host, request IRQs and register it 2729 * @host: target ATA host 2730 * @sht: scsi_host_template to use when registering the host 2731 * 2732 * LOCKING: 2733 * Inherited from calling layer (may sleep). 2734 * 2735 * RETURNS: 2736 * 0 on success, -errno otherwise. 2737 */ 2738 int ahci_host_activate(struct ata_host *host, const struct scsi_host_template *sht) 2739 { 2740 struct ahci_host_priv *hpriv = host->private_data; 2741 int irq = hpriv->irq; 2742 int rc; 2743 2744 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) { 2745 if (hpriv->irq_handler && 2746 hpriv->irq_handler != ahci_single_level_irq_intr) 2747 dev_warn(host->dev, 2748 "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n"); 2749 if (!hpriv->get_irq_vector) { 2750 dev_err(host->dev, 2751 "AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n"); 2752 return -EIO; 2753 } 2754 2755 rc = ahci_host_activate_multi_irqs(host, sht); 2756 } else { 2757 rc = ata_host_activate(host, irq, hpriv->irq_handler, 2758 IRQF_SHARED, sht); 2759 } 2760 2761 2762 return rc; 2763 } 2764 EXPORT_SYMBOL_GPL(ahci_host_activate); 2765 2766 MODULE_AUTHOR("Jeff Garzik"); 2767 MODULE_DESCRIPTION("Common AHCI SATA low-level routines"); 2768 MODULE_LICENSE("GPL"); 2769