1 /* 2 * libahci.c - Common AHCI SATA low-level routines 3 * 4 * Maintained by: Tejun Heo <tj@kernel.org> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2004-2005 Red Hat, Inc. 9 * 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; see the file COPYING. If not, write to 23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * 26 * libata documentation is available via 'make {ps|pdf}docs', 27 * as Documentation/DocBook/libata.* 28 * 29 * AHCI hardware documentation: 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 32 * 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/gfp.h> 37 #include <linux/module.h> 38 #include <linux/blkdev.h> 39 #include <linux/delay.h> 40 #include <linux/interrupt.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/device.h> 43 #include <scsi/scsi_host.h> 44 #include <scsi/scsi_cmnd.h> 45 #include <linux/libata.h> 46 #include "ahci.h" 47 #include "libata.h" 48 49 static int ahci_skip_host_reset; 50 int ahci_ignore_sss; 51 EXPORT_SYMBOL_GPL(ahci_ignore_sss); 52 53 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); 54 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); 55 56 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444); 57 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)"); 58 59 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 60 unsigned hints); 61 static ssize_t ahci_led_show(struct ata_port *ap, char *buf); 62 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 63 size_t size); 64 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 65 ssize_t size); 66 67 68 69 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); 70 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); 71 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); 72 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc); 73 static int ahci_port_start(struct ata_port *ap); 74 static void ahci_port_stop(struct ata_port *ap); 75 static void ahci_qc_prep(struct ata_queued_cmd *qc); 76 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc); 77 static void ahci_freeze(struct ata_port *ap); 78 static void ahci_thaw(struct ata_port *ap); 79 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep); 80 static void ahci_enable_fbs(struct ata_port *ap); 81 static void ahci_disable_fbs(struct ata_port *ap); 82 static void ahci_pmp_attach(struct ata_port *ap); 83 static void ahci_pmp_detach(struct ata_port *ap); 84 static int ahci_softreset(struct ata_link *link, unsigned int *class, 85 unsigned long deadline); 86 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class, 87 unsigned long deadline); 88 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 89 unsigned long deadline); 90 static void ahci_postreset(struct ata_link *link, unsigned int *class); 91 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); 92 static void ahci_dev_config(struct ata_device *dev); 93 #ifdef CONFIG_PM 94 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); 95 #endif 96 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf); 97 static ssize_t ahci_activity_store(struct ata_device *dev, 98 enum sw_activity val); 99 static void ahci_init_sw_activity(struct ata_link *link); 100 101 static ssize_t ahci_show_host_caps(struct device *dev, 102 struct device_attribute *attr, char *buf); 103 static ssize_t ahci_show_host_cap2(struct device *dev, 104 struct device_attribute *attr, char *buf); 105 static ssize_t ahci_show_host_version(struct device *dev, 106 struct device_attribute *attr, char *buf); 107 static ssize_t ahci_show_port_cmd(struct device *dev, 108 struct device_attribute *attr, char *buf); 109 static ssize_t ahci_read_em_buffer(struct device *dev, 110 struct device_attribute *attr, char *buf); 111 static ssize_t ahci_store_em_buffer(struct device *dev, 112 struct device_attribute *attr, 113 const char *buf, size_t size); 114 static ssize_t ahci_show_em_supported(struct device *dev, 115 struct device_attribute *attr, char *buf); 116 117 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL); 118 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL); 119 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL); 120 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL); 121 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO, 122 ahci_read_em_buffer, ahci_store_em_buffer); 123 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL); 124 125 struct device_attribute *ahci_shost_attrs[] = { 126 &dev_attr_link_power_management_policy, 127 &dev_attr_em_message_type, 128 &dev_attr_em_message, 129 &dev_attr_ahci_host_caps, 130 &dev_attr_ahci_host_cap2, 131 &dev_attr_ahci_host_version, 132 &dev_attr_ahci_port_cmd, 133 &dev_attr_em_buffer, 134 &dev_attr_em_message_supported, 135 NULL 136 }; 137 EXPORT_SYMBOL_GPL(ahci_shost_attrs); 138 139 struct device_attribute *ahci_sdev_attrs[] = { 140 &dev_attr_sw_activity, 141 &dev_attr_unload_heads, 142 NULL 143 }; 144 EXPORT_SYMBOL_GPL(ahci_sdev_attrs); 145 146 struct ata_port_operations ahci_ops = { 147 .inherits = &sata_pmp_port_ops, 148 149 .qc_defer = ahci_pmp_qc_defer, 150 .qc_prep = ahci_qc_prep, 151 .qc_issue = ahci_qc_issue, 152 .qc_fill_rtf = ahci_qc_fill_rtf, 153 154 .freeze = ahci_freeze, 155 .thaw = ahci_thaw, 156 .softreset = ahci_softreset, 157 .hardreset = ahci_hardreset, 158 .postreset = ahci_postreset, 159 .pmp_softreset = ahci_softreset, 160 .error_handler = ahci_error_handler, 161 .post_internal_cmd = ahci_post_internal_cmd, 162 .dev_config = ahci_dev_config, 163 164 .scr_read = ahci_scr_read, 165 .scr_write = ahci_scr_write, 166 .pmp_attach = ahci_pmp_attach, 167 .pmp_detach = ahci_pmp_detach, 168 169 .set_lpm = ahci_set_lpm, 170 .em_show = ahci_led_show, 171 .em_store = ahci_led_store, 172 .sw_activity_show = ahci_activity_show, 173 .sw_activity_store = ahci_activity_store, 174 .transmit_led_message = ahci_transmit_led_message, 175 #ifdef CONFIG_PM 176 .port_suspend = ahci_port_suspend, 177 .port_resume = ahci_port_resume, 178 #endif 179 .port_start = ahci_port_start, 180 .port_stop = ahci_port_stop, 181 }; 182 EXPORT_SYMBOL_GPL(ahci_ops); 183 184 struct ata_port_operations ahci_pmp_retry_srst_ops = { 185 .inherits = &ahci_ops, 186 .softreset = ahci_pmp_retry_softreset, 187 }; 188 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops); 189 190 static bool ahci_em_messages __read_mostly = true; 191 EXPORT_SYMBOL_GPL(ahci_em_messages); 192 module_param(ahci_em_messages, bool, 0444); 193 /* add other LED protocol types when they become supported */ 194 MODULE_PARM_DESC(ahci_em_messages, 195 "AHCI Enclosure Management Message control (0 = off, 1 = on)"); 196 197 /* device sleep idle timeout in ms */ 198 static int devslp_idle_timeout __read_mostly = 1000; 199 module_param(devslp_idle_timeout, int, 0644); 200 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout"); 201 202 static void ahci_enable_ahci(void __iomem *mmio) 203 { 204 int i; 205 u32 tmp; 206 207 /* turn on AHCI_EN */ 208 tmp = readl(mmio + HOST_CTL); 209 if (tmp & HOST_AHCI_EN) 210 return; 211 212 /* Some controllers need AHCI_EN to be written multiple times. 213 * Try a few times before giving up. 214 */ 215 for (i = 0; i < 5; i++) { 216 tmp |= HOST_AHCI_EN; 217 writel(tmp, mmio + HOST_CTL); 218 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ 219 if (tmp & HOST_AHCI_EN) 220 return; 221 msleep(10); 222 } 223 224 WARN_ON(1); 225 } 226 227 static ssize_t ahci_show_host_caps(struct device *dev, 228 struct device_attribute *attr, char *buf) 229 { 230 struct Scsi_Host *shost = class_to_shost(dev); 231 struct ata_port *ap = ata_shost_to_port(shost); 232 struct ahci_host_priv *hpriv = ap->host->private_data; 233 234 return sprintf(buf, "%x\n", hpriv->cap); 235 } 236 237 static ssize_t ahci_show_host_cap2(struct device *dev, 238 struct device_attribute *attr, char *buf) 239 { 240 struct Scsi_Host *shost = class_to_shost(dev); 241 struct ata_port *ap = ata_shost_to_port(shost); 242 struct ahci_host_priv *hpriv = ap->host->private_data; 243 244 return sprintf(buf, "%x\n", hpriv->cap2); 245 } 246 247 static ssize_t ahci_show_host_version(struct device *dev, 248 struct device_attribute *attr, char *buf) 249 { 250 struct Scsi_Host *shost = class_to_shost(dev); 251 struct ata_port *ap = ata_shost_to_port(shost); 252 struct ahci_host_priv *hpriv = ap->host->private_data; 253 void __iomem *mmio = hpriv->mmio; 254 255 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION)); 256 } 257 258 static ssize_t ahci_show_port_cmd(struct device *dev, 259 struct device_attribute *attr, char *buf) 260 { 261 struct Scsi_Host *shost = class_to_shost(dev); 262 struct ata_port *ap = ata_shost_to_port(shost); 263 void __iomem *port_mmio = ahci_port_base(ap); 264 265 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD)); 266 } 267 268 static ssize_t ahci_read_em_buffer(struct device *dev, 269 struct device_attribute *attr, char *buf) 270 { 271 struct Scsi_Host *shost = class_to_shost(dev); 272 struct ata_port *ap = ata_shost_to_port(shost); 273 struct ahci_host_priv *hpriv = ap->host->private_data; 274 void __iomem *mmio = hpriv->mmio; 275 void __iomem *em_mmio = mmio + hpriv->em_loc; 276 u32 em_ctl, msg; 277 unsigned long flags; 278 size_t count; 279 int i; 280 281 spin_lock_irqsave(ap->lock, flags); 282 283 em_ctl = readl(mmio + HOST_EM_CTL); 284 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT || 285 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) { 286 spin_unlock_irqrestore(ap->lock, flags); 287 return -EINVAL; 288 } 289 290 if (!(em_ctl & EM_CTL_MR)) { 291 spin_unlock_irqrestore(ap->lock, flags); 292 return -EAGAIN; 293 } 294 295 if (!(em_ctl & EM_CTL_SMB)) 296 em_mmio += hpriv->em_buf_sz; 297 298 count = hpriv->em_buf_sz; 299 300 /* the count should not be larger than PAGE_SIZE */ 301 if (count > PAGE_SIZE) { 302 if (printk_ratelimit()) 303 ata_port_warn(ap, 304 "EM read buffer size too large: " 305 "buffer size %u, page size %lu\n", 306 hpriv->em_buf_sz, PAGE_SIZE); 307 count = PAGE_SIZE; 308 } 309 310 for (i = 0; i < count; i += 4) { 311 msg = readl(em_mmio + i); 312 buf[i] = msg & 0xff; 313 buf[i + 1] = (msg >> 8) & 0xff; 314 buf[i + 2] = (msg >> 16) & 0xff; 315 buf[i + 3] = (msg >> 24) & 0xff; 316 } 317 318 spin_unlock_irqrestore(ap->lock, flags); 319 320 return i; 321 } 322 323 static ssize_t ahci_store_em_buffer(struct device *dev, 324 struct device_attribute *attr, 325 const char *buf, size_t size) 326 { 327 struct Scsi_Host *shost = class_to_shost(dev); 328 struct ata_port *ap = ata_shost_to_port(shost); 329 struct ahci_host_priv *hpriv = ap->host->private_data; 330 void __iomem *mmio = hpriv->mmio; 331 void __iomem *em_mmio = mmio + hpriv->em_loc; 332 const unsigned char *msg_buf = buf; 333 u32 em_ctl, msg; 334 unsigned long flags; 335 int i; 336 337 /* check size validity */ 338 if (!(ap->flags & ATA_FLAG_EM) || 339 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) || 340 size % 4 || size > hpriv->em_buf_sz) 341 return -EINVAL; 342 343 spin_lock_irqsave(ap->lock, flags); 344 345 em_ctl = readl(mmio + HOST_EM_CTL); 346 if (em_ctl & EM_CTL_TM) { 347 spin_unlock_irqrestore(ap->lock, flags); 348 return -EBUSY; 349 } 350 351 for (i = 0; i < size; i += 4) { 352 msg = msg_buf[i] | msg_buf[i + 1] << 8 | 353 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24; 354 writel(msg, em_mmio + i); 355 } 356 357 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 358 359 spin_unlock_irqrestore(ap->lock, flags); 360 361 return size; 362 } 363 364 static ssize_t ahci_show_em_supported(struct device *dev, 365 struct device_attribute *attr, char *buf) 366 { 367 struct Scsi_Host *shost = class_to_shost(dev); 368 struct ata_port *ap = ata_shost_to_port(shost); 369 struct ahci_host_priv *hpriv = ap->host->private_data; 370 void __iomem *mmio = hpriv->mmio; 371 u32 em_ctl; 372 373 em_ctl = readl(mmio + HOST_EM_CTL); 374 375 return sprintf(buf, "%s%s%s%s\n", 376 em_ctl & EM_CTL_LED ? "led " : "", 377 em_ctl & EM_CTL_SAFTE ? "saf-te " : "", 378 em_ctl & EM_CTL_SES ? "ses-2 " : "", 379 em_ctl & EM_CTL_SGPIO ? "sgpio " : ""); 380 } 381 382 /** 383 * ahci_save_initial_config - Save and fixup initial config values 384 * @dev: target AHCI device 385 * @hpriv: host private area to store config values 386 * @force_port_map: force port map to a specified value 387 * @mask_port_map: mask out particular bits from port map 388 * 389 * Some registers containing configuration info might be setup by 390 * BIOS and might be cleared on reset. This function saves the 391 * initial values of those registers into @hpriv such that they 392 * can be restored after controller reset. 393 * 394 * If inconsistent, config values are fixed up by this function. 395 * 396 * If it is not set already this function sets hpriv->start_engine to 397 * ahci_start_engine. 398 * 399 * LOCKING: 400 * None. 401 */ 402 void ahci_save_initial_config(struct device *dev, 403 struct ahci_host_priv *hpriv, 404 unsigned int force_port_map, 405 unsigned int mask_port_map) 406 { 407 void __iomem *mmio = hpriv->mmio; 408 u32 cap, cap2, vers, port_map; 409 int i; 410 411 /* make sure AHCI mode is enabled before accessing CAP */ 412 ahci_enable_ahci(mmio); 413 414 /* Values prefixed with saved_ are written back to host after 415 * reset. Values without are used for driver operation. 416 */ 417 hpriv->saved_cap = cap = readl(mmio + HOST_CAP); 418 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); 419 420 /* CAP2 register is only defined for AHCI 1.2 and later */ 421 vers = readl(mmio + HOST_VERSION); 422 if ((vers >> 16) > 1 || 423 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200)) 424 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2); 425 else 426 hpriv->saved_cap2 = cap2 = 0; 427 428 /* some chips have errata preventing 64bit use */ 429 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { 430 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n"); 431 cap &= ~HOST_CAP_64; 432 } 433 434 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { 435 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n"); 436 cap &= ~HOST_CAP_NCQ; 437 } 438 439 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) { 440 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n"); 441 cap |= HOST_CAP_NCQ; 442 } 443 444 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { 445 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n"); 446 cap &= ~HOST_CAP_PMP; 447 } 448 449 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) { 450 dev_info(dev, 451 "controller can't do SNTF, turning off CAP_SNTF\n"); 452 cap &= ~HOST_CAP_SNTF; 453 } 454 455 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) { 456 dev_info(dev, 457 "controller can't do DEVSLP, turning off\n"); 458 cap2 &= ~HOST_CAP2_SDS; 459 cap2 &= ~HOST_CAP2_SADM; 460 } 461 462 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) { 463 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n"); 464 cap |= HOST_CAP_FBS; 465 } 466 467 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) { 468 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n"); 469 cap &= ~HOST_CAP_FBS; 470 } 471 472 if (force_port_map && port_map != force_port_map) { 473 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n", 474 port_map, force_port_map); 475 port_map = force_port_map; 476 } 477 478 if (mask_port_map) { 479 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n", 480 port_map, 481 port_map & mask_port_map); 482 port_map &= mask_port_map; 483 } 484 485 /* cross check port_map and cap.n_ports */ 486 if (port_map) { 487 int map_ports = 0; 488 489 for (i = 0; i < AHCI_MAX_PORTS; i++) 490 if (port_map & (1 << i)) 491 map_ports++; 492 493 /* If PI has more ports than n_ports, whine, clear 494 * port_map and let it be generated from n_ports. 495 */ 496 if (map_ports > ahci_nr_ports(cap)) { 497 dev_warn(dev, 498 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n", 499 port_map, ahci_nr_ports(cap)); 500 port_map = 0; 501 } 502 } 503 504 /* fabricate port_map from cap.nr_ports */ 505 if (!port_map) { 506 port_map = (1 << ahci_nr_ports(cap)) - 1; 507 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map); 508 509 /* write the fixed up value to the PI register */ 510 hpriv->saved_port_map = port_map; 511 } 512 513 /* record values to use during operation */ 514 hpriv->cap = cap; 515 hpriv->cap2 = cap2; 516 hpriv->port_map = port_map; 517 518 if (!hpriv->start_engine) 519 hpriv->start_engine = ahci_start_engine; 520 } 521 EXPORT_SYMBOL_GPL(ahci_save_initial_config); 522 523 /** 524 * ahci_restore_initial_config - Restore initial config 525 * @host: target ATA host 526 * 527 * Restore initial config stored by ahci_save_initial_config(). 528 * 529 * LOCKING: 530 * None. 531 */ 532 static void ahci_restore_initial_config(struct ata_host *host) 533 { 534 struct ahci_host_priv *hpriv = host->private_data; 535 void __iomem *mmio = hpriv->mmio; 536 537 writel(hpriv->saved_cap, mmio + HOST_CAP); 538 if (hpriv->saved_cap2) 539 writel(hpriv->saved_cap2, mmio + HOST_CAP2); 540 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); 541 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ 542 } 543 544 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) 545 { 546 static const int offset[] = { 547 [SCR_STATUS] = PORT_SCR_STAT, 548 [SCR_CONTROL] = PORT_SCR_CTL, 549 [SCR_ERROR] = PORT_SCR_ERR, 550 [SCR_ACTIVE] = PORT_SCR_ACT, 551 [SCR_NOTIFICATION] = PORT_SCR_NTF, 552 }; 553 struct ahci_host_priv *hpriv = ap->host->private_data; 554 555 if (sc_reg < ARRAY_SIZE(offset) && 556 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) 557 return offset[sc_reg]; 558 return 0; 559 } 560 561 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) 562 { 563 void __iomem *port_mmio = ahci_port_base(link->ap); 564 int offset = ahci_scr_offset(link->ap, sc_reg); 565 566 if (offset) { 567 *val = readl(port_mmio + offset); 568 return 0; 569 } 570 return -EINVAL; 571 } 572 573 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) 574 { 575 void __iomem *port_mmio = ahci_port_base(link->ap); 576 int offset = ahci_scr_offset(link->ap, sc_reg); 577 578 if (offset) { 579 writel(val, port_mmio + offset); 580 return 0; 581 } 582 return -EINVAL; 583 } 584 585 void ahci_start_engine(struct ata_port *ap) 586 { 587 void __iomem *port_mmio = ahci_port_base(ap); 588 u32 tmp; 589 590 /* start DMA */ 591 tmp = readl(port_mmio + PORT_CMD); 592 tmp |= PORT_CMD_START; 593 writel(tmp, port_mmio + PORT_CMD); 594 readl(port_mmio + PORT_CMD); /* flush */ 595 } 596 EXPORT_SYMBOL_GPL(ahci_start_engine); 597 598 int ahci_stop_engine(struct ata_port *ap) 599 { 600 void __iomem *port_mmio = ahci_port_base(ap); 601 u32 tmp; 602 603 tmp = readl(port_mmio + PORT_CMD); 604 605 /* check if the HBA is idle */ 606 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) 607 return 0; 608 609 /* setting HBA to idle */ 610 tmp &= ~PORT_CMD_START; 611 writel(tmp, port_mmio + PORT_CMD); 612 613 /* wait for engine to stop. This could be as long as 500 msec */ 614 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 615 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); 616 if (tmp & PORT_CMD_LIST_ON) 617 return -EIO; 618 619 return 0; 620 } 621 EXPORT_SYMBOL_GPL(ahci_stop_engine); 622 623 static void ahci_start_fis_rx(struct ata_port *ap) 624 { 625 void __iomem *port_mmio = ahci_port_base(ap); 626 struct ahci_host_priv *hpriv = ap->host->private_data; 627 struct ahci_port_priv *pp = ap->private_data; 628 u32 tmp; 629 630 /* set FIS registers */ 631 if (hpriv->cap & HOST_CAP_64) 632 writel((pp->cmd_slot_dma >> 16) >> 16, 633 port_mmio + PORT_LST_ADDR_HI); 634 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); 635 636 if (hpriv->cap & HOST_CAP_64) 637 writel((pp->rx_fis_dma >> 16) >> 16, 638 port_mmio + PORT_FIS_ADDR_HI); 639 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); 640 641 /* enable FIS reception */ 642 tmp = readl(port_mmio + PORT_CMD); 643 tmp |= PORT_CMD_FIS_RX; 644 writel(tmp, port_mmio + PORT_CMD); 645 646 /* flush */ 647 readl(port_mmio + PORT_CMD); 648 } 649 650 static int ahci_stop_fis_rx(struct ata_port *ap) 651 { 652 void __iomem *port_mmio = ahci_port_base(ap); 653 u32 tmp; 654 655 /* disable FIS reception */ 656 tmp = readl(port_mmio + PORT_CMD); 657 tmp &= ~PORT_CMD_FIS_RX; 658 writel(tmp, port_mmio + PORT_CMD); 659 660 /* wait for completion, spec says 500ms, give it 1000 */ 661 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON, 662 PORT_CMD_FIS_ON, 10, 1000); 663 if (tmp & PORT_CMD_FIS_ON) 664 return -EBUSY; 665 666 return 0; 667 } 668 669 static void ahci_power_up(struct ata_port *ap) 670 { 671 struct ahci_host_priv *hpriv = ap->host->private_data; 672 void __iomem *port_mmio = ahci_port_base(ap); 673 u32 cmd; 674 675 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 676 677 /* spin up device */ 678 if (hpriv->cap & HOST_CAP_SSS) { 679 cmd |= PORT_CMD_SPIN_UP; 680 writel(cmd, port_mmio + PORT_CMD); 681 } 682 683 /* wake up link */ 684 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); 685 } 686 687 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 688 unsigned int hints) 689 { 690 struct ata_port *ap = link->ap; 691 struct ahci_host_priv *hpriv = ap->host->private_data; 692 struct ahci_port_priv *pp = ap->private_data; 693 void __iomem *port_mmio = ahci_port_base(ap); 694 695 if (policy != ATA_LPM_MAX_POWER) { 696 /* 697 * Disable interrupts on Phy Ready. This keeps us from 698 * getting woken up due to spurious phy ready 699 * interrupts. 700 */ 701 pp->intr_mask &= ~PORT_IRQ_PHYRDY; 702 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 703 704 sata_link_scr_lpm(link, policy, false); 705 } 706 707 if (hpriv->cap & HOST_CAP_ALPM) { 708 u32 cmd = readl(port_mmio + PORT_CMD); 709 710 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) { 711 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE); 712 cmd |= PORT_CMD_ICC_ACTIVE; 713 714 writel(cmd, port_mmio + PORT_CMD); 715 readl(port_mmio + PORT_CMD); 716 717 /* wait 10ms to be sure we've come out of LPM state */ 718 ata_msleep(ap, 10); 719 } else { 720 cmd |= PORT_CMD_ALPE; 721 if (policy == ATA_LPM_MIN_POWER) 722 cmd |= PORT_CMD_ASP; 723 724 /* write out new cmd value */ 725 writel(cmd, port_mmio + PORT_CMD); 726 } 727 } 728 729 /* set aggressive device sleep */ 730 if ((hpriv->cap2 & HOST_CAP2_SDS) && 731 (hpriv->cap2 & HOST_CAP2_SADM) && 732 (link->device->flags & ATA_DFLAG_DEVSLP)) { 733 if (policy == ATA_LPM_MIN_POWER) 734 ahci_set_aggressive_devslp(ap, true); 735 else 736 ahci_set_aggressive_devslp(ap, false); 737 } 738 739 if (policy == ATA_LPM_MAX_POWER) { 740 sata_link_scr_lpm(link, policy, false); 741 742 /* turn PHYRDY IRQ back on */ 743 pp->intr_mask |= PORT_IRQ_PHYRDY; 744 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 745 } 746 747 return 0; 748 } 749 750 #ifdef CONFIG_PM 751 static void ahci_power_down(struct ata_port *ap) 752 { 753 struct ahci_host_priv *hpriv = ap->host->private_data; 754 void __iomem *port_mmio = ahci_port_base(ap); 755 u32 cmd, scontrol; 756 757 if (!(hpriv->cap & HOST_CAP_SSS)) 758 return; 759 760 /* put device into listen mode, first set PxSCTL.DET to 0 */ 761 scontrol = readl(port_mmio + PORT_SCR_CTL); 762 scontrol &= ~0xf; 763 writel(scontrol, port_mmio + PORT_SCR_CTL); 764 765 /* then set PxCMD.SUD to 0 */ 766 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 767 cmd &= ~PORT_CMD_SPIN_UP; 768 writel(cmd, port_mmio + PORT_CMD); 769 } 770 #endif 771 772 static void ahci_start_port(struct ata_port *ap) 773 { 774 struct ahci_host_priv *hpriv = ap->host->private_data; 775 struct ahci_port_priv *pp = ap->private_data; 776 struct ata_link *link; 777 struct ahci_em_priv *emp; 778 ssize_t rc; 779 int i; 780 781 /* enable FIS reception */ 782 ahci_start_fis_rx(ap); 783 784 /* enable DMA */ 785 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE)) 786 hpriv->start_engine(ap); 787 788 /* turn on LEDs */ 789 if (ap->flags & ATA_FLAG_EM) { 790 ata_for_each_link(link, ap, EDGE) { 791 emp = &pp->em_priv[link->pmp]; 792 793 /* EM Transmit bit maybe busy during init */ 794 for (i = 0; i < EM_MAX_RETRY; i++) { 795 rc = ap->ops->transmit_led_message(ap, 796 emp->led_state, 797 4); 798 /* 799 * If busy, give a breather but do not 800 * release EH ownership by using msleep() 801 * instead of ata_msleep(). EM Transmit 802 * bit is busy for the whole host and 803 * releasing ownership will cause other 804 * ports to fail the same way. 805 */ 806 if (rc == -EBUSY) 807 msleep(1); 808 else 809 break; 810 } 811 } 812 } 813 814 if (ap->flags & ATA_FLAG_SW_ACTIVITY) 815 ata_for_each_link(link, ap, EDGE) 816 ahci_init_sw_activity(link); 817 818 } 819 820 static int ahci_deinit_port(struct ata_port *ap, const char **emsg) 821 { 822 int rc; 823 824 /* disable DMA */ 825 rc = ahci_stop_engine(ap); 826 if (rc) { 827 *emsg = "failed to stop engine"; 828 return rc; 829 } 830 831 /* disable FIS reception */ 832 rc = ahci_stop_fis_rx(ap); 833 if (rc) { 834 *emsg = "failed stop FIS RX"; 835 return rc; 836 } 837 838 return 0; 839 } 840 841 int ahci_reset_controller(struct ata_host *host) 842 { 843 struct ahci_host_priv *hpriv = host->private_data; 844 void __iomem *mmio = hpriv->mmio; 845 u32 tmp; 846 847 /* we must be in AHCI mode, before using anything 848 * AHCI-specific, such as HOST_RESET. 849 */ 850 ahci_enable_ahci(mmio); 851 852 /* global controller reset */ 853 if (!ahci_skip_host_reset) { 854 tmp = readl(mmio + HOST_CTL); 855 if ((tmp & HOST_RESET) == 0) { 856 writel(tmp | HOST_RESET, mmio + HOST_CTL); 857 readl(mmio + HOST_CTL); /* flush */ 858 } 859 860 /* 861 * to perform host reset, OS should set HOST_RESET 862 * and poll until this bit is read to be "0". 863 * reset must complete within 1 second, or 864 * the hardware should be considered fried. 865 */ 866 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET, 867 HOST_RESET, 10, 1000); 868 869 if (tmp & HOST_RESET) { 870 dev_err(host->dev, "controller reset failed (0x%x)\n", 871 tmp); 872 return -EIO; 873 } 874 875 /* turn on AHCI mode */ 876 ahci_enable_ahci(mmio); 877 878 /* Some registers might be cleared on reset. Restore 879 * initial values. 880 */ 881 ahci_restore_initial_config(host); 882 } else 883 dev_info(host->dev, "skipping global host reset\n"); 884 885 return 0; 886 } 887 EXPORT_SYMBOL_GPL(ahci_reset_controller); 888 889 static void ahci_sw_activity(struct ata_link *link) 890 { 891 struct ata_port *ap = link->ap; 892 struct ahci_port_priv *pp = ap->private_data; 893 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 894 895 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY)) 896 return; 897 898 emp->activity++; 899 if (!timer_pending(&emp->timer)) 900 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10)); 901 } 902 903 static void ahci_sw_activity_blink(unsigned long arg) 904 { 905 struct ata_link *link = (struct ata_link *)arg; 906 struct ata_port *ap = link->ap; 907 struct ahci_port_priv *pp = ap->private_data; 908 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 909 unsigned long led_message = emp->led_state; 910 u32 activity_led_state; 911 unsigned long flags; 912 913 led_message &= EM_MSG_LED_VALUE; 914 led_message |= ap->port_no | (link->pmp << 8); 915 916 /* check to see if we've had activity. If so, 917 * toggle state of LED and reset timer. If not, 918 * turn LED to desired idle state. 919 */ 920 spin_lock_irqsave(ap->lock, flags); 921 if (emp->saved_activity != emp->activity) { 922 emp->saved_activity = emp->activity; 923 /* get the current LED state */ 924 activity_led_state = led_message & EM_MSG_LED_VALUE_ON; 925 926 if (activity_led_state) 927 activity_led_state = 0; 928 else 929 activity_led_state = 1; 930 931 /* clear old state */ 932 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 933 934 /* toggle state */ 935 led_message |= (activity_led_state << 16); 936 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100)); 937 } else { 938 /* switch to idle */ 939 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 940 if (emp->blink_policy == BLINK_OFF) 941 led_message |= (1 << 16); 942 } 943 spin_unlock_irqrestore(ap->lock, flags); 944 ap->ops->transmit_led_message(ap, led_message, 4); 945 } 946 947 static void ahci_init_sw_activity(struct ata_link *link) 948 { 949 struct ata_port *ap = link->ap; 950 struct ahci_port_priv *pp = ap->private_data; 951 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 952 953 /* init activity stats, setup timer */ 954 emp->saved_activity = emp->activity = 0; 955 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link); 956 957 /* check our blink policy and set flag for link if it's enabled */ 958 if (emp->blink_policy) 959 link->flags |= ATA_LFLAG_SW_ACTIVITY; 960 } 961 962 int ahci_reset_em(struct ata_host *host) 963 { 964 struct ahci_host_priv *hpriv = host->private_data; 965 void __iomem *mmio = hpriv->mmio; 966 u32 em_ctl; 967 968 em_ctl = readl(mmio + HOST_EM_CTL); 969 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST)) 970 return -EINVAL; 971 972 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL); 973 return 0; 974 } 975 EXPORT_SYMBOL_GPL(ahci_reset_em); 976 977 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 978 ssize_t size) 979 { 980 struct ahci_host_priv *hpriv = ap->host->private_data; 981 struct ahci_port_priv *pp = ap->private_data; 982 void __iomem *mmio = hpriv->mmio; 983 u32 em_ctl; 984 u32 message[] = {0, 0}; 985 unsigned long flags; 986 int pmp; 987 struct ahci_em_priv *emp; 988 989 /* get the slot number from the message */ 990 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 991 if (pmp < EM_MAX_SLOTS) 992 emp = &pp->em_priv[pmp]; 993 else 994 return -EINVAL; 995 996 spin_lock_irqsave(ap->lock, flags); 997 998 /* 999 * if we are still busy transmitting a previous message, 1000 * do not allow 1001 */ 1002 em_ctl = readl(mmio + HOST_EM_CTL); 1003 if (em_ctl & EM_CTL_TM) { 1004 spin_unlock_irqrestore(ap->lock, flags); 1005 return -EBUSY; 1006 } 1007 1008 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) { 1009 /* 1010 * create message header - this is all zero except for 1011 * the message size, which is 4 bytes. 1012 */ 1013 message[0] |= (4 << 8); 1014 1015 /* ignore 0:4 of byte zero, fill in port info yourself */ 1016 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no); 1017 1018 /* write message to EM_LOC */ 1019 writel(message[0], mmio + hpriv->em_loc); 1020 writel(message[1], mmio + hpriv->em_loc+4); 1021 1022 /* 1023 * tell hardware to transmit the message 1024 */ 1025 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 1026 } 1027 1028 /* save off new led state for port/slot */ 1029 emp->led_state = state; 1030 1031 spin_unlock_irqrestore(ap->lock, flags); 1032 return size; 1033 } 1034 1035 static ssize_t ahci_led_show(struct ata_port *ap, char *buf) 1036 { 1037 struct ahci_port_priv *pp = ap->private_data; 1038 struct ata_link *link; 1039 struct ahci_em_priv *emp; 1040 int rc = 0; 1041 1042 ata_for_each_link(link, ap, EDGE) { 1043 emp = &pp->em_priv[link->pmp]; 1044 rc += sprintf(buf, "%lx\n", emp->led_state); 1045 } 1046 return rc; 1047 } 1048 1049 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 1050 size_t size) 1051 { 1052 unsigned int state; 1053 int pmp; 1054 struct ahci_port_priv *pp = ap->private_data; 1055 struct ahci_em_priv *emp; 1056 1057 if (kstrtouint(buf, 0, &state) < 0) 1058 return -EINVAL; 1059 1060 /* get the slot number from the message */ 1061 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1062 if (pmp < EM_MAX_SLOTS) 1063 emp = &pp->em_priv[pmp]; 1064 else 1065 return -EINVAL; 1066 1067 /* mask off the activity bits if we are in sw_activity 1068 * mode, user should turn off sw_activity before setting 1069 * activity led through em_message 1070 */ 1071 if (emp->blink_policy) 1072 state &= ~EM_MSG_LED_VALUE_ACTIVITY; 1073 1074 return ap->ops->transmit_led_message(ap, state, size); 1075 } 1076 1077 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val) 1078 { 1079 struct ata_link *link = dev->link; 1080 struct ata_port *ap = link->ap; 1081 struct ahci_port_priv *pp = ap->private_data; 1082 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1083 u32 port_led_state = emp->led_state; 1084 1085 /* save the desired Activity LED behavior */ 1086 if (val == OFF) { 1087 /* clear LFLAG */ 1088 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY); 1089 1090 /* set the LED to OFF */ 1091 port_led_state &= EM_MSG_LED_VALUE_OFF; 1092 port_led_state |= (ap->port_no | (link->pmp << 8)); 1093 ap->ops->transmit_led_message(ap, port_led_state, 4); 1094 } else { 1095 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1096 if (val == BLINK_OFF) { 1097 /* set LED to ON for idle */ 1098 port_led_state &= EM_MSG_LED_VALUE_OFF; 1099 port_led_state |= (ap->port_no | (link->pmp << 8)); 1100 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */ 1101 ap->ops->transmit_led_message(ap, port_led_state, 4); 1102 } 1103 } 1104 emp->blink_policy = val; 1105 return 0; 1106 } 1107 1108 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf) 1109 { 1110 struct ata_link *link = dev->link; 1111 struct ata_port *ap = link->ap; 1112 struct ahci_port_priv *pp = ap->private_data; 1113 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1114 1115 /* display the saved value of activity behavior for this 1116 * disk. 1117 */ 1118 return sprintf(buf, "%d\n", emp->blink_policy); 1119 } 1120 1121 static void ahci_port_init(struct device *dev, struct ata_port *ap, 1122 int port_no, void __iomem *mmio, 1123 void __iomem *port_mmio) 1124 { 1125 const char *emsg = NULL; 1126 int rc; 1127 u32 tmp; 1128 1129 /* make sure port is not active */ 1130 rc = ahci_deinit_port(ap, &emsg); 1131 if (rc) 1132 dev_warn(dev, "%s (%d)\n", emsg, rc); 1133 1134 /* clear SError */ 1135 tmp = readl(port_mmio + PORT_SCR_ERR); 1136 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); 1137 writel(tmp, port_mmio + PORT_SCR_ERR); 1138 1139 /* clear port IRQ */ 1140 tmp = readl(port_mmio + PORT_IRQ_STAT); 1141 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 1142 if (tmp) 1143 writel(tmp, port_mmio + PORT_IRQ_STAT); 1144 1145 writel(1 << port_no, mmio + HOST_IRQ_STAT); 1146 } 1147 1148 void ahci_init_controller(struct ata_host *host) 1149 { 1150 struct ahci_host_priv *hpriv = host->private_data; 1151 void __iomem *mmio = hpriv->mmio; 1152 int i; 1153 void __iomem *port_mmio; 1154 u32 tmp; 1155 1156 for (i = 0; i < host->n_ports; i++) { 1157 struct ata_port *ap = host->ports[i]; 1158 1159 port_mmio = ahci_port_base(ap); 1160 if (ata_port_is_dummy(ap)) 1161 continue; 1162 1163 ahci_port_init(host->dev, ap, i, mmio, port_mmio); 1164 } 1165 1166 tmp = readl(mmio + HOST_CTL); 1167 VPRINTK("HOST_CTL 0x%x\n", tmp); 1168 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); 1169 tmp = readl(mmio + HOST_CTL); 1170 VPRINTK("HOST_CTL 0x%x\n", tmp); 1171 } 1172 EXPORT_SYMBOL_GPL(ahci_init_controller); 1173 1174 static void ahci_dev_config(struct ata_device *dev) 1175 { 1176 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data; 1177 1178 if (hpriv->flags & AHCI_HFLAG_SECT255) { 1179 dev->max_sectors = 255; 1180 ata_dev_info(dev, 1181 "SB600 AHCI: limiting to 255 sectors per cmd\n"); 1182 } 1183 } 1184 1185 unsigned int ahci_dev_classify(struct ata_port *ap) 1186 { 1187 void __iomem *port_mmio = ahci_port_base(ap); 1188 struct ata_taskfile tf; 1189 u32 tmp; 1190 1191 tmp = readl(port_mmio + PORT_SIG); 1192 tf.lbah = (tmp >> 24) & 0xff; 1193 tf.lbam = (tmp >> 16) & 0xff; 1194 tf.lbal = (tmp >> 8) & 0xff; 1195 tf.nsect = (tmp) & 0xff; 1196 1197 return ata_dev_classify(&tf); 1198 } 1199 EXPORT_SYMBOL_GPL(ahci_dev_classify); 1200 1201 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 1202 u32 opts) 1203 { 1204 dma_addr_t cmd_tbl_dma; 1205 1206 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; 1207 1208 pp->cmd_slot[tag].opts = cpu_to_le32(opts); 1209 pp->cmd_slot[tag].status = 0; 1210 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); 1211 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); 1212 } 1213 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot); 1214 1215 int ahci_kick_engine(struct ata_port *ap) 1216 { 1217 void __iomem *port_mmio = ahci_port_base(ap); 1218 struct ahci_host_priv *hpriv = ap->host->private_data; 1219 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1220 u32 tmp; 1221 int busy, rc; 1222 1223 /* stop engine */ 1224 rc = ahci_stop_engine(ap); 1225 if (rc) 1226 goto out_restart; 1227 1228 /* need to do CLO? 1229 * always do CLO if PMP is attached (AHCI-1.3 9.2) 1230 */ 1231 busy = status & (ATA_BUSY | ATA_DRQ); 1232 if (!busy && !sata_pmp_attached(ap)) { 1233 rc = 0; 1234 goto out_restart; 1235 } 1236 1237 if (!(hpriv->cap & HOST_CAP_CLO)) { 1238 rc = -EOPNOTSUPP; 1239 goto out_restart; 1240 } 1241 1242 /* perform CLO */ 1243 tmp = readl(port_mmio + PORT_CMD); 1244 tmp |= PORT_CMD_CLO; 1245 writel(tmp, port_mmio + PORT_CMD); 1246 1247 rc = 0; 1248 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 1249 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); 1250 if (tmp & PORT_CMD_CLO) 1251 rc = -EIO; 1252 1253 /* restart engine */ 1254 out_restart: 1255 hpriv->start_engine(ap); 1256 return rc; 1257 } 1258 EXPORT_SYMBOL_GPL(ahci_kick_engine); 1259 1260 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, 1261 struct ata_taskfile *tf, int is_cmd, u16 flags, 1262 unsigned long timeout_msec) 1263 { 1264 const u32 cmd_fis_len = 5; /* five dwords */ 1265 struct ahci_port_priv *pp = ap->private_data; 1266 void __iomem *port_mmio = ahci_port_base(ap); 1267 u8 *fis = pp->cmd_tbl; 1268 u32 tmp; 1269 1270 /* prep the command */ 1271 ata_tf_to_fis(tf, pmp, is_cmd, fis); 1272 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); 1273 1274 /* issue & wait */ 1275 writel(1, port_mmio + PORT_CMD_ISSUE); 1276 1277 if (timeout_msec) { 1278 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE, 1279 0x1, 0x1, 1, timeout_msec); 1280 if (tmp & 0x1) { 1281 ahci_kick_engine(ap); 1282 return -EBUSY; 1283 } 1284 } else 1285 readl(port_mmio + PORT_CMD_ISSUE); /* flush */ 1286 1287 return 0; 1288 } 1289 1290 int ahci_do_softreset(struct ata_link *link, unsigned int *class, 1291 int pmp, unsigned long deadline, 1292 int (*check_ready)(struct ata_link *link)) 1293 { 1294 struct ata_port *ap = link->ap; 1295 struct ahci_host_priv *hpriv = ap->host->private_data; 1296 struct ahci_port_priv *pp = ap->private_data; 1297 const char *reason = NULL; 1298 unsigned long now, msecs; 1299 struct ata_taskfile tf; 1300 bool fbs_disabled = false; 1301 int rc; 1302 1303 DPRINTK("ENTER\n"); 1304 1305 /* prepare for SRST (AHCI-1.1 10.4.1) */ 1306 rc = ahci_kick_engine(ap); 1307 if (rc && rc != -EOPNOTSUPP) 1308 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc); 1309 1310 /* 1311 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall 1312 * clear PxFBS.EN to '0' prior to issuing software reset to devices 1313 * that is attached to port multiplier. 1314 */ 1315 if (!ata_is_host_link(link) && pp->fbs_enabled) { 1316 ahci_disable_fbs(ap); 1317 fbs_disabled = true; 1318 } 1319 1320 ata_tf_init(link->device, &tf); 1321 1322 /* issue the first D2H Register FIS */ 1323 msecs = 0; 1324 now = jiffies; 1325 if (time_after(deadline, now)) 1326 msecs = jiffies_to_msecs(deadline - now); 1327 1328 tf.ctl |= ATA_SRST; 1329 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, 1330 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { 1331 rc = -EIO; 1332 reason = "1st FIS failed"; 1333 goto fail; 1334 } 1335 1336 /* spec says at least 5us, but be generous and sleep for 1ms */ 1337 ata_msleep(ap, 1); 1338 1339 /* issue the second D2H Register FIS */ 1340 tf.ctl &= ~ATA_SRST; 1341 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); 1342 1343 /* wait for link to become ready */ 1344 rc = ata_wait_after_reset(link, deadline, check_ready); 1345 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) { 1346 /* 1347 * Workaround for cases where link online status can't 1348 * be trusted. Treat device readiness timeout as link 1349 * offline. 1350 */ 1351 ata_link_info(link, "device not ready, treating as offline\n"); 1352 *class = ATA_DEV_NONE; 1353 } else if (rc) { 1354 /* link occupied, -ENODEV too is an error */ 1355 reason = "device not ready"; 1356 goto fail; 1357 } else 1358 *class = ahci_dev_classify(ap); 1359 1360 /* re-enable FBS if disabled before */ 1361 if (fbs_disabled) 1362 ahci_enable_fbs(ap); 1363 1364 DPRINTK("EXIT, class=%u\n", *class); 1365 return 0; 1366 1367 fail: 1368 ata_link_err(link, "softreset failed (%s)\n", reason); 1369 return rc; 1370 } 1371 1372 int ahci_check_ready(struct ata_link *link) 1373 { 1374 void __iomem *port_mmio = ahci_port_base(link->ap); 1375 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1376 1377 return ata_check_ready(status); 1378 } 1379 EXPORT_SYMBOL_GPL(ahci_check_ready); 1380 1381 static int ahci_softreset(struct ata_link *link, unsigned int *class, 1382 unsigned long deadline) 1383 { 1384 int pmp = sata_srst_pmp(link); 1385 1386 DPRINTK("ENTER\n"); 1387 1388 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready); 1389 } 1390 EXPORT_SYMBOL_GPL(ahci_do_softreset); 1391 1392 static int ahci_bad_pmp_check_ready(struct ata_link *link) 1393 { 1394 void __iomem *port_mmio = ahci_port_base(link->ap); 1395 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1396 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT); 1397 1398 /* 1399 * There is no need to check TFDATA if BAD PMP is found due to HW bug, 1400 * which can save timeout delay. 1401 */ 1402 if (irq_status & PORT_IRQ_BAD_PMP) 1403 return -EIO; 1404 1405 return ata_check_ready(status); 1406 } 1407 1408 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class, 1409 unsigned long deadline) 1410 { 1411 struct ata_port *ap = link->ap; 1412 void __iomem *port_mmio = ahci_port_base(ap); 1413 int pmp = sata_srst_pmp(link); 1414 int rc; 1415 u32 irq_sts; 1416 1417 DPRINTK("ENTER\n"); 1418 1419 rc = ahci_do_softreset(link, class, pmp, deadline, 1420 ahci_bad_pmp_check_ready); 1421 1422 /* 1423 * Soft reset fails with IPMS set when PMP is enabled but 1424 * SATA HDD/ODD is connected to SATA port, do soft reset 1425 * again to port 0. 1426 */ 1427 if (rc == -EIO) { 1428 irq_sts = readl(port_mmio + PORT_IRQ_STAT); 1429 if (irq_sts & PORT_IRQ_BAD_PMP) { 1430 ata_link_warn(link, 1431 "applying PMP SRST workaround " 1432 "and retrying\n"); 1433 rc = ahci_do_softreset(link, class, 0, deadline, 1434 ahci_check_ready); 1435 } 1436 } 1437 1438 return rc; 1439 } 1440 1441 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 1442 unsigned long deadline) 1443 { 1444 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 1445 struct ata_port *ap = link->ap; 1446 struct ahci_port_priv *pp = ap->private_data; 1447 struct ahci_host_priv *hpriv = ap->host->private_data; 1448 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 1449 struct ata_taskfile tf; 1450 bool online; 1451 int rc; 1452 1453 DPRINTK("ENTER\n"); 1454 1455 ahci_stop_engine(ap); 1456 1457 /* clear D2H reception area to properly wait for D2H FIS */ 1458 ata_tf_init(link->device, &tf); 1459 tf.command = ATA_BUSY; 1460 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 1461 1462 rc = sata_link_hardreset(link, timing, deadline, &online, 1463 ahci_check_ready); 1464 1465 hpriv->start_engine(ap); 1466 1467 if (online) 1468 *class = ahci_dev_classify(ap); 1469 1470 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 1471 return rc; 1472 } 1473 1474 static void ahci_postreset(struct ata_link *link, unsigned int *class) 1475 { 1476 struct ata_port *ap = link->ap; 1477 void __iomem *port_mmio = ahci_port_base(ap); 1478 u32 new_tmp, tmp; 1479 1480 ata_std_postreset(link, class); 1481 1482 /* Make sure port's ATAPI bit is set appropriately */ 1483 new_tmp = tmp = readl(port_mmio + PORT_CMD); 1484 if (*class == ATA_DEV_ATAPI) 1485 new_tmp |= PORT_CMD_ATAPI; 1486 else 1487 new_tmp &= ~PORT_CMD_ATAPI; 1488 if (new_tmp != tmp) { 1489 writel(new_tmp, port_mmio + PORT_CMD); 1490 readl(port_mmio + PORT_CMD); /* flush */ 1491 } 1492 } 1493 1494 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) 1495 { 1496 struct scatterlist *sg; 1497 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; 1498 unsigned int si; 1499 1500 VPRINTK("ENTER\n"); 1501 1502 /* 1503 * Next, the S/G list. 1504 */ 1505 for_each_sg(qc->sg, sg, qc->n_elem, si) { 1506 dma_addr_t addr = sg_dma_address(sg); 1507 u32 sg_len = sg_dma_len(sg); 1508 1509 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); 1510 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); 1511 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); 1512 } 1513 1514 return si; 1515 } 1516 1517 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc) 1518 { 1519 struct ata_port *ap = qc->ap; 1520 struct ahci_port_priv *pp = ap->private_data; 1521 1522 if (!sata_pmp_attached(ap) || pp->fbs_enabled) 1523 return ata_std_qc_defer(qc); 1524 else 1525 return sata_pmp_qc_defer_cmd_switch(qc); 1526 } 1527 1528 static void ahci_qc_prep(struct ata_queued_cmd *qc) 1529 { 1530 struct ata_port *ap = qc->ap; 1531 struct ahci_port_priv *pp = ap->private_data; 1532 int is_atapi = ata_is_atapi(qc->tf.protocol); 1533 void *cmd_tbl; 1534 u32 opts; 1535 const u32 cmd_fis_len = 5; /* five dwords */ 1536 unsigned int n_elem; 1537 1538 /* 1539 * Fill in command table information. First, the header, 1540 * a SATA Register - Host to Device command FIS. 1541 */ 1542 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; 1543 1544 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); 1545 if (is_atapi) { 1546 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); 1547 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); 1548 } 1549 1550 n_elem = 0; 1551 if (qc->flags & ATA_QCFLAG_DMAMAP) 1552 n_elem = ahci_fill_sg(qc, cmd_tbl); 1553 1554 /* 1555 * Fill in command slot information. 1556 */ 1557 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); 1558 if (qc->tf.flags & ATA_TFLAG_WRITE) 1559 opts |= AHCI_CMD_WRITE; 1560 if (is_atapi) 1561 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; 1562 1563 ahci_fill_cmd_slot(pp, qc->tag, opts); 1564 } 1565 1566 static void ahci_fbs_dec_intr(struct ata_port *ap) 1567 { 1568 struct ahci_port_priv *pp = ap->private_data; 1569 void __iomem *port_mmio = ahci_port_base(ap); 1570 u32 fbs = readl(port_mmio + PORT_FBS); 1571 int retries = 3; 1572 1573 DPRINTK("ENTER\n"); 1574 BUG_ON(!pp->fbs_enabled); 1575 1576 /* time to wait for DEC is not specified by AHCI spec, 1577 * add a retry loop for safety. 1578 */ 1579 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS); 1580 fbs = readl(port_mmio + PORT_FBS); 1581 while ((fbs & PORT_FBS_DEC) && retries--) { 1582 udelay(1); 1583 fbs = readl(port_mmio + PORT_FBS); 1584 } 1585 1586 if (fbs & PORT_FBS_DEC) 1587 dev_err(ap->host->dev, "failed to clear device error\n"); 1588 } 1589 1590 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) 1591 { 1592 struct ahci_host_priv *hpriv = ap->host->private_data; 1593 struct ahci_port_priv *pp = ap->private_data; 1594 struct ata_eh_info *host_ehi = &ap->link.eh_info; 1595 struct ata_link *link = NULL; 1596 struct ata_queued_cmd *active_qc; 1597 struct ata_eh_info *active_ehi; 1598 bool fbs_need_dec = false; 1599 u32 serror; 1600 1601 /* determine active link with error */ 1602 if (pp->fbs_enabled) { 1603 void __iomem *port_mmio = ahci_port_base(ap); 1604 u32 fbs = readl(port_mmio + PORT_FBS); 1605 int pmp = fbs >> PORT_FBS_DWE_OFFSET; 1606 1607 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) { 1608 link = &ap->pmp_link[pmp]; 1609 fbs_need_dec = true; 1610 } 1611 1612 } else 1613 ata_for_each_link(link, ap, EDGE) 1614 if (ata_link_active(link)) 1615 break; 1616 1617 if (!link) 1618 link = &ap->link; 1619 1620 active_qc = ata_qc_from_tag(ap, link->active_tag); 1621 active_ehi = &link->eh_info; 1622 1623 /* record irq stat */ 1624 ata_ehi_clear_desc(host_ehi); 1625 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); 1626 1627 /* AHCI needs SError cleared; otherwise, it might lock up */ 1628 ahci_scr_read(&ap->link, SCR_ERROR, &serror); 1629 ahci_scr_write(&ap->link, SCR_ERROR, serror); 1630 host_ehi->serror |= serror; 1631 1632 /* some controllers set IRQ_IF_ERR on device errors, ignore it */ 1633 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) 1634 irq_stat &= ~PORT_IRQ_IF_ERR; 1635 1636 if (irq_stat & PORT_IRQ_TF_ERR) { 1637 /* If qc is active, charge it; otherwise, the active 1638 * link. There's no active qc on NCQ errors. It will 1639 * be determined by EH by reading log page 10h. 1640 */ 1641 if (active_qc) 1642 active_qc->err_mask |= AC_ERR_DEV; 1643 else 1644 active_ehi->err_mask |= AC_ERR_DEV; 1645 1646 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) 1647 host_ehi->serror &= ~SERR_INTERNAL; 1648 } 1649 1650 if (irq_stat & PORT_IRQ_UNK_FIS) { 1651 u32 *unk = pp->rx_fis + RX_FIS_UNK; 1652 1653 active_ehi->err_mask |= AC_ERR_HSM; 1654 active_ehi->action |= ATA_EH_RESET; 1655 ata_ehi_push_desc(active_ehi, 1656 "unknown FIS %08x %08x %08x %08x" , 1657 unk[0], unk[1], unk[2], unk[3]); 1658 } 1659 1660 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) { 1661 active_ehi->err_mask |= AC_ERR_HSM; 1662 active_ehi->action |= ATA_EH_RESET; 1663 ata_ehi_push_desc(active_ehi, "incorrect PMP"); 1664 } 1665 1666 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { 1667 host_ehi->err_mask |= AC_ERR_HOST_BUS; 1668 host_ehi->action |= ATA_EH_RESET; 1669 ata_ehi_push_desc(host_ehi, "host bus error"); 1670 } 1671 1672 if (irq_stat & PORT_IRQ_IF_ERR) { 1673 if (fbs_need_dec) 1674 active_ehi->err_mask |= AC_ERR_DEV; 1675 else { 1676 host_ehi->err_mask |= AC_ERR_ATA_BUS; 1677 host_ehi->action |= ATA_EH_RESET; 1678 } 1679 1680 ata_ehi_push_desc(host_ehi, "interface fatal error"); 1681 } 1682 1683 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { 1684 ata_ehi_hotplugged(host_ehi); 1685 ata_ehi_push_desc(host_ehi, "%s", 1686 irq_stat & PORT_IRQ_CONNECT ? 1687 "connection status changed" : "PHY RDY changed"); 1688 } 1689 1690 /* okay, let's hand over to EH */ 1691 1692 if (irq_stat & PORT_IRQ_FREEZE) 1693 ata_port_freeze(ap); 1694 else if (fbs_need_dec) { 1695 ata_link_abort(link); 1696 ahci_fbs_dec_intr(ap); 1697 } else 1698 ata_port_abort(ap); 1699 } 1700 1701 static void ahci_handle_port_interrupt(struct ata_port *ap, 1702 void __iomem *port_mmio, u32 status) 1703 { 1704 struct ata_eh_info *ehi = &ap->link.eh_info; 1705 struct ahci_port_priv *pp = ap->private_data; 1706 struct ahci_host_priv *hpriv = ap->host->private_data; 1707 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING); 1708 u32 qc_active = 0; 1709 int rc; 1710 1711 /* ignore BAD_PMP while resetting */ 1712 if (unlikely(resetting)) 1713 status &= ~PORT_IRQ_BAD_PMP; 1714 1715 /* if LPM is enabled, PHYRDY doesn't mean anything */ 1716 if (ap->link.lpm_policy > ATA_LPM_MAX_POWER) { 1717 status &= ~PORT_IRQ_PHYRDY; 1718 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG); 1719 } 1720 1721 if (unlikely(status & PORT_IRQ_ERROR)) { 1722 ahci_error_intr(ap, status); 1723 return; 1724 } 1725 1726 if (status & PORT_IRQ_SDB_FIS) { 1727 /* If SNotification is available, leave notification 1728 * handling to sata_async_notification(). If not, 1729 * emulate it by snooping SDB FIS RX area. 1730 * 1731 * Snooping FIS RX area is probably cheaper than 1732 * poking SNotification but some constrollers which 1733 * implement SNotification, ICH9 for example, don't 1734 * store AN SDB FIS into receive area. 1735 */ 1736 if (hpriv->cap & HOST_CAP_SNTF) 1737 sata_async_notification(ap); 1738 else { 1739 /* If the 'N' bit in word 0 of the FIS is set, 1740 * we just received asynchronous notification. 1741 * Tell libata about it. 1742 * 1743 * Lack of SNotification should not appear in 1744 * ahci 1.2, so the workaround is unnecessary 1745 * when FBS is enabled. 1746 */ 1747 if (pp->fbs_enabled) 1748 WARN_ON_ONCE(1); 1749 else { 1750 const __le32 *f = pp->rx_fis + RX_FIS_SDB; 1751 u32 f0 = le32_to_cpu(f[0]); 1752 if (f0 & (1 << 15)) 1753 sata_async_notification(ap); 1754 } 1755 } 1756 } 1757 1758 /* pp->active_link is not reliable once FBS is enabled, both 1759 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because 1760 * NCQ and non-NCQ commands may be in flight at the same time. 1761 */ 1762 if (pp->fbs_enabled) { 1763 if (ap->qc_active) { 1764 qc_active = readl(port_mmio + PORT_SCR_ACT); 1765 qc_active |= readl(port_mmio + PORT_CMD_ISSUE); 1766 } 1767 } else { 1768 /* pp->active_link is valid iff any command is in flight */ 1769 if (ap->qc_active && pp->active_link->sactive) 1770 qc_active = readl(port_mmio + PORT_SCR_ACT); 1771 else 1772 qc_active = readl(port_mmio + PORT_CMD_ISSUE); 1773 } 1774 1775 1776 rc = ata_qc_complete_multiple(ap, qc_active); 1777 1778 /* while resetting, invalid completions are expected */ 1779 if (unlikely(rc < 0 && !resetting)) { 1780 ehi->err_mask |= AC_ERR_HSM; 1781 ehi->action |= ATA_EH_RESET; 1782 ata_port_freeze(ap); 1783 } 1784 } 1785 1786 static void ahci_port_intr(struct ata_port *ap) 1787 { 1788 void __iomem *port_mmio = ahci_port_base(ap); 1789 u32 status; 1790 1791 status = readl(port_mmio + PORT_IRQ_STAT); 1792 writel(status, port_mmio + PORT_IRQ_STAT); 1793 1794 ahci_handle_port_interrupt(ap, port_mmio, status); 1795 } 1796 1797 irqreturn_t ahci_thread_fn(int irq, void *dev_instance) 1798 { 1799 struct ata_port *ap = dev_instance; 1800 struct ahci_port_priv *pp = ap->private_data; 1801 void __iomem *port_mmio = ahci_port_base(ap); 1802 unsigned long flags; 1803 u32 status; 1804 1805 spin_lock_irqsave(&ap->host->lock, flags); 1806 status = pp->intr_status; 1807 if (status) 1808 pp->intr_status = 0; 1809 spin_unlock_irqrestore(&ap->host->lock, flags); 1810 1811 spin_lock_bh(ap->lock); 1812 ahci_handle_port_interrupt(ap, port_mmio, status); 1813 spin_unlock_bh(ap->lock); 1814 1815 return IRQ_HANDLED; 1816 } 1817 EXPORT_SYMBOL_GPL(ahci_thread_fn); 1818 1819 static void ahci_hw_port_interrupt(struct ata_port *ap) 1820 { 1821 void __iomem *port_mmio = ahci_port_base(ap); 1822 struct ahci_port_priv *pp = ap->private_data; 1823 u32 status; 1824 1825 status = readl(port_mmio + PORT_IRQ_STAT); 1826 writel(status, port_mmio + PORT_IRQ_STAT); 1827 1828 pp->intr_status |= status; 1829 } 1830 1831 irqreturn_t ahci_hw_interrupt(int irq, void *dev_instance) 1832 { 1833 struct ata_port *ap_this = dev_instance; 1834 struct ahci_port_priv *pp = ap_this->private_data; 1835 struct ata_host *host = ap_this->host; 1836 struct ahci_host_priv *hpriv = host->private_data; 1837 void __iomem *mmio = hpriv->mmio; 1838 unsigned int i; 1839 u32 irq_stat, irq_masked; 1840 1841 VPRINTK("ENTER\n"); 1842 1843 spin_lock(&host->lock); 1844 1845 irq_stat = readl(mmio + HOST_IRQ_STAT); 1846 1847 if (!irq_stat) { 1848 u32 status = pp->intr_status; 1849 1850 spin_unlock(&host->lock); 1851 1852 VPRINTK("EXIT\n"); 1853 1854 return status ? IRQ_WAKE_THREAD : IRQ_NONE; 1855 } 1856 1857 irq_masked = irq_stat & hpriv->port_map; 1858 1859 for (i = 0; i < host->n_ports; i++) { 1860 struct ata_port *ap; 1861 1862 if (!(irq_masked & (1 << i))) 1863 continue; 1864 1865 ap = host->ports[i]; 1866 if (ap) { 1867 ahci_hw_port_interrupt(ap); 1868 VPRINTK("port %u\n", i); 1869 } else { 1870 VPRINTK("port %u (no irq)\n", i); 1871 if (ata_ratelimit()) 1872 dev_warn(host->dev, 1873 "interrupt on disabled port %u\n", i); 1874 } 1875 } 1876 1877 writel(irq_stat, mmio + HOST_IRQ_STAT); 1878 1879 spin_unlock(&host->lock); 1880 1881 VPRINTK("EXIT\n"); 1882 1883 return IRQ_WAKE_THREAD; 1884 } 1885 EXPORT_SYMBOL_GPL(ahci_hw_interrupt); 1886 1887 irqreturn_t ahci_interrupt(int irq, void *dev_instance) 1888 { 1889 struct ata_host *host = dev_instance; 1890 struct ahci_host_priv *hpriv; 1891 unsigned int i, handled = 0; 1892 void __iomem *mmio; 1893 u32 irq_stat, irq_masked; 1894 1895 VPRINTK("ENTER\n"); 1896 1897 hpriv = host->private_data; 1898 mmio = hpriv->mmio; 1899 1900 /* sigh. 0xffffffff is a valid return from h/w */ 1901 irq_stat = readl(mmio + HOST_IRQ_STAT); 1902 if (!irq_stat) 1903 return IRQ_NONE; 1904 1905 irq_masked = irq_stat & hpriv->port_map; 1906 1907 spin_lock(&host->lock); 1908 1909 for (i = 0; i < host->n_ports; i++) { 1910 struct ata_port *ap; 1911 1912 if (!(irq_masked & (1 << i))) 1913 continue; 1914 1915 ap = host->ports[i]; 1916 if (ap) { 1917 ahci_port_intr(ap); 1918 VPRINTK("port %u\n", i); 1919 } else { 1920 VPRINTK("port %u (no irq)\n", i); 1921 if (ata_ratelimit()) 1922 dev_warn(host->dev, 1923 "interrupt on disabled port %u\n", i); 1924 } 1925 1926 handled = 1; 1927 } 1928 1929 /* HOST_IRQ_STAT behaves as level triggered latch meaning that 1930 * it should be cleared after all the port events are cleared; 1931 * otherwise, it will raise a spurious interrupt after each 1932 * valid one. Please read section 10.6.2 of ahci 1.1 for more 1933 * information. 1934 * 1935 * Also, use the unmasked value to clear interrupt as spurious 1936 * pending event on a dummy port might cause screaming IRQ. 1937 */ 1938 writel(irq_stat, mmio + HOST_IRQ_STAT); 1939 1940 spin_unlock(&host->lock); 1941 1942 VPRINTK("EXIT\n"); 1943 1944 return IRQ_RETVAL(handled); 1945 } 1946 EXPORT_SYMBOL_GPL(ahci_interrupt); 1947 1948 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) 1949 { 1950 struct ata_port *ap = qc->ap; 1951 void __iomem *port_mmio = ahci_port_base(ap); 1952 struct ahci_port_priv *pp = ap->private_data; 1953 1954 /* Keep track of the currently active link. It will be used 1955 * in completion path to determine whether NCQ phase is in 1956 * progress. 1957 */ 1958 pp->active_link = qc->dev->link; 1959 1960 if (qc->tf.protocol == ATA_PROT_NCQ) 1961 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); 1962 1963 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) { 1964 u32 fbs = readl(port_mmio + PORT_FBS); 1965 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); 1966 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET; 1967 writel(fbs, port_mmio + PORT_FBS); 1968 pp->fbs_last_dev = qc->dev->link->pmp; 1969 } 1970 1971 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); 1972 1973 ahci_sw_activity(qc->dev->link); 1974 1975 return 0; 1976 } 1977 1978 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc) 1979 { 1980 struct ahci_port_priv *pp = qc->ap->private_data; 1981 u8 *rx_fis = pp->rx_fis; 1982 1983 if (pp->fbs_enabled) 1984 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ; 1985 1986 /* 1987 * After a successful execution of an ATA PIO data-in command, 1988 * the device doesn't send D2H Reg FIS to update the TF and 1989 * the host should take TF and E_Status from the preceding PIO 1990 * Setup FIS. 1991 */ 1992 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE && 1993 !(qc->flags & ATA_QCFLAG_FAILED)) { 1994 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf); 1995 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15]; 1996 } else 1997 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf); 1998 1999 return true; 2000 } 2001 2002 static void ahci_freeze(struct ata_port *ap) 2003 { 2004 void __iomem *port_mmio = ahci_port_base(ap); 2005 2006 /* turn IRQ off */ 2007 writel(0, port_mmio + PORT_IRQ_MASK); 2008 } 2009 2010 static void ahci_thaw(struct ata_port *ap) 2011 { 2012 struct ahci_host_priv *hpriv = ap->host->private_data; 2013 void __iomem *mmio = hpriv->mmio; 2014 void __iomem *port_mmio = ahci_port_base(ap); 2015 u32 tmp; 2016 struct ahci_port_priv *pp = ap->private_data; 2017 2018 /* clear IRQ */ 2019 tmp = readl(port_mmio + PORT_IRQ_STAT); 2020 writel(tmp, port_mmio + PORT_IRQ_STAT); 2021 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); 2022 2023 /* turn IRQ back on */ 2024 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2025 } 2026 2027 void ahci_error_handler(struct ata_port *ap) 2028 { 2029 struct ahci_host_priv *hpriv = ap->host->private_data; 2030 2031 if (!(ap->pflags & ATA_PFLAG_FROZEN)) { 2032 /* restart engine */ 2033 ahci_stop_engine(ap); 2034 hpriv->start_engine(ap); 2035 } 2036 2037 sata_pmp_error_handler(ap); 2038 2039 if (!ata_dev_enabled(ap->link.device)) 2040 ahci_stop_engine(ap); 2041 } 2042 EXPORT_SYMBOL_GPL(ahci_error_handler); 2043 2044 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) 2045 { 2046 struct ata_port *ap = qc->ap; 2047 2048 /* make DMA engine forget about the failed command */ 2049 if (qc->flags & ATA_QCFLAG_FAILED) 2050 ahci_kick_engine(ap); 2051 } 2052 2053 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep) 2054 { 2055 struct ahci_host_priv *hpriv = ap->host->private_data; 2056 void __iomem *port_mmio = ahci_port_base(ap); 2057 struct ata_device *dev = ap->link.device; 2058 u32 devslp, dm, dito, mdat, deto; 2059 int rc; 2060 unsigned int err_mask; 2061 2062 devslp = readl(port_mmio + PORT_DEVSLP); 2063 if (!(devslp & PORT_DEVSLP_DSP)) { 2064 dev_err(ap->host->dev, "port does not support device sleep\n"); 2065 return; 2066 } 2067 2068 /* disable device sleep */ 2069 if (!sleep) { 2070 if (devslp & PORT_DEVSLP_ADSE) { 2071 writel(devslp & ~PORT_DEVSLP_ADSE, 2072 port_mmio + PORT_DEVSLP); 2073 err_mask = ata_dev_set_feature(dev, 2074 SETFEATURES_SATA_DISABLE, 2075 SATA_DEVSLP); 2076 if (err_mask && err_mask != AC_ERR_DEV) 2077 ata_dev_warn(dev, "failed to disable DEVSLP\n"); 2078 } 2079 return; 2080 } 2081 2082 /* device sleep was already enabled */ 2083 if (devslp & PORT_DEVSLP_ADSE) 2084 return; 2085 2086 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */ 2087 rc = ahci_stop_engine(ap); 2088 if (rc) 2089 return; 2090 2091 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET; 2092 dito = devslp_idle_timeout / (dm + 1); 2093 if (dito > 0x3ff) 2094 dito = 0x3ff; 2095 2096 /* Use the nominal value 10 ms if the read MDAT is zero, 2097 * the nominal value of DETO is 20 ms. 2098 */ 2099 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] & 2100 ATA_LOG_DEVSLP_VALID_MASK) { 2101 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] & 2102 ATA_LOG_DEVSLP_MDAT_MASK; 2103 if (!mdat) 2104 mdat = 10; 2105 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO]; 2106 if (!deto) 2107 deto = 20; 2108 } else { 2109 mdat = 10; 2110 deto = 20; 2111 } 2112 2113 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) | 2114 (mdat << PORT_DEVSLP_MDAT_OFFSET) | 2115 (deto << PORT_DEVSLP_DETO_OFFSET) | 2116 PORT_DEVSLP_ADSE); 2117 writel(devslp, port_mmio + PORT_DEVSLP); 2118 2119 hpriv->start_engine(ap); 2120 2121 /* enable device sleep feature for the drive */ 2122 err_mask = ata_dev_set_feature(dev, 2123 SETFEATURES_SATA_ENABLE, 2124 SATA_DEVSLP); 2125 if (err_mask && err_mask != AC_ERR_DEV) 2126 ata_dev_warn(dev, "failed to enable DEVSLP\n"); 2127 } 2128 2129 static void ahci_enable_fbs(struct ata_port *ap) 2130 { 2131 struct ahci_host_priv *hpriv = ap->host->private_data; 2132 struct ahci_port_priv *pp = ap->private_data; 2133 void __iomem *port_mmio = ahci_port_base(ap); 2134 u32 fbs; 2135 int rc; 2136 2137 if (!pp->fbs_supported) 2138 return; 2139 2140 fbs = readl(port_mmio + PORT_FBS); 2141 if (fbs & PORT_FBS_EN) { 2142 pp->fbs_enabled = true; 2143 pp->fbs_last_dev = -1; /* initialization */ 2144 return; 2145 } 2146 2147 rc = ahci_stop_engine(ap); 2148 if (rc) 2149 return; 2150 2151 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS); 2152 fbs = readl(port_mmio + PORT_FBS); 2153 if (fbs & PORT_FBS_EN) { 2154 dev_info(ap->host->dev, "FBS is enabled\n"); 2155 pp->fbs_enabled = true; 2156 pp->fbs_last_dev = -1; /* initialization */ 2157 } else 2158 dev_err(ap->host->dev, "Failed to enable FBS\n"); 2159 2160 hpriv->start_engine(ap); 2161 } 2162 2163 static void ahci_disable_fbs(struct ata_port *ap) 2164 { 2165 struct ahci_host_priv *hpriv = ap->host->private_data; 2166 struct ahci_port_priv *pp = ap->private_data; 2167 void __iomem *port_mmio = ahci_port_base(ap); 2168 u32 fbs; 2169 int rc; 2170 2171 if (!pp->fbs_supported) 2172 return; 2173 2174 fbs = readl(port_mmio + PORT_FBS); 2175 if ((fbs & PORT_FBS_EN) == 0) { 2176 pp->fbs_enabled = false; 2177 return; 2178 } 2179 2180 rc = ahci_stop_engine(ap); 2181 if (rc) 2182 return; 2183 2184 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS); 2185 fbs = readl(port_mmio + PORT_FBS); 2186 if (fbs & PORT_FBS_EN) 2187 dev_err(ap->host->dev, "Failed to disable FBS\n"); 2188 else { 2189 dev_info(ap->host->dev, "FBS is disabled\n"); 2190 pp->fbs_enabled = false; 2191 } 2192 2193 hpriv->start_engine(ap); 2194 } 2195 2196 static void ahci_pmp_attach(struct ata_port *ap) 2197 { 2198 void __iomem *port_mmio = ahci_port_base(ap); 2199 struct ahci_port_priv *pp = ap->private_data; 2200 u32 cmd; 2201 2202 cmd = readl(port_mmio + PORT_CMD); 2203 cmd |= PORT_CMD_PMP; 2204 writel(cmd, port_mmio + PORT_CMD); 2205 2206 ahci_enable_fbs(ap); 2207 2208 pp->intr_mask |= PORT_IRQ_BAD_PMP; 2209 2210 /* 2211 * We must not change the port interrupt mask register if the 2212 * port is marked frozen, the value in pp->intr_mask will be 2213 * restored later when the port is thawed. 2214 * 2215 * Note that during initialization, the port is marked as 2216 * frozen since the irq handler is not yet registered. 2217 */ 2218 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 2219 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2220 } 2221 2222 static void ahci_pmp_detach(struct ata_port *ap) 2223 { 2224 void __iomem *port_mmio = ahci_port_base(ap); 2225 struct ahci_port_priv *pp = ap->private_data; 2226 u32 cmd; 2227 2228 ahci_disable_fbs(ap); 2229 2230 cmd = readl(port_mmio + PORT_CMD); 2231 cmd &= ~PORT_CMD_PMP; 2232 writel(cmd, port_mmio + PORT_CMD); 2233 2234 pp->intr_mask &= ~PORT_IRQ_BAD_PMP; 2235 2236 /* see comment above in ahci_pmp_attach() */ 2237 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 2238 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2239 } 2240 2241 int ahci_port_resume(struct ata_port *ap) 2242 { 2243 ahci_power_up(ap); 2244 ahci_start_port(ap); 2245 2246 if (sata_pmp_attached(ap)) 2247 ahci_pmp_attach(ap); 2248 else 2249 ahci_pmp_detach(ap); 2250 2251 return 0; 2252 } 2253 EXPORT_SYMBOL_GPL(ahci_port_resume); 2254 2255 #ifdef CONFIG_PM 2256 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) 2257 { 2258 const char *emsg = NULL; 2259 int rc; 2260 2261 rc = ahci_deinit_port(ap, &emsg); 2262 if (rc == 0) 2263 ahci_power_down(ap); 2264 else { 2265 ata_port_err(ap, "%s (%d)\n", emsg, rc); 2266 ata_port_freeze(ap); 2267 } 2268 2269 return rc; 2270 } 2271 #endif 2272 2273 static int ahci_port_start(struct ata_port *ap) 2274 { 2275 struct ahci_host_priv *hpriv = ap->host->private_data; 2276 struct device *dev = ap->host->dev; 2277 struct ahci_port_priv *pp; 2278 void *mem; 2279 dma_addr_t mem_dma; 2280 size_t dma_sz, rx_fis_sz; 2281 2282 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 2283 if (!pp) 2284 return -ENOMEM; 2285 2286 if (ap->host->n_ports > 1) { 2287 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL); 2288 if (!pp->irq_desc) { 2289 devm_kfree(dev, pp); 2290 return -ENOMEM; 2291 } 2292 snprintf(pp->irq_desc, 8, 2293 "%s%d", dev_driver_string(dev), ap->port_no); 2294 } 2295 2296 /* check FBS capability */ 2297 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) { 2298 void __iomem *port_mmio = ahci_port_base(ap); 2299 u32 cmd = readl(port_mmio + PORT_CMD); 2300 if (cmd & PORT_CMD_FBSCP) 2301 pp->fbs_supported = true; 2302 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) { 2303 dev_info(dev, "port %d can do FBS, forcing FBSCP\n", 2304 ap->port_no); 2305 pp->fbs_supported = true; 2306 } else 2307 dev_warn(dev, "port %d is not capable of FBS\n", 2308 ap->port_no); 2309 } 2310 2311 if (pp->fbs_supported) { 2312 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ; 2313 rx_fis_sz = AHCI_RX_FIS_SZ * 16; 2314 } else { 2315 dma_sz = AHCI_PORT_PRIV_DMA_SZ; 2316 rx_fis_sz = AHCI_RX_FIS_SZ; 2317 } 2318 2319 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL); 2320 if (!mem) 2321 return -ENOMEM; 2322 memset(mem, 0, dma_sz); 2323 2324 /* 2325 * First item in chunk of DMA memory: 32-slot command table, 2326 * 32 bytes each in size 2327 */ 2328 pp->cmd_slot = mem; 2329 pp->cmd_slot_dma = mem_dma; 2330 2331 mem += AHCI_CMD_SLOT_SZ; 2332 mem_dma += AHCI_CMD_SLOT_SZ; 2333 2334 /* 2335 * Second item: Received-FIS area 2336 */ 2337 pp->rx_fis = mem; 2338 pp->rx_fis_dma = mem_dma; 2339 2340 mem += rx_fis_sz; 2341 mem_dma += rx_fis_sz; 2342 2343 /* 2344 * Third item: data area for storing a single command 2345 * and its scatter-gather table 2346 */ 2347 pp->cmd_tbl = mem; 2348 pp->cmd_tbl_dma = mem_dma; 2349 2350 /* 2351 * Save off initial list of interrupts to be enabled. 2352 * This could be changed later 2353 */ 2354 pp->intr_mask = DEF_PORT_IRQ; 2355 2356 /* 2357 * Switch to per-port locking in case each port has its own MSI vector. 2358 */ 2359 if ((hpriv->flags & AHCI_HFLAG_MULTI_MSI)) { 2360 spin_lock_init(&pp->lock); 2361 ap->lock = &pp->lock; 2362 } 2363 2364 ap->private_data = pp; 2365 2366 /* engage engines, captain */ 2367 return ahci_port_resume(ap); 2368 } 2369 2370 static void ahci_port_stop(struct ata_port *ap) 2371 { 2372 const char *emsg = NULL; 2373 int rc; 2374 2375 /* de-initialize port */ 2376 rc = ahci_deinit_port(ap, &emsg); 2377 if (rc) 2378 ata_port_warn(ap, "%s (%d)\n", emsg, rc); 2379 } 2380 2381 void ahci_print_info(struct ata_host *host, const char *scc_s) 2382 { 2383 struct ahci_host_priv *hpriv = host->private_data; 2384 void __iomem *mmio = hpriv->mmio; 2385 u32 vers, cap, cap2, impl, speed; 2386 const char *speed_s; 2387 2388 vers = readl(mmio + HOST_VERSION); 2389 cap = hpriv->cap; 2390 cap2 = hpriv->cap2; 2391 impl = hpriv->port_map; 2392 2393 speed = (cap >> 20) & 0xf; 2394 if (speed == 1) 2395 speed_s = "1.5"; 2396 else if (speed == 2) 2397 speed_s = "3"; 2398 else if (speed == 3) 2399 speed_s = "6"; 2400 else 2401 speed_s = "?"; 2402 2403 dev_info(host->dev, 2404 "AHCI %02x%02x.%02x%02x " 2405 "%u slots %u ports %s Gbps 0x%x impl %s mode\n" 2406 , 2407 2408 (vers >> 24) & 0xff, 2409 (vers >> 16) & 0xff, 2410 (vers >> 8) & 0xff, 2411 vers & 0xff, 2412 2413 ((cap >> 8) & 0x1f) + 1, 2414 (cap & 0x1f) + 1, 2415 speed_s, 2416 impl, 2417 scc_s); 2418 2419 dev_info(host->dev, 2420 "flags: " 2421 "%s%s%s%s%s%s%s" 2422 "%s%s%s%s%s%s%s" 2423 "%s%s%s%s%s%s%s" 2424 "%s%s\n" 2425 , 2426 2427 cap & HOST_CAP_64 ? "64bit " : "", 2428 cap & HOST_CAP_NCQ ? "ncq " : "", 2429 cap & HOST_CAP_SNTF ? "sntf " : "", 2430 cap & HOST_CAP_MPS ? "ilck " : "", 2431 cap & HOST_CAP_SSS ? "stag " : "", 2432 cap & HOST_CAP_ALPM ? "pm " : "", 2433 cap & HOST_CAP_LED ? "led " : "", 2434 cap & HOST_CAP_CLO ? "clo " : "", 2435 cap & HOST_CAP_ONLY ? "only " : "", 2436 cap & HOST_CAP_PMP ? "pmp " : "", 2437 cap & HOST_CAP_FBS ? "fbs " : "", 2438 cap & HOST_CAP_PIO_MULTI ? "pio " : "", 2439 cap & HOST_CAP_SSC ? "slum " : "", 2440 cap & HOST_CAP_PART ? "part " : "", 2441 cap & HOST_CAP_CCC ? "ccc " : "", 2442 cap & HOST_CAP_EMS ? "ems " : "", 2443 cap & HOST_CAP_SXS ? "sxs " : "", 2444 cap2 & HOST_CAP2_DESO ? "deso " : "", 2445 cap2 & HOST_CAP2_SADM ? "sadm " : "", 2446 cap2 & HOST_CAP2_SDS ? "sds " : "", 2447 cap2 & HOST_CAP2_APST ? "apst " : "", 2448 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "", 2449 cap2 & HOST_CAP2_BOH ? "boh " : "" 2450 ); 2451 } 2452 EXPORT_SYMBOL_GPL(ahci_print_info); 2453 2454 void ahci_set_em_messages(struct ahci_host_priv *hpriv, 2455 struct ata_port_info *pi) 2456 { 2457 u8 messages; 2458 void __iomem *mmio = hpriv->mmio; 2459 u32 em_loc = readl(mmio + HOST_EM_LOC); 2460 u32 em_ctl = readl(mmio + HOST_EM_CTL); 2461 2462 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS)) 2463 return; 2464 2465 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16; 2466 2467 if (messages) { 2468 /* store em_loc */ 2469 hpriv->em_loc = ((em_loc >> 16) * 4); 2470 hpriv->em_buf_sz = ((em_loc & 0xff) * 4); 2471 hpriv->em_msg_type = messages; 2472 pi->flags |= ATA_FLAG_EM; 2473 if (!(em_ctl & EM_CTL_ALHD)) 2474 pi->flags |= ATA_FLAG_SW_ACTIVITY; 2475 } 2476 } 2477 EXPORT_SYMBOL_GPL(ahci_set_em_messages); 2478 2479 MODULE_AUTHOR("Jeff Garzik"); 2480 MODULE_DESCRIPTION("Common AHCI SATA low-level routines"); 2481 MODULE_LICENSE("GPL"); 2482