1 /* 2 * libahci.c - Common AHCI SATA low-level routines 3 * 4 * Maintained by: Tejun Heo <tj@kernel.org> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2004-2005 Red Hat, Inc. 9 * 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; see the file COPYING. If not, write to 23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * 26 * libata documentation is available via 'make {ps|pdf}docs', 27 * as Documentation/driver-api/libata.rst 28 * 29 * AHCI hardware documentation: 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 32 * 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/gfp.h> 37 #include <linux/module.h> 38 #include <linux/nospec.h> 39 #include <linux/blkdev.h> 40 #include <linux/delay.h> 41 #include <linux/interrupt.h> 42 #include <linux/dma-mapping.h> 43 #include <linux/device.h> 44 #include <scsi/scsi_host.h> 45 #include <scsi/scsi_cmnd.h> 46 #include <linux/libata.h> 47 #include <linux/pci.h> 48 #include "ahci.h" 49 #include "libata.h" 50 51 static int ahci_skip_host_reset; 52 int ahci_ignore_sss; 53 EXPORT_SYMBOL_GPL(ahci_ignore_sss); 54 55 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); 56 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); 57 58 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444); 59 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)"); 60 61 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 62 unsigned hints); 63 static ssize_t ahci_led_show(struct ata_port *ap, char *buf); 64 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 65 size_t size); 66 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 67 ssize_t size); 68 69 70 71 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); 72 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); 73 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc); 74 static int ahci_port_start(struct ata_port *ap); 75 static void ahci_port_stop(struct ata_port *ap); 76 static void ahci_qc_prep(struct ata_queued_cmd *qc); 77 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc); 78 static void ahci_freeze(struct ata_port *ap); 79 static void ahci_thaw(struct ata_port *ap); 80 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep); 81 static void ahci_enable_fbs(struct ata_port *ap); 82 static void ahci_disable_fbs(struct ata_port *ap); 83 static void ahci_pmp_attach(struct ata_port *ap); 84 static void ahci_pmp_detach(struct ata_port *ap); 85 static int ahci_softreset(struct ata_link *link, unsigned int *class, 86 unsigned long deadline); 87 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class, 88 unsigned long deadline); 89 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 90 unsigned long deadline); 91 static void ahci_postreset(struct ata_link *link, unsigned int *class); 92 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); 93 static void ahci_dev_config(struct ata_device *dev); 94 #ifdef CONFIG_PM 95 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); 96 #endif 97 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf); 98 static ssize_t ahci_activity_store(struct ata_device *dev, 99 enum sw_activity val); 100 static void ahci_init_sw_activity(struct ata_link *link); 101 102 static ssize_t ahci_show_host_caps(struct device *dev, 103 struct device_attribute *attr, char *buf); 104 static ssize_t ahci_show_host_cap2(struct device *dev, 105 struct device_attribute *attr, char *buf); 106 static ssize_t ahci_show_host_version(struct device *dev, 107 struct device_attribute *attr, char *buf); 108 static ssize_t ahci_show_port_cmd(struct device *dev, 109 struct device_attribute *attr, char *buf); 110 static ssize_t ahci_read_em_buffer(struct device *dev, 111 struct device_attribute *attr, char *buf); 112 static ssize_t ahci_store_em_buffer(struct device *dev, 113 struct device_attribute *attr, 114 const char *buf, size_t size); 115 static ssize_t ahci_show_em_supported(struct device *dev, 116 struct device_attribute *attr, char *buf); 117 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance); 118 119 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL); 120 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL); 121 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL); 122 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL); 123 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO, 124 ahci_read_em_buffer, ahci_store_em_buffer); 125 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL); 126 127 struct device_attribute *ahci_shost_attrs[] = { 128 &dev_attr_link_power_management_policy, 129 &dev_attr_em_message_type, 130 &dev_attr_em_message, 131 &dev_attr_ahci_host_caps, 132 &dev_attr_ahci_host_cap2, 133 &dev_attr_ahci_host_version, 134 &dev_attr_ahci_port_cmd, 135 &dev_attr_em_buffer, 136 &dev_attr_em_message_supported, 137 NULL 138 }; 139 EXPORT_SYMBOL_GPL(ahci_shost_attrs); 140 141 struct device_attribute *ahci_sdev_attrs[] = { 142 &dev_attr_sw_activity, 143 &dev_attr_unload_heads, 144 &dev_attr_ncq_prio_enable, 145 NULL 146 }; 147 EXPORT_SYMBOL_GPL(ahci_sdev_attrs); 148 149 struct ata_port_operations ahci_ops = { 150 .inherits = &sata_pmp_port_ops, 151 152 .qc_defer = ahci_pmp_qc_defer, 153 .qc_prep = ahci_qc_prep, 154 .qc_issue = ahci_qc_issue, 155 .qc_fill_rtf = ahci_qc_fill_rtf, 156 157 .freeze = ahci_freeze, 158 .thaw = ahci_thaw, 159 .softreset = ahci_softreset, 160 .hardreset = ahci_hardreset, 161 .postreset = ahci_postreset, 162 .pmp_softreset = ahci_softreset, 163 .error_handler = ahci_error_handler, 164 .post_internal_cmd = ahci_post_internal_cmd, 165 .dev_config = ahci_dev_config, 166 167 .scr_read = ahci_scr_read, 168 .scr_write = ahci_scr_write, 169 .pmp_attach = ahci_pmp_attach, 170 .pmp_detach = ahci_pmp_detach, 171 172 .set_lpm = ahci_set_lpm, 173 .em_show = ahci_led_show, 174 .em_store = ahci_led_store, 175 .sw_activity_show = ahci_activity_show, 176 .sw_activity_store = ahci_activity_store, 177 .transmit_led_message = ahci_transmit_led_message, 178 #ifdef CONFIG_PM 179 .port_suspend = ahci_port_suspend, 180 .port_resume = ahci_port_resume, 181 #endif 182 .port_start = ahci_port_start, 183 .port_stop = ahci_port_stop, 184 }; 185 EXPORT_SYMBOL_GPL(ahci_ops); 186 187 struct ata_port_operations ahci_pmp_retry_srst_ops = { 188 .inherits = &ahci_ops, 189 .softreset = ahci_pmp_retry_softreset, 190 }; 191 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops); 192 193 static bool ahci_em_messages __read_mostly = true; 194 EXPORT_SYMBOL_GPL(ahci_em_messages); 195 module_param(ahci_em_messages, bool, 0444); 196 /* add other LED protocol types when they become supported */ 197 MODULE_PARM_DESC(ahci_em_messages, 198 "AHCI Enclosure Management Message control (0 = off, 1 = on)"); 199 200 /* device sleep idle timeout in ms */ 201 static int devslp_idle_timeout __read_mostly = 1000; 202 module_param(devslp_idle_timeout, int, 0644); 203 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout"); 204 205 static void ahci_enable_ahci(void __iomem *mmio) 206 { 207 int i; 208 u32 tmp; 209 210 /* turn on AHCI_EN */ 211 tmp = readl(mmio + HOST_CTL); 212 if (tmp & HOST_AHCI_EN) 213 return; 214 215 /* Some controllers need AHCI_EN to be written multiple times. 216 * Try a few times before giving up. 217 */ 218 for (i = 0; i < 5; i++) { 219 tmp |= HOST_AHCI_EN; 220 writel(tmp, mmio + HOST_CTL); 221 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ 222 if (tmp & HOST_AHCI_EN) 223 return; 224 msleep(10); 225 } 226 227 WARN_ON(1); 228 } 229 230 /** 231 * ahci_rpm_get_port - Make sure the port is powered on 232 * @ap: Port to power on 233 * 234 * Whenever there is need to access the AHCI host registers outside of 235 * normal execution paths, call this function to make sure the host is 236 * actually powered on. 237 */ 238 static int ahci_rpm_get_port(struct ata_port *ap) 239 { 240 return pm_runtime_get_sync(ap->dev); 241 } 242 243 /** 244 * ahci_rpm_put_port - Undoes ahci_rpm_get_port() 245 * @ap: Port to power down 246 * 247 * Undoes ahci_rpm_get_port() and possibly powers down the AHCI host 248 * if it has no more active users. 249 */ 250 static void ahci_rpm_put_port(struct ata_port *ap) 251 { 252 pm_runtime_put(ap->dev); 253 } 254 255 static ssize_t ahci_show_host_caps(struct device *dev, 256 struct device_attribute *attr, char *buf) 257 { 258 struct Scsi_Host *shost = class_to_shost(dev); 259 struct ata_port *ap = ata_shost_to_port(shost); 260 struct ahci_host_priv *hpriv = ap->host->private_data; 261 262 return sprintf(buf, "%x\n", hpriv->cap); 263 } 264 265 static ssize_t ahci_show_host_cap2(struct device *dev, 266 struct device_attribute *attr, char *buf) 267 { 268 struct Scsi_Host *shost = class_to_shost(dev); 269 struct ata_port *ap = ata_shost_to_port(shost); 270 struct ahci_host_priv *hpriv = ap->host->private_data; 271 272 return sprintf(buf, "%x\n", hpriv->cap2); 273 } 274 275 static ssize_t ahci_show_host_version(struct device *dev, 276 struct device_attribute *attr, char *buf) 277 { 278 struct Scsi_Host *shost = class_to_shost(dev); 279 struct ata_port *ap = ata_shost_to_port(shost); 280 struct ahci_host_priv *hpriv = ap->host->private_data; 281 282 return sprintf(buf, "%x\n", hpriv->version); 283 } 284 285 static ssize_t ahci_show_port_cmd(struct device *dev, 286 struct device_attribute *attr, char *buf) 287 { 288 struct Scsi_Host *shost = class_to_shost(dev); 289 struct ata_port *ap = ata_shost_to_port(shost); 290 void __iomem *port_mmio = ahci_port_base(ap); 291 ssize_t ret; 292 293 ahci_rpm_get_port(ap); 294 ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD)); 295 ahci_rpm_put_port(ap); 296 297 return ret; 298 } 299 300 static ssize_t ahci_read_em_buffer(struct device *dev, 301 struct device_attribute *attr, char *buf) 302 { 303 struct Scsi_Host *shost = class_to_shost(dev); 304 struct ata_port *ap = ata_shost_to_port(shost); 305 struct ahci_host_priv *hpriv = ap->host->private_data; 306 void __iomem *mmio = hpriv->mmio; 307 void __iomem *em_mmio = mmio + hpriv->em_loc; 308 u32 em_ctl, msg; 309 unsigned long flags; 310 size_t count; 311 int i; 312 313 ahci_rpm_get_port(ap); 314 spin_lock_irqsave(ap->lock, flags); 315 316 em_ctl = readl(mmio + HOST_EM_CTL); 317 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT || 318 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) { 319 spin_unlock_irqrestore(ap->lock, flags); 320 ahci_rpm_put_port(ap); 321 return -EINVAL; 322 } 323 324 if (!(em_ctl & EM_CTL_MR)) { 325 spin_unlock_irqrestore(ap->lock, flags); 326 ahci_rpm_put_port(ap); 327 return -EAGAIN; 328 } 329 330 if (!(em_ctl & EM_CTL_SMB)) 331 em_mmio += hpriv->em_buf_sz; 332 333 count = hpriv->em_buf_sz; 334 335 /* the count should not be larger than PAGE_SIZE */ 336 if (count > PAGE_SIZE) { 337 if (printk_ratelimit()) 338 ata_port_warn(ap, 339 "EM read buffer size too large: " 340 "buffer size %u, page size %lu\n", 341 hpriv->em_buf_sz, PAGE_SIZE); 342 count = PAGE_SIZE; 343 } 344 345 for (i = 0; i < count; i += 4) { 346 msg = readl(em_mmio + i); 347 buf[i] = msg & 0xff; 348 buf[i + 1] = (msg >> 8) & 0xff; 349 buf[i + 2] = (msg >> 16) & 0xff; 350 buf[i + 3] = (msg >> 24) & 0xff; 351 } 352 353 spin_unlock_irqrestore(ap->lock, flags); 354 ahci_rpm_put_port(ap); 355 356 return i; 357 } 358 359 static ssize_t ahci_store_em_buffer(struct device *dev, 360 struct device_attribute *attr, 361 const char *buf, size_t size) 362 { 363 struct Scsi_Host *shost = class_to_shost(dev); 364 struct ata_port *ap = ata_shost_to_port(shost); 365 struct ahci_host_priv *hpriv = ap->host->private_data; 366 void __iomem *mmio = hpriv->mmio; 367 void __iomem *em_mmio = mmio + hpriv->em_loc; 368 const unsigned char *msg_buf = buf; 369 u32 em_ctl, msg; 370 unsigned long flags; 371 int i; 372 373 /* check size validity */ 374 if (!(ap->flags & ATA_FLAG_EM) || 375 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) || 376 size % 4 || size > hpriv->em_buf_sz) 377 return -EINVAL; 378 379 ahci_rpm_get_port(ap); 380 spin_lock_irqsave(ap->lock, flags); 381 382 em_ctl = readl(mmio + HOST_EM_CTL); 383 if (em_ctl & EM_CTL_TM) { 384 spin_unlock_irqrestore(ap->lock, flags); 385 ahci_rpm_put_port(ap); 386 return -EBUSY; 387 } 388 389 for (i = 0; i < size; i += 4) { 390 msg = msg_buf[i] | msg_buf[i + 1] << 8 | 391 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24; 392 writel(msg, em_mmio + i); 393 } 394 395 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 396 397 spin_unlock_irqrestore(ap->lock, flags); 398 ahci_rpm_put_port(ap); 399 400 return size; 401 } 402 403 static ssize_t ahci_show_em_supported(struct device *dev, 404 struct device_attribute *attr, char *buf) 405 { 406 struct Scsi_Host *shost = class_to_shost(dev); 407 struct ata_port *ap = ata_shost_to_port(shost); 408 struct ahci_host_priv *hpriv = ap->host->private_data; 409 void __iomem *mmio = hpriv->mmio; 410 u32 em_ctl; 411 412 ahci_rpm_get_port(ap); 413 em_ctl = readl(mmio + HOST_EM_CTL); 414 ahci_rpm_put_port(ap); 415 416 return sprintf(buf, "%s%s%s%s\n", 417 em_ctl & EM_CTL_LED ? "led " : "", 418 em_ctl & EM_CTL_SAFTE ? "saf-te " : "", 419 em_ctl & EM_CTL_SES ? "ses-2 " : "", 420 em_ctl & EM_CTL_SGPIO ? "sgpio " : ""); 421 } 422 423 /** 424 * ahci_save_initial_config - Save and fixup initial config values 425 * @dev: target AHCI device 426 * @hpriv: host private area to store config values 427 * 428 * Some registers containing configuration info might be setup by 429 * BIOS and might be cleared on reset. This function saves the 430 * initial values of those registers into @hpriv such that they 431 * can be restored after controller reset. 432 * 433 * If inconsistent, config values are fixed up by this function. 434 * 435 * If it is not set already this function sets hpriv->start_engine to 436 * ahci_start_engine. 437 * 438 * LOCKING: 439 * None. 440 */ 441 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv) 442 { 443 void __iomem *mmio = hpriv->mmio; 444 u32 cap, cap2, vers, port_map; 445 int i; 446 447 /* make sure AHCI mode is enabled before accessing CAP */ 448 ahci_enable_ahci(mmio); 449 450 /* Values prefixed with saved_ are written back to host after 451 * reset. Values without are used for driver operation. 452 */ 453 hpriv->saved_cap = cap = readl(mmio + HOST_CAP); 454 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); 455 456 /* CAP2 register is only defined for AHCI 1.2 and later */ 457 vers = readl(mmio + HOST_VERSION); 458 if ((vers >> 16) > 1 || 459 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200)) 460 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2); 461 else 462 hpriv->saved_cap2 = cap2 = 0; 463 464 /* some chips have errata preventing 64bit use */ 465 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { 466 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n"); 467 cap &= ~HOST_CAP_64; 468 } 469 470 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { 471 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n"); 472 cap &= ~HOST_CAP_NCQ; 473 } 474 475 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) { 476 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n"); 477 cap |= HOST_CAP_NCQ; 478 } 479 480 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { 481 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n"); 482 cap &= ~HOST_CAP_PMP; 483 } 484 485 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) { 486 dev_info(dev, 487 "controller can't do SNTF, turning off CAP_SNTF\n"); 488 cap &= ~HOST_CAP_SNTF; 489 } 490 491 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) { 492 dev_info(dev, 493 "controller can't do DEVSLP, turning off\n"); 494 cap2 &= ~HOST_CAP2_SDS; 495 cap2 &= ~HOST_CAP2_SADM; 496 } 497 498 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) { 499 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n"); 500 cap |= HOST_CAP_FBS; 501 } 502 503 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) { 504 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n"); 505 cap &= ~HOST_CAP_FBS; 506 } 507 508 if (!(cap & HOST_CAP_ALPM) && (hpriv->flags & AHCI_HFLAG_YES_ALPM)) { 509 dev_info(dev, "controller can do ALPM, turning on CAP_ALPM\n"); 510 cap |= HOST_CAP_ALPM; 511 } 512 513 if (hpriv->force_port_map && port_map != hpriv->force_port_map) { 514 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n", 515 port_map, hpriv->force_port_map); 516 port_map = hpriv->force_port_map; 517 hpriv->saved_port_map = port_map; 518 } 519 520 if (hpriv->mask_port_map) { 521 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n", 522 port_map, 523 port_map & hpriv->mask_port_map); 524 port_map &= hpriv->mask_port_map; 525 } 526 527 /* cross check port_map and cap.n_ports */ 528 if (port_map) { 529 int map_ports = 0; 530 531 for (i = 0; i < AHCI_MAX_PORTS; i++) 532 if (port_map & (1 << i)) 533 map_ports++; 534 535 /* If PI has more ports than n_ports, whine, clear 536 * port_map and let it be generated from n_ports. 537 */ 538 if (map_ports > ahci_nr_ports(cap)) { 539 dev_warn(dev, 540 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n", 541 port_map, ahci_nr_ports(cap)); 542 port_map = 0; 543 } 544 } 545 546 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */ 547 if (!port_map && vers < 0x10300) { 548 port_map = (1 << ahci_nr_ports(cap)) - 1; 549 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map); 550 551 /* write the fixed up value to the PI register */ 552 hpriv->saved_port_map = port_map; 553 } 554 555 /* record values to use during operation */ 556 hpriv->cap = cap; 557 hpriv->cap2 = cap2; 558 hpriv->version = readl(mmio + HOST_VERSION); 559 hpriv->port_map = port_map; 560 561 if (!hpriv->start_engine) 562 hpriv->start_engine = ahci_start_engine; 563 564 if (!hpriv->stop_engine) 565 hpriv->stop_engine = ahci_stop_engine; 566 567 if (!hpriv->irq_handler) 568 hpriv->irq_handler = ahci_single_level_irq_intr; 569 } 570 EXPORT_SYMBOL_GPL(ahci_save_initial_config); 571 572 /** 573 * ahci_restore_initial_config - Restore initial config 574 * @host: target ATA host 575 * 576 * Restore initial config stored by ahci_save_initial_config(). 577 * 578 * LOCKING: 579 * None. 580 */ 581 static void ahci_restore_initial_config(struct ata_host *host) 582 { 583 struct ahci_host_priv *hpriv = host->private_data; 584 void __iomem *mmio = hpriv->mmio; 585 586 writel(hpriv->saved_cap, mmio + HOST_CAP); 587 if (hpriv->saved_cap2) 588 writel(hpriv->saved_cap2, mmio + HOST_CAP2); 589 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); 590 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ 591 } 592 593 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) 594 { 595 static const int offset[] = { 596 [SCR_STATUS] = PORT_SCR_STAT, 597 [SCR_CONTROL] = PORT_SCR_CTL, 598 [SCR_ERROR] = PORT_SCR_ERR, 599 [SCR_ACTIVE] = PORT_SCR_ACT, 600 [SCR_NOTIFICATION] = PORT_SCR_NTF, 601 }; 602 struct ahci_host_priv *hpriv = ap->host->private_data; 603 604 if (sc_reg < ARRAY_SIZE(offset) && 605 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) 606 return offset[sc_reg]; 607 return 0; 608 } 609 610 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) 611 { 612 void __iomem *port_mmio = ahci_port_base(link->ap); 613 int offset = ahci_scr_offset(link->ap, sc_reg); 614 615 if (offset) { 616 *val = readl(port_mmio + offset); 617 return 0; 618 } 619 return -EINVAL; 620 } 621 622 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) 623 { 624 void __iomem *port_mmio = ahci_port_base(link->ap); 625 int offset = ahci_scr_offset(link->ap, sc_reg); 626 627 if (offset) { 628 writel(val, port_mmio + offset); 629 return 0; 630 } 631 return -EINVAL; 632 } 633 634 void ahci_start_engine(struct ata_port *ap) 635 { 636 void __iomem *port_mmio = ahci_port_base(ap); 637 u32 tmp; 638 639 /* start DMA */ 640 tmp = readl(port_mmio + PORT_CMD); 641 tmp |= PORT_CMD_START; 642 writel(tmp, port_mmio + PORT_CMD); 643 readl(port_mmio + PORT_CMD); /* flush */ 644 } 645 EXPORT_SYMBOL_GPL(ahci_start_engine); 646 647 int ahci_stop_engine(struct ata_port *ap) 648 { 649 void __iomem *port_mmio = ahci_port_base(ap); 650 struct ahci_host_priv *hpriv = ap->host->private_data; 651 u32 tmp; 652 653 /* 654 * On some controllers, stopping a port's DMA engine while the port 655 * is in ALPM state (partial or slumber) results in failures on 656 * subsequent DMA engine starts. For those controllers, put the 657 * port back in active state before stopping its DMA engine. 658 */ 659 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) && 660 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) && 661 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) { 662 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n"); 663 return -EIO; 664 } 665 666 tmp = readl(port_mmio + PORT_CMD); 667 668 /* check if the HBA is idle */ 669 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) 670 return 0; 671 672 /* 673 * Don't try to issue commands but return with ENODEV if the 674 * AHCI controller not available anymore (e.g. due to PCIe hot 675 * unplugging). Otherwise a 500ms delay for each port is added. 676 */ 677 if (tmp == 0xffffffff) { 678 dev_err(ap->host->dev, "AHCI controller unavailable!\n"); 679 return -ENODEV; 680 } 681 682 /* setting HBA to idle */ 683 tmp &= ~PORT_CMD_START; 684 writel(tmp, port_mmio + PORT_CMD); 685 686 /* wait for engine to stop. This could be as long as 500 msec */ 687 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 688 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); 689 if (tmp & PORT_CMD_LIST_ON) 690 return -EIO; 691 692 return 0; 693 } 694 EXPORT_SYMBOL_GPL(ahci_stop_engine); 695 696 void ahci_start_fis_rx(struct ata_port *ap) 697 { 698 void __iomem *port_mmio = ahci_port_base(ap); 699 struct ahci_host_priv *hpriv = ap->host->private_data; 700 struct ahci_port_priv *pp = ap->private_data; 701 u32 tmp; 702 703 /* set FIS registers */ 704 if (hpriv->cap & HOST_CAP_64) 705 writel((pp->cmd_slot_dma >> 16) >> 16, 706 port_mmio + PORT_LST_ADDR_HI); 707 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); 708 709 if (hpriv->cap & HOST_CAP_64) 710 writel((pp->rx_fis_dma >> 16) >> 16, 711 port_mmio + PORT_FIS_ADDR_HI); 712 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); 713 714 /* enable FIS reception */ 715 tmp = readl(port_mmio + PORT_CMD); 716 tmp |= PORT_CMD_FIS_RX; 717 writel(tmp, port_mmio + PORT_CMD); 718 719 /* flush */ 720 readl(port_mmio + PORT_CMD); 721 } 722 EXPORT_SYMBOL_GPL(ahci_start_fis_rx); 723 724 static int ahci_stop_fis_rx(struct ata_port *ap) 725 { 726 void __iomem *port_mmio = ahci_port_base(ap); 727 u32 tmp; 728 729 /* disable FIS reception */ 730 tmp = readl(port_mmio + PORT_CMD); 731 tmp &= ~PORT_CMD_FIS_RX; 732 writel(tmp, port_mmio + PORT_CMD); 733 734 /* wait for completion, spec says 500ms, give it 1000 */ 735 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON, 736 PORT_CMD_FIS_ON, 10, 1000); 737 if (tmp & PORT_CMD_FIS_ON) 738 return -EBUSY; 739 740 return 0; 741 } 742 743 static void ahci_power_up(struct ata_port *ap) 744 { 745 struct ahci_host_priv *hpriv = ap->host->private_data; 746 void __iomem *port_mmio = ahci_port_base(ap); 747 u32 cmd; 748 749 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 750 751 /* spin up device */ 752 if (hpriv->cap & HOST_CAP_SSS) { 753 cmd |= PORT_CMD_SPIN_UP; 754 writel(cmd, port_mmio + PORT_CMD); 755 } 756 757 /* wake up link */ 758 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); 759 } 760 761 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 762 unsigned int hints) 763 { 764 struct ata_port *ap = link->ap; 765 struct ahci_host_priv *hpriv = ap->host->private_data; 766 struct ahci_port_priv *pp = ap->private_data; 767 void __iomem *port_mmio = ahci_port_base(ap); 768 769 if (policy != ATA_LPM_MAX_POWER) { 770 /* wakeup flag only applies to the max power policy */ 771 hints &= ~ATA_LPM_WAKE_ONLY; 772 773 /* 774 * Disable interrupts on Phy Ready. This keeps us from 775 * getting woken up due to spurious phy ready 776 * interrupts. 777 */ 778 pp->intr_mask &= ~PORT_IRQ_PHYRDY; 779 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 780 781 sata_link_scr_lpm(link, policy, false); 782 } 783 784 if (hpriv->cap & HOST_CAP_ALPM) { 785 u32 cmd = readl(port_mmio + PORT_CMD); 786 787 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) { 788 if (!(hints & ATA_LPM_WAKE_ONLY)) 789 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE); 790 cmd |= PORT_CMD_ICC_ACTIVE; 791 792 writel(cmd, port_mmio + PORT_CMD); 793 readl(port_mmio + PORT_CMD); 794 795 /* wait 10ms to be sure we've come out of LPM state */ 796 ata_msleep(ap, 10); 797 798 if (hints & ATA_LPM_WAKE_ONLY) 799 return 0; 800 } else { 801 cmd |= PORT_CMD_ALPE; 802 if (policy == ATA_LPM_MIN_POWER) 803 cmd |= PORT_CMD_ASP; 804 805 /* write out new cmd value */ 806 writel(cmd, port_mmio + PORT_CMD); 807 } 808 } 809 810 /* set aggressive device sleep */ 811 if ((hpriv->cap2 & HOST_CAP2_SDS) && 812 (hpriv->cap2 & HOST_CAP2_SADM) && 813 (link->device->flags & ATA_DFLAG_DEVSLP)) { 814 if (policy == ATA_LPM_MIN_POWER) 815 ahci_set_aggressive_devslp(ap, true); 816 else 817 ahci_set_aggressive_devslp(ap, false); 818 } 819 820 if (policy == ATA_LPM_MAX_POWER) { 821 sata_link_scr_lpm(link, policy, false); 822 823 /* turn PHYRDY IRQ back on */ 824 pp->intr_mask |= PORT_IRQ_PHYRDY; 825 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 826 } 827 828 return 0; 829 } 830 831 #ifdef CONFIG_PM 832 static void ahci_power_down(struct ata_port *ap) 833 { 834 struct ahci_host_priv *hpriv = ap->host->private_data; 835 void __iomem *port_mmio = ahci_port_base(ap); 836 u32 cmd, scontrol; 837 838 if (!(hpriv->cap & HOST_CAP_SSS)) 839 return; 840 841 /* put device into listen mode, first set PxSCTL.DET to 0 */ 842 scontrol = readl(port_mmio + PORT_SCR_CTL); 843 scontrol &= ~0xf; 844 writel(scontrol, port_mmio + PORT_SCR_CTL); 845 846 /* then set PxCMD.SUD to 0 */ 847 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 848 cmd &= ~PORT_CMD_SPIN_UP; 849 writel(cmd, port_mmio + PORT_CMD); 850 } 851 #endif 852 853 static void ahci_start_port(struct ata_port *ap) 854 { 855 struct ahci_host_priv *hpriv = ap->host->private_data; 856 struct ahci_port_priv *pp = ap->private_data; 857 struct ata_link *link; 858 struct ahci_em_priv *emp; 859 ssize_t rc; 860 int i; 861 862 /* enable FIS reception */ 863 ahci_start_fis_rx(ap); 864 865 /* enable DMA */ 866 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE)) 867 hpriv->start_engine(ap); 868 869 /* turn on LEDs */ 870 if (ap->flags & ATA_FLAG_EM) { 871 ata_for_each_link(link, ap, EDGE) { 872 emp = &pp->em_priv[link->pmp]; 873 874 /* EM Transmit bit maybe busy during init */ 875 for (i = 0; i < EM_MAX_RETRY; i++) { 876 rc = ap->ops->transmit_led_message(ap, 877 emp->led_state, 878 4); 879 /* 880 * If busy, give a breather but do not 881 * release EH ownership by using msleep() 882 * instead of ata_msleep(). EM Transmit 883 * bit is busy for the whole host and 884 * releasing ownership will cause other 885 * ports to fail the same way. 886 */ 887 if (rc == -EBUSY) 888 msleep(1); 889 else 890 break; 891 } 892 } 893 } 894 895 if (ap->flags & ATA_FLAG_SW_ACTIVITY) 896 ata_for_each_link(link, ap, EDGE) 897 ahci_init_sw_activity(link); 898 899 } 900 901 static int ahci_deinit_port(struct ata_port *ap, const char **emsg) 902 { 903 int rc; 904 struct ahci_host_priv *hpriv = ap->host->private_data; 905 906 /* disable DMA */ 907 rc = hpriv->stop_engine(ap); 908 if (rc) { 909 *emsg = "failed to stop engine"; 910 return rc; 911 } 912 913 /* disable FIS reception */ 914 rc = ahci_stop_fis_rx(ap); 915 if (rc) { 916 *emsg = "failed stop FIS RX"; 917 return rc; 918 } 919 920 return 0; 921 } 922 923 int ahci_reset_controller(struct ata_host *host) 924 { 925 struct ahci_host_priv *hpriv = host->private_data; 926 void __iomem *mmio = hpriv->mmio; 927 u32 tmp; 928 929 /* we must be in AHCI mode, before using anything 930 * AHCI-specific, such as HOST_RESET. 931 */ 932 ahci_enable_ahci(mmio); 933 934 /* global controller reset */ 935 if (!ahci_skip_host_reset) { 936 tmp = readl(mmio + HOST_CTL); 937 if ((tmp & HOST_RESET) == 0) { 938 writel(tmp | HOST_RESET, mmio + HOST_CTL); 939 readl(mmio + HOST_CTL); /* flush */ 940 } 941 942 /* 943 * to perform host reset, OS should set HOST_RESET 944 * and poll until this bit is read to be "0". 945 * reset must complete within 1 second, or 946 * the hardware should be considered fried. 947 */ 948 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET, 949 HOST_RESET, 10, 1000); 950 951 if (tmp & HOST_RESET) { 952 dev_err(host->dev, "controller reset failed (0x%x)\n", 953 tmp); 954 return -EIO; 955 } 956 957 /* turn on AHCI mode */ 958 ahci_enable_ahci(mmio); 959 960 /* Some registers might be cleared on reset. Restore 961 * initial values. 962 */ 963 if (!(hpriv->flags & AHCI_HFLAG_NO_WRITE_TO_RO)) 964 ahci_restore_initial_config(host); 965 } else 966 dev_info(host->dev, "skipping global host reset\n"); 967 968 return 0; 969 } 970 EXPORT_SYMBOL_GPL(ahci_reset_controller); 971 972 static void ahci_sw_activity(struct ata_link *link) 973 { 974 struct ata_port *ap = link->ap; 975 struct ahci_port_priv *pp = ap->private_data; 976 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 977 978 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY)) 979 return; 980 981 emp->activity++; 982 if (!timer_pending(&emp->timer)) 983 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10)); 984 } 985 986 static void ahci_sw_activity_blink(struct timer_list *t) 987 { 988 struct ahci_em_priv *emp = from_timer(emp, t, timer); 989 struct ata_link *link = emp->link; 990 struct ata_port *ap = link->ap; 991 992 unsigned long led_message = emp->led_state; 993 u32 activity_led_state; 994 unsigned long flags; 995 996 led_message &= EM_MSG_LED_VALUE; 997 led_message |= ap->port_no | (link->pmp << 8); 998 999 /* check to see if we've had activity. If so, 1000 * toggle state of LED and reset timer. If not, 1001 * turn LED to desired idle state. 1002 */ 1003 spin_lock_irqsave(ap->lock, flags); 1004 if (emp->saved_activity != emp->activity) { 1005 emp->saved_activity = emp->activity; 1006 /* get the current LED state */ 1007 activity_led_state = led_message & EM_MSG_LED_VALUE_ON; 1008 1009 if (activity_led_state) 1010 activity_led_state = 0; 1011 else 1012 activity_led_state = 1; 1013 1014 /* clear old state */ 1015 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 1016 1017 /* toggle state */ 1018 led_message |= (activity_led_state << 16); 1019 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100)); 1020 } else { 1021 /* switch to idle */ 1022 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 1023 if (emp->blink_policy == BLINK_OFF) 1024 led_message |= (1 << 16); 1025 } 1026 spin_unlock_irqrestore(ap->lock, flags); 1027 ap->ops->transmit_led_message(ap, led_message, 4); 1028 } 1029 1030 static void ahci_init_sw_activity(struct ata_link *link) 1031 { 1032 struct ata_port *ap = link->ap; 1033 struct ahci_port_priv *pp = ap->private_data; 1034 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1035 1036 /* init activity stats, setup timer */ 1037 emp->saved_activity = emp->activity = 0; 1038 emp->link = link; 1039 timer_setup(&emp->timer, ahci_sw_activity_blink, 0); 1040 1041 /* check our blink policy and set flag for link if it's enabled */ 1042 if (emp->blink_policy) 1043 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1044 } 1045 1046 int ahci_reset_em(struct ata_host *host) 1047 { 1048 struct ahci_host_priv *hpriv = host->private_data; 1049 void __iomem *mmio = hpriv->mmio; 1050 u32 em_ctl; 1051 1052 em_ctl = readl(mmio + HOST_EM_CTL); 1053 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST)) 1054 return -EINVAL; 1055 1056 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL); 1057 return 0; 1058 } 1059 EXPORT_SYMBOL_GPL(ahci_reset_em); 1060 1061 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 1062 ssize_t size) 1063 { 1064 struct ahci_host_priv *hpriv = ap->host->private_data; 1065 struct ahci_port_priv *pp = ap->private_data; 1066 void __iomem *mmio = hpriv->mmio; 1067 u32 em_ctl; 1068 u32 message[] = {0, 0}; 1069 unsigned long flags; 1070 int pmp; 1071 struct ahci_em_priv *emp; 1072 1073 /* get the slot number from the message */ 1074 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1075 if (pmp < EM_MAX_SLOTS) 1076 emp = &pp->em_priv[pmp]; 1077 else 1078 return -EINVAL; 1079 1080 ahci_rpm_get_port(ap); 1081 spin_lock_irqsave(ap->lock, flags); 1082 1083 /* 1084 * if we are still busy transmitting a previous message, 1085 * do not allow 1086 */ 1087 em_ctl = readl(mmio + HOST_EM_CTL); 1088 if (em_ctl & EM_CTL_TM) { 1089 spin_unlock_irqrestore(ap->lock, flags); 1090 ahci_rpm_put_port(ap); 1091 return -EBUSY; 1092 } 1093 1094 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) { 1095 /* 1096 * create message header - this is all zero except for 1097 * the message size, which is 4 bytes. 1098 */ 1099 message[0] |= (4 << 8); 1100 1101 /* ignore 0:4 of byte zero, fill in port info yourself */ 1102 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no); 1103 1104 /* write message to EM_LOC */ 1105 writel(message[0], mmio + hpriv->em_loc); 1106 writel(message[1], mmio + hpriv->em_loc+4); 1107 1108 /* 1109 * tell hardware to transmit the message 1110 */ 1111 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 1112 } 1113 1114 /* save off new led state for port/slot */ 1115 emp->led_state = state; 1116 1117 spin_unlock_irqrestore(ap->lock, flags); 1118 ahci_rpm_put_port(ap); 1119 1120 return size; 1121 } 1122 1123 static ssize_t ahci_led_show(struct ata_port *ap, char *buf) 1124 { 1125 struct ahci_port_priv *pp = ap->private_data; 1126 struct ata_link *link; 1127 struct ahci_em_priv *emp; 1128 int rc = 0; 1129 1130 ata_for_each_link(link, ap, EDGE) { 1131 emp = &pp->em_priv[link->pmp]; 1132 rc += sprintf(buf, "%lx\n", emp->led_state); 1133 } 1134 return rc; 1135 } 1136 1137 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 1138 size_t size) 1139 { 1140 unsigned int state; 1141 int pmp; 1142 struct ahci_port_priv *pp = ap->private_data; 1143 struct ahci_em_priv *emp; 1144 1145 if (kstrtouint(buf, 0, &state) < 0) 1146 return -EINVAL; 1147 1148 /* get the slot number from the message */ 1149 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1150 if (pmp < EM_MAX_SLOTS) { 1151 pmp = array_index_nospec(pmp, EM_MAX_SLOTS); 1152 emp = &pp->em_priv[pmp]; 1153 } else { 1154 return -EINVAL; 1155 } 1156 1157 /* mask off the activity bits if we are in sw_activity 1158 * mode, user should turn off sw_activity before setting 1159 * activity led through em_message 1160 */ 1161 if (emp->blink_policy) 1162 state &= ~EM_MSG_LED_VALUE_ACTIVITY; 1163 1164 return ap->ops->transmit_led_message(ap, state, size); 1165 } 1166 1167 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val) 1168 { 1169 struct ata_link *link = dev->link; 1170 struct ata_port *ap = link->ap; 1171 struct ahci_port_priv *pp = ap->private_data; 1172 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1173 u32 port_led_state = emp->led_state; 1174 1175 /* save the desired Activity LED behavior */ 1176 if (val == OFF) { 1177 /* clear LFLAG */ 1178 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY); 1179 1180 /* set the LED to OFF */ 1181 port_led_state &= EM_MSG_LED_VALUE_OFF; 1182 port_led_state |= (ap->port_no | (link->pmp << 8)); 1183 ap->ops->transmit_led_message(ap, port_led_state, 4); 1184 } else { 1185 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1186 if (val == BLINK_OFF) { 1187 /* set LED to ON for idle */ 1188 port_led_state &= EM_MSG_LED_VALUE_OFF; 1189 port_led_state |= (ap->port_no | (link->pmp << 8)); 1190 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */ 1191 ap->ops->transmit_led_message(ap, port_led_state, 4); 1192 } 1193 } 1194 emp->blink_policy = val; 1195 return 0; 1196 } 1197 1198 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf) 1199 { 1200 struct ata_link *link = dev->link; 1201 struct ata_port *ap = link->ap; 1202 struct ahci_port_priv *pp = ap->private_data; 1203 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1204 1205 /* display the saved value of activity behavior for this 1206 * disk. 1207 */ 1208 return sprintf(buf, "%d\n", emp->blink_policy); 1209 } 1210 1211 static void ahci_port_init(struct device *dev, struct ata_port *ap, 1212 int port_no, void __iomem *mmio, 1213 void __iomem *port_mmio) 1214 { 1215 struct ahci_host_priv *hpriv = ap->host->private_data; 1216 const char *emsg = NULL; 1217 int rc; 1218 u32 tmp; 1219 1220 /* make sure port is not active */ 1221 rc = ahci_deinit_port(ap, &emsg); 1222 if (rc) 1223 dev_warn(dev, "%s (%d)\n", emsg, rc); 1224 1225 /* clear SError */ 1226 tmp = readl(port_mmio + PORT_SCR_ERR); 1227 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); 1228 writel(tmp, port_mmio + PORT_SCR_ERR); 1229 1230 /* clear port IRQ */ 1231 tmp = readl(port_mmio + PORT_IRQ_STAT); 1232 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 1233 if (tmp) 1234 writel(tmp, port_mmio + PORT_IRQ_STAT); 1235 1236 writel(1 << port_no, mmio + HOST_IRQ_STAT); 1237 1238 /* mark esata ports */ 1239 tmp = readl(port_mmio + PORT_CMD); 1240 if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS)) 1241 ap->pflags |= ATA_PFLAG_EXTERNAL; 1242 } 1243 1244 void ahci_init_controller(struct ata_host *host) 1245 { 1246 struct ahci_host_priv *hpriv = host->private_data; 1247 void __iomem *mmio = hpriv->mmio; 1248 int i; 1249 void __iomem *port_mmio; 1250 u32 tmp; 1251 1252 for (i = 0; i < host->n_ports; i++) { 1253 struct ata_port *ap = host->ports[i]; 1254 1255 port_mmio = ahci_port_base(ap); 1256 if (ata_port_is_dummy(ap)) 1257 continue; 1258 1259 ahci_port_init(host->dev, ap, i, mmio, port_mmio); 1260 } 1261 1262 tmp = readl(mmio + HOST_CTL); 1263 VPRINTK("HOST_CTL 0x%x\n", tmp); 1264 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); 1265 tmp = readl(mmio + HOST_CTL); 1266 VPRINTK("HOST_CTL 0x%x\n", tmp); 1267 } 1268 EXPORT_SYMBOL_GPL(ahci_init_controller); 1269 1270 static void ahci_dev_config(struct ata_device *dev) 1271 { 1272 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data; 1273 1274 if (hpriv->flags & AHCI_HFLAG_SECT255) { 1275 dev->max_sectors = 255; 1276 ata_dev_info(dev, 1277 "SB600 AHCI: limiting to 255 sectors per cmd\n"); 1278 } 1279 } 1280 1281 unsigned int ahci_dev_classify(struct ata_port *ap) 1282 { 1283 void __iomem *port_mmio = ahci_port_base(ap); 1284 struct ata_taskfile tf; 1285 u32 tmp; 1286 1287 tmp = readl(port_mmio + PORT_SIG); 1288 tf.lbah = (tmp >> 24) & 0xff; 1289 tf.lbam = (tmp >> 16) & 0xff; 1290 tf.lbal = (tmp >> 8) & 0xff; 1291 tf.nsect = (tmp) & 0xff; 1292 1293 return ata_dev_classify(&tf); 1294 } 1295 EXPORT_SYMBOL_GPL(ahci_dev_classify); 1296 1297 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 1298 u32 opts) 1299 { 1300 dma_addr_t cmd_tbl_dma; 1301 1302 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; 1303 1304 pp->cmd_slot[tag].opts = cpu_to_le32(opts); 1305 pp->cmd_slot[tag].status = 0; 1306 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); 1307 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); 1308 } 1309 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot); 1310 1311 int ahci_kick_engine(struct ata_port *ap) 1312 { 1313 void __iomem *port_mmio = ahci_port_base(ap); 1314 struct ahci_host_priv *hpriv = ap->host->private_data; 1315 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1316 u32 tmp; 1317 int busy, rc; 1318 1319 /* stop engine */ 1320 rc = hpriv->stop_engine(ap); 1321 if (rc) 1322 goto out_restart; 1323 1324 /* need to do CLO? 1325 * always do CLO if PMP is attached (AHCI-1.3 9.2) 1326 */ 1327 busy = status & (ATA_BUSY | ATA_DRQ); 1328 if (!busy && !sata_pmp_attached(ap)) { 1329 rc = 0; 1330 goto out_restart; 1331 } 1332 1333 if (!(hpriv->cap & HOST_CAP_CLO)) { 1334 rc = -EOPNOTSUPP; 1335 goto out_restart; 1336 } 1337 1338 /* perform CLO */ 1339 tmp = readl(port_mmio + PORT_CMD); 1340 tmp |= PORT_CMD_CLO; 1341 writel(tmp, port_mmio + PORT_CMD); 1342 1343 rc = 0; 1344 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 1345 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); 1346 if (tmp & PORT_CMD_CLO) 1347 rc = -EIO; 1348 1349 /* restart engine */ 1350 out_restart: 1351 hpriv->start_engine(ap); 1352 return rc; 1353 } 1354 EXPORT_SYMBOL_GPL(ahci_kick_engine); 1355 1356 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, 1357 struct ata_taskfile *tf, int is_cmd, u16 flags, 1358 unsigned long timeout_msec) 1359 { 1360 const u32 cmd_fis_len = 5; /* five dwords */ 1361 struct ahci_port_priv *pp = ap->private_data; 1362 void __iomem *port_mmio = ahci_port_base(ap); 1363 u8 *fis = pp->cmd_tbl; 1364 u32 tmp; 1365 1366 /* prep the command */ 1367 ata_tf_to_fis(tf, pmp, is_cmd, fis); 1368 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); 1369 1370 /* set port value for softreset of Port Multiplier */ 1371 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) { 1372 tmp = readl(port_mmio + PORT_FBS); 1373 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); 1374 tmp |= pmp << PORT_FBS_DEV_OFFSET; 1375 writel(tmp, port_mmio + PORT_FBS); 1376 pp->fbs_last_dev = pmp; 1377 } 1378 1379 /* issue & wait */ 1380 writel(1, port_mmio + PORT_CMD_ISSUE); 1381 1382 if (timeout_msec) { 1383 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE, 1384 0x1, 0x1, 1, timeout_msec); 1385 if (tmp & 0x1) { 1386 ahci_kick_engine(ap); 1387 return -EBUSY; 1388 } 1389 } else 1390 readl(port_mmio + PORT_CMD_ISSUE); /* flush */ 1391 1392 return 0; 1393 } 1394 1395 int ahci_do_softreset(struct ata_link *link, unsigned int *class, 1396 int pmp, unsigned long deadline, 1397 int (*check_ready)(struct ata_link *link)) 1398 { 1399 struct ata_port *ap = link->ap; 1400 struct ahci_host_priv *hpriv = ap->host->private_data; 1401 struct ahci_port_priv *pp = ap->private_data; 1402 const char *reason = NULL; 1403 unsigned long now, msecs; 1404 struct ata_taskfile tf; 1405 bool fbs_disabled = false; 1406 int rc; 1407 1408 DPRINTK("ENTER\n"); 1409 1410 /* prepare for SRST (AHCI-1.1 10.4.1) */ 1411 rc = ahci_kick_engine(ap); 1412 if (rc && rc != -EOPNOTSUPP) 1413 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc); 1414 1415 /* 1416 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall 1417 * clear PxFBS.EN to '0' prior to issuing software reset to devices 1418 * that is attached to port multiplier. 1419 */ 1420 if (!ata_is_host_link(link) && pp->fbs_enabled) { 1421 ahci_disable_fbs(ap); 1422 fbs_disabled = true; 1423 } 1424 1425 ata_tf_init(link->device, &tf); 1426 1427 /* issue the first H2D Register FIS */ 1428 msecs = 0; 1429 now = jiffies; 1430 if (time_after(deadline, now)) 1431 msecs = jiffies_to_msecs(deadline - now); 1432 1433 tf.ctl |= ATA_SRST; 1434 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, 1435 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { 1436 rc = -EIO; 1437 reason = "1st FIS failed"; 1438 goto fail; 1439 } 1440 1441 /* spec says at least 5us, but be generous and sleep for 1ms */ 1442 ata_msleep(ap, 1); 1443 1444 /* issue the second H2D Register FIS */ 1445 tf.ctl &= ~ATA_SRST; 1446 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); 1447 1448 /* wait for link to become ready */ 1449 rc = ata_wait_after_reset(link, deadline, check_ready); 1450 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) { 1451 /* 1452 * Workaround for cases where link online status can't 1453 * be trusted. Treat device readiness timeout as link 1454 * offline. 1455 */ 1456 ata_link_info(link, "device not ready, treating as offline\n"); 1457 *class = ATA_DEV_NONE; 1458 } else if (rc) { 1459 /* link occupied, -ENODEV too is an error */ 1460 reason = "device not ready"; 1461 goto fail; 1462 } else 1463 *class = ahci_dev_classify(ap); 1464 1465 /* re-enable FBS if disabled before */ 1466 if (fbs_disabled) 1467 ahci_enable_fbs(ap); 1468 1469 DPRINTK("EXIT, class=%u\n", *class); 1470 return 0; 1471 1472 fail: 1473 ata_link_err(link, "softreset failed (%s)\n", reason); 1474 return rc; 1475 } 1476 1477 int ahci_check_ready(struct ata_link *link) 1478 { 1479 void __iomem *port_mmio = ahci_port_base(link->ap); 1480 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1481 1482 return ata_check_ready(status); 1483 } 1484 EXPORT_SYMBOL_GPL(ahci_check_ready); 1485 1486 static int ahci_softreset(struct ata_link *link, unsigned int *class, 1487 unsigned long deadline) 1488 { 1489 int pmp = sata_srst_pmp(link); 1490 1491 DPRINTK("ENTER\n"); 1492 1493 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready); 1494 } 1495 EXPORT_SYMBOL_GPL(ahci_do_softreset); 1496 1497 static int ahci_bad_pmp_check_ready(struct ata_link *link) 1498 { 1499 void __iomem *port_mmio = ahci_port_base(link->ap); 1500 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1501 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT); 1502 1503 /* 1504 * There is no need to check TFDATA if BAD PMP is found due to HW bug, 1505 * which can save timeout delay. 1506 */ 1507 if (irq_status & PORT_IRQ_BAD_PMP) 1508 return -EIO; 1509 1510 return ata_check_ready(status); 1511 } 1512 1513 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class, 1514 unsigned long deadline) 1515 { 1516 struct ata_port *ap = link->ap; 1517 void __iomem *port_mmio = ahci_port_base(ap); 1518 int pmp = sata_srst_pmp(link); 1519 int rc; 1520 u32 irq_sts; 1521 1522 DPRINTK("ENTER\n"); 1523 1524 rc = ahci_do_softreset(link, class, pmp, deadline, 1525 ahci_bad_pmp_check_ready); 1526 1527 /* 1528 * Soft reset fails with IPMS set when PMP is enabled but 1529 * SATA HDD/ODD is connected to SATA port, do soft reset 1530 * again to port 0. 1531 */ 1532 if (rc == -EIO) { 1533 irq_sts = readl(port_mmio + PORT_IRQ_STAT); 1534 if (irq_sts & PORT_IRQ_BAD_PMP) { 1535 ata_link_warn(link, 1536 "applying PMP SRST workaround " 1537 "and retrying\n"); 1538 rc = ahci_do_softreset(link, class, 0, deadline, 1539 ahci_check_ready); 1540 } 1541 } 1542 1543 return rc; 1544 } 1545 1546 int ahci_do_hardreset(struct ata_link *link, unsigned int *class, 1547 unsigned long deadline, bool *online) 1548 { 1549 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 1550 struct ata_port *ap = link->ap; 1551 struct ahci_port_priv *pp = ap->private_data; 1552 struct ahci_host_priv *hpriv = ap->host->private_data; 1553 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 1554 struct ata_taskfile tf; 1555 int rc; 1556 1557 DPRINTK("ENTER\n"); 1558 1559 hpriv->stop_engine(ap); 1560 1561 /* clear D2H reception area to properly wait for D2H FIS */ 1562 ata_tf_init(link->device, &tf); 1563 tf.command = ATA_BUSY; 1564 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 1565 1566 rc = sata_link_hardreset(link, timing, deadline, online, 1567 ahci_check_ready); 1568 1569 hpriv->start_engine(ap); 1570 1571 if (*online) 1572 *class = ahci_dev_classify(ap); 1573 1574 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 1575 return rc; 1576 } 1577 EXPORT_SYMBOL_GPL(ahci_do_hardreset); 1578 1579 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 1580 unsigned long deadline) 1581 { 1582 bool online; 1583 1584 return ahci_do_hardreset(link, class, deadline, &online); 1585 } 1586 1587 static void ahci_postreset(struct ata_link *link, unsigned int *class) 1588 { 1589 struct ata_port *ap = link->ap; 1590 void __iomem *port_mmio = ahci_port_base(ap); 1591 u32 new_tmp, tmp; 1592 1593 ata_std_postreset(link, class); 1594 1595 /* Make sure port's ATAPI bit is set appropriately */ 1596 new_tmp = tmp = readl(port_mmio + PORT_CMD); 1597 if (*class == ATA_DEV_ATAPI) 1598 new_tmp |= PORT_CMD_ATAPI; 1599 else 1600 new_tmp &= ~PORT_CMD_ATAPI; 1601 if (new_tmp != tmp) { 1602 writel(new_tmp, port_mmio + PORT_CMD); 1603 readl(port_mmio + PORT_CMD); /* flush */ 1604 } 1605 } 1606 1607 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) 1608 { 1609 struct scatterlist *sg; 1610 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; 1611 unsigned int si; 1612 1613 VPRINTK("ENTER\n"); 1614 1615 /* 1616 * Next, the S/G list. 1617 */ 1618 for_each_sg(qc->sg, sg, qc->n_elem, si) { 1619 dma_addr_t addr = sg_dma_address(sg); 1620 u32 sg_len = sg_dma_len(sg); 1621 1622 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); 1623 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); 1624 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); 1625 } 1626 1627 return si; 1628 } 1629 1630 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc) 1631 { 1632 struct ata_port *ap = qc->ap; 1633 struct ahci_port_priv *pp = ap->private_data; 1634 1635 if (!sata_pmp_attached(ap) || pp->fbs_enabled) 1636 return ata_std_qc_defer(qc); 1637 else 1638 return sata_pmp_qc_defer_cmd_switch(qc); 1639 } 1640 1641 static void ahci_qc_prep(struct ata_queued_cmd *qc) 1642 { 1643 struct ata_port *ap = qc->ap; 1644 struct ahci_port_priv *pp = ap->private_data; 1645 int is_atapi = ata_is_atapi(qc->tf.protocol); 1646 void *cmd_tbl; 1647 u32 opts; 1648 const u32 cmd_fis_len = 5; /* five dwords */ 1649 unsigned int n_elem; 1650 1651 /* 1652 * Fill in command table information. First, the header, 1653 * a SATA Register - Host to Device command FIS. 1654 */ 1655 cmd_tbl = pp->cmd_tbl + qc->hw_tag * AHCI_CMD_TBL_SZ; 1656 1657 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); 1658 if (is_atapi) { 1659 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); 1660 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); 1661 } 1662 1663 n_elem = 0; 1664 if (qc->flags & ATA_QCFLAG_DMAMAP) 1665 n_elem = ahci_fill_sg(qc, cmd_tbl); 1666 1667 /* 1668 * Fill in command slot information. 1669 */ 1670 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); 1671 if (qc->tf.flags & ATA_TFLAG_WRITE) 1672 opts |= AHCI_CMD_WRITE; 1673 if (is_atapi) 1674 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; 1675 1676 ahci_fill_cmd_slot(pp, qc->hw_tag, opts); 1677 } 1678 1679 static void ahci_fbs_dec_intr(struct ata_port *ap) 1680 { 1681 struct ahci_port_priv *pp = ap->private_data; 1682 void __iomem *port_mmio = ahci_port_base(ap); 1683 u32 fbs = readl(port_mmio + PORT_FBS); 1684 int retries = 3; 1685 1686 DPRINTK("ENTER\n"); 1687 BUG_ON(!pp->fbs_enabled); 1688 1689 /* time to wait for DEC is not specified by AHCI spec, 1690 * add a retry loop for safety. 1691 */ 1692 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS); 1693 fbs = readl(port_mmio + PORT_FBS); 1694 while ((fbs & PORT_FBS_DEC) && retries--) { 1695 udelay(1); 1696 fbs = readl(port_mmio + PORT_FBS); 1697 } 1698 1699 if (fbs & PORT_FBS_DEC) 1700 dev_err(ap->host->dev, "failed to clear device error\n"); 1701 } 1702 1703 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) 1704 { 1705 struct ahci_host_priv *hpriv = ap->host->private_data; 1706 struct ahci_port_priv *pp = ap->private_data; 1707 struct ata_eh_info *host_ehi = &ap->link.eh_info; 1708 struct ata_link *link = NULL; 1709 struct ata_queued_cmd *active_qc; 1710 struct ata_eh_info *active_ehi; 1711 bool fbs_need_dec = false; 1712 u32 serror; 1713 1714 /* determine active link with error */ 1715 if (pp->fbs_enabled) { 1716 void __iomem *port_mmio = ahci_port_base(ap); 1717 u32 fbs = readl(port_mmio + PORT_FBS); 1718 int pmp = fbs >> PORT_FBS_DWE_OFFSET; 1719 1720 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) { 1721 link = &ap->pmp_link[pmp]; 1722 fbs_need_dec = true; 1723 } 1724 1725 } else 1726 ata_for_each_link(link, ap, EDGE) 1727 if (ata_link_active(link)) 1728 break; 1729 1730 if (!link) 1731 link = &ap->link; 1732 1733 active_qc = ata_qc_from_tag(ap, link->active_tag); 1734 active_ehi = &link->eh_info; 1735 1736 /* record irq stat */ 1737 ata_ehi_clear_desc(host_ehi); 1738 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); 1739 1740 /* AHCI needs SError cleared; otherwise, it might lock up */ 1741 ahci_scr_read(&ap->link, SCR_ERROR, &serror); 1742 ahci_scr_write(&ap->link, SCR_ERROR, serror); 1743 host_ehi->serror |= serror; 1744 1745 /* some controllers set IRQ_IF_ERR on device errors, ignore it */ 1746 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) 1747 irq_stat &= ~PORT_IRQ_IF_ERR; 1748 1749 if (irq_stat & PORT_IRQ_TF_ERR) { 1750 /* If qc is active, charge it; otherwise, the active 1751 * link. There's no active qc on NCQ errors. It will 1752 * be determined by EH by reading log page 10h. 1753 */ 1754 if (active_qc) 1755 active_qc->err_mask |= AC_ERR_DEV; 1756 else 1757 active_ehi->err_mask |= AC_ERR_DEV; 1758 1759 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) 1760 host_ehi->serror &= ~SERR_INTERNAL; 1761 } 1762 1763 if (irq_stat & PORT_IRQ_UNK_FIS) { 1764 u32 *unk = pp->rx_fis + RX_FIS_UNK; 1765 1766 active_ehi->err_mask |= AC_ERR_HSM; 1767 active_ehi->action |= ATA_EH_RESET; 1768 ata_ehi_push_desc(active_ehi, 1769 "unknown FIS %08x %08x %08x %08x" , 1770 unk[0], unk[1], unk[2], unk[3]); 1771 } 1772 1773 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) { 1774 active_ehi->err_mask |= AC_ERR_HSM; 1775 active_ehi->action |= ATA_EH_RESET; 1776 ata_ehi_push_desc(active_ehi, "incorrect PMP"); 1777 } 1778 1779 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { 1780 host_ehi->err_mask |= AC_ERR_HOST_BUS; 1781 host_ehi->action |= ATA_EH_RESET; 1782 ata_ehi_push_desc(host_ehi, "host bus error"); 1783 } 1784 1785 if (irq_stat & PORT_IRQ_IF_ERR) { 1786 if (fbs_need_dec) 1787 active_ehi->err_mask |= AC_ERR_DEV; 1788 else { 1789 host_ehi->err_mask |= AC_ERR_ATA_BUS; 1790 host_ehi->action |= ATA_EH_RESET; 1791 } 1792 1793 ata_ehi_push_desc(host_ehi, "interface fatal error"); 1794 } 1795 1796 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { 1797 ata_ehi_hotplugged(host_ehi); 1798 ata_ehi_push_desc(host_ehi, "%s", 1799 irq_stat & PORT_IRQ_CONNECT ? 1800 "connection status changed" : "PHY RDY changed"); 1801 } 1802 1803 /* okay, let's hand over to EH */ 1804 1805 if (irq_stat & PORT_IRQ_FREEZE) 1806 ata_port_freeze(ap); 1807 else if (fbs_need_dec) { 1808 ata_link_abort(link); 1809 ahci_fbs_dec_intr(ap); 1810 } else 1811 ata_port_abort(ap); 1812 } 1813 1814 static void ahci_handle_port_interrupt(struct ata_port *ap, 1815 void __iomem *port_mmio, u32 status) 1816 { 1817 struct ata_eh_info *ehi = &ap->link.eh_info; 1818 struct ahci_port_priv *pp = ap->private_data; 1819 struct ahci_host_priv *hpriv = ap->host->private_data; 1820 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING); 1821 u32 qc_active = 0; 1822 int rc; 1823 1824 /* ignore BAD_PMP while resetting */ 1825 if (unlikely(resetting)) 1826 status &= ~PORT_IRQ_BAD_PMP; 1827 1828 if (sata_lpm_ignore_phy_events(&ap->link)) { 1829 status &= ~PORT_IRQ_PHYRDY; 1830 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG); 1831 } 1832 1833 if (unlikely(status & PORT_IRQ_ERROR)) { 1834 ahci_error_intr(ap, status); 1835 return; 1836 } 1837 1838 if (status & PORT_IRQ_SDB_FIS) { 1839 /* If SNotification is available, leave notification 1840 * handling to sata_async_notification(). If not, 1841 * emulate it by snooping SDB FIS RX area. 1842 * 1843 * Snooping FIS RX area is probably cheaper than 1844 * poking SNotification but some constrollers which 1845 * implement SNotification, ICH9 for example, don't 1846 * store AN SDB FIS into receive area. 1847 */ 1848 if (hpriv->cap & HOST_CAP_SNTF) 1849 sata_async_notification(ap); 1850 else { 1851 /* If the 'N' bit in word 0 of the FIS is set, 1852 * we just received asynchronous notification. 1853 * Tell libata about it. 1854 * 1855 * Lack of SNotification should not appear in 1856 * ahci 1.2, so the workaround is unnecessary 1857 * when FBS is enabled. 1858 */ 1859 if (pp->fbs_enabled) 1860 WARN_ON_ONCE(1); 1861 else { 1862 const __le32 *f = pp->rx_fis + RX_FIS_SDB; 1863 u32 f0 = le32_to_cpu(f[0]); 1864 if (f0 & (1 << 15)) 1865 sata_async_notification(ap); 1866 } 1867 } 1868 } 1869 1870 /* pp->active_link is not reliable once FBS is enabled, both 1871 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because 1872 * NCQ and non-NCQ commands may be in flight at the same time. 1873 */ 1874 if (pp->fbs_enabled) { 1875 if (ap->qc_active) { 1876 qc_active = readl(port_mmio + PORT_SCR_ACT); 1877 qc_active |= readl(port_mmio + PORT_CMD_ISSUE); 1878 } 1879 } else { 1880 /* pp->active_link is valid iff any command is in flight */ 1881 if (ap->qc_active && pp->active_link->sactive) 1882 qc_active = readl(port_mmio + PORT_SCR_ACT); 1883 else 1884 qc_active = readl(port_mmio + PORT_CMD_ISSUE); 1885 } 1886 1887 1888 rc = ata_qc_complete_multiple(ap, qc_active); 1889 1890 /* while resetting, invalid completions are expected */ 1891 if (unlikely(rc < 0 && !resetting)) { 1892 ehi->err_mask |= AC_ERR_HSM; 1893 ehi->action |= ATA_EH_RESET; 1894 ata_port_freeze(ap); 1895 } 1896 } 1897 1898 static void ahci_port_intr(struct ata_port *ap) 1899 { 1900 void __iomem *port_mmio = ahci_port_base(ap); 1901 u32 status; 1902 1903 status = readl(port_mmio + PORT_IRQ_STAT); 1904 writel(status, port_mmio + PORT_IRQ_STAT); 1905 1906 ahci_handle_port_interrupt(ap, port_mmio, status); 1907 } 1908 1909 static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance) 1910 { 1911 struct ata_port *ap = dev_instance; 1912 void __iomem *port_mmio = ahci_port_base(ap); 1913 u32 status; 1914 1915 VPRINTK("ENTER\n"); 1916 1917 status = readl(port_mmio + PORT_IRQ_STAT); 1918 writel(status, port_mmio + PORT_IRQ_STAT); 1919 1920 spin_lock(ap->lock); 1921 ahci_handle_port_interrupt(ap, port_mmio, status); 1922 spin_unlock(ap->lock); 1923 1924 VPRINTK("EXIT\n"); 1925 1926 return IRQ_HANDLED; 1927 } 1928 1929 u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked) 1930 { 1931 unsigned int i, handled = 0; 1932 1933 for (i = 0; i < host->n_ports; i++) { 1934 struct ata_port *ap; 1935 1936 if (!(irq_masked & (1 << i))) 1937 continue; 1938 1939 ap = host->ports[i]; 1940 if (ap) { 1941 ahci_port_intr(ap); 1942 VPRINTK("port %u\n", i); 1943 } else { 1944 VPRINTK("port %u (no irq)\n", i); 1945 if (ata_ratelimit()) 1946 dev_warn(host->dev, 1947 "interrupt on disabled port %u\n", i); 1948 } 1949 1950 handled = 1; 1951 } 1952 1953 return handled; 1954 } 1955 EXPORT_SYMBOL_GPL(ahci_handle_port_intr); 1956 1957 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance) 1958 { 1959 struct ata_host *host = dev_instance; 1960 struct ahci_host_priv *hpriv; 1961 unsigned int rc = 0; 1962 void __iomem *mmio; 1963 u32 irq_stat, irq_masked; 1964 1965 VPRINTK("ENTER\n"); 1966 1967 hpriv = host->private_data; 1968 mmio = hpriv->mmio; 1969 1970 /* sigh. 0xffffffff is a valid return from h/w */ 1971 irq_stat = readl(mmio + HOST_IRQ_STAT); 1972 if (!irq_stat) 1973 return IRQ_NONE; 1974 1975 irq_masked = irq_stat & hpriv->port_map; 1976 1977 spin_lock(&host->lock); 1978 1979 rc = ahci_handle_port_intr(host, irq_masked); 1980 1981 /* HOST_IRQ_STAT behaves as level triggered latch meaning that 1982 * it should be cleared after all the port events are cleared; 1983 * otherwise, it will raise a spurious interrupt after each 1984 * valid one. Please read section 10.6.2 of ahci 1.1 for more 1985 * information. 1986 * 1987 * Also, use the unmasked value to clear interrupt as spurious 1988 * pending event on a dummy port might cause screaming IRQ. 1989 */ 1990 writel(irq_stat, mmio + HOST_IRQ_STAT); 1991 1992 spin_unlock(&host->lock); 1993 1994 VPRINTK("EXIT\n"); 1995 1996 return IRQ_RETVAL(rc); 1997 } 1998 1999 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) 2000 { 2001 struct ata_port *ap = qc->ap; 2002 void __iomem *port_mmio = ahci_port_base(ap); 2003 struct ahci_port_priv *pp = ap->private_data; 2004 2005 /* Keep track of the currently active link. It will be used 2006 * in completion path to determine whether NCQ phase is in 2007 * progress. 2008 */ 2009 pp->active_link = qc->dev->link; 2010 2011 if (ata_is_ncq(qc->tf.protocol)) 2012 writel(1 << qc->hw_tag, port_mmio + PORT_SCR_ACT); 2013 2014 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) { 2015 u32 fbs = readl(port_mmio + PORT_FBS); 2016 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); 2017 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET; 2018 writel(fbs, port_mmio + PORT_FBS); 2019 pp->fbs_last_dev = qc->dev->link->pmp; 2020 } 2021 2022 writel(1 << qc->hw_tag, port_mmio + PORT_CMD_ISSUE); 2023 2024 ahci_sw_activity(qc->dev->link); 2025 2026 return 0; 2027 } 2028 EXPORT_SYMBOL_GPL(ahci_qc_issue); 2029 2030 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc) 2031 { 2032 struct ahci_port_priv *pp = qc->ap->private_data; 2033 u8 *rx_fis = pp->rx_fis; 2034 2035 if (pp->fbs_enabled) 2036 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ; 2037 2038 /* 2039 * After a successful execution of an ATA PIO data-in command, 2040 * the device doesn't send D2H Reg FIS to update the TF and 2041 * the host should take TF and E_Status from the preceding PIO 2042 * Setup FIS. 2043 */ 2044 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE && 2045 !(qc->flags & ATA_QCFLAG_FAILED)) { 2046 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf); 2047 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15]; 2048 } else 2049 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf); 2050 2051 return true; 2052 } 2053 2054 static void ahci_freeze(struct ata_port *ap) 2055 { 2056 void __iomem *port_mmio = ahci_port_base(ap); 2057 2058 /* turn IRQ off */ 2059 writel(0, port_mmio + PORT_IRQ_MASK); 2060 } 2061 2062 static void ahci_thaw(struct ata_port *ap) 2063 { 2064 struct ahci_host_priv *hpriv = ap->host->private_data; 2065 void __iomem *mmio = hpriv->mmio; 2066 void __iomem *port_mmio = ahci_port_base(ap); 2067 u32 tmp; 2068 struct ahci_port_priv *pp = ap->private_data; 2069 2070 /* clear IRQ */ 2071 tmp = readl(port_mmio + PORT_IRQ_STAT); 2072 writel(tmp, port_mmio + PORT_IRQ_STAT); 2073 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); 2074 2075 /* turn IRQ back on */ 2076 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2077 } 2078 2079 void ahci_error_handler(struct ata_port *ap) 2080 { 2081 struct ahci_host_priv *hpriv = ap->host->private_data; 2082 2083 if (!(ap->pflags & ATA_PFLAG_FROZEN)) { 2084 /* restart engine */ 2085 hpriv->stop_engine(ap); 2086 hpriv->start_engine(ap); 2087 } 2088 2089 sata_pmp_error_handler(ap); 2090 2091 if (!ata_dev_enabled(ap->link.device)) 2092 hpriv->stop_engine(ap); 2093 } 2094 EXPORT_SYMBOL_GPL(ahci_error_handler); 2095 2096 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) 2097 { 2098 struct ata_port *ap = qc->ap; 2099 2100 /* make DMA engine forget about the failed command */ 2101 if (qc->flags & ATA_QCFLAG_FAILED) 2102 ahci_kick_engine(ap); 2103 } 2104 2105 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep) 2106 { 2107 struct ahci_host_priv *hpriv = ap->host->private_data; 2108 void __iomem *port_mmio = ahci_port_base(ap); 2109 struct ata_device *dev = ap->link.device; 2110 u32 devslp, dm, dito, mdat, deto; 2111 int rc; 2112 unsigned int err_mask; 2113 2114 devslp = readl(port_mmio + PORT_DEVSLP); 2115 if (!(devslp & PORT_DEVSLP_DSP)) { 2116 dev_info(ap->host->dev, "port does not support device sleep\n"); 2117 return; 2118 } 2119 2120 /* disable device sleep */ 2121 if (!sleep) { 2122 if (devslp & PORT_DEVSLP_ADSE) { 2123 writel(devslp & ~PORT_DEVSLP_ADSE, 2124 port_mmio + PORT_DEVSLP); 2125 err_mask = ata_dev_set_feature(dev, 2126 SETFEATURES_SATA_DISABLE, 2127 SATA_DEVSLP); 2128 if (err_mask && err_mask != AC_ERR_DEV) 2129 ata_dev_warn(dev, "failed to disable DEVSLP\n"); 2130 } 2131 return; 2132 } 2133 2134 /* device sleep was already enabled */ 2135 if (devslp & PORT_DEVSLP_ADSE) 2136 return; 2137 2138 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */ 2139 rc = hpriv->stop_engine(ap); 2140 if (rc) 2141 return; 2142 2143 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET; 2144 dito = devslp_idle_timeout / (dm + 1); 2145 if (dito > 0x3ff) 2146 dito = 0x3ff; 2147 2148 /* Use the nominal value 10 ms if the read MDAT is zero, 2149 * the nominal value of DETO is 20 ms. 2150 */ 2151 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] & 2152 ATA_LOG_DEVSLP_VALID_MASK) { 2153 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] & 2154 ATA_LOG_DEVSLP_MDAT_MASK; 2155 if (!mdat) 2156 mdat = 10; 2157 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO]; 2158 if (!deto) 2159 deto = 20; 2160 } else { 2161 mdat = 10; 2162 deto = 20; 2163 } 2164 2165 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) | 2166 (mdat << PORT_DEVSLP_MDAT_OFFSET) | 2167 (deto << PORT_DEVSLP_DETO_OFFSET) | 2168 PORT_DEVSLP_ADSE); 2169 writel(devslp, port_mmio + PORT_DEVSLP); 2170 2171 hpriv->start_engine(ap); 2172 2173 /* enable device sleep feature for the drive */ 2174 err_mask = ata_dev_set_feature(dev, 2175 SETFEATURES_SATA_ENABLE, 2176 SATA_DEVSLP); 2177 if (err_mask && err_mask != AC_ERR_DEV) 2178 ata_dev_warn(dev, "failed to enable DEVSLP\n"); 2179 } 2180 2181 static void ahci_enable_fbs(struct ata_port *ap) 2182 { 2183 struct ahci_host_priv *hpriv = ap->host->private_data; 2184 struct ahci_port_priv *pp = ap->private_data; 2185 void __iomem *port_mmio = ahci_port_base(ap); 2186 u32 fbs; 2187 int rc; 2188 2189 if (!pp->fbs_supported) 2190 return; 2191 2192 fbs = readl(port_mmio + PORT_FBS); 2193 if (fbs & PORT_FBS_EN) { 2194 pp->fbs_enabled = true; 2195 pp->fbs_last_dev = -1; /* initialization */ 2196 return; 2197 } 2198 2199 rc = hpriv->stop_engine(ap); 2200 if (rc) 2201 return; 2202 2203 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS); 2204 fbs = readl(port_mmio + PORT_FBS); 2205 if (fbs & PORT_FBS_EN) { 2206 dev_info(ap->host->dev, "FBS is enabled\n"); 2207 pp->fbs_enabled = true; 2208 pp->fbs_last_dev = -1; /* initialization */ 2209 } else 2210 dev_err(ap->host->dev, "Failed to enable FBS\n"); 2211 2212 hpriv->start_engine(ap); 2213 } 2214 2215 static void ahci_disable_fbs(struct ata_port *ap) 2216 { 2217 struct ahci_host_priv *hpriv = ap->host->private_data; 2218 struct ahci_port_priv *pp = ap->private_data; 2219 void __iomem *port_mmio = ahci_port_base(ap); 2220 u32 fbs; 2221 int rc; 2222 2223 if (!pp->fbs_supported) 2224 return; 2225 2226 fbs = readl(port_mmio + PORT_FBS); 2227 if ((fbs & PORT_FBS_EN) == 0) { 2228 pp->fbs_enabled = false; 2229 return; 2230 } 2231 2232 rc = hpriv->stop_engine(ap); 2233 if (rc) 2234 return; 2235 2236 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS); 2237 fbs = readl(port_mmio + PORT_FBS); 2238 if (fbs & PORT_FBS_EN) 2239 dev_err(ap->host->dev, "Failed to disable FBS\n"); 2240 else { 2241 dev_info(ap->host->dev, "FBS is disabled\n"); 2242 pp->fbs_enabled = false; 2243 } 2244 2245 hpriv->start_engine(ap); 2246 } 2247 2248 static void ahci_pmp_attach(struct ata_port *ap) 2249 { 2250 void __iomem *port_mmio = ahci_port_base(ap); 2251 struct ahci_port_priv *pp = ap->private_data; 2252 u32 cmd; 2253 2254 cmd = readl(port_mmio + PORT_CMD); 2255 cmd |= PORT_CMD_PMP; 2256 writel(cmd, port_mmio + PORT_CMD); 2257 2258 ahci_enable_fbs(ap); 2259 2260 pp->intr_mask |= PORT_IRQ_BAD_PMP; 2261 2262 /* 2263 * We must not change the port interrupt mask register if the 2264 * port is marked frozen, the value in pp->intr_mask will be 2265 * restored later when the port is thawed. 2266 * 2267 * Note that during initialization, the port is marked as 2268 * frozen since the irq handler is not yet registered. 2269 */ 2270 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 2271 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2272 } 2273 2274 static void ahci_pmp_detach(struct ata_port *ap) 2275 { 2276 void __iomem *port_mmio = ahci_port_base(ap); 2277 struct ahci_port_priv *pp = ap->private_data; 2278 u32 cmd; 2279 2280 ahci_disable_fbs(ap); 2281 2282 cmd = readl(port_mmio + PORT_CMD); 2283 cmd &= ~PORT_CMD_PMP; 2284 writel(cmd, port_mmio + PORT_CMD); 2285 2286 pp->intr_mask &= ~PORT_IRQ_BAD_PMP; 2287 2288 /* see comment above in ahci_pmp_attach() */ 2289 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 2290 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2291 } 2292 2293 int ahci_port_resume(struct ata_port *ap) 2294 { 2295 ahci_rpm_get_port(ap); 2296 2297 ahci_power_up(ap); 2298 ahci_start_port(ap); 2299 2300 if (sata_pmp_attached(ap)) 2301 ahci_pmp_attach(ap); 2302 else 2303 ahci_pmp_detach(ap); 2304 2305 return 0; 2306 } 2307 EXPORT_SYMBOL_GPL(ahci_port_resume); 2308 2309 #ifdef CONFIG_PM 2310 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) 2311 { 2312 const char *emsg = NULL; 2313 int rc; 2314 2315 rc = ahci_deinit_port(ap, &emsg); 2316 if (rc == 0) 2317 ahci_power_down(ap); 2318 else { 2319 ata_port_err(ap, "%s (%d)\n", emsg, rc); 2320 ata_port_freeze(ap); 2321 } 2322 2323 ahci_rpm_put_port(ap); 2324 return rc; 2325 } 2326 #endif 2327 2328 static int ahci_port_start(struct ata_port *ap) 2329 { 2330 struct ahci_host_priv *hpriv = ap->host->private_data; 2331 struct device *dev = ap->host->dev; 2332 struct ahci_port_priv *pp; 2333 void *mem; 2334 dma_addr_t mem_dma; 2335 size_t dma_sz, rx_fis_sz; 2336 2337 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 2338 if (!pp) 2339 return -ENOMEM; 2340 2341 if (ap->host->n_ports > 1) { 2342 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL); 2343 if (!pp->irq_desc) { 2344 devm_kfree(dev, pp); 2345 return -ENOMEM; 2346 } 2347 snprintf(pp->irq_desc, 8, 2348 "%s%d", dev_driver_string(dev), ap->port_no); 2349 } 2350 2351 /* check FBS capability */ 2352 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) { 2353 void __iomem *port_mmio = ahci_port_base(ap); 2354 u32 cmd = readl(port_mmio + PORT_CMD); 2355 if (cmd & PORT_CMD_FBSCP) 2356 pp->fbs_supported = true; 2357 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) { 2358 dev_info(dev, "port %d can do FBS, forcing FBSCP\n", 2359 ap->port_no); 2360 pp->fbs_supported = true; 2361 } else 2362 dev_warn(dev, "port %d is not capable of FBS\n", 2363 ap->port_no); 2364 } 2365 2366 if (pp->fbs_supported) { 2367 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ; 2368 rx_fis_sz = AHCI_RX_FIS_SZ * 16; 2369 } else { 2370 dma_sz = AHCI_PORT_PRIV_DMA_SZ; 2371 rx_fis_sz = AHCI_RX_FIS_SZ; 2372 } 2373 2374 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL); 2375 if (!mem) 2376 return -ENOMEM; 2377 memset(mem, 0, dma_sz); 2378 2379 /* 2380 * First item in chunk of DMA memory: 32-slot command table, 2381 * 32 bytes each in size 2382 */ 2383 pp->cmd_slot = mem; 2384 pp->cmd_slot_dma = mem_dma; 2385 2386 mem += AHCI_CMD_SLOT_SZ; 2387 mem_dma += AHCI_CMD_SLOT_SZ; 2388 2389 /* 2390 * Second item: Received-FIS area 2391 */ 2392 pp->rx_fis = mem; 2393 pp->rx_fis_dma = mem_dma; 2394 2395 mem += rx_fis_sz; 2396 mem_dma += rx_fis_sz; 2397 2398 /* 2399 * Third item: data area for storing a single command 2400 * and its scatter-gather table 2401 */ 2402 pp->cmd_tbl = mem; 2403 pp->cmd_tbl_dma = mem_dma; 2404 2405 /* 2406 * Save off initial list of interrupts to be enabled. 2407 * This could be changed later 2408 */ 2409 pp->intr_mask = DEF_PORT_IRQ; 2410 2411 /* 2412 * Switch to per-port locking in case each port has its own MSI vector. 2413 */ 2414 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) { 2415 spin_lock_init(&pp->lock); 2416 ap->lock = &pp->lock; 2417 } 2418 2419 ap->private_data = pp; 2420 2421 /* engage engines, captain */ 2422 return ahci_port_resume(ap); 2423 } 2424 2425 static void ahci_port_stop(struct ata_port *ap) 2426 { 2427 const char *emsg = NULL; 2428 struct ahci_host_priv *hpriv = ap->host->private_data; 2429 void __iomem *host_mmio = hpriv->mmio; 2430 int rc; 2431 2432 /* de-initialize port */ 2433 rc = ahci_deinit_port(ap, &emsg); 2434 if (rc) 2435 ata_port_warn(ap, "%s (%d)\n", emsg, rc); 2436 2437 /* 2438 * Clear GHC.IS to prevent stuck INTx after disabling MSI and 2439 * re-enabling INTx. 2440 */ 2441 writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT); 2442 } 2443 2444 void ahci_print_info(struct ata_host *host, const char *scc_s) 2445 { 2446 struct ahci_host_priv *hpriv = host->private_data; 2447 u32 vers, cap, cap2, impl, speed; 2448 const char *speed_s; 2449 2450 vers = hpriv->version; 2451 cap = hpriv->cap; 2452 cap2 = hpriv->cap2; 2453 impl = hpriv->port_map; 2454 2455 speed = (cap >> 20) & 0xf; 2456 if (speed == 1) 2457 speed_s = "1.5"; 2458 else if (speed == 2) 2459 speed_s = "3"; 2460 else if (speed == 3) 2461 speed_s = "6"; 2462 else 2463 speed_s = "?"; 2464 2465 dev_info(host->dev, 2466 "AHCI %02x%02x.%02x%02x " 2467 "%u slots %u ports %s Gbps 0x%x impl %s mode\n" 2468 , 2469 2470 (vers >> 24) & 0xff, 2471 (vers >> 16) & 0xff, 2472 (vers >> 8) & 0xff, 2473 vers & 0xff, 2474 2475 ((cap >> 8) & 0x1f) + 1, 2476 (cap & 0x1f) + 1, 2477 speed_s, 2478 impl, 2479 scc_s); 2480 2481 dev_info(host->dev, 2482 "flags: " 2483 "%s%s%s%s%s%s%s" 2484 "%s%s%s%s%s%s%s" 2485 "%s%s%s%s%s%s%s" 2486 "%s%s\n" 2487 , 2488 2489 cap & HOST_CAP_64 ? "64bit " : "", 2490 cap & HOST_CAP_NCQ ? "ncq " : "", 2491 cap & HOST_CAP_SNTF ? "sntf " : "", 2492 cap & HOST_CAP_MPS ? "ilck " : "", 2493 cap & HOST_CAP_SSS ? "stag " : "", 2494 cap & HOST_CAP_ALPM ? "pm " : "", 2495 cap & HOST_CAP_LED ? "led " : "", 2496 cap & HOST_CAP_CLO ? "clo " : "", 2497 cap & HOST_CAP_ONLY ? "only " : "", 2498 cap & HOST_CAP_PMP ? "pmp " : "", 2499 cap & HOST_CAP_FBS ? "fbs " : "", 2500 cap & HOST_CAP_PIO_MULTI ? "pio " : "", 2501 cap & HOST_CAP_SSC ? "slum " : "", 2502 cap & HOST_CAP_PART ? "part " : "", 2503 cap & HOST_CAP_CCC ? "ccc " : "", 2504 cap & HOST_CAP_EMS ? "ems " : "", 2505 cap & HOST_CAP_SXS ? "sxs " : "", 2506 cap2 & HOST_CAP2_DESO ? "deso " : "", 2507 cap2 & HOST_CAP2_SADM ? "sadm " : "", 2508 cap2 & HOST_CAP2_SDS ? "sds " : "", 2509 cap2 & HOST_CAP2_APST ? "apst " : "", 2510 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "", 2511 cap2 & HOST_CAP2_BOH ? "boh " : "" 2512 ); 2513 } 2514 EXPORT_SYMBOL_GPL(ahci_print_info); 2515 2516 void ahci_set_em_messages(struct ahci_host_priv *hpriv, 2517 struct ata_port_info *pi) 2518 { 2519 u8 messages; 2520 void __iomem *mmio = hpriv->mmio; 2521 u32 em_loc = readl(mmio + HOST_EM_LOC); 2522 u32 em_ctl = readl(mmio + HOST_EM_CTL); 2523 2524 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS)) 2525 return; 2526 2527 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16; 2528 2529 if (messages) { 2530 /* store em_loc */ 2531 hpriv->em_loc = ((em_loc >> 16) * 4); 2532 hpriv->em_buf_sz = ((em_loc & 0xff) * 4); 2533 hpriv->em_msg_type = messages; 2534 pi->flags |= ATA_FLAG_EM; 2535 if (!(em_ctl & EM_CTL_ALHD)) 2536 pi->flags |= ATA_FLAG_SW_ACTIVITY; 2537 } 2538 } 2539 EXPORT_SYMBOL_GPL(ahci_set_em_messages); 2540 2541 static int ahci_host_activate_multi_irqs(struct ata_host *host, 2542 struct scsi_host_template *sht) 2543 { 2544 struct ahci_host_priv *hpriv = host->private_data; 2545 int i, rc; 2546 2547 rc = ata_host_start(host); 2548 if (rc) 2549 return rc; 2550 /* 2551 * Requests IRQs according to AHCI-1.1 when multiple MSIs were 2552 * allocated. That is one MSI per port, starting from @irq. 2553 */ 2554 for (i = 0; i < host->n_ports; i++) { 2555 struct ahci_port_priv *pp = host->ports[i]->private_data; 2556 int irq = hpriv->get_irq_vector(host, i); 2557 2558 /* Do not receive interrupts sent by dummy ports */ 2559 if (!pp) { 2560 disable_irq(irq); 2561 continue; 2562 } 2563 2564 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard, 2565 0, pp->irq_desc, host->ports[i]); 2566 2567 if (rc) 2568 return rc; 2569 ata_port_desc(host->ports[i], "irq %d", irq); 2570 } 2571 2572 return ata_host_register(host, sht); 2573 } 2574 2575 /** 2576 * ahci_host_activate - start AHCI host, request IRQs and register it 2577 * @host: target ATA host 2578 * @sht: scsi_host_template to use when registering the host 2579 * 2580 * LOCKING: 2581 * Inherited from calling layer (may sleep). 2582 * 2583 * RETURNS: 2584 * 0 on success, -errno otherwise. 2585 */ 2586 int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht) 2587 { 2588 struct ahci_host_priv *hpriv = host->private_data; 2589 int irq = hpriv->irq; 2590 int rc; 2591 2592 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) { 2593 if (hpriv->irq_handler) 2594 dev_warn(host->dev, 2595 "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n"); 2596 if (!hpriv->get_irq_vector) { 2597 dev_err(host->dev, 2598 "AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n"); 2599 return -EIO; 2600 } 2601 2602 rc = ahci_host_activate_multi_irqs(host, sht); 2603 } else { 2604 rc = ata_host_activate(host, irq, hpriv->irq_handler, 2605 IRQF_SHARED, sht); 2606 } 2607 2608 2609 return rc; 2610 } 2611 EXPORT_SYMBOL_GPL(ahci_host_activate); 2612 2613 MODULE_AUTHOR("Jeff Garzik"); 2614 MODULE_DESCRIPTION("Common AHCI SATA low-level routines"); 2615 MODULE_LICENSE("GPL"); 2616