1 /* 2 * libahci.c - Common AHCI SATA low-level routines 3 * 4 * Maintained by: Tejun Heo <tj@kernel.org> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2004-2005 Red Hat, Inc. 9 * 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; see the file COPYING. If not, write to 23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * 26 * libata documentation is available via 'make {ps|pdf}docs', 27 * as Documentation/DocBook/libata.* 28 * 29 * AHCI hardware documentation: 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 32 * 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/gfp.h> 37 #include <linux/module.h> 38 #include <linux/blkdev.h> 39 #include <linux/delay.h> 40 #include <linux/interrupt.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/device.h> 43 #include <scsi/scsi_host.h> 44 #include <scsi/scsi_cmnd.h> 45 #include <linux/libata.h> 46 #include <linux/pci.h> 47 #include "ahci.h" 48 #include "libata.h" 49 50 static int ahci_skip_host_reset; 51 int ahci_ignore_sss; 52 EXPORT_SYMBOL_GPL(ahci_ignore_sss); 53 54 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); 55 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); 56 57 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444); 58 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)"); 59 60 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 61 unsigned hints); 62 static ssize_t ahci_led_show(struct ata_port *ap, char *buf); 63 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 64 size_t size); 65 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 66 ssize_t size); 67 68 69 70 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); 71 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); 72 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc); 73 static int ahci_port_start(struct ata_port *ap); 74 static void ahci_port_stop(struct ata_port *ap); 75 static void ahci_qc_prep(struct ata_queued_cmd *qc); 76 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc); 77 static void ahci_freeze(struct ata_port *ap); 78 static void ahci_thaw(struct ata_port *ap); 79 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep); 80 static void ahci_enable_fbs(struct ata_port *ap); 81 static void ahci_disable_fbs(struct ata_port *ap); 82 static void ahci_pmp_attach(struct ata_port *ap); 83 static void ahci_pmp_detach(struct ata_port *ap); 84 static int ahci_softreset(struct ata_link *link, unsigned int *class, 85 unsigned long deadline); 86 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class, 87 unsigned long deadline); 88 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 89 unsigned long deadline); 90 static void ahci_postreset(struct ata_link *link, unsigned int *class); 91 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); 92 static void ahci_dev_config(struct ata_device *dev); 93 #ifdef CONFIG_PM 94 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); 95 #endif 96 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf); 97 static ssize_t ahci_activity_store(struct ata_device *dev, 98 enum sw_activity val); 99 static void ahci_init_sw_activity(struct ata_link *link); 100 101 static ssize_t ahci_show_host_caps(struct device *dev, 102 struct device_attribute *attr, char *buf); 103 static ssize_t ahci_show_host_cap2(struct device *dev, 104 struct device_attribute *attr, char *buf); 105 static ssize_t ahci_show_host_version(struct device *dev, 106 struct device_attribute *attr, char *buf); 107 static ssize_t ahci_show_port_cmd(struct device *dev, 108 struct device_attribute *attr, char *buf); 109 static ssize_t ahci_read_em_buffer(struct device *dev, 110 struct device_attribute *attr, char *buf); 111 static ssize_t ahci_store_em_buffer(struct device *dev, 112 struct device_attribute *attr, 113 const char *buf, size_t size); 114 static ssize_t ahci_show_em_supported(struct device *dev, 115 struct device_attribute *attr, char *buf); 116 117 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL); 118 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL); 119 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL); 120 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL); 121 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO, 122 ahci_read_em_buffer, ahci_store_em_buffer); 123 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL); 124 125 struct device_attribute *ahci_shost_attrs[] = { 126 &dev_attr_link_power_management_policy, 127 &dev_attr_em_message_type, 128 &dev_attr_em_message, 129 &dev_attr_ahci_host_caps, 130 &dev_attr_ahci_host_cap2, 131 &dev_attr_ahci_host_version, 132 &dev_attr_ahci_port_cmd, 133 &dev_attr_em_buffer, 134 &dev_attr_em_message_supported, 135 NULL 136 }; 137 EXPORT_SYMBOL_GPL(ahci_shost_attrs); 138 139 struct device_attribute *ahci_sdev_attrs[] = { 140 &dev_attr_sw_activity, 141 &dev_attr_unload_heads, 142 NULL 143 }; 144 EXPORT_SYMBOL_GPL(ahci_sdev_attrs); 145 146 struct ata_port_operations ahci_ops = { 147 .inherits = &sata_pmp_port_ops, 148 149 .qc_defer = ahci_pmp_qc_defer, 150 .qc_prep = ahci_qc_prep, 151 .qc_issue = ahci_qc_issue, 152 .qc_fill_rtf = ahci_qc_fill_rtf, 153 154 .freeze = ahci_freeze, 155 .thaw = ahci_thaw, 156 .softreset = ahci_softreset, 157 .hardreset = ahci_hardreset, 158 .postreset = ahci_postreset, 159 .pmp_softreset = ahci_softreset, 160 .error_handler = ahci_error_handler, 161 .post_internal_cmd = ahci_post_internal_cmd, 162 .dev_config = ahci_dev_config, 163 164 .scr_read = ahci_scr_read, 165 .scr_write = ahci_scr_write, 166 .pmp_attach = ahci_pmp_attach, 167 .pmp_detach = ahci_pmp_detach, 168 169 .set_lpm = ahci_set_lpm, 170 .em_show = ahci_led_show, 171 .em_store = ahci_led_store, 172 .sw_activity_show = ahci_activity_show, 173 .sw_activity_store = ahci_activity_store, 174 .transmit_led_message = ahci_transmit_led_message, 175 #ifdef CONFIG_PM 176 .port_suspend = ahci_port_suspend, 177 .port_resume = ahci_port_resume, 178 #endif 179 .port_start = ahci_port_start, 180 .port_stop = ahci_port_stop, 181 }; 182 EXPORT_SYMBOL_GPL(ahci_ops); 183 184 struct ata_port_operations ahci_pmp_retry_srst_ops = { 185 .inherits = &ahci_ops, 186 .softreset = ahci_pmp_retry_softreset, 187 }; 188 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops); 189 190 static bool ahci_em_messages __read_mostly = true; 191 EXPORT_SYMBOL_GPL(ahci_em_messages); 192 module_param(ahci_em_messages, bool, 0444); 193 /* add other LED protocol types when they become supported */ 194 MODULE_PARM_DESC(ahci_em_messages, 195 "AHCI Enclosure Management Message control (0 = off, 1 = on)"); 196 197 /* device sleep idle timeout in ms */ 198 static int devslp_idle_timeout __read_mostly = 1000; 199 module_param(devslp_idle_timeout, int, 0644); 200 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout"); 201 202 static void ahci_enable_ahci(void __iomem *mmio) 203 { 204 int i; 205 u32 tmp; 206 207 /* turn on AHCI_EN */ 208 tmp = readl(mmio + HOST_CTL); 209 if (tmp & HOST_AHCI_EN) 210 return; 211 212 /* Some controllers need AHCI_EN to be written multiple times. 213 * Try a few times before giving up. 214 */ 215 for (i = 0; i < 5; i++) { 216 tmp |= HOST_AHCI_EN; 217 writel(tmp, mmio + HOST_CTL); 218 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ 219 if (tmp & HOST_AHCI_EN) 220 return; 221 msleep(10); 222 } 223 224 WARN_ON(1); 225 } 226 227 static ssize_t ahci_show_host_caps(struct device *dev, 228 struct device_attribute *attr, char *buf) 229 { 230 struct Scsi_Host *shost = class_to_shost(dev); 231 struct ata_port *ap = ata_shost_to_port(shost); 232 struct ahci_host_priv *hpriv = ap->host->private_data; 233 234 return sprintf(buf, "%x\n", hpriv->cap); 235 } 236 237 static ssize_t ahci_show_host_cap2(struct device *dev, 238 struct device_attribute *attr, char *buf) 239 { 240 struct Scsi_Host *shost = class_to_shost(dev); 241 struct ata_port *ap = ata_shost_to_port(shost); 242 struct ahci_host_priv *hpriv = ap->host->private_data; 243 244 return sprintf(buf, "%x\n", hpriv->cap2); 245 } 246 247 static ssize_t ahci_show_host_version(struct device *dev, 248 struct device_attribute *attr, char *buf) 249 { 250 struct Scsi_Host *shost = class_to_shost(dev); 251 struct ata_port *ap = ata_shost_to_port(shost); 252 struct ahci_host_priv *hpriv = ap->host->private_data; 253 void __iomem *mmio = hpriv->mmio; 254 255 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION)); 256 } 257 258 static ssize_t ahci_show_port_cmd(struct device *dev, 259 struct device_attribute *attr, char *buf) 260 { 261 struct Scsi_Host *shost = class_to_shost(dev); 262 struct ata_port *ap = ata_shost_to_port(shost); 263 void __iomem *port_mmio = ahci_port_base(ap); 264 265 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD)); 266 } 267 268 static ssize_t ahci_read_em_buffer(struct device *dev, 269 struct device_attribute *attr, char *buf) 270 { 271 struct Scsi_Host *shost = class_to_shost(dev); 272 struct ata_port *ap = ata_shost_to_port(shost); 273 struct ahci_host_priv *hpriv = ap->host->private_data; 274 void __iomem *mmio = hpriv->mmio; 275 void __iomem *em_mmio = mmio + hpriv->em_loc; 276 u32 em_ctl, msg; 277 unsigned long flags; 278 size_t count; 279 int i; 280 281 spin_lock_irqsave(ap->lock, flags); 282 283 em_ctl = readl(mmio + HOST_EM_CTL); 284 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT || 285 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) { 286 spin_unlock_irqrestore(ap->lock, flags); 287 return -EINVAL; 288 } 289 290 if (!(em_ctl & EM_CTL_MR)) { 291 spin_unlock_irqrestore(ap->lock, flags); 292 return -EAGAIN; 293 } 294 295 if (!(em_ctl & EM_CTL_SMB)) 296 em_mmio += hpriv->em_buf_sz; 297 298 count = hpriv->em_buf_sz; 299 300 /* the count should not be larger than PAGE_SIZE */ 301 if (count > PAGE_SIZE) { 302 if (printk_ratelimit()) 303 ata_port_warn(ap, 304 "EM read buffer size too large: " 305 "buffer size %u, page size %lu\n", 306 hpriv->em_buf_sz, PAGE_SIZE); 307 count = PAGE_SIZE; 308 } 309 310 for (i = 0; i < count; i += 4) { 311 msg = readl(em_mmio + i); 312 buf[i] = msg & 0xff; 313 buf[i + 1] = (msg >> 8) & 0xff; 314 buf[i + 2] = (msg >> 16) & 0xff; 315 buf[i + 3] = (msg >> 24) & 0xff; 316 } 317 318 spin_unlock_irqrestore(ap->lock, flags); 319 320 return i; 321 } 322 323 static ssize_t ahci_store_em_buffer(struct device *dev, 324 struct device_attribute *attr, 325 const char *buf, size_t size) 326 { 327 struct Scsi_Host *shost = class_to_shost(dev); 328 struct ata_port *ap = ata_shost_to_port(shost); 329 struct ahci_host_priv *hpriv = ap->host->private_data; 330 void __iomem *mmio = hpriv->mmio; 331 void __iomem *em_mmio = mmio + hpriv->em_loc; 332 const unsigned char *msg_buf = buf; 333 u32 em_ctl, msg; 334 unsigned long flags; 335 int i; 336 337 /* check size validity */ 338 if (!(ap->flags & ATA_FLAG_EM) || 339 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) || 340 size % 4 || size > hpriv->em_buf_sz) 341 return -EINVAL; 342 343 spin_lock_irqsave(ap->lock, flags); 344 345 em_ctl = readl(mmio + HOST_EM_CTL); 346 if (em_ctl & EM_CTL_TM) { 347 spin_unlock_irqrestore(ap->lock, flags); 348 return -EBUSY; 349 } 350 351 for (i = 0; i < size; i += 4) { 352 msg = msg_buf[i] | msg_buf[i + 1] << 8 | 353 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24; 354 writel(msg, em_mmio + i); 355 } 356 357 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 358 359 spin_unlock_irqrestore(ap->lock, flags); 360 361 return size; 362 } 363 364 static ssize_t ahci_show_em_supported(struct device *dev, 365 struct device_attribute *attr, char *buf) 366 { 367 struct Scsi_Host *shost = class_to_shost(dev); 368 struct ata_port *ap = ata_shost_to_port(shost); 369 struct ahci_host_priv *hpriv = ap->host->private_data; 370 void __iomem *mmio = hpriv->mmio; 371 u32 em_ctl; 372 373 em_ctl = readl(mmio + HOST_EM_CTL); 374 375 return sprintf(buf, "%s%s%s%s\n", 376 em_ctl & EM_CTL_LED ? "led " : "", 377 em_ctl & EM_CTL_SAFTE ? "saf-te " : "", 378 em_ctl & EM_CTL_SES ? "ses-2 " : "", 379 em_ctl & EM_CTL_SGPIO ? "sgpio " : ""); 380 } 381 382 /** 383 * ahci_save_initial_config - Save and fixup initial config values 384 * @dev: target AHCI device 385 * @hpriv: host private area to store config values 386 * 387 * Some registers containing configuration info might be setup by 388 * BIOS and might be cleared on reset. This function saves the 389 * initial values of those registers into @hpriv such that they 390 * can be restored after controller reset. 391 * 392 * If inconsistent, config values are fixed up by this function. 393 * 394 * If it is not set already this function sets hpriv->start_engine to 395 * ahci_start_engine. 396 * 397 * LOCKING: 398 * None. 399 */ 400 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv) 401 { 402 void __iomem *mmio = hpriv->mmio; 403 u32 cap, cap2, vers, port_map; 404 int i; 405 406 /* make sure AHCI mode is enabled before accessing CAP */ 407 ahci_enable_ahci(mmio); 408 409 /* Values prefixed with saved_ are written back to host after 410 * reset. Values without are used for driver operation. 411 */ 412 hpriv->saved_cap = cap = readl(mmio + HOST_CAP); 413 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); 414 415 /* CAP2 register is only defined for AHCI 1.2 and later */ 416 vers = readl(mmio + HOST_VERSION); 417 if ((vers >> 16) > 1 || 418 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200)) 419 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2); 420 else 421 hpriv->saved_cap2 = cap2 = 0; 422 423 /* some chips have errata preventing 64bit use */ 424 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { 425 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n"); 426 cap &= ~HOST_CAP_64; 427 } 428 429 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { 430 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n"); 431 cap &= ~HOST_CAP_NCQ; 432 } 433 434 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) { 435 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n"); 436 cap |= HOST_CAP_NCQ; 437 } 438 439 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { 440 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n"); 441 cap &= ~HOST_CAP_PMP; 442 } 443 444 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) { 445 dev_info(dev, 446 "controller can't do SNTF, turning off CAP_SNTF\n"); 447 cap &= ~HOST_CAP_SNTF; 448 } 449 450 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) { 451 dev_info(dev, 452 "controller can't do DEVSLP, turning off\n"); 453 cap2 &= ~HOST_CAP2_SDS; 454 cap2 &= ~HOST_CAP2_SADM; 455 } 456 457 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) { 458 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n"); 459 cap |= HOST_CAP_FBS; 460 } 461 462 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) { 463 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n"); 464 cap &= ~HOST_CAP_FBS; 465 } 466 467 if (hpriv->force_port_map && port_map != hpriv->force_port_map) { 468 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n", 469 port_map, hpriv->force_port_map); 470 port_map = hpriv->force_port_map; 471 } 472 473 if (hpriv->mask_port_map) { 474 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n", 475 port_map, 476 port_map & hpriv->mask_port_map); 477 port_map &= hpriv->mask_port_map; 478 } 479 480 /* cross check port_map and cap.n_ports */ 481 if (port_map) { 482 int map_ports = 0; 483 484 for (i = 0; i < AHCI_MAX_PORTS; i++) 485 if (port_map & (1 << i)) 486 map_ports++; 487 488 /* If PI has more ports than n_ports, whine, clear 489 * port_map and let it be generated from n_ports. 490 */ 491 if (map_ports > ahci_nr_ports(cap)) { 492 dev_warn(dev, 493 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n", 494 port_map, ahci_nr_ports(cap)); 495 port_map = 0; 496 } 497 } 498 499 /* fabricate port_map from cap.nr_ports */ 500 if (!port_map) { 501 port_map = (1 << ahci_nr_ports(cap)) - 1; 502 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map); 503 504 /* write the fixed up value to the PI register */ 505 hpriv->saved_port_map = port_map; 506 } 507 508 /* record values to use during operation */ 509 hpriv->cap = cap; 510 hpriv->cap2 = cap2; 511 hpriv->port_map = port_map; 512 513 if (!hpriv->start_engine) 514 hpriv->start_engine = ahci_start_engine; 515 } 516 EXPORT_SYMBOL_GPL(ahci_save_initial_config); 517 518 /** 519 * ahci_restore_initial_config - Restore initial config 520 * @host: target ATA host 521 * 522 * Restore initial config stored by ahci_save_initial_config(). 523 * 524 * LOCKING: 525 * None. 526 */ 527 static void ahci_restore_initial_config(struct ata_host *host) 528 { 529 struct ahci_host_priv *hpriv = host->private_data; 530 void __iomem *mmio = hpriv->mmio; 531 532 writel(hpriv->saved_cap, mmio + HOST_CAP); 533 if (hpriv->saved_cap2) 534 writel(hpriv->saved_cap2, mmio + HOST_CAP2); 535 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); 536 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ 537 } 538 539 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) 540 { 541 static const int offset[] = { 542 [SCR_STATUS] = PORT_SCR_STAT, 543 [SCR_CONTROL] = PORT_SCR_CTL, 544 [SCR_ERROR] = PORT_SCR_ERR, 545 [SCR_ACTIVE] = PORT_SCR_ACT, 546 [SCR_NOTIFICATION] = PORT_SCR_NTF, 547 }; 548 struct ahci_host_priv *hpriv = ap->host->private_data; 549 550 if (sc_reg < ARRAY_SIZE(offset) && 551 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) 552 return offset[sc_reg]; 553 return 0; 554 } 555 556 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) 557 { 558 void __iomem *port_mmio = ahci_port_base(link->ap); 559 int offset = ahci_scr_offset(link->ap, sc_reg); 560 561 if (offset) { 562 *val = readl(port_mmio + offset); 563 return 0; 564 } 565 return -EINVAL; 566 } 567 568 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) 569 { 570 void __iomem *port_mmio = ahci_port_base(link->ap); 571 int offset = ahci_scr_offset(link->ap, sc_reg); 572 573 if (offset) { 574 writel(val, port_mmio + offset); 575 return 0; 576 } 577 return -EINVAL; 578 } 579 580 void ahci_start_engine(struct ata_port *ap) 581 { 582 void __iomem *port_mmio = ahci_port_base(ap); 583 u32 tmp; 584 585 /* start DMA */ 586 tmp = readl(port_mmio + PORT_CMD); 587 tmp |= PORT_CMD_START; 588 writel(tmp, port_mmio + PORT_CMD); 589 readl(port_mmio + PORT_CMD); /* flush */ 590 } 591 EXPORT_SYMBOL_GPL(ahci_start_engine); 592 593 int ahci_stop_engine(struct ata_port *ap) 594 { 595 void __iomem *port_mmio = ahci_port_base(ap); 596 u32 tmp; 597 598 tmp = readl(port_mmio + PORT_CMD); 599 600 /* check if the HBA is idle */ 601 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) 602 return 0; 603 604 /* setting HBA to idle */ 605 tmp &= ~PORT_CMD_START; 606 writel(tmp, port_mmio + PORT_CMD); 607 608 /* wait for engine to stop. This could be as long as 500 msec */ 609 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 610 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); 611 if (tmp & PORT_CMD_LIST_ON) 612 return -EIO; 613 614 return 0; 615 } 616 EXPORT_SYMBOL_GPL(ahci_stop_engine); 617 618 void ahci_start_fis_rx(struct ata_port *ap) 619 { 620 void __iomem *port_mmio = ahci_port_base(ap); 621 struct ahci_host_priv *hpriv = ap->host->private_data; 622 struct ahci_port_priv *pp = ap->private_data; 623 u32 tmp; 624 625 /* set FIS registers */ 626 if (hpriv->cap & HOST_CAP_64) 627 writel((pp->cmd_slot_dma >> 16) >> 16, 628 port_mmio + PORT_LST_ADDR_HI); 629 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); 630 631 if (hpriv->cap & HOST_CAP_64) 632 writel((pp->rx_fis_dma >> 16) >> 16, 633 port_mmio + PORT_FIS_ADDR_HI); 634 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); 635 636 /* enable FIS reception */ 637 tmp = readl(port_mmio + PORT_CMD); 638 tmp |= PORT_CMD_FIS_RX; 639 writel(tmp, port_mmio + PORT_CMD); 640 641 /* flush */ 642 readl(port_mmio + PORT_CMD); 643 } 644 EXPORT_SYMBOL_GPL(ahci_start_fis_rx); 645 646 static int ahci_stop_fis_rx(struct ata_port *ap) 647 { 648 void __iomem *port_mmio = ahci_port_base(ap); 649 u32 tmp; 650 651 /* disable FIS reception */ 652 tmp = readl(port_mmio + PORT_CMD); 653 tmp &= ~PORT_CMD_FIS_RX; 654 writel(tmp, port_mmio + PORT_CMD); 655 656 /* wait for completion, spec says 500ms, give it 1000 */ 657 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON, 658 PORT_CMD_FIS_ON, 10, 1000); 659 if (tmp & PORT_CMD_FIS_ON) 660 return -EBUSY; 661 662 return 0; 663 } 664 665 static void ahci_power_up(struct ata_port *ap) 666 { 667 struct ahci_host_priv *hpriv = ap->host->private_data; 668 void __iomem *port_mmio = ahci_port_base(ap); 669 u32 cmd; 670 671 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 672 673 /* spin up device */ 674 if (hpriv->cap & HOST_CAP_SSS) { 675 cmd |= PORT_CMD_SPIN_UP; 676 writel(cmd, port_mmio + PORT_CMD); 677 } 678 679 /* wake up link */ 680 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); 681 } 682 683 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 684 unsigned int hints) 685 { 686 struct ata_port *ap = link->ap; 687 struct ahci_host_priv *hpriv = ap->host->private_data; 688 struct ahci_port_priv *pp = ap->private_data; 689 void __iomem *port_mmio = ahci_port_base(ap); 690 691 if (policy != ATA_LPM_MAX_POWER) { 692 /* 693 * Disable interrupts on Phy Ready. This keeps us from 694 * getting woken up due to spurious phy ready 695 * interrupts. 696 */ 697 pp->intr_mask &= ~PORT_IRQ_PHYRDY; 698 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 699 700 sata_link_scr_lpm(link, policy, false); 701 } 702 703 if (hpriv->cap & HOST_CAP_ALPM) { 704 u32 cmd = readl(port_mmio + PORT_CMD); 705 706 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) { 707 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE); 708 cmd |= PORT_CMD_ICC_ACTIVE; 709 710 writel(cmd, port_mmio + PORT_CMD); 711 readl(port_mmio + PORT_CMD); 712 713 /* wait 10ms to be sure we've come out of LPM state */ 714 ata_msleep(ap, 10); 715 } else { 716 cmd |= PORT_CMD_ALPE; 717 if (policy == ATA_LPM_MIN_POWER) 718 cmd |= PORT_CMD_ASP; 719 720 /* write out new cmd value */ 721 writel(cmd, port_mmio + PORT_CMD); 722 } 723 } 724 725 /* set aggressive device sleep */ 726 if ((hpriv->cap2 & HOST_CAP2_SDS) && 727 (hpriv->cap2 & HOST_CAP2_SADM) && 728 (link->device->flags & ATA_DFLAG_DEVSLP)) { 729 if (policy == ATA_LPM_MIN_POWER) 730 ahci_set_aggressive_devslp(ap, true); 731 else 732 ahci_set_aggressive_devslp(ap, false); 733 } 734 735 if (policy == ATA_LPM_MAX_POWER) { 736 sata_link_scr_lpm(link, policy, false); 737 738 /* turn PHYRDY IRQ back on */ 739 pp->intr_mask |= PORT_IRQ_PHYRDY; 740 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 741 } 742 743 return 0; 744 } 745 746 #ifdef CONFIG_PM 747 static void ahci_power_down(struct ata_port *ap) 748 { 749 struct ahci_host_priv *hpriv = ap->host->private_data; 750 void __iomem *port_mmio = ahci_port_base(ap); 751 u32 cmd, scontrol; 752 753 if (!(hpriv->cap & HOST_CAP_SSS)) 754 return; 755 756 /* put device into listen mode, first set PxSCTL.DET to 0 */ 757 scontrol = readl(port_mmio + PORT_SCR_CTL); 758 scontrol &= ~0xf; 759 writel(scontrol, port_mmio + PORT_SCR_CTL); 760 761 /* then set PxCMD.SUD to 0 */ 762 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 763 cmd &= ~PORT_CMD_SPIN_UP; 764 writel(cmd, port_mmio + PORT_CMD); 765 } 766 #endif 767 768 static void ahci_start_port(struct ata_port *ap) 769 { 770 struct ahci_host_priv *hpriv = ap->host->private_data; 771 struct ahci_port_priv *pp = ap->private_data; 772 struct ata_link *link; 773 struct ahci_em_priv *emp; 774 ssize_t rc; 775 int i; 776 777 /* enable FIS reception */ 778 ahci_start_fis_rx(ap); 779 780 /* enable DMA */ 781 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE)) 782 hpriv->start_engine(ap); 783 784 /* turn on LEDs */ 785 if (ap->flags & ATA_FLAG_EM) { 786 ata_for_each_link(link, ap, EDGE) { 787 emp = &pp->em_priv[link->pmp]; 788 789 /* EM Transmit bit maybe busy during init */ 790 for (i = 0; i < EM_MAX_RETRY; i++) { 791 rc = ap->ops->transmit_led_message(ap, 792 emp->led_state, 793 4); 794 /* 795 * If busy, give a breather but do not 796 * release EH ownership by using msleep() 797 * instead of ata_msleep(). EM Transmit 798 * bit is busy for the whole host and 799 * releasing ownership will cause other 800 * ports to fail the same way. 801 */ 802 if (rc == -EBUSY) 803 msleep(1); 804 else 805 break; 806 } 807 } 808 } 809 810 if (ap->flags & ATA_FLAG_SW_ACTIVITY) 811 ata_for_each_link(link, ap, EDGE) 812 ahci_init_sw_activity(link); 813 814 } 815 816 static int ahci_deinit_port(struct ata_port *ap, const char **emsg) 817 { 818 int rc; 819 820 /* disable DMA */ 821 rc = ahci_stop_engine(ap); 822 if (rc) { 823 *emsg = "failed to stop engine"; 824 return rc; 825 } 826 827 /* disable FIS reception */ 828 rc = ahci_stop_fis_rx(ap); 829 if (rc) { 830 *emsg = "failed stop FIS RX"; 831 return rc; 832 } 833 834 return 0; 835 } 836 837 int ahci_reset_controller(struct ata_host *host) 838 { 839 struct ahci_host_priv *hpriv = host->private_data; 840 void __iomem *mmio = hpriv->mmio; 841 u32 tmp; 842 843 /* we must be in AHCI mode, before using anything 844 * AHCI-specific, such as HOST_RESET. 845 */ 846 ahci_enable_ahci(mmio); 847 848 /* global controller reset */ 849 if (!ahci_skip_host_reset) { 850 tmp = readl(mmio + HOST_CTL); 851 if ((tmp & HOST_RESET) == 0) { 852 writel(tmp | HOST_RESET, mmio + HOST_CTL); 853 readl(mmio + HOST_CTL); /* flush */ 854 } 855 856 /* 857 * to perform host reset, OS should set HOST_RESET 858 * and poll until this bit is read to be "0". 859 * reset must complete within 1 second, or 860 * the hardware should be considered fried. 861 */ 862 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET, 863 HOST_RESET, 10, 1000); 864 865 if (tmp & HOST_RESET) { 866 dev_err(host->dev, "controller reset failed (0x%x)\n", 867 tmp); 868 return -EIO; 869 } 870 871 /* turn on AHCI mode */ 872 ahci_enable_ahci(mmio); 873 874 /* Some registers might be cleared on reset. Restore 875 * initial values. 876 */ 877 ahci_restore_initial_config(host); 878 } else 879 dev_info(host->dev, "skipping global host reset\n"); 880 881 return 0; 882 } 883 EXPORT_SYMBOL_GPL(ahci_reset_controller); 884 885 static void ahci_sw_activity(struct ata_link *link) 886 { 887 struct ata_port *ap = link->ap; 888 struct ahci_port_priv *pp = ap->private_data; 889 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 890 891 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY)) 892 return; 893 894 emp->activity++; 895 if (!timer_pending(&emp->timer)) 896 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10)); 897 } 898 899 static void ahci_sw_activity_blink(unsigned long arg) 900 { 901 struct ata_link *link = (struct ata_link *)arg; 902 struct ata_port *ap = link->ap; 903 struct ahci_port_priv *pp = ap->private_data; 904 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 905 unsigned long led_message = emp->led_state; 906 u32 activity_led_state; 907 unsigned long flags; 908 909 led_message &= EM_MSG_LED_VALUE; 910 led_message |= ap->port_no | (link->pmp << 8); 911 912 /* check to see if we've had activity. If so, 913 * toggle state of LED and reset timer. If not, 914 * turn LED to desired idle state. 915 */ 916 spin_lock_irqsave(ap->lock, flags); 917 if (emp->saved_activity != emp->activity) { 918 emp->saved_activity = emp->activity; 919 /* get the current LED state */ 920 activity_led_state = led_message & EM_MSG_LED_VALUE_ON; 921 922 if (activity_led_state) 923 activity_led_state = 0; 924 else 925 activity_led_state = 1; 926 927 /* clear old state */ 928 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 929 930 /* toggle state */ 931 led_message |= (activity_led_state << 16); 932 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100)); 933 } else { 934 /* switch to idle */ 935 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 936 if (emp->blink_policy == BLINK_OFF) 937 led_message |= (1 << 16); 938 } 939 spin_unlock_irqrestore(ap->lock, flags); 940 ap->ops->transmit_led_message(ap, led_message, 4); 941 } 942 943 static void ahci_init_sw_activity(struct ata_link *link) 944 { 945 struct ata_port *ap = link->ap; 946 struct ahci_port_priv *pp = ap->private_data; 947 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 948 949 /* init activity stats, setup timer */ 950 emp->saved_activity = emp->activity = 0; 951 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link); 952 953 /* check our blink policy and set flag for link if it's enabled */ 954 if (emp->blink_policy) 955 link->flags |= ATA_LFLAG_SW_ACTIVITY; 956 } 957 958 int ahci_reset_em(struct ata_host *host) 959 { 960 struct ahci_host_priv *hpriv = host->private_data; 961 void __iomem *mmio = hpriv->mmio; 962 u32 em_ctl; 963 964 em_ctl = readl(mmio + HOST_EM_CTL); 965 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST)) 966 return -EINVAL; 967 968 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL); 969 return 0; 970 } 971 EXPORT_SYMBOL_GPL(ahci_reset_em); 972 973 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 974 ssize_t size) 975 { 976 struct ahci_host_priv *hpriv = ap->host->private_data; 977 struct ahci_port_priv *pp = ap->private_data; 978 void __iomem *mmio = hpriv->mmio; 979 u32 em_ctl; 980 u32 message[] = {0, 0}; 981 unsigned long flags; 982 int pmp; 983 struct ahci_em_priv *emp; 984 985 /* get the slot number from the message */ 986 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 987 if (pmp < EM_MAX_SLOTS) 988 emp = &pp->em_priv[pmp]; 989 else 990 return -EINVAL; 991 992 spin_lock_irqsave(ap->lock, flags); 993 994 /* 995 * if we are still busy transmitting a previous message, 996 * do not allow 997 */ 998 em_ctl = readl(mmio + HOST_EM_CTL); 999 if (em_ctl & EM_CTL_TM) { 1000 spin_unlock_irqrestore(ap->lock, flags); 1001 return -EBUSY; 1002 } 1003 1004 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) { 1005 /* 1006 * create message header - this is all zero except for 1007 * the message size, which is 4 bytes. 1008 */ 1009 message[0] |= (4 << 8); 1010 1011 /* ignore 0:4 of byte zero, fill in port info yourself */ 1012 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no); 1013 1014 /* write message to EM_LOC */ 1015 writel(message[0], mmio + hpriv->em_loc); 1016 writel(message[1], mmio + hpriv->em_loc+4); 1017 1018 /* 1019 * tell hardware to transmit the message 1020 */ 1021 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 1022 } 1023 1024 /* save off new led state for port/slot */ 1025 emp->led_state = state; 1026 1027 spin_unlock_irqrestore(ap->lock, flags); 1028 return size; 1029 } 1030 1031 static ssize_t ahci_led_show(struct ata_port *ap, char *buf) 1032 { 1033 struct ahci_port_priv *pp = ap->private_data; 1034 struct ata_link *link; 1035 struct ahci_em_priv *emp; 1036 int rc = 0; 1037 1038 ata_for_each_link(link, ap, EDGE) { 1039 emp = &pp->em_priv[link->pmp]; 1040 rc += sprintf(buf, "%lx\n", emp->led_state); 1041 } 1042 return rc; 1043 } 1044 1045 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 1046 size_t size) 1047 { 1048 unsigned int state; 1049 int pmp; 1050 struct ahci_port_priv *pp = ap->private_data; 1051 struct ahci_em_priv *emp; 1052 1053 if (kstrtouint(buf, 0, &state) < 0) 1054 return -EINVAL; 1055 1056 /* get the slot number from the message */ 1057 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1058 if (pmp < EM_MAX_SLOTS) 1059 emp = &pp->em_priv[pmp]; 1060 else 1061 return -EINVAL; 1062 1063 /* mask off the activity bits if we are in sw_activity 1064 * mode, user should turn off sw_activity before setting 1065 * activity led through em_message 1066 */ 1067 if (emp->blink_policy) 1068 state &= ~EM_MSG_LED_VALUE_ACTIVITY; 1069 1070 return ap->ops->transmit_led_message(ap, state, size); 1071 } 1072 1073 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val) 1074 { 1075 struct ata_link *link = dev->link; 1076 struct ata_port *ap = link->ap; 1077 struct ahci_port_priv *pp = ap->private_data; 1078 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1079 u32 port_led_state = emp->led_state; 1080 1081 /* save the desired Activity LED behavior */ 1082 if (val == OFF) { 1083 /* clear LFLAG */ 1084 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY); 1085 1086 /* set the LED to OFF */ 1087 port_led_state &= EM_MSG_LED_VALUE_OFF; 1088 port_led_state |= (ap->port_no | (link->pmp << 8)); 1089 ap->ops->transmit_led_message(ap, port_led_state, 4); 1090 } else { 1091 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1092 if (val == BLINK_OFF) { 1093 /* set LED to ON for idle */ 1094 port_led_state &= EM_MSG_LED_VALUE_OFF; 1095 port_led_state |= (ap->port_no | (link->pmp << 8)); 1096 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */ 1097 ap->ops->transmit_led_message(ap, port_led_state, 4); 1098 } 1099 } 1100 emp->blink_policy = val; 1101 return 0; 1102 } 1103 1104 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf) 1105 { 1106 struct ata_link *link = dev->link; 1107 struct ata_port *ap = link->ap; 1108 struct ahci_port_priv *pp = ap->private_data; 1109 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1110 1111 /* display the saved value of activity behavior for this 1112 * disk. 1113 */ 1114 return sprintf(buf, "%d\n", emp->blink_policy); 1115 } 1116 1117 static void ahci_port_init(struct device *dev, struct ata_port *ap, 1118 int port_no, void __iomem *mmio, 1119 void __iomem *port_mmio) 1120 { 1121 struct ahci_host_priv *hpriv = ap->host->private_data; 1122 const char *emsg = NULL; 1123 int rc; 1124 u32 tmp; 1125 1126 /* make sure port is not active */ 1127 rc = ahci_deinit_port(ap, &emsg); 1128 if (rc) 1129 dev_warn(dev, "%s (%d)\n", emsg, rc); 1130 1131 /* clear SError */ 1132 tmp = readl(port_mmio + PORT_SCR_ERR); 1133 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); 1134 writel(tmp, port_mmio + PORT_SCR_ERR); 1135 1136 /* clear port IRQ */ 1137 tmp = readl(port_mmio + PORT_IRQ_STAT); 1138 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 1139 if (tmp) 1140 writel(tmp, port_mmio + PORT_IRQ_STAT); 1141 1142 writel(1 << port_no, mmio + HOST_IRQ_STAT); 1143 1144 /* mark esata ports */ 1145 tmp = readl(port_mmio + PORT_CMD); 1146 if ((tmp & PORT_CMD_HPCP) || 1147 ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS))) 1148 ap->pflags |= ATA_PFLAG_EXTERNAL; 1149 } 1150 1151 void ahci_init_controller(struct ata_host *host) 1152 { 1153 struct ahci_host_priv *hpriv = host->private_data; 1154 void __iomem *mmio = hpriv->mmio; 1155 int i; 1156 void __iomem *port_mmio; 1157 u32 tmp; 1158 1159 for (i = 0; i < host->n_ports; i++) { 1160 struct ata_port *ap = host->ports[i]; 1161 1162 port_mmio = ahci_port_base(ap); 1163 if (ata_port_is_dummy(ap)) 1164 continue; 1165 1166 ahci_port_init(host->dev, ap, i, mmio, port_mmio); 1167 } 1168 1169 tmp = readl(mmio + HOST_CTL); 1170 VPRINTK("HOST_CTL 0x%x\n", tmp); 1171 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); 1172 tmp = readl(mmio + HOST_CTL); 1173 VPRINTK("HOST_CTL 0x%x\n", tmp); 1174 } 1175 EXPORT_SYMBOL_GPL(ahci_init_controller); 1176 1177 static void ahci_dev_config(struct ata_device *dev) 1178 { 1179 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data; 1180 1181 if (hpriv->flags & AHCI_HFLAG_SECT255) { 1182 dev->max_sectors = 255; 1183 ata_dev_info(dev, 1184 "SB600 AHCI: limiting to 255 sectors per cmd\n"); 1185 } 1186 } 1187 1188 unsigned int ahci_dev_classify(struct ata_port *ap) 1189 { 1190 void __iomem *port_mmio = ahci_port_base(ap); 1191 struct ata_taskfile tf; 1192 u32 tmp; 1193 1194 tmp = readl(port_mmio + PORT_SIG); 1195 tf.lbah = (tmp >> 24) & 0xff; 1196 tf.lbam = (tmp >> 16) & 0xff; 1197 tf.lbal = (tmp >> 8) & 0xff; 1198 tf.nsect = (tmp) & 0xff; 1199 1200 return ata_dev_classify(&tf); 1201 } 1202 EXPORT_SYMBOL_GPL(ahci_dev_classify); 1203 1204 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 1205 u32 opts) 1206 { 1207 dma_addr_t cmd_tbl_dma; 1208 1209 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; 1210 1211 pp->cmd_slot[tag].opts = cpu_to_le32(opts); 1212 pp->cmd_slot[tag].status = 0; 1213 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); 1214 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); 1215 } 1216 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot); 1217 1218 int ahci_kick_engine(struct ata_port *ap) 1219 { 1220 void __iomem *port_mmio = ahci_port_base(ap); 1221 struct ahci_host_priv *hpriv = ap->host->private_data; 1222 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1223 u32 tmp; 1224 int busy, rc; 1225 1226 /* stop engine */ 1227 rc = ahci_stop_engine(ap); 1228 if (rc) 1229 goto out_restart; 1230 1231 /* need to do CLO? 1232 * always do CLO if PMP is attached (AHCI-1.3 9.2) 1233 */ 1234 busy = status & (ATA_BUSY | ATA_DRQ); 1235 if (!busy && !sata_pmp_attached(ap)) { 1236 rc = 0; 1237 goto out_restart; 1238 } 1239 1240 if (!(hpriv->cap & HOST_CAP_CLO)) { 1241 rc = -EOPNOTSUPP; 1242 goto out_restart; 1243 } 1244 1245 /* perform CLO */ 1246 tmp = readl(port_mmio + PORT_CMD); 1247 tmp |= PORT_CMD_CLO; 1248 writel(tmp, port_mmio + PORT_CMD); 1249 1250 rc = 0; 1251 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 1252 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); 1253 if (tmp & PORT_CMD_CLO) 1254 rc = -EIO; 1255 1256 /* restart engine */ 1257 out_restart: 1258 hpriv->start_engine(ap); 1259 return rc; 1260 } 1261 EXPORT_SYMBOL_GPL(ahci_kick_engine); 1262 1263 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, 1264 struct ata_taskfile *tf, int is_cmd, u16 flags, 1265 unsigned long timeout_msec) 1266 { 1267 const u32 cmd_fis_len = 5; /* five dwords */ 1268 struct ahci_port_priv *pp = ap->private_data; 1269 void __iomem *port_mmio = ahci_port_base(ap); 1270 u8 *fis = pp->cmd_tbl; 1271 u32 tmp; 1272 1273 /* prep the command */ 1274 ata_tf_to_fis(tf, pmp, is_cmd, fis); 1275 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); 1276 1277 /* set port value for softreset of Port Multiplier */ 1278 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) { 1279 tmp = readl(port_mmio + PORT_FBS); 1280 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); 1281 tmp |= pmp << PORT_FBS_DEV_OFFSET; 1282 writel(tmp, port_mmio + PORT_FBS); 1283 pp->fbs_last_dev = pmp; 1284 } 1285 1286 /* issue & wait */ 1287 writel(1, port_mmio + PORT_CMD_ISSUE); 1288 1289 if (timeout_msec) { 1290 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE, 1291 0x1, 0x1, 1, timeout_msec); 1292 if (tmp & 0x1) { 1293 ahci_kick_engine(ap); 1294 return -EBUSY; 1295 } 1296 } else 1297 readl(port_mmio + PORT_CMD_ISSUE); /* flush */ 1298 1299 return 0; 1300 } 1301 1302 int ahci_do_softreset(struct ata_link *link, unsigned int *class, 1303 int pmp, unsigned long deadline, 1304 int (*check_ready)(struct ata_link *link)) 1305 { 1306 struct ata_port *ap = link->ap; 1307 struct ahci_host_priv *hpriv = ap->host->private_data; 1308 struct ahci_port_priv *pp = ap->private_data; 1309 const char *reason = NULL; 1310 unsigned long now, msecs; 1311 struct ata_taskfile tf; 1312 bool fbs_disabled = false; 1313 int rc; 1314 1315 DPRINTK("ENTER\n"); 1316 1317 /* prepare for SRST (AHCI-1.1 10.4.1) */ 1318 rc = ahci_kick_engine(ap); 1319 if (rc && rc != -EOPNOTSUPP) 1320 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc); 1321 1322 /* 1323 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall 1324 * clear PxFBS.EN to '0' prior to issuing software reset to devices 1325 * that is attached to port multiplier. 1326 */ 1327 if (!ata_is_host_link(link) && pp->fbs_enabled) { 1328 ahci_disable_fbs(ap); 1329 fbs_disabled = true; 1330 } 1331 1332 ata_tf_init(link->device, &tf); 1333 1334 /* issue the first D2H Register FIS */ 1335 msecs = 0; 1336 now = jiffies; 1337 if (time_after(deadline, now)) 1338 msecs = jiffies_to_msecs(deadline - now); 1339 1340 tf.ctl |= ATA_SRST; 1341 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, 1342 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { 1343 rc = -EIO; 1344 reason = "1st FIS failed"; 1345 goto fail; 1346 } 1347 1348 /* spec says at least 5us, but be generous and sleep for 1ms */ 1349 ata_msleep(ap, 1); 1350 1351 /* issue the second D2H Register FIS */ 1352 tf.ctl &= ~ATA_SRST; 1353 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); 1354 1355 /* wait for link to become ready */ 1356 rc = ata_wait_after_reset(link, deadline, check_ready); 1357 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) { 1358 /* 1359 * Workaround for cases where link online status can't 1360 * be trusted. Treat device readiness timeout as link 1361 * offline. 1362 */ 1363 ata_link_info(link, "device not ready, treating as offline\n"); 1364 *class = ATA_DEV_NONE; 1365 } else if (rc) { 1366 /* link occupied, -ENODEV too is an error */ 1367 reason = "device not ready"; 1368 goto fail; 1369 } else 1370 *class = ahci_dev_classify(ap); 1371 1372 /* re-enable FBS if disabled before */ 1373 if (fbs_disabled) 1374 ahci_enable_fbs(ap); 1375 1376 DPRINTK("EXIT, class=%u\n", *class); 1377 return 0; 1378 1379 fail: 1380 ata_link_err(link, "softreset failed (%s)\n", reason); 1381 return rc; 1382 } 1383 1384 int ahci_check_ready(struct ata_link *link) 1385 { 1386 void __iomem *port_mmio = ahci_port_base(link->ap); 1387 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1388 1389 return ata_check_ready(status); 1390 } 1391 EXPORT_SYMBOL_GPL(ahci_check_ready); 1392 1393 static int ahci_softreset(struct ata_link *link, unsigned int *class, 1394 unsigned long deadline) 1395 { 1396 int pmp = sata_srst_pmp(link); 1397 1398 DPRINTK("ENTER\n"); 1399 1400 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready); 1401 } 1402 EXPORT_SYMBOL_GPL(ahci_do_softreset); 1403 1404 static int ahci_bad_pmp_check_ready(struct ata_link *link) 1405 { 1406 void __iomem *port_mmio = ahci_port_base(link->ap); 1407 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1408 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT); 1409 1410 /* 1411 * There is no need to check TFDATA if BAD PMP is found due to HW bug, 1412 * which can save timeout delay. 1413 */ 1414 if (irq_status & PORT_IRQ_BAD_PMP) 1415 return -EIO; 1416 1417 return ata_check_ready(status); 1418 } 1419 1420 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class, 1421 unsigned long deadline) 1422 { 1423 struct ata_port *ap = link->ap; 1424 void __iomem *port_mmio = ahci_port_base(ap); 1425 int pmp = sata_srst_pmp(link); 1426 int rc; 1427 u32 irq_sts; 1428 1429 DPRINTK("ENTER\n"); 1430 1431 rc = ahci_do_softreset(link, class, pmp, deadline, 1432 ahci_bad_pmp_check_ready); 1433 1434 /* 1435 * Soft reset fails with IPMS set when PMP is enabled but 1436 * SATA HDD/ODD is connected to SATA port, do soft reset 1437 * again to port 0. 1438 */ 1439 if (rc == -EIO) { 1440 irq_sts = readl(port_mmio + PORT_IRQ_STAT); 1441 if (irq_sts & PORT_IRQ_BAD_PMP) { 1442 ata_link_warn(link, 1443 "applying PMP SRST workaround " 1444 "and retrying\n"); 1445 rc = ahci_do_softreset(link, class, 0, deadline, 1446 ahci_check_ready); 1447 } 1448 } 1449 1450 return rc; 1451 } 1452 1453 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 1454 unsigned long deadline) 1455 { 1456 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 1457 struct ata_port *ap = link->ap; 1458 struct ahci_port_priv *pp = ap->private_data; 1459 struct ahci_host_priv *hpriv = ap->host->private_data; 1460 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 1461 struct ata_taskfile tf; 1462 bool online; 1463 int rc; 1464 1465 DPRINTK("ENTER\n"); 1466 1467 ahci_stop_engine(ap); 1468 1469 /* clear D2H reception area to properly wait for D2H FIS */ 1470 ata_tf_init(link->device, &tf); 1471 tf.command = ATA_BUSY; 1472 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 1473 1474 rc = sata_link_hardreset(link, timing, deadline, &online, 1475 ahci_check_ready); 1476 1477 hpriv->start_engine(ap); 1478 1479 if (online) 1480 *class = ahci_dev_classify(ap); 1481 1482 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 1483 return rc; 1484 } 1485 1486 static void ahci_postreset(struct ata_link *link, unsigned int *class) 1487 { 1488 struct ata_port *ap = link->ap; 1489 void __iomem *port_mmio = ahci_port_base(ap); 1490 u32 new_tmp, tmp; 1491 1492 ata_std_postreset(link, class); 1493 1494 /* Make sure port's ATAPI bit is set appropriately */ 1495 new_tmp = tmp = readl(port_mmio + PORT_CMD); 1496 if (*class == ATA_DEV_ATAPI) 1497 new_tmp |= PORT_CMD_ATAPI; 1498 else 1499 new_tmp &= ~PORT_CMD_ATAPI; 1500 if (new_tmp != tmp) { 1501 writel(new_tmp, port_mmio + PORT_CMD); 1502 readl(port_mmio + PORT_CMD); /* flush */ 1503 } 1504 } 1505 1506 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) 1507 { 1508 struct scatterlist *sg; 1509 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; 1510 unsigned int si; 1511 1512 VPRINTK("ENTER\n"); 1513 1514 /* 1515 * Next, the S/G list. 1516 */ 1517 for_each_sg(qc->sg, sg, qc->n_elem, si) { 1518 dma_addr_t addr = sg_dma_address(sg); 1519 u32 sg_len = sg_dma_len(sg); 1520 1521 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); 1522 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); 1523 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); 1524 } 1525 1526 return si; 1527 } 1528 1529 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc) 1530 { 1531 struct ata_port *ap = qc->ap; 1532 struct ahci_port_priv *pp = ap->private_data; 1533 1534 if (!sata_pmp_attached(ap) || pp->fbs_enabled) 1535 return ata_std_qc_defer(qc); 1536 else 1537 return sata_pmp_qc_defer_cmd_switch(qc); 1538 } 1539 1540 static void ahci_qc_prep(struct ata_queued_cmd *qc) 1541 { 1542 struct ata_port *ap = qc->ap; 1543 struct ahci_port_priv *pp = ap->private_data; 1544 int is_atapi = ata_is_atapi(qc->tf.protocol); 1545 void *cmd_tbl; 1546 u32 opts; 1547 const u32 cmd_fis_len = 5; /* five dwords */ 1548 unsigned int n_elem; 1549 1550 /* 1551 * Fill in command table information. First, the header, 1552 * a SATA Register - Host to Device command FIS. 1553 */ 1554 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; 1555 1556 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); 1557 if (is_atapi) { 1558 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); 1559 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); 1560 } 1561 1562 n_elem = 0; 1563 if (qc->flags & ATA_QCFLAG_DMAMAP) 1564 n_elem = ahci_fill_sg(qc, cmd_tbl); 1565 1566 /* 1567 * Fill in command slot information. 1568 */ 1569 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); 1570 if (qc->tf.flags & ATA_TFLAG_WRITE) 1571 opts |= AHCI_CMD_WRITE; 1572 if (is_atapi) 1573 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; 1574 1575 ahci_fill_cmd_slot(pp, qc->tag, opts); 1576 } 1577 1578 static void ahci_fbs_dec_intr(struct ata_port *ap) 1579 { 1580 struct ahci_port_priv *pp = ap->private_data; 1581 void __iomem *port_mmio = ahci_port_base(ap); 1582 u32 fbs = readl(port_mmio + PORT_FBS); 1583 int retries = 3; 1584 1585 DPRINTK("ENTER\n"); 1586 BUG_ON(!pp->fbs_enabled); 1587 1588 /* time to wait for DEC is not specified by AHCI spec, 1589 * add a retry loop for safety. 1590 */ 1591 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS); 1592 fbs = readl(port_mmio + PORT_FBS); 1593 while ((fbs & PORT_FBS_DEC) && retries--) { 1594 udelay(1); 1595 fbs = readl(port_mmio + PORT_FBS); 1596 } 1597 1598 if (fbs & PORT_FBS_DEC) 1599 dev_err(ap->host->dev, "failed to clear device error\n"); 1600 } 1601 1602 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) 1603 { 1604 struct ahci_host_priv *hpriv = ap->host->private_data; 1605 struct ahci_port_priv *pp = ap->private_data; 1606 struct ata_eh_info *host_ehi = &ap->link.eh_info; 1607 struct ata_link *link = NULL; 1608 struct ata_queued_cmd *active_qc; 1609 struct ata_eh_info *active_ehi; 1610 bool fbs_need_dec = false; 1611 u32 serror; 1612 1613 /* determine active link with error */ 1614 if (pp->fbs_enabled) { 1615 void __iomem *port_mmio = ahci_port_base(ap); 1616 u32 fbs = readl(port_mmio + PORT_FBS); 1617 int pmp = fbs >> PORT_FBS_DWE_OFFSET; 1618 1619 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) { 1620 link = &ap->pmp_link[pmp]; 1621 fbs_need_dec = true; 1622 } 1623 1624 } else 1625 ata_for_each_link(link, ap, EDGE) 1626 if (ata_link_active(link)) 1627 break; 1628 1629 if (!link) 1630 link = &ap->link; 1631 1632 active_qc = ata_qc_from_tag(ap, link->active_tag); 1633 active_ehi = &link->eh_info; 1634 1635 /* record irq stat */ 1636 ata_ehi_clear_desc(host_ehi); 1637 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); 1638 1639 /* AHCI needs SError cleared; otherwise, it might lock up */ 1640 ahci_scr_read(&ap->link, SCR_ERROR, &serror); 1641 ahci_scr_write(&ap->link, SCR_ERROR, serror); 1642 host_ehi->serror |= serror; 1643 1644 /* some controllers set IRQ_IF_ERR on device errors, ignore it */ 1645 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) 1646 irq_stat &= ~PORT_IRQ_IF_ERR; 1647 1648 if (irq_stat & PORT_IRQ_TF_ERR) { 1649 /* If qc is active, charge it; otherwise, the active 1650 * link. There's no active qc on NCQ errors. It will 1651 * be determined by EH by reading log page 10h. 1652 */ 1653 if (active_qc) 1654 active_qc->err_mask |= AC_ERR_DEV; 1655 else 1656 active_ehi->err_mask |= AC_ERR_DEV; 1657 1658 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) 1659 host_ehi->serror &= ~SERR_INTERNAL; 1660 } 1661 1662 if (irq_stat & PORT_IRQ_UNK_FIS) { 1663 u32 *unk = pp->rx_fis + RX_FIS_UNK; 1664 1665 active_ehi->err_mask |= AC_ERR_HSM; 1666 active_ehi->action |= ATA_EH_RESET; 1667 ata_ehi_push_desc(active_ehi, 1668 "unknown FIS %08x %08x %08x %08x" , 1669 unk[0], unk[1], unk[2], unk[3]); 1670 } 1671 1672 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) { 1673 active_ehi->err_mask |= AC_ERR_HSM; 1674 active_ehi->action |= ATA_EH_RESET; 1675 ata_ehi_push_desc(active_ehi, "incorrect PMP"); 1676 } 1677 1678 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { 1679 host_ehi->err_mask |= AC_ERR_HOST_BUS; 1680 host_ehi->action |= ATA_EH_RESET; 1681 ata_ehi_push_desc(host_ehi, "host bus error"); 1682 } 1683 1684 if (irq_stat & PORT_IRQ_IF_ERR) { 1685 if (fbs_need_dec) 1686 active_ehi->err_mask |= AC_ERR_DEV; 1687 else { 1688 host_ehi->err_mask |= AC_ERR_ATA_BUS; 1689 host_ehi->action |= ATA_EH_RESET; 1690 } 1691 1692 ata_ehi_push_desc(host_ehi, "interface fatal error"); 1693 } 1694 1695 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { 1696 ata_ehi_hotplugged(host_ehi); 1697 ata_ehi_push_desc(host_ehi, "%s", 1698 irq_stat & PORT_IRQ_CONNECT ? 1699 "connection status changed" : "PHY RDY changed"); 1700 } 1701 1702 /* okay, let's hand over to EH */ 1703 1704 if (irq_stat & PORT_IRQ_FREEZE) 1705 ata_port_freeze(ap); 1706 else if (fbs_need_dec) { 1707 ata_link_abort(link); 1708 ahci_fbs_dec_intr(ap); 1709 } else 1710 ata_port_abort(ap); 1711 } 1712 1713 static void ahci_handle_port_interrupt(struct ata_port *ap, 1714 void __iomem *port_mmio, u32 status) 1715 { 1716 struct ata_eh_info *ehi = &ap->link.eh_info; 1717 struct ahci_port_priv *pp = ap->private_data; 1718 struct ahci_host_priv *hpriv = ap->host->private_data; 1719 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING); 1720 u32 qc_active = 0; 1721 int rc; 1722 1723 /* ignore BAD_PMP while resetting */ 1724 if (unlikely(resetting)) 1725 status &= ~PORT_IRQ_BAD_PMP; 1726 1727 if (sata_lpm_ignore_phy_events(&ap->link)) { 1728 status &= ~PORT_IRQ_PHYRDY; 1729 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG); 1730 } 1731 1732 if (unlikely(status & PORT_IRQ_ERROR)) { 1733 ahci_error_intr(ap, status); 1734 return; 1735 } 1736 1737 if (status & PORT_IRQ_SDB_FIS) { 1738 /* If SNotification is available, leave notification 1739 * handling to sata_async_notification(). If not, 1740 * emulate it by snooping SDB FIS RX area. 1741 * 1742 * Snooping FIS RX area is probably cheaper than 1743 * poking SNotification but some constrollers which 1744 * implement SNotification, ICH9 for example, don't 1745 * store AN SDB FIS into receive area. 1746 */ 1747 if (hpriv->cap & HOST_CAP_SNTF) 1748 sata_async_notification(ap); 1749 else { 1750 /* If the 'N' bit in word 0 of the FIS is set, 1751 * we just received asynchronous notification. 1752 * Tell libata about it. 1753 * 1754 * Lack of SNotification should not appear in 1755 * ahci 1.2, so the workaround is unnecessary 1756 * when FBS is enabled. 1757 */ 1758 if (pp->fbs_enabled) 1759 WARN_ON_ONCE(1); 1760 else { 1761 const __le32 *f = pp->rx_fis + RX_FIS_SDB; 1762 u32 f0 = le32_to_cpu(f[0]); 1763 if (f0 & (1 << 15)) 1764 sata_async_notification(ap); 1765 } 1766 } 1767 } 1768 1769 /* pp->active_link is not reliable once FBS is enabled, both 1770 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because 1771 * NCQ and non-NCQ commands may be in flight at the same time. 1772 */ 1773 if (pp->fbs_enabled) { 1774 if (ap->qc_active) { 1775 qc_active = readl(port_mmio + PORT_SCR_ACT); 1776 qc_active |= readl(port_mmio + PORT_CMD_ISSUE); 1777 } 1778 } else { 1779 /* pp->active_link is valid iff any command is in flight */ 1780 if (ap->qc_active && pp->active_link->sactive) 1781 qc_active = readl(port_mmio + PORT_SCR_ACT); 1782 else 1783 qc_active = readl(port_mmio + PORT_CMD_ISSUE); 1784 } 1785 1786 1787 rc = ata_qc_complete_multiple(ap, qc_active); 1788 1789 /* while resetting, invalid completions are expected */ 1790 if (unlikely(rc < 0 && !resetting)) { 1791 ehi->err_mask |= AC_ERR_HSM; 1792 ehi->action |= ATA_EH_RESET; 1793 ata_port_freeze(ap); 1794 } 1795 } 1796 1797 static void ahci_port_intr(struct ata_port *ap) 1798 { 1799 void __iomem *port_mmio = ahci_port_base(ap); 1800 u32 status; 1801 1802 status = readl(port_mmio + PORT_IRQ_STAT); 1803 writel(status, port_mmio + PORT_IRQ_STAT); 1804 1805 ahci_handle_port_interrupt(ap, port_mmio, status); 1806 } 1807 1808 static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance) 1809 { 1810 struct ata_port *ap = dev_instance; 1811 void __iomem *port_mmio = ahci_port_base(ap); 1812 u32 status; 1813 1814 VPRINTK("ENTER\n"); 1815 1816 status = readl(port_mmio + PORT_IRQ_STAT); 1817 writel(status, port_mmio + PORT_IRQ_STAT); 1818 1819 spin_lock(ap->lock); 1820 ahci_handle_port_interrupt(ap, port_mmio, status); 1821 spin_unlock(ap->lock); 1822 1823 VPRINTK("EXIT\n"); 1824 1825 return IRQ_HANDLED; 1826 } 1827 1828 static u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked) 1829 { 1830 unsigned int i, handled = 0; 1831 1832 for (i = 0; i < host->n_ports; i++) { 1833 struct ata_port *ap; 1834 1835 if (!(irq_masked & (1 << i))) 1836 continue; 1837 1838 ap = host->ports[i]; 1839 if (ap) { 1840 ahci_port_intr(ap); 1841 VPRINTK("port %u\n", i); 1842 } else { 1843 VPRINTK("port %u (no irq)\n", i); 1844 if (ata_ratelimit()) 1845 dev_warn(host->dev, 1846 "interrupt on disabled port %u\n", i); 1847 } 1848 1849 handled = 1; 1850 } 1851 1852 return handled; 1853 } 1854 1855 static irqreturn_t ahci_single_edge_irq_intr(int irq, void *dev_instance) 1856 { 1857 struct ata_host *host = dev_instance; 1858 struct ahci_host_priv *hpriv; 1859 unsigned int rc = 0; 1860 void __iomem *mmio; 1861 u32 irq_stat, irq_masked; 1862 1863 VPRINTK("ENTER\n"); 1864 1865 hpriv = host->private_data; 1866 mmio = hpriv->mmio; 1867 1868 /* sigh. 0xffffffff is a valid return from h/w */ 1869 irq_stat = readl(mmio + HOST_IRQ_STAT); 1870 if (!irq_stat) 1871 return IRQ_NONE; 1872 1873 irq_masked = irq_stat & hpriv->port_map; 1874 1875 spin_lock(&host->lock); 1876 1877 /* 1878 * HOST_IRQ_STAT behaves as edge triggered latch meaning that 1879 * it should be cleared before all the port events are cleared. 1880 */ 1881 writel(irq_stat, mmio + HOST_IRQ_STAT); 1882 1883 rc = ahci_handle_port_intr(host, irq_masked); 1884 1885 spin_unlock(&host->lock); 1886 1887 VPRINTK("EXIT\n"); 1888 1889 return IRQ_RETVAL(rc); 1890 } 1891 1892 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance) 1893 { 1894 struct ata_host *host = dev_instance; 1895 struct ahci_host_priv *hpriv; 1896 unsigned int rc = 0; 1897 void __iomem *mmio; 1898 u32 irq_stat, irq_masked; 1899 1900 VPRINTK("ENTER\n"); 1901 1902 hpriv = host->private_data; 1903 mmio = hpriv->mmio; 1904 1905 /* sigh. 0xffffffff is a valid return from h/w */ 1906 irq_stat = readl(mmio + HOST_IRQ_STAT); 1907 if (!irq_stat) 1908 return IRQ_NONE; 1909 1910 irq_masked = irq_stat & hpriv->port_map; 1911 1912 spin_lock(&host->lock); 1913 1914 rc = ahci_handle_port_intr(host, irq_masked); 1915 1916 /* HOST_IRQ_STAT behaves as level triggered latch meaning that 1917 * it should be cleared after all the port events are cleared; 1918 * otherwise, it will raise a spurious interrupt after each 1919 * valid one. Please read section 10.6.2 of ahci 1.1 for more 1920 * information. 1921 * 1922 * Also, use the unmasked value to clear interrupt as spurious 1923 * pending event on a dummy port might cause screaming IRQ. 1924 */ 1925 writel(irq_stat, mmio + HOST_IRQ_STAT); 1926 1927 spin_unlock(&host->lock); 1928 1929 VPRINTK("EXIT\n"); 1930 1931 return IRQ_RETVAL(rc); 1932 } 1933 1934 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) 1935 { 1936 struct ata_port *ap = qc->ap; 1937 void __iomem *port_mmio = ahci_port_base(ap); 1938 struct ahci_port_priv *pp = ap->private_data; 1939 1940 /* Keep track of the currently active link. It will be used 1941 * in completion path to determine whether NCQ phase is in 1942 * progress. 1943 */ 1944 pp->active_link = qc->dev->link; 1945 1946 if (qc->tf.protocol == ATA_PROT_NCQ) 1947 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); 1948 1949 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) { 1950 u32 fbs = readl(port_mmio + PORT_FBS); 1951 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); 1952 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET; 1953 writel(fbs, port_mmio + PORT_FBS); 1954 pp->fbs_last_dev = qc->dev->link->pmp; 1955 } 1956 1957 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); 1958 1959 ahci_sw_activity(qc->dev->link); 1960 1961 return 0; 1962 } 1963 EXPORT_SYMBOL_GPL(ahci_qc_issue); 1964 1965 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc) 1966 { 1967 struct ahci_port_priv *pp = qc->ap->private_data; 1968 u8 *rx_fis = pp->rx_fis; 1969 1970 if (pp->fbs_enabled) 1971 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ; 1972 1973 /* 1974 * After a successful execution of an ATA PIO data-in command, 1975 * the device doesn't send D2H Reg FIS to update the TF and 1976 * the host should take TF and E_Status from the preceding PIO 1977 * Setup FIS. 1978 */ 1979 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE && 1980 !(qc->flags & ATA_QCFLAG_FAILED)) { 1981 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf); 1982 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15]; 1983 } else 1984 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf); 1985 1986 return true; 1987 } 1988 1989 static void ahci_freeze(struct ata_port *ap) 1990 { 1991 void __iomem *port_mmio = ahci_port_base(ap); 1992 1993 /* turn IRQ off */ 1994 writel(0, port_mmio + PORT_IRQ_MASK); 1995 } 1996 1997 static void ahci_thaw(struct ata_port *ap) 1998 { 1999 struct ahci_host_priv *hpriv = ap->host->private_data; 2000 void __iomem *mmio = hpriv->mmio; 2001 void __iomem *port_mmio = ahci_port_base(ap); 2002 u32 tmp; 2003 struct ahci_port_priv *pp = ap->private_data; 2004 2005 /* clear IRQ */ 2006 tmp = readl(port_mmio + PORT_IRQ_STAT); 2007 writel(tmp, port_mmio + PORT_IRQ_STAT); 2008 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); 2009 2010 /* turn IRQ back on */ 2011 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2012 } 2013 2014 void ahci_error_handler(struct ata_port *ap) 2015 { 2016 struct ahci_host_priv *hpriv = ap->host->private_data; 2017 2018 if (!(ap->pflags & ATA_PFLAG_FROZEN)) { 2019 /* restart engine */ 2020 ahci_stop_engine(ap); 2021 hpriv->start_engine(ap); 2022 } 2023 2024 sata_pmp_error_handler(ap); 2025 2026 if (!ata_dev_enabled(ap->link.device)) 2027 ahci_stop_engine(ap); 2028 } 2029 EXPORT_SYMBOL_GPL(ahci_error_handler); 2030 2031 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) 2032 { 2033 struct ata_port *ap = qc->ap; 2034 2035 /* make DMA engine forget about the failed command */ 2036 if (qc->flags & ATA_QCFLAG_FAILED) 2037 ahci_kick_engine(ap); 2038 } 2039 2040 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep) 2041 { 2042 struct ahci_host_priv *hpriv = ap->host->private_data; 2043 void __iomem *port_mmio = ahci_port_base(ap); 2044 struct ata_device *dev = ap->link.device; 2045 u32 devslp, dm, dito, mdat, deto; 2046 int rc; 2047 unsigned int err_mask; 2048 2049 devslp = readl(port_mmio + PORT_DEVSLP); 2050 if (!(devslp & PORT_DEVSLP_DSP)) { 2051 dev_info(ap->host->dev, "port does not support device sleep\n"); 2052 return; 2053 } 2054 2055 /* disable device sleep */ 2056 if (!sleep) { 2057 if (devslp & PORT_DEVSLP_ADSE) { 2058 writel(devslp & ~PORT_DEVSLP_ADSE, 2059 port_mmio + PORT_DEVSLP); 2060 err_mask = ata_dev_set_feature(dev, 2061 SETFEATURES_SATA_DISABLE, 2062 SATA_DEVSLP); 2063 if (err_mask && err_mask != AC_ERR_DEV) 2064 ata_dev_warn(dev, "failed to disable DEVSLP\n"); 2065 } 2066 return; 2067 } 2068 2069 /* device sleep was already enabled */ 2070 if (devslp & PORT_DEVSLP_ADSE) 2071 return; 2072 2073 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */ 2074 rc = ahci_stop_engine(ap); 2075 if (rc) 2076 return; 2077 2078 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET; 2079 dito = devslp_idle_timeout / (dm + 1); 2080 if (dito > 0x3ff) 2081 dito = 0x3ff; 2082 2083 /* Use the nominal value 10 ms if the read MDAT is zero, 2084 * the nominal value of DETO is 20 ms. 2085 */ 2086 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] & 2087 ATA_LOG_DEVSLP_VALID_MASK) { 2088 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] & 2089 ATA_LOG_DEVSLP_MDAT_MASK; 2090 if (!mdat) 2091 mdat = 10; 2092 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO]; 2093 if (!deto) 2094 deto = 20; 2095 } else { 2096 mdat = 10; 2097 deto = 20; 2098 } 2099 2100 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) | 2101 (mdat << PORT_DEVSLP_MDAT_OFFSET) | 2102 (deto << PORT_DEVSLP_DETO_OFFSET) | 2103 PORT_DEVSLP_ADSE); 2104 writel(devslp, port_mmio + PORT_DEVSLP); 2105 2106 hpriv->start_engine(ap); 2107 2108 /* enable device sleep feature for the drive */ 2109 err_mask = ata_dev_set_feature(dev, 2110 SETFEATURES_SATA_ENABLE, 2111 SATA_DEVSLP); 2112 if (err_mask && err_mask != AC_ERR_DEV) 2113 ata_dev_warn(dev, "failed to enable DEVSLP\n"); 2114 } 2115 2116 static void ahci_enable_fbs(struct ata_port *ap) 2117 { 2118 struct ahci_host_priv *hpriv = ap->host->private_data; 2119 struct ahci_port_priv *pp = ap->private_data; 2120 void __iomem *port_mmio = ahci_port_base(ap); 2121 u32 fbs; 2122 int rc; 2123 2124 if (!pp->fbs_supported) 2125 return; 2126 2127 fbs = readl(port_mmio + PORT_FBS); 2128 if (fbs & PORT_FBS_EN) { 2129 pp->fbs_enabled = true; 2130 pp->fbs_last_dev = -1; /* initialization */ 2131 return; 2132 } 2133 2134 rc = ahci_stop_engine(ap); 2135 if (rc) 2136 return; 2137 2138 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS); 2139 fbs = readl(port_mmio + PORT_FBS); 2140 if (fbs & PORT_FBS_EN) { 2141 dev_info(ap->host->dev, "FBS is enabled\n"); 2142 pp->fbs_enabled = true; 2143 pp->fbs_last_dev = -1; /* initialization */ 2144 } else 2145 dev_err(ap->host->dev, "Failed to enable FBS\n"); 2146 2147 hpriv->start_engine(ap); 2148 } 2149 2150 static void ahci_disable_fbs(struct ata_port *ap) 2151 { 2152 struct ahci_host_priv *hpriv = ap->host->private_data; 2153 struct ahci_port_priv *pp = ap->private_data; 2154 void __iomem *port_mmio = ahci_port_base(ap); 2155 u32 fbs; 2156 int rc; 2157 2158 if (!pp->fbs_supported) 2159 return; 2160 2161 fbs = readl(port_mmio + PORT_FBS); 2162 if ((fbs & PORT_FBS_EN) == 0) { 2163 pp->fbs_enabled = false; 2164 return; 2165 } 2166 2167 rc = ahci_stop_engine(ap); 2168 if (rc) 2169 return; 2170 2171 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS); 2172 fbs = readl(port_mmio + PORT_FBS); 2173 if (fbs & PORT_FBS_EN) 2174 dev_err(ap->host->dev, "Failed to disable FBS\n"); 2175 else { 2176 dev_info(ap->host->dev, "FBS is disabled\n"); 2177 pp->fbs_enabled = false; 2178 } 2179 2180 hpriv->start_engine(ap); 2181 } 2182 2183 static void ahci_pmp_attach(struct ata_port *ap) 2184 { 2185 void __iomem *port_mmio = ahci_port_base(ap); 2186 struct ahci_port_priv *pp = ap->private_data; 2187 u32 cmd; 2188 2189 cmd = readl(port_mmio + PORT_CMD); 2190 cmd |= PORT_CMD_PMP; 2191 writel(cmd, port_mmio + PORT_CMD); 2192 2193 ahci_enable_fbs(ap); 2194 2195 pp->intr_mask |= PORT_IRQ_BAD_PMP; 2196 2197 /* 2198 * We must not change the port interrupt mask register if the 2199 * port is marked frozen, the value in pp->intr_mask will be 2200 * restored later when the port is thawed. 2201 * 2202 * Note that during initialization, the port is marked as 2203 * frozen since the irq handler is not yet registered. 2204 */ 2205 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 2206 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2207 } 2208 2209 static void ahci_pmp_detach(struct ata_port *ap) 2210 { 2211 void __iomem *port_mmio = ahci_port_base(ap); 2212 struct ahci_port_priv *pp = ap->private_data; 2213 u32 cmd; 2214 2215 ahci_disable_fbs(ap); 2216 2217 cmd = readl(port_mmio + PORT_CMD); 2218 cmd &= ~PORT_CMD_PMP; 2219 writel(cmd, port_mmio + PORT_CMD); 2220 2221 pp->intr_mask &= ~PORT_IRQ_BAD_PMP; 2222 2223 /* see comment above in ahci_pmp_attach() */ 2224 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 2225 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2226 } 2227 2228 int ahci_port_resume(struct ata_port *ap) 2229 { 2230 ahci_power_up(ap); 2231 ahci_start_port(ap); 2232 2233 if (sata_pmp_attached(ap)) 2234 ahci_pmp_attach(ap); 2235 else 2236 ahci_pmp_detach(ap); 2237 2238 return 0; 2239 } 2240 EXPORT_SYMBOL_GPL(ahci_port_resume); 2241 2242 #ifdef CONFIG_PM 2243 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) 2244 { 2245 const char *emsg = NULL; 2246 int rc; 2247 2248 rc = ahci_deinit_port(ap, &emsg); 2249 if (rc == 0) 2250 ahci_power_down(ap); 2251 else { 2252 ata_port_err(ap, "%s (%d)\n", emsg, rc); 2253 ata_port_freeze(ap); 2254 } 2255 2256 return rc; 2257 } 2258 #endif 2259 2260 static int ahci_port_start(struct ata_port *ap) 2261 { 2262 struct ahci_host_priv *hpriv = ap->host->private_data; 2263 struct device *dev = ap->host->dev; 2264 struct ahci_port_priv *pp; 2265 void *mem; 2266 dma_addr_t mem_dma; 2267 size_t dma_sz, rx_fis_sz; 2268 2269 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 2270 if (!pp) 2271 return -ENOMEM; 2272 2273 if (ap->host->n_ports > 1) { 2274 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL); 2275 if (!pp->irq_desc) { 2276 devm_kfree(dev, pp); 2277 return -ENOMEM; 2278 } 2279 snprintf(pp->irq_desc, 8, 2280 "%s%d", dev_driver_string(dev), ap->port_no); 2281 } 2282 2283 /* check FBS capability */ 2284 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) { 2285 void __iomem *port_mmio = ahci_port_base(ap); 2286 u32 cmd = readl(port_mmio + PORT_CMD); 2287 if (cmd & PORT_CMD_FBSCP) 2288 pp->fbs_supported = true; 2289 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) { 2290 dev_info(dev, "port %d can do FBS, forcing FBSCP\n", 2291 ap->port_no); 2292 pp->fbs_supported = true; 2293 } else 2294 dev_warn(dev, "port %d is not capable of FBS\n", 2295 ap->port_no); 2296 } 2297 2298 if (pp->fbs_supported) { 2299 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ; 2300 rx_fis_sz = AHCI_RX_FIS_SZ * 16; 2301 } else { 2302 dma_sz = AHCI_PORT_PRIV_DMA_SZ; 2303 rx_fis_sz = AHCI_RX_FIS_SZ; 2304 } 2305 2306 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL); 2307 if (!mem) 2308 return -ENOMEM; 2309 memset(mem, 0, dma_sz); 2310 2311 /* 2312 * First item in chunk of DMA memory: 32-slot command table, 2313 * 32 bytes each in size 2314 */ 2315 pp->cmd_slot = mem; 2316 pp->cmd_slot_dma = mem_dma; 2317 2318 mem += AHCI_CMD_SLOT_SZ; 2319 mem_dma += AHCI_CMD_SLOT_SZ; 2320 2321 /* 2322 * Second item: Received-FIS area 2323 */ 2324 pp->rx_fis = mem; 2325 pp->rx_fis_dma = mem_dma; 2326 2327 mem += rx_fis_sz; 2328 mem_dma += rx_fis_sz; 2329 2330 /* 2331 * Third item: data area for storing a single command 2332 * and its scatter-gather table 2333 */ 2334 pp->cmd_tbl = mem; 2335 pp->cmd_tbl_dma = mem_dma; 2336 2337 /* 2338 * Save off initial list of interrupts to be enabled. 2339 * This could be changed later 2340 */ 2341 pp->intr_mask = DEF_PORT_IRQ; 2342 2343 /* 2344 * Switch to per-port locking in case each port has its own MSI vector. 2345 */ 2346 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) { 2347 spin_lock_init(&pp->lock); 2348 ap->lock = &pp->lock; 2349 } 2350 2351 ap->private_data = pp; 2352 2353 /* engage engines, captain */ 2354 return ahci_port_resume(ap); 2355 } 2356 2357 static void ahci_port_stop(struct ata_port *ap) 2358 { 2359 const char *emsg = NULL; 2360 int rc; 2361 2362 /* de-initialize port */ 2363 rc = ahci_deinit_port(ap, &emsg); 2364 if (rc) 2365 ata_port_warn(ap, "%s (%d)\n", emsg, rc); 2366 } 2367 2368 void ahci_print_info(struct ata_host *host, const char *scc_s) 2369 { 2370 struct ahci_host_priv *hpriv = host->private_data; 2371 void __iomem *mmio = hpriv->mmio; 2372 u32 vers, cap, cap2, impl, speed; 2373 const char *speed_s; 2374 2375 vers = readl(mmio + HOST_VERSION); 2376 cap = hpriv->cap; 2377 cap2 = hpriv->cap2; 2378 impl = hpriv->port_map; 2379 2380 speed = (cap >> 20) & 0xf; 2381 if (speed == 1) 2382 speed_s = "1.5"; 2383 else if (speed == 2) 2384 speed_s = "3"; 2385 else if (speed == 3) 2386 speed_s = "6"; 2387 else 2388 speed_s = "?"; 2389 2390 dev_info(host->dev, 2391 "AHCI %02x%02x.%02x%02x " 2392 "%u slots %u ports %s Gbps 0x%x impl %s mode\n" 2393 , 2394 2395 (vers >> 24) & 0xff, 2396 (vers >> 16) & 0xff, 2397 (vers >> 8) & 0xff, 2398 vers & 0xff, 2399 2400 ((cap >> 8) & 0x1f) + 1, 2401 (cap & 0x1f) + 1, 2402 speed_s, 2403 impl, 2404 scc_s); 2405 2406 dev_info(host->dev, 2407 "flags: " 2408 "%s%s%s%s%s%s%s" 2409 "%s%s%s%s%s%s%s" 2410 "%s%s%s%s%s%s%s" 2411 "%s%s\n" 2412 , 2413 2414 cap & HOST_CAP_64 ? "64bit " : "", 2415 cap & HOST_CAP_NCQ ? "ncq " : "", 2416 cap & HOST_CAP_SNTF ? "sntf " : "", 2417 cap & HOST_CAP_MPS ? "ilck " : "", 2418 cap & HOST_CAP_SSS ? "stag " : "", 2419 cap & HOST_CAP_ALPM ? "pm " : "", 2420 cap & HOST_CAP_LED ? "led " : "", 2421 cap & HOST_CAP_CLO ? "clo " : "", 2422 cap & HOST_CAP_ONLY ? "only " : "", 2423 cap & HOST_CAP_PMP ? "pmp " : "", 2424 cap & HOST_CAP_FBS ? "fbs " : "", 2425 cap & HOST_CAP_PIO_MULTI ? "pio " : "", 2426 cap & HOST_CAP_SSC ? "slum " : "", 2427 cap & HOST_CAP_PART ? "part " : "", 2428 cap & HOST_CAP_CCC ? "ccc " : "", 2429 cap & HOST_CAP_EMS ? "ems " : "", 2430 cap & HOST_CAP_SXS ? "sxs " : "", 2431 cap2 & HOST_CAP2_DESO ? "deso " : "", 2432 cap2 & HOST_CAP2_SADM ? "sadm " : "", 2433 cap2 & HOST_CAP2_SDS ? "sds " : "", 2434 cap2 & HOST_CAP2_APST ? "apst " : "", 2435 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "", 2436 cap2 & HOST_CAP2_BOH ? "boh " : "" 2437 ); 2438 } 2439 EXPORT_SYMBOL_GPL(ahci_print_info); 2440 2441 void ahci_set_em_messages(struct ahci_host_priv *hpriv, 2442 struct ata_port_info *pi) 2443 { 2444 u8 messages; 2445 void __iomem *mmio = hpriv->mmio; 2446 u32 em_loc = readl(mmio + HOST_EM_LOC); 2447 u32 em_ctl = readl(mmio + HOST_EM_CTL); 2448 2449 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS)) 2450 return; 2451 2452 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16; 2453 2454 if (messages) { 2455 /* store em_loc */ 2456 hpriv->em_loc = ((em_loc >> 16) * 4); 2457 hpriv->em_buf_sz = ((em_loc & 0xff) * 4); 2458 hpriv->em_msg_type = messages; 2459 pi->flags |= ATA_FLAG_EM; 2460 if (!(em_ctl & EM_CTL_ALHD)) 2461 pi->flags |= ATA_FLAG_SW_ACTIVITY; 2462 } 2463 } 2464 EXPORT_SYMBOL_GPL(ahci_set_em_messages); 2465 2466 static int ahci_host_activate_multi_irqs(struct ata_host *host, 2467 struct scsi_host_template *sht) 2468 { 2469 struct ahci_host_priv *hpriv = host->private_data; 2470 int i, rc; 2471 2472 rc = ata_host_start(host); 2473 if (rc) 2474 return rc; 2475 /* 2476 * Requests IRQs according to AHCI-1.1 when multiple MSIs were 2477 * allocated. That is one MSI per port, starting from @irq. 2478 */ 2479 for (i = 0; i < host->n_ports; i++) { 2480 struct ahci_port_priv *pp = host->ports[i]->private_data; 2481 int irq = ahci_irq_vector(hpriv, i); 2482 2483 /* Do not receive interrupts sent by dummy ports */ 2484 if (!pp) { 2485 disable_irq(irq + i); 2486 continue; 2487 } 2488 2489 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard, 2490 0, pp->irq_desc, host->ports[i]); 2491 2492 if (rc) 2493 return rc; 2494 ata_port_desc(host->ports[i], "irq %d", irq); 2495 } 2496 2497 return ata_host_register(host, sht); 2498 } 2499 2500 /** 2501 * ahci_host_activate - start AHCI host, request IRQs and register it 2502 * @host: target ATA host 2503 * @sht: scsi_host_template to use when registering the host 2504 * 2505 * LOCKING: 2506 * Inherited from calling layer (may sleep). 2507 * 2508 * RETURNS: 2509 * 0 on success, -errno otherwise. 2510 */ 2511 int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht) 2512 { 2513 struct ahci_host_priv *hpriv = host->private_data; 2514 int irq = hpriv->irq; 2515 int rc; 2516 2517 if (hpriv->flags & (AHCI_HFLAG_MULTI_MSI | AHCI_HFLAG_MULTI_MSIX)) 2518 rc = ahci_host_activate_multi_irqs(host, sht); 2519 else if (hpriv->flags & AHCI_HFLAG_EDGE_IRQ) 2520 rc = ata_host_activate(host, irq, ahci_single_edge_irq_intr, 2521 IRQF_SHARED, sht); 2522 else 2523 rc = ata_host_activate(host, irq, ahci_single_level_irq_intr, 2524 IRQF_SHARED, sht); 2525 return rc; 2526 } 2527 EXPORT_SYMBOL_GPL(ahci_host_activate); 2528 2529 MODULE_AUTHOR("Jeff Garzik"); 2530 MODULE_DESCRIPTION("Common AHCI SATA low-level routines"); 2531 MODULE_LICENSE("GPL"); 2532