xref: /openbmc/linux/drivers/ata/libahci.c (revision 236a9bf2)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  *  libahci.c - Common AHCI SATA low-level routines
4  *
5  *  Maintained by:  Tejun Heo <tj@kernel.org>
6  *    		    Please ALWAYS copy linux-ide@vger.kernel.org
7  *		    on emails.
8  *
9  *  Copyright 2004-2005 Red Hat, Inc.
10  *
11  * libata documentation is available via 'make {ps|pdf}docs',
12  * as Documentation/driver-api/libata.rst
13  *
14  * AHCI hardware documentation:
15  * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16  * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
17  */
18 
19 #include <linux/bitops.h>
20 #include <linux/kernel.h>
21 #include <linux/gfp.h>
22 #include <linux/module.h>
23 #include <linux/nospec.h>
24 #include <linux/blkdev.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/device.h>
29 #include <scsi/scsi_host.h>
30 #include <scsi/scsi_cmnd.h>
31 #include <linux/libata.h>
32 #include <linux/pci.h>
33 #include "ahci.h"
34 #include "libata.h"
35 
36 static int ahci_skip_host_reset;
37 int ahci_ignore_sss;
38 EXPORT_SYMBOL_GPL(ahci_ignore_sss);
39 
40 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
41 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
42 
43 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
44 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
45 
46 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
47 			unsigned hints);
48 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
49 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
50 			      size_t size);
51 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
52 					ssize_t size);
53 
54 
55 
56 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
57 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
58 static void ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
59 static void ahci_qc_ncq_fill_rtf(struct ata_port *ap, u64 done_mask);
60 static int ahci_port_start(struct ata_port *ap);
61 static void ahci_port_stop(struct ata_port *ap);
62 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc);
63 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
64 static void ahci_freeze(struct ata_port *ap);
65 static void ahci_thaw(struct ata_port *ap);
66 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
67 static void ahci_enable_fbs(struct ata_port *ap);
68 static void ahci_disable_fbs(struct ata_port *ap);
69 static void ahci_pmp_attach(struct ata_port *ap);
70 static void ahci_pmp_detach(struct ata_port *ap);
71 static int ahci_softreset(struct ata_link *link, unsigned int *class,
72 			  unsigned long deadline);
73 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
74 			  unsigned long deadline);
75 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
76 			  unsigned long deadline);
77 static void ahci_postreset(struct ata_link *link, unsigned int *class);
78 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
79 static void ahci_dev_config(struct ata_device *dev);
80 #ifdef CONFIG_PM
81 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
82 #endif
83 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
84 static ssize_t ahci_activity_store(struct ata_device *dev,
85 				   enum sw_activity val);
86 static void ahci_init_sw_activity(struct ata_link *link);
87 
88 static ssize_t ahci_show_host_caps(struct device *dev,
89 				   struct device_attribute *attr, char *buf);
90 static ssize_t ahci_show_host_cap2(struct device *dev,
91 				   struct device_attribute *attr, char *buf);
92 static ssize_t ahci_show_host_version(struct device *dev,
93 				      struct device_attribute *attr, char *buf);
94 static ssize_t ahci_show_port_cmd(struct device *dev,
95 				  struct device_attribute *attr, char *buf);
96 static ssize_t ahci_read_em_buffer(struct device *dev,
97 				   struct device_attribute *attr, char *buf);
98 static ssize_t ahci_store_em_buffer(struct device *dev,
99 				    struct device_attribute *attr,
100 				    const char *buf, size_t size);
101 static ssize_t ahci_show_em_supported(struct device *dev,
102 				      struct device_attribute *attr, char *buf);
103 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance);
104 
105 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
106 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
107 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
108 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
109 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
110 		   ahci_read_em_buffer, ahci_store_em_buffer);
111 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
112 
113 static struct attribute *ahci_shost_attrs[] = {
114 	&dev_attr_link_power_management_policy.attr,
115 	&dev_attr_em_message_type.attr,
116 	&dev_attr_em_message.attr,
117 	&dev_attr_ahci_host_caps.attr,
118 	&dev_attr_ahci_host_cap2.attr,
119 	&dev_attr_ahci_host_version.attr,
120 	&dev_attr_ahci_port_cmd.attr,
121 	&dev_attr_em_buffer.attr,
122 	&dev_attr_em_message_supported.attr,
123 	NULL
124 };
125 
126 static const struct attribute_group ahci_shost_attr_group = {
127 	.attrs = ahci_shost_attrs
128 };
129 
130 const struct attribute_group *ahci_shost_groups[] = {
131 	&ahci_shost_attr_group,
132 	NULL
133 };
134 EXPORT_SYMBOL_GPL(ahci_shost_groups);
135 
136 static struct attribute *ahci_sdev_attrs[] = {
137 	&dev_attr_sw_activity.attr,
138 	&dev_attr_unload_heads.attr,
139 	&dev_attr_ncq_prio_supported.attr,
140 	&dev_attr_ncq_prio_enable.attr,
141 	NULL
142 };
143 
144 static const struct attribute_group ahci_sdev_attr_group = {
145 	.attrs = ahci_sdev_attrs
146 };
147 
148 const struct attribute_group *ahci_sdev_groups[] = {
149 	&ahci_sdev_attr_group,
150 	NULL
151 };
152 EXPORT_SYMBOL_GPL(ahci_sdev_groups);
153 
154 struct ata_port_operations ahci_ops = {
155 	.inherits		= &sata_pmp_port_ops,
156 
157 	.qc_defer		= ahci_pmp_qc_defer,
158 	.qc_prep		= ahci_qc_prep,
159 	.qc_issue		= ahci_qc_issue,
160 	.qc_fill_rtf		= ahci_qc_fill_rtf,
161 	.qc_ncq_fill_rtf	= ahci_qc_ncq_fill_rtf,
162 
163 	.freeze			= ahci_freeze,
164 	.thaw			= ahci_thaw,
165 	.softreset		= ahci_softreset,
166 	.hardreset		= ahci_hardreset,
167 	.postreset		= ahci_postreset,
168 	.pmp_softreset		= ahci_softreset,
169 	.error_handler		= ahci_error_handler,
170 	.post_internal_cmd	= ahci_post_internal_cmd,
171 	.dev_config		= ahci_dev_config,
172 
173 	.scr_read		= ahci_scr_read,
174 	.scr_write		= ahci_scr_write,
175 	.pmp_attach		= ahci_pmp_attach,
176 	.pmp_detach		= ahci_pmp_detach,
177 
178 	.set_lpm		= ahci_set_lpm,
179 	.em_show		= ahci_led_show,
180 	.em_store		= ahci_led_store,
181 	.sw_activity_show	= ahci_activity_show,
182 	.sw_activity_store	= ahci_activity_store,
183 	.transmit_led_message	= ahci_transmit_led_message,
184 #ifdef CONFIG_PM
185 	.port_suspend		= ahci_port_suspend,
186 	.port_resume		= ahci_port_resume,
187 #endif
188 	.port_start		= ahci_port_start,
189 	.port_stop		= ahci_port_stop,
190 };
191 EXPORT_SYMBOL_GPL(ahci_ops);
192 
193 struct ata_port_operations ahci_pmp_retry_srst_ops = {
194 	.inherits		= &ahci_ops,
195 	.softreset		= ahci_pmp_retry_softreset,
196 };
197 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
198 
199 static bool ahci_em_messages __read_mostly = true;
200 module_param(ahci_em_messages, bool, 0444);
201 /* add other LED protocol types when they become supported */
202 MODULE_PARM_DESC(ahci_em_messages,
203 	"AHCI Enclosure Management Message control (0 = off, 1 = on)");
204 
205 /* device sleep idle timeout in ms */
206 static int devslp_idle_timeout __read_mostly = 1000;
207 module_param(devslp_idle_timeout, int, 0644);
208 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
209 
210 static void ahci_enable_ahci(void __iomem *mmio)
211 {
212 	int i;
213 	u32 tmp;
214 
215 	/* turn on AHCI_EN */
216 	tmp = readl(mmio + HOST_CTL);
217 	if (tmp & HOST_AHCI_EN)
218 		return;
219 
220 	/* Some controllers need AHCI_EN to be written multiple times.
221 	 * Try a few times before giving up.
222 	 */
223 	for (i = 0; i < 5; i++) {
224 		tmp |= HOST_AHCI_EN;
225 		writel(tmp, mmio + HOST_CTL);
226 		tmp = readl(mmio + HOST_CTL);	/* flush && sanity check */
227 		if (tmp & HOST_AHCI_EN)
228 			return;
229 		msleep(10);
230 	}
231 
232 	WARN_ON(1);
233 }
234 
235 /**
236  *	ahci_rpm_get_port - Make sure the port is powered on
237  *	@ap: Port to power on
238  *
239  *	Whenever there is need to access the AHCI host registers outside of
240  *	normal execution paths, call this function to make sure the host is
241  *	actually powered on.
242  */
243 static int ahci_rpm_get_port(struct ata_port *ap)
244 {
245 	return pm_runtime_get_sync(ap->dev);
246 }
247 
248 /**
249  *	ahci_rpm_put_port - Undoes ahci_rpm_get_port()
250  *	@ap: Port to power down
251  *
252  *	Undoes ahci_rpm_get_port() and possibly powers down the AHCI host
253  *	if it has no more active users.
254  */
255 static void ahci_rpm_put_port(struct ata_port *ap)
256 {
257 	pm_runtime_put(ap->dev);
258 }
259 
260 static ssize_t ahci_show_host_caps(struct device *dev,
261 				   struct device_attribute *attr, char *buf)
262 {
263 	struct Scsi_Host *shost = class_to_shost(dev);
264 	struct ata_port *ap = ata_shost_to_port(shost);
265 	struct ahci_host_priv *hpriv = ap->host->private_data;
266 
267 	return sprintf(buf, "%x\n", hpriv->cap);
268 }
269 
270 static ssize_t ahci_show_host_cap2(struct device *dev,
271 				   struct device_attribute *attr, char *buf)
272 {
273 	struct Scsi_Host *shost = class_to_shost(dev);
274 	struct ata_port *ap = ata_shost_to_port(shost);
275 	struct ahci_host_priv *hpriv = ap->host->private_data;
276 
277 	return sprintf(buf, "%x\n", hpriv->cap2);
278 }
279 
280 static ssize_t ahci_show_host_version(struct device *dev,
281 				   struct device_attribute *attr, char *buf)
282 {
283 	struct Scsi_Host *shost = class_to_shost(dev);
284 	struct ata_port *ap = ata_shost_to_port(shost);
285 	struct ahci_host_priv *hpriv = ap->host->private_data;
286 
287 	return sprintf(buf, "%x\n", hpriv->version);
288 }
289 
290 static ssize_t ahci_show_port_cmd(struct device *dev,
291 				  struct device_attribute *attr, char *buf)
292 {
293 	struct Scsi_Host *shost = class_to_shost(dev);
294 	struct ata_port *ap = ata_shost_to_port(shost);
295 	void __iomem *port_mmio = ahci_port_base(ap);
296 	ssize_t ret;
297 
298 	ahci_rpm_get_port(ap);
299 	ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
300 	ahci_rpm_put_port(ap);
301 
302 	return ret;
303 }
304 
305 static ssize_t ahci_read_em_buffer(struct device *dev,
306 				   struct device_attribute *attr, char *buf)
307 {
308 	struct Scsi_Host *shost = class_to_shost(dev);
309 	struct ata_port *ap = ata_shost_to_port(shost);
310 	struct ahci_host_priv *hpriv = ap->host->private_data;
311 	void __iomem *mmio = hpriv->mmio;
312 	void __iomem *em_mmio = mmio + hpriv->em_loc;
313 	u32 em_ctl, msg;
314 	unsigned long flags;
315 	size_t count;
316 	int i;
317 
318 	ahci_rpm_get_port(ap);
319 	spin_lock_irqsave(ap->lock, flags);
320 
321 	em_ctl = readl(mmio + HOST_EM_CTL);
322 	if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
323 	    !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
324 		spin_unlock_irqrestore(ap->lock, flags);
325 		ahci_rpm_put_port(ap);
326 		return -EINVAL;
327 	}
328 
329 	if (!(em_ctl & EM_CTL_MR)) {
330 		spin_unlock_irqrestore(ap->lock, flags);
331 		ahci_rpm_put_port(ap);
332 		return -EAGAIN;
333 	}
334 
335 	if (!(em_ctl & EM_CTL_SMB))
336 		em_mmio += hpriv->em_buf_sz;
337 
338 	count = hpriv->em_buf_sz;
339 
340 	/* the count should not be larger than PAGE_SIZE */
341 	if (count > PAGE_SIZE) {
342 		if (printk_ratelimit())
343 			ata_port_warn(ap,
344 				      "EM read buffer size too large: "
345 				      "buffer size %u, page size %lu\n",
346 				      hpriv->em_buf_sz, PAGE_SIZE);
347 		count = PAGE_SIZE;
348 	}
349 
350 	for (i = 0; i < count; i += 4) {
351 		msg = readl(em_mmio + i);
352 		buf[i] = msg & 0xff;
353 		buf[i + 1] = (msg >> 8) & 0xff;
354 		buf[i + 2] = (msg >> 16) & 0xff;
355 		buf[i + 3] = (msg >> 24) & 0xff;
356 	}
357 
358 	spin_unlock_irqrestore(ap->lock, flags);
359 	ahci_rpm_put_port(ap);
360 
361 	return i;
362 }
363 
364 static ssize_t ahci_store_em_buffer(struct device *dev,
365 				    struct device_attribute *attr,
366 				    const char *buf, size_t size)
367 {
368 	struct Scsi_Host *shost = class_to_shost(dev);
369 	struct ata_port *ap = ata_shost_to_port(shost);
370 	struct ahci_host_priv *hpriv = ap->host->private_data;
371 	void __iomem *mmio = hpriv->mmio;
372 	void __iomem *em_mmio = mmio + hpriv->em_loc;
373 	const unsigned char *msg_buf = buf;
374 	u32 em_ctl, msg;
375 	unsigned long flags;
376 	int i;
377 
378 	/* check size validity */
379 	if (!(ap->flags & ATA_FLAG_EM) ||
380 	    !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
381 	    size % 4 || size > hpriv->em_buf_sz)
382 		return -EINVAL;
383 
384 	ahci_rpm_get_port(ap);
385 	spin_lock_irqsave(ap->lock, flags);
386 
387 	em_ctl = readl(mmio + HOST_EM_CTL);
388 	if (em_ctl & EM_CTL_TM) {
389 		spin_unlock_irqrestore(ap->lock, flags);
390 		ahci_rpm_put_port(ap);
391 		return -EBUSY;
392 	}
393 
394 	for (i = 0; i < size; i += 4) {
395 		msg = msg_buf[i] | msg_buf[i + 1] << 8 |
396 		      msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
397 		writel(msg, em_mmio + i);
398 	}
399 
400 	writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
401 
402 	spin_unlock_irqrestore(ap->lock, flags);
403 	ahci_rpm_put_port(ap);
404 
405 	return size;
406 }
407 
408 static ssize_t ahci_show_em_supported(struct device *dev,
409 				      struct device_attribute *attr, char *buf)
410 {
411 	struct Scsi_Host *shost = class_to_shost(dev);
412 	struct ata_port *ap = ata_shost_to_port(shost);
413 	struct ahci_host_priv *hpriv = ap->host->private_data;
414 	void __iomem *mmio = hpriv->mmio;
415 	u32 em_ctl;
416 
417 	ahci_rpm_get_port(ap);
418 	em_ctl = readl(mmio + HOST_EM_CTL);
419 	ahci_rpm_put_port(ap);
420 
421 	return sprintf(buf, "%s%s%s%s\n",
422 		       em_ctl & EM_CTL_LED ? "led " : "",
423 		       em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
424 		       em_ctl & EM_CTL_SES ? "ses-2 " : "",
425 		       em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
426 }
427 
428 /**
429  *	ahci_save_initial_config - Save and fixup initial config values
430  *	@dev: target AHCI device
431  *	@hpriv: host private area to store config values
432  *
433  *	Some registers containing configuration info might be setup by
434  *	BIOS and might be cleared on reset.  This function saves the
435  *	initial values of those registers into @hpriv such that they
436  *	can be restored after controller reset.
437  *
438  *	If inconsistent, config values are fixed up by this function.
439  *
440  *	If it is not set already this function sets hpriv->start_engine to
441  *	ahci_start_engine.
442  *
443  *	LOCKING:
444  *	None.
445  */
446 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
447 {
448 	void __iomem *mmio = hpriv->mmio;
449 	void __iomem *port_mmio;
450 	unsigned long port_map;
451 	u32 cap, cap2, vers;
452 	int i;
453 
454 	/* make sure AHCI mode is enabled before accessing CAP */
455 	ahci_enable_ahci(mmio);
456 
457 	/*
458 	 * Values prefixed with saved_ are written back to the HBA and ports
459 	 * registers after reset. Values without are used for driver operation.
460 	 */
461 
462 	/*
463 	 * Override HW-init HBA capability fields with the platform-specific
464 	 * values. The rest of the HBA capabilities are defined as Read-only
465 	 * and can't be modified in CSR anyway.
466 	 */
467 	cap = readl(mmio + HOST_CAP);
468 	if (hpriv->saved_cap)
469 		cap = (cap & ~(HOST_CAP_SSS | HOST_CAP_MPS)) | hpriv->saved_cap;
470 	hpriv->saved_cap = cap;
471 
472 	/* CAP2 register is only defined for AHCI 1.2 and later */
473 	vers = readl(mmio + HOST_VERSION);
474 	if ((vers >> 16) > 1 ||
475 	   ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
476 		hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
477 	else
478 		hpriv->saved_cap2 = cap2 = 0;
479 
480 	/* some chips have errata preventing 64bit use */
481 	if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
482 		dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
483 		cap &= ~HOST_CAP_64;
484 	}
485 
486 	if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
487 		dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
488 		cap &= ~HOST_CAP_NCQ;
489 	}
490 
491 	if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
492 		dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
493 		cap |= HOST_CAP_NCQ;
494 	}
495 
496 	if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
497 		dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
498 		cap &= ~HOST_CAP_PMP;
499 	}
500 
501 	if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
502 		dev_info(dev,
503 			 "controller can't do SNTF, turning off CAP_SNTF\n");
504 		cap &= ~HOST_CAP_SNTF;
505 	}
506 
507 	if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
508 		dev_info(dev,
509 			 "controller can't do DEVSLP, turning off\n");
510 		cap2 &= ~HOST_CAP2_SDS;
511 		cap2 &= ~HOST_CAP2_SADM;
512 	}
513 
514 	if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
515 		dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
516 		cap |= HOST_CAP_FBS;
517 	}
518 
519 	if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
520 		dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
521 		cap &= ~HOST_CAP_FBS;
522 	}
523 
524 	if (!(cap & HOST_CAP_ALPM) && (hpriv->flags & AHCI_HFLAG_YES_ALPM)) {
525 		dev_info(dev, "controller can do ALPM, turning on CAP_ALPM\n");
526 		cap |= HOST_CAP_ALPM;
527 	}
528 
529 	if ((cap & HOST_CAP_SXS) && (hpriv->flags & AHCI_HFLAG_NO_SXS)) {
530 		dev_info(dev, "controller does not support SXS, disabling CAP_SXS\n");
531 		cap &= ~HOST_CAP_SXS;
532 	}
533 
534 	/* Override the HBA ports mapping if the platform needs it */
535 	port_map = readl(mmio + HOST_PORTS_IMPL);
536 	if (hpriv->saved_port_map && port_map != hpriv->saved_port_map) {
537 		dev_info(dev, "forcing port_map 0x%lx -> 0x%x\n",
538 			 port_map, hpriv->saved_port_map);
539 		port_map = hpriv->saved_port_map;
540 	} else {
541 		hpriv->saved_port_map = port_map;
542 	}
543 
544 	if (hpriv->mask_port_map) {
545 		dev_warn(dev, "masking port_map 0x%lx -> 0x%lx\n",
546 			port_map,
547 			port_map & hpriv->mask_port_map);
548 		port_map &= hpriv->mask_port_map;
549 	}
550 
551 	/* cross check port_map and cap.n_ports */
552 	if (port_map) {
553 		int map_ports = 0;
554 
555 		for (i = 0; i < AHCI_MAX_PORTS; i++)
556 			if (port_map & (1 << i))
557 				map_ports++;
558 
559 		/* If PI has more ports than n_ports, whine, clear
560 		 * port_map and let it be generated from n_ports.
561 		 */
562 		if (map_ports > ahci_nr_ports(cap)) {
563 			dev_warn(dev,
564 				 "implemented port map (0x%lx) contains more ports than nr_ports (%u), using nr_ports\n",
565 				 port_map, ahci_nr_ports(cap));
566 			port_map = 0;
567 		}
568 	}
569 
570 	/* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
571 	if (!port_map && vers < 0x10300) {
572 		port_map = (1 << ahci_nr_ports(cap)) - 1;
573 		dev_warn(dev, "forcing PORTS_IMPL to 0x%lx\n", port_map);
574 
575 		/* write the fixed up value to the PI register */
576 		hpriv->saved_port_map = port_map;
577 	}
578 
579 	/*
580 	 * Preserve the ports capabilities defined by the platform. Note there
581 	 * is no need in storing the rest of the P#.CMD fields since they are
582 	 * volatile.
583 	 */
584 	for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) {
585 		if (hpriv->saved_port_cap[i])
586 			continue;
587 
588 		port_mmio = __ahci_port_base(hpriv, i);
589 		hpriv->saved_port_cap[i] =
590 			readl(port_mmio + PORT_CMD) & PORT_CMD_CAP;
591 	}
592 
593 	/* record values to use during operation */
594 	hpriv->cap = cap;
595 	hpriv->cap2 = cap2;
596 	hpriv->version = vers;
597 	hpriv->port_map = port_map;
598 
599 	if (!hpriv->start_engine)
600 		hpriv->start_engine = ahci_start_engine;
601 
602 	if (!hpriv->stop_engine)
603 		hpriv->stop_engine = ahci_stop_engine;
604 
605 	if (!hpriv->irq_handler)
606 		hpriv->irq_handler = ahci_single_level_irq_intr;
607 }
608 EXPORT_SYMBOL_GPL(ahci_save_initial_config);
609 
610 /**
611  *	ahci_restore_initial_config - Restore initial config
612  *	@host: target ATA host
613  *
614  *	Restore initial config stored by ahci_save_initial_config().
615  *
616  *	LOCKING:
617  *	None.
618  */
619 static void ahci_restore_initial_config(struct ata_host *host)
620 {
621 	struct ahci_host_priv *hpriv = host->private_data;
622 	unsigned long port_map = hpriv->port_map;
623 	void __iomem *mmio = hpriv->mmio;
624 	void __iomem *port_mmio;
625 	int i;
626 
627 	writel(hpriv->saved_cap, mmio + HOST_CAP);
628 	if (hpriv->saved_cap2)
629 		writel(hpriv->saved_cap2, mmio + HOST_CAP2);
630 	writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
631 	(void) readl(mmio + HOST_PORTS_IMPL);	/* flush */
632 
633 	for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) {
634 		port_mmio = __ahci_port_base(hpriv, i);
635 		writel(hpriv->saved_port_cap[i], port_mmio + PORT_CMD);
636 	}
637 }
638 
639 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
640 {
641 	static const int offset[] = {
642 		[SCR_STATUS]		= PORT_SCR_STAT,
643 		[SCR_CONTROL]		= PORT_SCR_CTL,
644 		[SCR_ERROR]		= PORT_SCR_ERR,
645 		[SCR_ACTIVE]		= PORT_SCR_ACT,
646 		[SCR_NOTIFICATION]	= PORT_SCR_NTF,
647 	};
648 	struct ahci_host_priv *hpriv = ap->host->private_data;
649 
650 	if (sc_reg < ARRAY_SIZE(offset) &&
651 	    (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
652 		return offset[sc_reg];
653 	return 0;
654 }
655 
656 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
657 {
658 	void __iomem *port_mmio = ahci_port_base(link->ap);
659 	int offset = ahci_scr_offset(link->ap, sc_reg);
660 
661 	if (offset) {
662 		*val = readl(port_mmio + offset);
663 		return 0;
664 	}
665 	return -EINVAL;
666 }
667 
668 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
669 {
670 	void __iomem *port_mmio = ahci_port_base(link->ap);
671 	int offset = ahci_scr_offset(link->ap, sc_reg);
672 
673 	if (offset) {
674 		writel(val, port_mmio + offset);
675 		return 0;
676 	}
677 	return -EINVAL;
678 }
679 
680 void ahci_start_engine(struct ata_port *ap)
681 {
682 	void __iomem *port_mmio = ahci_port_base(ap);
683 	u32 tmp;
684 
685 	/* start DMA */
686 	tmp = readl(port_mmio + PORT_CMD);
687 	tmp |= PORT_CMD_START;
688 	writel(tmp, port_mmio + PORT_CMD);
689 	readl(port_mmio + PORT_CMD); /* flush */
690 }
691 EXPORT_SYMBOL_GPL(ahci_start_engine);
692 
693 int ahci_stop_engine(struct ata_port *ap)
694 {
695 	void __iomem *port_mmio = ahci_port_base(ap);
696 	struct ahci_host_priv *hpriv = ap->host->private_data;
697 	u32 tmp;
698 
699 	/*
700 	 * On some controllers, stopping a port's DMA engine while the port
701 	 * is in ALPM state (partial or slumber) results in failures on
702 	 * subsequent DMA engine starts.  For those controllers, put the
703 	 * port back in active state before stopping its DMA engine.
704 	 */
705 	if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) &&
706 	    (ap->link.lpm_policy > ATA_LPM_MAX_POWER) &&
707 	    ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) {
708 		dev_err(ap->host->dev, "Failed to wake up port before engine stop\n");
709 		return -EIO;
710 	}
711 
712 	tmp = readl(port_mmio + PORT_CMD);
713 
714 	/* check if the HBA is idle */
715 	if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
716 		return 0;
717 
718 	/*
719 	 * Don't try to issue commands but return with ENODEV if the
720 	 * AHCI controller not available anymore (e.g. due to PCIe hot
721 	 * unplugging). Otherwise a 500ms delay for each port is added.
722 	 */
723 	if (tmp == 0xffffffff) {
724 		dev_err(ap->host->dev, "AHCI controller unavailable!\n");
725 		return -ENODEV;
726 	}
727 
728 	/* setting HBA to idle */
729 	tmp &= ~PORT_CMD_START;
730 	writel(tmp, port_mmio + PORT_CMD);
731 
732 	/* wait for engine to stop. This could be as long as 500 msec */
733 	tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
734 				PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
735 	if (tmp & PORT_CMD_LIST_ON)
736 		return -EIO;
737 
738 	return 0;
739 }
740 EXPORT_SYMBOL_GPL(ahci_stop_engine);
741 
742 void ahci_start_fis_rx(struct ata_port *ap)
743 {
744 	void __iomem *port_mmio = ahci_port_base(ap);
745 	struct ahci_host_priv *hpriv = ap->host->private_data;
746 	struct ahci_port_priv *pp = ap->private_data;
747 	u32 tmp;
748 
749 	/* set FIS registers */
750 	if (hpriv->cap & HOST_CAP_64)
751 		writel((pp->cmd_slot_dma >> 16) >> 16,
752 		       port_mmio + PORT_LST_ADDR_HI);
753 	writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
754 
755 	if (hpriv->cap & HOST_CAP_64)
756 		writel((pp->rx_fis_dma >> 16) >> 16,
757 		       port_mmio + PORT_FIS_ADDR_HI);
758 	writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
759 
760 	/* enable FIS reception */
761 	tmp = readl(port_mmio + PORT_CMD);
762 	tmp |= PORT_CMD_FIS_RX;
763 	writel(tmp, port_mmio + PORT_CMD);
764 
765 	/* flush */
766 	readl(port_mmio + PORT_CMD);
767 }
768 EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
769 
770 static int ahci_stop_fis_rx(struct ata_port *ap)
771 {
772 	void __iomem *port_mmio = ahci_port_base(ap);
773 	u32 tmp;
774 
775 	/* disable FIS reception */
776 	tmp = readl(port_mmio + PORT_CMD);
777 	tmp &= ~PORT_CMD_FIS_RX;
778 	writel(tmp, port_mmio + PORT_CMD);
779 
780 	/* wait for completion, spec says 500ms, give it 1000 */
781 	tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
782 				PORT_CMD_FIS_ON, 10, 1000);
783 	if (tmp & PORT_CMD_FIS_ON)
784 		return -EBUSY;
785 
786 	return 0;
787 }
788 
789 static void ahci_power_up(struct ata_port *ap)
790 {
791 	struct ahci_host_priv *hpriv = ap->host->private_data;
792 	void __iomem *port_mmio = ahci_port_base(ap);
793 	u32 cmd;
794 
795 	cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
796 
797 	/* spin up device */
798 	if (hpriv->cap & HOST_CAP_SSS) {
799 		cmd |= PORT_CMD_SPIN_UP;
800 		writel(cmd, port_mmio + PORT_CMD);
801 	}
802 
803 	/* wake up link */
804 	writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
805 }
806 
807 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
808 			unsigned int hints)
809 {
810 	struct ata_port *ap = link->ap;
811 	struct ahci_host_priv *hpriv = ap->host->private_data;
812 	struct ahci_port_priv *pp = ap->private_data;
813 	void __iomem *port_mmio = ahci_port_base(ap);
814 
815 	if (policy != ATA_LPM_MAX_POWER) {
816 		/* wakeup flag only applies to the max power policy */
817 		hints &= ~ATA_LPM_WAKE_ONLY;
818 
819 		/*
820 		 * Disable interrupts on Phy Ready. This keeps us from
821 		 * getting woken up due to spurious phy ready
822 		 * interrupts.
823 		 */
824 		pp->intr_mask &= ~PORT_IRQ_PHYRDY;
825 		writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
826 
827 		sata_link_scr_lpm(link, policy, false);
828 	}
829 
830 	if (hpriv->cap & HOST_CAP_ALPM) {
831 		u32 cmd = readl(port_mmio + PORT_CMD);
832 
833 		if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
834 			if (!(hints & ATA_LPM_WAKE_ONLY))
835 				cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
836 			cmd |= PORT_CMD_ICC_ACTIVE;
837 
838 			writel(cmd, port_mmio + PORT_CMD);
839 			readl(port_mmio + PORT_CMD);
840 
841 			/* wait 10ms to be sure we've come out of LPM state */
842 			ata_msleep(ap, 10);
843 
844 			if (hints & ATA_LPM_WAKE_ONLY)
845 				return 0;
846 		} else {
847 			cmd |= PORT_CMD_ALPE;
848 			if (policy == ATA_LPM_MIN_POWER)
849 				cmd |= PORT_CMD_ASP;
850 			else if (policy == ATA_LPM_MIN_POWER_WITH_PARTIAL)
851 				cmd &= ~PORT_CMD_ASP;
852 
853 			/* write out new cmd value */
854 			writel(cmd, port_mmio + PORT_CMD);
855 		}
856 	}
857 
858 	/* set aggressive device sleep */
859 	if ((hpriv->cap2 & HOST_CAP2_SDS) &&
860 	    (hpriv->cap2 & HOST_CAP2_SADM) &&
861 	    (link->device->flags & ATA_DFLAG_DEVSLP)) {
862 		if (policy == ATA_LPM_MIN_POWER ||
863 		    policy == ATA_LPM_MIN_POWER_WITH_PARTIAL)
864 			ahci_set_aggressive_devslp(ap, true);
865 		else
866 			ahci_set_aggressive_devslp(ap, false);
867 	}
868 
869 	if (policy == ATA_LPM_MAX_POWER) {
870 		sata_link_scr_lpm(link, policy, false);
871 
872 		/* turn PHYRDY IRQ back on */
873 		pp->intr_mask |= PORT_IRQ_PHYRDY;
874 		writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
875 	}
876 
877 	return 0;
878 }
879 
880 #ifdef CONFIG_PM
881 static void ahci_power_down(struct ata_port *ap)
882 {
883 	struct ahci_host_priv *hpriv = ap->host->private_data;
884 	void __iomem *port_mmio = ahci_port_base(ap);
885 	u32 cmd, scontrol;
886 
887 	if (!(hpriv->cap & HOST_CAP_SSS))
888 		return;
889 
890 	/* put device into listen mode, first set PxSCTL.DET to 0 */
891 	scontrol = readl(port_mmio + PORT_SCR_CTL);
892 	scontrol &= ~0xf;
893 	writel(scontrol, port_mmio + PORT_SCR_CTL);
894 
895 	/* then set PxCMD.SUD to 0 */
896 	cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
897 	cmd &= ~PORT_CMD_SPIN_UP;
898 	writel(cmd, port_mmio + PORT_CMD);
899 }
900 #endif
901 
902 static void ahci_start_port(struct ata_port *ap)
903 {
904 	struct ahci_host_priv *hpriv = ap->host->private_data;
905 	struct ahci_port_priv *pp = ap->private_data;
906 	struct ata_link *link;
907 	struct ahci_em_priv *emp;
908 	ssize_t rc;
909 	int i;
910 
911 	/* enable FIS reception */
912 	ahci_start_fis_rx(ap);
913 
914 	/* enable DMA */
915 	if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
916 		hpriv->start_engine(ap);
917 
918 	/* turn on LEDs */
919 	if (ap->flags & ATA_FLAG_EM) {
920 		ata_for_each_link(link, ap, EDGE) {
921 			emp = &pp->em_priv[link->pmp];
922 
923 			/* EM Transmit bit maybe busy during init */
924 			for (i = 0; i < EM_MAX_RETRY; i++) {
925 				rc = ap->ops->transmit_led_message(ap,
926 							       emp->led_state,
927 							       4);
928 				/*
929 				 * If busy, give a breather but do not
930 				 * release EH ownership by using msleep()
931 				 * instead of ata_msleep().  EM Transmit
932 				 * bit is busy for the whole host and
933 				 * releasing ownership will cause other
934 				 * ports to fail the same way.
935 				 */
936 				if (rc == -EBUSY)
937 					msleep(1);
938 				else
939 					break;
940 			}
941 		}
942 	}
943 
944 	if (ap->flags & ATA_FLAG_SW_ACTIVITY)
945 		ata_for_each_link(link, ap, EDGE)
946 			ahci_init_sw_activity(link);
947 
948 }
949 
950 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
951 {
952 	int rc;
953 	struct ahci_host_priv *hpriv = ap->host->private_data;
954 
955 	/* disable DMA */
956 	rc = hpriv->stop_engine(ap);
957 	if (rc) {
958 		*emsg = "failed to stop engine";
959 		return rc;
960 	}
961 
962 	/* disable FIS reception */
963 	rc = ahci_stop_fis_rx(ap);
964 	if (rc) {
965 		*emsg = "failed stop FIS RX";
966 		return rc;
967 	}
968 
969 	return 0;
970 }
971 
972 int ahci_reset_controller(struct ata_host *host)
973 {
974 	struct ahci_host_priv *hpriv = host->private_data;
975 	void __iomem *mmio = hpriv->mmio;
976 	u32 tmp;
977 
978 	/*
979 	 * We must be in AHCI mode, before using anything AHCI-specific, such
980 	 * as HOST_RESET.
981 	 */
982 	ahci_enable_ahci(mmio);
983 
984 	/* Global controller reset */
985 	if (ahci_skip_host_reset) {
986 		dev_info(host->dev, "Skipping global host reset\n");
987 		return 0;
988 	}
989 
990 	tmp = readl(mmio + HOST_CTL);
991 	if (!(tmp & HOST_RESET)) {
992 		writel(tmp | HOST_RESET, mmio + HOST_CTL);
993 		readl(mmio + HOST_CTL); /* flush */
994 	}
995 
996 	/*
997 	 * To perform host reset, OS should set HOST_RESET and poll until this
998 	 * bit is read to be "0". Reset must complete within 1 second, or the
999 	 * hardware should be considered fried.
1000 	 */
1001 	tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
1002 				HOST_RESET, 10, 1000);
1003 	if (tmp & HOST_RESET) {
1004 		dev_err(host->dev, "Controller reset failed (0x%x)\n",
1005 			tmp);
1006 		return -EIO;
1007 	}
1008 
1009 	/* Turn on AHCI mode */
1010 	ahci_enable_ahci(mmio);
1011 
1012 	/* Some registers might be cleared on reset. Restore initial values. */
1013 	if (!(hpriv->flags & AHCI_HFLAG_NO_WRITE_TO_RO))
1014 		ahci_restore_initial_config(host);
1015 
1016 	return 0;
1017 }
1018 EXPORT_SYMBOL_GPL(ahci_reset_controller);
1019 
1020 static void ahci_sw_activity(struct ata_link *link)
1021 {
1022 	struct ata_port *ap = link->ap;
1023 	struct ahci_port_priv *pp = ap->private_data;
1024 	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1025 
1026 	if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
1027 		return;
1028 
1029 	emp->activity++;
1030 	if (!timer_pending(&emp->timer))
1031 		mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
1032 }
1033 
1034 static void ahci_sw_activity_blink(struct timer_list *t)
1035 {
1036 	struct ahci_em_priv *emp = from_timer(emp, t, timer);
1037 	struct ata_link *link = emp->link;
1038 	struct ata_port *ap = link->ap;
1039 
1040 	unsigned long led_message = emp->led_state;
1041 	u32 activity_led_state;
1042 	unsigned long flags;
1043 
1044 	led_message &= EM_MSG_LED_VALUE;
1045 	led_message |= ap->port_no | (link->pmp << 8);
1046 
1047 	/* check to see if we've had activity.  If so,
1048 	 * toggle state of LED and reset timer.  If not,
1049 	 * turn LED to desired idle state.
1050 	 */
1051 	spin_lock_irqsave(ap->lock, flags);
1052 	if (emp->saved_activity != emp->activity) {
1053 		emp->saved_activity = emp->activity;
1054 		/* get the current LED state */
1055 		activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
1056 
1057 		if (activity_led_state)
1058 			activity_led_state = 0;
1059 		else
1060 			activity_led_state = 1;
1061 
1062 		/* clear old state */
1063 		led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1064 
1065 		/* toggle state */
1066 		led_message |= (activity_led_state << 16);
1067 		mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1068 	} else {
1069 		/* switch to idle */
1070 		led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1071 		if (emp->blink_policy == BLINK_OFF)
1072 			led_message |= (1 << 16);
1073 	}
1074 	spin_unlock_irqrestore(ap->lock, flags);
1075 	ap->ops->transmit_led_message(ap, led_message, 4);
1076 }
1077 
1078 static void ahci_init_sw_activity(struct ata_link *link)
1079 {
1080 	struct ata_port *ap = link->ap;
1081 	struct ahci_port_priv *pp = ap->private_data;
1082 	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1083 
1084 	/* init activity stats, setup timer */
1085 	emp->saved_activity = emp->activity = 0;
1086 	emp->link = link;
1087 	timer_setup(&emp->timer, ahci_sw_activity_blink, 0);
1088 
1089 	/* check our blink policy and set flag for link if it's enabled */
1090 	if (emp->blink_policy)
1091 		link->flags |= ATA_LFLAG_SW_ACTIVITY;
1092 }
1093 
1094 int ahci_reset_em(struct ata_host *host)
1095 {
1096 	struct ahci_host_priv *hpriv = host->private_data;
1097 	void __iomem *mmio = hpriv->mmio;
1098 	u32 em_ctl;
1099 
1100 	em_ctl = readl(mmio + HOST_EM_CTL);
1101 	if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1102 		return -EINVAL;
1103 
1104 	writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1105 	return 0;
1106 }
1107 EXPORT_SYMBOL_GPL(ahci_reset_em);
1108 
1109 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1110 					ssize_t size)
1111 {
1112 	struct ahci_host_priv *hpriv = ap->host->private_data;
1113 	struct ahci_port_priv *pp = ap->private_data;
1114 	void __iomem *mmio = hpriv->mmio;
1115 	u32 em_ctl;
1116 	u32 message[] = {0, 0};
1117 	unsigned long flags;
1118 	int pmp;
1119 	struct ahci_em_priv *emp;
1120 
1121 	/* get the slot number from the message */
1122 	pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1123 	if (pmp < EM_MAX_SLOTS)
1124 		emp = &pp->em_priv[pmp];
1125 	else
1126 		return -EINVAL;
1127 
1128 	ahci_rpm_get_port(ap);
1129 	spin_lock_irqsave(ap->lock, flags);
1130 
1131 	/*
1132 	 * if we are still busy transmitting a previous message,
1133 	 * do not allow
1134 	 */
1135 	em_ctl = readl(mmio + HOST_EM_CTL);
1136 	if (em_ctl & EM_CTL_TM) {
1137 		spin_unlock_irqrestore(ap->lock, flags);
1138 		ahci_rpm_put_port(ap);
1139 		return -EBUSY;
1140 	}
1141 
1142 	if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1143 		/*
1144 		 * create message header - this is all zero except for
1145 		 * the message size, which is 4 bytes.
1146 		 */
1147 		message[0] |= (4 << 8);
1148 
1149 		/* ignore 0:4 of byte zero, fill in port info yourself */
1150 		message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1151 
1152 		/* write message to EM_LOC */
1153 		writel(message[0], mmio + hpriv->em_loc);
1154 		writel(message[1], mmio + hpriv->em_loc+4);
1155 
1156 		/*
1157 		 * tell hardware to transmit the message
1158 		 */
1159 		writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1160 	}
1161 
1162 	/* save off new led state for port/slot */
1163 	emp->led_state = state;
1164 
1165 	spin_unlock_irqrestore(ap->lock, flags);
1166 	ahci_rpm_put_port(ap);
1167 
1168 	return size;
1169 }
1170 
1171 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1172 {
1173 	struct ahci_port_priv *pp = ap->private_data;
1174 	struct ata_link *link;
1175 	struct ahci_em_priv *emp;
1176 	int rc = 0;
1177 
1178 	ata_for_each_link(link, ap, EDGE) {
1179 		emp = &pp->em_priv[link->pmp];
1180 		rc += sprintf(buf, "%lx\n", emp->led_state);
1181 	}
1182 	return rc;
1183 }
1184 
1185 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1186 				size_t size)
1187 {
1188 	unsigned int state;
1189 	int pmp;
1190 	struct ahci_port_priv *pp = ap->private_data;
1191 	struct ahci_em_priv *emp;
1192 
1193 	if (kstrtouint(buf, 0, &state) < 0)
1194 		return -EINVAL;
1195 
1196 	/* get the slot number from the message */
1197 	pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1198 	if (pmp < EM_MAX_SLOTS) {
1199 		pmp = array_index_nospec(pmp, EM_MAX_SLOTS);
1200 		emp = &pp->em_priv[pmp];
1201 	} else {
1202 		return -EINVAL;
1203 	}
1204 
1205 	/* mask off the activity bits if we are in sw_activity
1206 	 * mode, user should turn off sw_activity before setting
1207 	 * activity led through em_message
1208 	 */
1209 	if (emp->blink_policy)
1210 		state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1211 
1212 	return ap->ops->transmit_led_message(ap, state, size);
1213 }
1214 
1215 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1216 {
1217 	struct ata_link *link = dev->link;
1218 	struct ata_port *ap = link->ap;
1219 	struct ahci_port_priv *pp = ap->private_data;
1220 	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1221 	u32 port_led_state = emp->led_state;
1222 
1223 	/* save the desired Activity LED behavior */
1224 	if (val == OFF) {
1225 		/* clear LFLAG */
1226 		link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1227 
1228 		/* set the LED to OFF */
1229 		port_led_state &= EM_MSG_LED_VALUE_OFF;
1230 		port_led_state |= (ap->port_no | (link->pmp << 8));
1231 		ap->ops->transmit_led_message(ap, port_led_state, 4);
1232 	} else {
1233 		link->flags |= ATA_LFLAG_SW_ACTIVITY;
1234 		if (val == BLINK_OFF) {
1235 			/* set LED to ON for idle */
1236 			port_led_state &= EM_MSG_LED_VALUE_OFF;
1237 			port_led_state |= (ap->port_no | (link->pmp << 8));
1238 			port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1239 			ap->ops->transmit_led_message(ap, port_led_state, 4);
1240 		}
1241 	}
1242 	emp->blink_policy = val;
1243 	return 0;
1244 }
1245 
1246 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1247 {
1248 	struct ata_link *link = dev->link;
1249 	struct ata_port *ap = link->ap;
1250 	struct ahci_port_priv *pp = ap->private_data;
1251 	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1252 
1253 	/* display the saved value of activity behavior for this
1254 	 * disk.
1255 	 */
1256 	return sprintf(buf, "%d\n", emp->blink_policy);
1257 }
1258 
1259 static void ahci_port_clear_pending_irq(struct ata_port *ap)
1260 {
1261 	struct ahci_host_priv *hpriv = ap->host->private_data;
1262 	void __iomem *port_mmio = ahci_port_base(ap);
1263 	u32 tmp;
1264 
1265 	/* clear SError */
1266 	tmp = readl(port_mmio + PORT_SCR_ERR);
1267 	dev_dbg(ap->host->dev, "PORT_SCR_ERR 0x%x\n", tmp);
1268 	writel(tmp, port_mmio + PORT_SCR_ERR);
1269 
1270 	/* clear port IRQ */
1271 	tmp = readl(port_mmio + PORT_IRQ_STAT);
1272 	dev_dbg(ap->host->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
1273 	if (tmp)
1274 		writel(tmp, port_mmio + PORT_IRQ_STAT);
1275 
1276 	writel(1 << ap->port_no, hpriv->mmio + HOST_IRQ_STAT);
1277 }
1278 
1279 static void ahci_port_init(struct device *dev, struct ata_port *ap,
1280 			   int port_no, void __iomem *mmio,
1281 			   void __iomem *port_mmio)
1282 {
1283 	struct ahci_host_priv *hpriv = ap->host->private_data;
1284 	const char *emsg = NULL;
1285 	int rc;
1286 	u32 tmp;
1287 
1288 	/* make sure port is not active */
1289 	rc = ahci_deinit_port(ap, &emsg);
1290 	if (rc)
1291 		dev_warn(dev, "%s (%d)\n", emsg, rc);
1292 
1293 	ahci_port_clear_pending_irq(ap);
1294 
1295 	/* mark esata ports */
1296 	tmp = readl(port_mmio + PORT_CMD);
1297 	if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS))
1298 		ap->pflags |= ATA_PFLAG_EXTERNAL;
1299 }
1300 
1301 void ahci_init_controller(struct ata_host *host)
1302 {
1303 	struct ahci_host_priv *hpriv = host->private_data;
1304 	void __iomem *mmio = hpriv->mmio;
1305 	int i;
1306 	void __iomem *port_mmio;
1307 	u32 tmp;
1308 
1309 	for (i = 0; i < host->n_ports; i++) {
1310 		struct ata_port *ap = host->ports[i];
1311 
1312 		port_mmio = ahci_port_base(ap);
1313 		if (ata_port_is_dummy(ap))
1314 			continue;
1315 
1316 		ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1317 	}
1318 
1319 	tmp = readl(mmio + HOST_CTL);
1320 	dev_dbg(host->dev, "HOST_CTL 0x%x\n", tmp);
1321 	writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1322 	tmp = readl(mmio + HOST_CTL);
1323 	dev_dbg(host->dev, "HOST_CTL 0x%x\n", tmp);
1324 }
1325 EXPORT_SYMBOL_GPL(ahci_init_controller);
1326 
1327 static void ahci_dev_config(struct ata_device *dev)
1328 {
1329 	struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1330 
1331 	if (hpriv->flags & AHCI_HFLAG_SECT255) {
1332 		dev->max_sectors = 255;
1333 		ata_dev_info(dev,
1334 			     "SB600 AHCI: limiting to 255 sectors per cmd\n");
1335 	}
1336 }
1337 
1338 unsigned int ahci_dev_classify(struct ata_port *ap)
1339 {
1340 	void __iomem *port_mmio = ahci_port_base(ap);
1341 	struct ata_taskfile tf;
1342 	u32 tmp;
1343 
1344 	tmp = readl(port_mmio + PORT_SIG);
1345 	tf.lbah		= (tmp >> 24)	& 0xff;
1346 	tf.lbam		= (tmp >> 16)	& 0xff;
1347 	tf.lbal		= (tmp >> 8)	& 0xff;
1348 	tf.nsect	= (tmp)		& 0xff;
1349 
1350 	return ata_port_classify(ap, &tf);
1351 }
1352 EXPORT_SYMBOL_GPL(ahci_dev_classify);
1353 
1354 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1355 			u32 opts)
1356 {
1357 	dma_addr_t cmd_tbl_dma;
1358 
1359 	cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1360 
1361 	pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1362 	pp->cmd_slot[tag].status = 0;
1363 	pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1364 	pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1365 }
1366 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
1367 
1368 int ahci_kick_engine(struct ata_port *ap)
1369 {
1370 	void __iomem *port_mmio = ahci_port_base(ap);
1371 	struct ahci_host_priv *hpriv = ap->host->private_data;
1372 	u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1373 	u32 tmp;
1374 	int busy, rc;
1375 
1376 	/* stop engine */
1377 	rc = hpriv->stop_engine(ap);
1378 	if (rc)
1379 		goto out_restart;
1380 
1381 	/* need to do CLO?
1382 	 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1383 	 */
1384 	busy = status & (ATA_BUSY | ATA_DRQ);
1385 	if (!busy && !sata_pmp_attached(ap)) {
1386 		rc = 0;
1387 		goto out_restart;
1388 	}
1389 
1390 	if (!(hpriv->cap & HOST_CAP_CLO)) {
1391 		rc = -EOPNOTSUPP;
1392 		goto out_restart;
1393 	}
1394 
1395 	/* perform CLO */
1396 	tmp = readl(port_mmio + PORT_CMD);
1397 	tmp |= PORT_CMD_CLO;
1398 	writel(tmp, port_mmio + PORT_CMD);
1399 
1400 	rc = 0;
1401 	tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1402 				PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1403 	if (tmp & PORT_CMD_CLO)
1404 		rc = -EIO;
1405 
1406 	/* restart engine */
1407  out_restart:
1408 	hpriv->start_engine(ap);
1409 	return rc;
1410 }
1411 EXPORT_SYMBOL_GPL(ahci_kick_engine);
1412 
1413 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1414 				struct ata_taskfile *tf, int is_cmd, u16 flags,
1415 				unsigned int timeout_msec)
1416 {
1417 	const u32 cmd_fis_len = 5; /* five dwords */
1418 	struct ahci_port_priv *pp = ap->private_data;
1419 	void __iomem *port_mmio = ahci_port_base(ap);
1420 	u8 *fis = pp->cmd_tbl;
1421 	u32 tmp;
1422 
1423 	/* prep the command */
1424 	ata_tf_to_fis(tf, pmp, is_cmd, fis);
1425 	ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1426 
1427 	/* set port value for softreset of Port Multiplier */
1428 	if (pp->fbs_enabled && pp->fbs_last_dev != pmp) {
1429 		tmp = readl(port_mmio + PORT_FBS);
1430 		tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1431 		tmp |= pmp << PORT_FBS_DEV_OFFSET;
1432 		writel(tmp, port_mmio + PORT_FBS);
1433 		pp->fbs_last_dev = pmp;
1434 	}
1435 
1436 	/* issue & wait */
1437 	writel(1, port_mmio + PORT_CMD_ISSUE);
1438 
1439 	if (timeout_msec) {
1440 		tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1441 					0x1, 0x1, 1, timeout_msec);
1442 		if (tmp & 0x1) {
1443 			ahci_kick_engine(ap);
1444 			return -EBUSY;
1445 		}
1446 	} else
1447 		readl(port_mmio + PORT_CMD_ISSUE);	/* flush */
1448 
1449 	return 0;
1450 }
1451 
1452 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1453 		      int pmp, unsigned long deadline,
1454 		      int (*check_ready)(struct ata_link *link))
1455 {
1456 	struct ata_port *ap = link->ap;
1457 	struct ahci_host_priv *hpriv = ap->host->private_data;
1458 	struct ahci_port_priv *pp = ap->private_data;
1459 	const char *reason = NULL;
1460 	unsigned long now;
1461 	unsigned int msecs;
1462 	struct ata_taskfile tf;
1463 	bool fbs_disabled = false;
1464 	int rc;
1465 
1466 	/* prepare for SRST (AHCI-1.1 10.4.1) */
1467 	rc = ahci_kick_engine(ap);
1468 	if (rc && rc != -EOPNOTSUPP)
1469 		ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
1470 
1471 	/*
1472 	 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1473 	 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1474 	 * that is attached to port multiplier.
1475 	 */
1476 	if (!ata_is_host_link(link) && pp->fbs_enabled) {
1477 		ahci_disable_fbs(ap);
1478 		fbs_disabled = true;
1479 	}
1480 
1481 	ata_tf_init(link->device, &tf);
1482 
1483 	/* issue the first H2D Register FIS */
1484 	msecs = 0;
1485 	now = jiffies;
1486 	if (time_after(deadline, now))
1487 		msecs = jiffies_to_msecs(deadline - now);
1488 
1489 	tf.ctl |= ATA_SRST;
1490 	if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1491 				 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1492 		rc = -EIO;
1493 		reason = "1st FIS failed";
1494 		goto fail;
1495 	}
1496 
1497 	/* spec says at least 5us, but be generous and sleep for 1ms */
1498 	ata_msleep(ap, 1);
1499 
1500 	/* issue the second H2D Register FIS */
1501 	tf.ctl &= ~ATA_SRST;
1502 	ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1503 
1504 	/* wait for link to become ready */
1505 	rc = ata_wait_after_reset(link, deadline, check_ready);
1506 	if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1507 		/*
1508 		 * Workaround for cases where link online status can't
1509 		 * be trusted.  Treat device readiness timeout as link
1510 		 * offline.
1511 		 */
1512 		ata_link_info(link, "device not ready, treating as offline\n");
1513 		*class = ATA_DEV_NONE;
1514 	} else if (rc) {
1515 		/* link occupied, -ENODEV too is an error */
1516 		reason = "device not ready";
1517 		goto fail;
1518 	} else
1519 		*class = ahci_dev_classify(ap);
1520 
1521 	/* re-enable FBS if disabled before */
1522 	if (fbs_disabled)
1523 		ahci_enable_fbs(ap);
1524 
1525 	return 0;
1526 
1527  fail:
1528 	ata_link_err(link, "softreset failed (%s)\n", reason);
1529 	return rc;
1530 }
1531 
1532 int ahci_check_ready(struct ata_link *link)
1533 {
1534 	void __iomem *port_mmio = ahci_port_base(link->ap);
1535 	u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1536 
1537 	return ata_check_ready(status);
1538 }
1539 EXPORT_SYMBOL_GPL(ahci_check_ready);
1540 
1541 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1542 			  unsigned long deadline)
1543 {
1544 	int pmp = sata_srst_pmp(link);
1545 
1546 	return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1547 }
1548 EXPORT_SYMBOL_GPL(ahci_do_softreset);
1549 
1550 static int ahci_bad_pmp_check_ready(struct ata_link *link)
1551 {
1552 	void __iomem *port_mmio = ahci_port_base(link->ap);
1553 	u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1554 	u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1555 
1556 	/*
1557 	 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1558 	 * which can save timeout delay.
1559 	 */
1560 	if (irq_status & PORT_IRQ_BAD_PMP)
1561 		return -EIO;
1562 
1563 	return ata_check_ready(status);
1564 }
1565 
1566 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1567 				    unsigned long deadline)
1568 {
1569 	struct ata_port *ap = link->ap;
1570 	void __iomem *port_mmio = ahci_port_base(ap);
1571 	int pmp = sata_srst_pmp(link);
1572 	int rc;
1573 	u32 irq_sts;
1574 
1575 	rc = ahci_do_softreset(link, class, pmp, deadline,
1576 			       ahci_bad_pmp_check_ready);
1577 
1578 	/*
1579 	 * Soft reset fails with IPMS set when PMP is enabled but
1580 	 * SATA HDD/ODD is connected to SATA port, do soft reset
1581 	 * again to port 0.
1582 	 */
1583 	if (rc == -EIO) {
1584 		irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1585 		if (irq_sts & PORT_IRQ_BAD_PMP) {
1586 			ata_link_warn(link,
1587 					"applying PMP SRST workaround "
1588 					"and retrying\n");
1589 			rc = ahci_do_softreset(link, class, 0, deadline,
1590 					       ahci_check_ready);
1591 		}
1592 	}
1593 
1594 	return rc;
1595 }
1596 
1597 int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
1598 		      unsigned long deadline, bool *online)
1599 {
1600 	const unsigned int *timing = sata_ehc_deb_timing(&link->eh_context);
1601 	struct ata_port *ap = link->ap;
1602 	struct ahci_port_priv *pp = ap->private_data;
1603 	struct ahci_host_priv *hpriv = ap->host->private_data;
1604 	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1605 	struct ata_taskfile tf;
1606 	int rc;
1607 
1608 	hpriv->stop_engine(ap);
1609 
1610 	/* clear D2H reception area to properly wait for D2H FIS */
1611 	ata_tf_init(link->device, &tf);
1612 	tf.status = ATA_BUSY;
1613 	ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1614 
1615 	ahci_port_clear_pending_irq(ap);
1616 
1617 	rc = sata_link_hardreset(link, timing, deadline, online,
1618 				 ahci_check_ready);
1619 
1620 	hpriv->start_engine(ap);
1621 
1622 	if (*online)
1623 		*class = ahci_dev_classify(ap);
1624 
1625 	return rc;
1626 }
1627 EXPORT_SYMBOL_GPL(ahci_do_hardreset);
1628 
1629 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1630 			  unsigned long deadline)
1631 {
1632 	bool online;
1633 
1634 	return ahci_do_hardreset(link, class, deadline, &online);
1635 }
1636 
1637 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1638 {
1639 	struct ata_port *ap = link->ap;
1640 	void __iomem *port_mmio = ahci_port_base(ap);
1641 	u32 new_tmp, tmp;
1642 
1643 	ata_std_postreset(link, class);
1644 
1645 	/* Make sure port's ATAPI bit is set appropriately */
1646 	new_tmp = tmp = readl(port_mmio + PORT_CMD);
1647 	if (*class == ATA_DEV_ATAPI)
1648 		new_tmp |= PORT_CMD_ATAPI;
1649 	else
1650 		new_tmp &= ~PORT_CMD_ATAPI;
1651 	if (new_tmp != tmp) {
1652 		writel(new_tmp, port_mmio + PORT_CMD);
1653 		readl(port_mmio + PORT_CMD); /* flush */
1654 	}
1655 }
1656 
1657 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1658 {
1659 	struct scatterlist *sg;
1660 	struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1661 	unsigned int si;
1662 
1663 	/*
1664 	 * Next, the S/G list.
1665 	 */
1666 	for_each_sg(qc->sg, sg, qc->n_elem, si) {
1667 		dma_addr_t addr = sg_dma_address(sg);
1668 		u32 sg_len = sg_dma_len(sg);
1669 
1670 		ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1671 		ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1672 		ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1673 	}
1674 
1675 	return si;
1676 }
1677 
1678 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1679 {
1680 	struct ata_port *ap = qc->ap;
1681 	struct ahci_port_priv *pp = ap->private_data;
1682 
1683 	if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1684 		return ata_std_qc_defer(qc);
1685 	else
1686 		return sata_pmp_qc_defer_cmd_switch(qc);
1687 }
1688 
1689 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc)
1690 {
1691 	struct ata_port *ap = qc->ap;
1692 	struct ahci_port_priv *pp = ap->private_data;
1693 	int is_atapi = ata_is_atapi(qc->tf.protocol);
1694 	void *cmd_tbl;
1695 	u32 opts;
1696 	const u32 cmd_fis_len = 5; /* five dwords */
1697 	unsigned int n_elem;
1698 
1699 	/*
1700 	 * Fill in command table information.  First, the header,
1701 	 * a SATA Register - Host to Device command FIS.
1702 	 */
1703 	cmd_tbl = pp->cmd_tbl + qc->hw_tag * AHCI_CMD_TBL_SZ;
1704 
1705 	ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1706 	if (is_atapi) {
1707 		memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1708 		memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1709 	}
1710 
1711 	n_elem = 0;
1712 	if (qc->flags & ATA_QCFLAG_DMAMAP)
1713 		n_elem = ahci_fill_sg(qc, cmd_tbl);
1714 
1715 	/*
1716 	 * Fill in command slot information.
1717 	 */
1718 	opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1719 	if (qc->tf.flags & ATA_TFLAG_WRITE)
1720 		opts |= AHCI_CMD_WRITE;
1721 	if (is_atapi)
1722 		opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1723 
1724 	ahci_fill_cmd_slot(pp, qc->hw_tag, opts);
1725 
1726 	return AC_ERR_OK;
1727 }
1728 
1729 static void ahci_fbs_dec_intr(struct ata_port *ap)
1730 {
1731 	struct ahci_port_priv *pp = ap->private_data;
1732 	void __iomem *port_mmio = ahci_port_base(ap);
1733 	u32 fbs = readl(port_mmio + PORT_FBS);
1734 	int retries = 3;
1735 
1736 	BUG_ON(!pp->fbs_enabled);
1737 
1738 	/* time to wait for DEC is not specified by AHCI spec,
1739 	 * add a retry loop for safety.
1740 	 */
1741 	writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1742 	fbs = readl(port_mmio + PORT_FBS);
1743 	while ((fbs & PORT_FBS_DEC) && retries--) {
1744 		udelay(1);
1745 		fbs = readl(port_mmio + PORT_FBS);
1746 	}
1747 
1748 	if (fbs & PORT_FBS_DEC)
1749 		dev_err(ap->host->dev, "failed to clear device error\n");
1750 }
1751 
1752 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1753 {
1754 	struct ahci_host_priv *hpriv = ap->host->private_data;
1755 	struct ahci_port_priv *pp = ap->private_data;
1756 	struct ata_eh_info *host_ehi = &ap->link.eh_info;
1757 	struct ata_link *link = NULL;
1758 	struct ata_queued_cmd *active_qc;
1759 	struct ata_eh_info *active_ehi;
1760 	bool fbs_need_dec = false;
1761 	u32 serror;
1762 
1763 	/* determine active link with error */
1764 	if (pp->fbs_enabled) {
1765 		void __iomem *port_mmio = ahci_port_base(ap);
1766 		u32 fbs = readl(port_mmio + PORT_FBS);
1767 		int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1768 
1769 		if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
1770 			link = &ap->pmp_link[pmp];
1771 			fbs_need_dec = true;
1772 		}
1773 
1774 	} else
1775 		ata_for_each_link(link, ap, EDGE)
1776 			if (ata_link_active(link))
1777 				break;
1778 
1779 	if (!link)
1780 		link = &ap->link;
1781 
1782 	active_qc = ata_qc_from_tag(ap, link->active_tag);
1783 	active_ehi = &link->eh_info;
1784 
1785 	/* record irq stat */
1786 	ata_ehi_clear_desc(host_ehi);
1787 	ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1788 
1789 	/* AHCI needs SError cleared; otherwise, it might lock up */
1790 	ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1791 	ahci_scr_write(&ap->link, SCR_ERROR, serror);
1792 	host_ehi->serror |= serror;
1793 
1794 	/* some controllers set IRQ_IF_ERR on device errors, ignore it */
1795 	if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1796 		irq_stat &= ~PORT_IRQ_IF_ERR;
1797 
1798 	if (irq_stat & PORT_IRQ_TF_ERR) {
1799 		/* If qc is active, charge it; otherwise, the active
1800 		 * link.  There's no active qc on NCQ errors.  It will
1801 		 * be determined by EH by reading log page 10h.
1802 		 */
1803 		if (active_qc)
1804 			active_qc->err_mask |= AC_ERR_DEV;
1805 		else
1806 			active_ehi->err_mask |= AC_ERR_DEV;
1807 
1808 		if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1809 			host_ehi->serror &= ~SERR_INTERNAL;
1810 	}
1811 
1812 	if (irq_stat & PORT_IRQ_UNK_FIS) {
1813 		u32 *unk = pp->rx_fis + RX_FIS_UNK;
1814 
1815 		active_ehi->err_mask |= AC_ERR_HSM;
1816 		active_ehi->action |= ATA_EH_RESET;
1817 		ata_ehi_push_desc(active_ehi,
1818 				  "unknown FIS %08x %08x %08x %08x" ,
1819 				  unk[0], unk[1], unk[2], unk[3]);
1820 	}
1821 
1822 	if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1823 		active_ehi->err_mask |= AC_ERR_HSM;
1824 		active_ehi->action |= ATA_EH_RESET;
1825 		ata_ehi_push_desc(active_ehi, "incorrect PMP");
1826 	}
1827 
1828 	if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1829 		host_ehi->err_mask |= AC_ERR_HOST_BUS;
1830 		host_ehi->action |= ATA_EH_RESET;
1831 		ata_ehi_push_desc(host_ehi, "host bus error");
1832 	}
1833 
1834 	if (irq_stat & PORT_IRQ_IF_ERR) {
1835 		if (fbs_need_dec)
1836 			active_ehi->err_mask |= AC_ERR_DEV;
1837 		else {
1838 			host_ehi->err_mask |= AC_ERR_ATA_BUS;
1839 			host_ehi->action |= ATA_EH_RESET;
1840 		}
1841 
1842 		ata_ehi_push_desc(host_ehi, "interface fatal error");
1843 	}
1844 
1845 	if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1846 		ata_ehi_hotplugged(host_ehi);
1847 		ata_ehi_push_desc(host_ehi, "%s",
1848 			irq_stat & PORT_IRQ_CONNECT ?
1849 			"connection status changed" : "PHY RDY changed");
1850 	}
1851 
1852 	/* okay, let's hand over to EH */
1853 
1854 	if (irq_stat & PORT_IRQ_FREEZE)
1855 		ata_port_freeze(ap);
1856 	else if (fbs_need_dec) {
1857 		ata_link_abort(link);
1858 		ahci_fbs_dec_intr(ap);
1859 	} else
1860 		ata_port_abort(ap);
1861 }
1862 
1863 static void ahci_qc_complete(struct ata_port *ap, void __iomem *port_mmio)
1864 {
1865 	struct ata_eh_info *ehi = &ap->link.eh_info;
1866 	struct ahci_port_priv *pp = ap->private_data;
1867 	u32 qc_active = 0;
1868 	int rc;
1869 
1870 	/*
1871 	 * pp->active_link is not reliable once FBS is enabled, both
1872 	 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1873 	 * NCQ and non-NCQ commands may be in flight at the same time.
1874 	 */
1875 	if (pp->fbs_enabled) {
1876 		if (ap->qc_active) {
1877 			qc_active = readl(port_mmio + PORT_SCR_ACT);
1878 			qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1879 		}
1880 	} else {
1881 		/* pp->active_link is valid iff any command is in flight */
1882 		if (ap->qc_active && pp->active_link->sactive)
1883 			qc_active = readl(port_mmio + PORT_SCR_ACT);
1884 		else
1885 			qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1886 	}
1887 
1888 	rc = ata_qc_complete_multiple(ap, qc_active);
1889 	if (unlikely(rc < 0 && !(ap->pflags & ATA_PFLAG_RESETTING))) {
1890 		ehi->err_mask |= AC_ERR_HSM;
1891 		ehi->action |= ATA_EH_RESET;
1892 		ata_port_freeze(ap);
1893 	}
1894 }
1895 
1896 static void ahci_handle_port_interrupt(struct ata_port *ap,
1897 				       void __iomem *port_mmio, u32 status)
1898 {
1899 	struct ahci_port_priv *pp = ap->private_data;
1900 	struct ahci_host_priv *hpriv = ap->host->private_data;
1901 
1902 	/* ignore BAD_PMP while resetting */
1903 	if (unlikely(ap->pflags & ATA_PFLAG_RESETTING))
1904 		status &= ~PORT_IRQ_BAD_PMP;
1905 
1906 	if (sata_lpm_ignore_phy_events(&ap->link)) {
1907 		status &= ~PORT_IRQ_PHYRDY;
1908 		ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
1909 	}
1910 
1911 	if (unlikely(status & PORT_IRQ_ERROR)) {
1912 		/*
1913 		 * Before getting the error notification, we may have
1914 		 * received SDB FISes notifying successful completions.
1915 		 * Handle these first and then handle the error.
1916 		 */
1917 		ahci_qc_complete(ap, port_mmio);
1918 		ahci_error_intr(ap, status);
1919 		return;
1920 	}
1921 
1922 	if (status & PORT_IRQ_SDB_FIS) {
1923 		/* If SNotification is available, leave notification
1924 		 * handling to sata_async_notification().  If not,
1925 		 * emulate it by snooping SDB FIS RX area.
1926 		 *
1927 		 * Snooping FIS RX area is probably cheaper than
1928 		 * poking SNotification but some constrollers which
1929 		 * implement SNotification, ICH9 for example, don't
1930 		 * store AN SDB FIS into receive area.
1931 		 */
1932 		if (hpriv->cap & HOST_CAP_SNTF)
1933 			sata_async_notification(ap);
1934 		else {
1935 			/* If the 'N' bit in word 0 of the FIS is set,
1936 			 * we just received asynchronous notification.
1937 			 * Tell libata about it.
1938 			 *
1939 			 * Lack of SNotification should not appear in
1940 			 * ahci 1.2, so the workaround is unnecessary
1941 			 * when FBS is enabled.
1942 			 */
1943 			if (pp->fbs_enabled)
1944 				WARN_ON_ONCE(1);
1945 			else {
1946 				const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1947 				u32 f0 = le32_to_cpu(f[0]);
1948 				if (f0 & (1 << 15))
1949 					sata_async_notification(ap);
1950 			}
1951 		}
1952 	}
1953 
1954 	/* Handle completed commands */
1955 	ahci_qc_complete(ap, port_mmio);
1956 }
1957 
1958 static void ahci_port_intr(struct ata_port *ap)
1959 {
1960 	void __iomem *port_mmio = ahci_port_base(ap);
1961 	u32 status;
1962 
1963 	status = readl(port_mmio + PORT_IRQ_STAT);
1964 	writel(status, port_mmio + PORT_IRQ_STAT);
1965 
1966 	ahci_handle_port_interrupt(ap, port_mmio, status);
1967 }
1968 
1969 static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
1970 {
1971 	struct ata_port *ap = dev_instance;
1972 	void __iomem *port_mmio = ahci_port_base(ap);
1973 	u32 status;
1974 
1975 	status = readl(port_mmio + PORT_IRQ_STAT);
1976 	writel(status, port_mmio + PORT_IRQ_STAT);
1977 
1978 	spin_lock(ap->lock);
1979 	ahci_handle_port_interrupt(ap, port_mmio, status);
1980 	spin_unlock(ap->lock);
1981 
1982 	return IRQ_HANDLED;
1983 }
1984 
1985 u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
1986 {
1987 	unsigned int i, handled = 0;
1988 
1989 	for (i = 0; i < host->n_ports; i++) {
1990 		struct ata_port *ap;
1991 
1992 		if (!(irq_masked & (1 << i)))
1993 			continue;
1994 
1995 		ap = host->ports[i];
1996 		if (ap) {
1997 			ahci_port_intr(ap);
1998 		} else {
1999 			if (ata_ratelimit())
2000 				dev_warn(host->dev,
2001 					 "interrupt on disabled port %u\n", i);
2002 		}
2003 
2004 		handled = 1;
2005 	}
2006 
2007 	return handled;
2008 }
2009 EXPORT_SYMBOL_GPL(ahci_handle_port_intr);
2010 
2011 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
2012 {
2013 	struct ata_host *host = dev_instance;
2014 	struct ahci_host_priv *hpriv;
2015 	unsigned int rc = 0;
2016 	void __iomem *mmio;
2017 	u32 irq_stat, irq_masked;
2018 
2019 	hpriv = host->private_data;
2020 	mmio = hpriv->mmio;
2021 
2022 	/* sigh.  0xffffffff is a valid return from h/w */
2023 	irq_stat = readl(mmio + HOST_IRQ_STAT);
2024 	if (!irq_stat)
2025 		return IRQ_NONE;
2026 
2027 	irq_masked = irq_stat & hpriv->port_map;
2028 
2029 	spin_lock(&host->lock);
2030 
2031 	rc = ahci_handle_port_intr(host, irq_masked);
2032 
2033 	/* HOST_IRQ_STAT behaves as level triggered latch meaning that
2034 	 * it should be cleared after all the port events are cleared;
2035 	 * otherwise, it will raise a spurious interrupt after each
2036 	 * valid one.  Please read section 10.6.2 of ahci 1.1 for more
2037 	 * information.
2038 	 *
2039 	 * Also, use the unmasked value to clear interrupt as spurious
2040 	 * pending event on a dummy port might cause screaming IRQ.
2041 	 */
2042 	writel(irq_stat, mmio + HOST_IRQ_STAT);
2043 
2044 	spin_unlock(&host->lock);
2045 
2046 	return IRQ_RETVAL(rc);
2047 }
2048 
2049 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
2050 {
2051 	struct ata_port *ap = qc->ap;
2052 	void __iomem *port_mmio = ahci_port_base(ap);
2053 	struct ahci_port_priv *pp = ap->private_data;
2054 
2055 	/* Keep track of the currently active link.  It will be used
2056 	 * in completion path to determine whether NCQ phase is in
2057 	 * progress.
2058 	 */
2059 	pp->active_link = qc->dev->link;
2060 
2061 	if (ata_is_ncq(qc->tf.protocol))
2062 		writel(1 << qc->hw_tag, port_mmio + PORT_SCR_ACT);
2063 
2064 	if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
2065 		u32 fbs = readl(port_mmio + PORT_FBS);
2066 		fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
2067 		fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
2068 		writel(fbs, port_mmio + PORT_FBS);
2069 		pp->fbs_last_dev = qc->dev->link->pmp;
2070 	}
2071 
2072 	writel(1 << qc->hw_tag, port_mmio + PORT_CMD_ISSUE);
2073 
2074 	ahci_sw_activity(qc->dev->link);
2075 
2076 	return 0;
2077 }
2078 EXPORT_SYMBOL_GPL(ahci_qc_issue);
2079 
2080 static void ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2081 {
2082 	struct ahci_port_priv *pp = qc->ap->private_data;
2083 	u8 *rx_fis = pp->rx_fis;
2084 
2085 	/*
2086 	 * rtf may already be filled (e.g. for successful NCQ commands).
2087 	 * If that is the case, we have nothing to do.
2088 	 */
2089 	if (qc->flags & ATA_QCFLAG_RTF_FILLED)
2090 		return;
2091 
2092 	if (pp->fbs_enabled)
2093 		rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
2094 
2095 	/*
2096 	 * After a successful execution of an ATA PIO data-in command,
2097 	 * the device doesn't send D2H Reg FIS to update the TF and
2098 	 * the host should take TF and E_Status from the preceding PIO
2099 	 * Setup FIS.
2100 	 */
2101 	if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
2102 	    !(qc->flags & ATA_QCFLAG_EH)) {
2103 		ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
2104 		qc->result_tf.status = (rx_fis + RX_FIS_PIO_SETUP)[15];
2105 		qc->flags |= ATA_QCFLAG_RTF_FILLED;
2106 		return;
2107 	}
2108 
2109 	/*
2110 	 * For NCQ commands, we never get a D2H FIS, so reading the D2H Register
2111 	 * FIS area of the Received FIS Structure (which contains a copy of the
2112 	 * last D2H FIS received) will contain an outdated status code.
2113 	 * For NCQ commands, we instead get a SDB FIS, so read the SDB FIS area
2114 	 * instead. However, the SDB FIS does not contain the LBA, so we can't
2115 	 * use the ata_tf_from_fis() helper.
2116 	 */
2117 	if (ata_is_ncq(qc->tf.protocol)) {
2118 		const u8 *fis = rx_fis + RX_FIS_SDB;
2119 
2120 		/*
2121 		 * Successful NCQ commands have been filled already.
2122 		 * A failed NCQ command will read the status here.
2123 		 * (Note that a failed NCQ command will get a more specific
2124 		 * error when reading the NCQ Command Error log.)
2125 		 */
2126 		qc->result_tf.status = fis[2];
2127 		qc->result_tf.error = fis[3];
2128 		qc->flags |= ATA_QCFLAG_RTF_FILLED;
2129 		return;
2130 	}
2131 
2132 	ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
2133 	qc->flags |= ATA_QCFLAG_RTF_FILLED;
2134 }
2135 
2136 static void ahci_qc_ncq_fill_rtf(struct ata_port *ap, u64 done_mask)
2137 {
2138 	struct ahci_port_priv *pp = ap->private_data;
2139 	const u8 *fis;
2140 
2141 	/* No outstanding commands. */
2142 	if (!ap->qc_active)
2143 		return;
2144 
2145 	/*
2146 	 * FBS not enabled, so read status and error once, since they are shared
2147 	 * for all QCs.
2148 	 */
2149 	if (!pp->fbs_enabled) {
2150 		u8 status, error;
2151 
2152 		/* No outstanding NCQ commands. */
2153 		if (!pp->active_link->sactive)
2154 			return;
2155 
2156 		fis = pp->rx_fis + RX_FIS_SDB;
2157 		status = fis[2];
2158 		error = fis[3];
2159 
2160 		while (done_mask) {
2161 			struct ata_queued_cmd *qc;
2162 			unsigned int tag = __ffs64(done_mask);
2163 
2164 			qc = ata_qc_from_tag(ap, tag);
2165 			if (qc && ata_is_ncq(qc->tf.protocol)) {
2166 				qc->result_tf.status = status;
2167 				qc->result_tf.error = error;
2168 				qc->flags |= ATA_QCFLAG_RTF_FILLED;
2169 			}
2170 			done_mask &= ~(1ULL << tag);
2171 		}
2172 
2173 		return;
2174 	}
2175 
2176 	/*
2177 	 * FBS enabled, so read the status and error for each QC, since the QCs
2178 	 * can belong to different PMP links. (Each PMP link has its own FIS
2179 	 * Receive Area.)
2180 	 */
2181 	while (done_mask) {
2182 		struct ata_queued_cmd *qc;
2183 		unsigned int tag = __ffs64(done_mask);
2184 
2185 		qc = ata_qc_from_tag(ap, tag);
2186 		if (qc && ata_is_ncq(qc->tf.protocol)) {
2187 			fis = pp->rx_fis;
2188 			fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
2189 			fis += RX_FIS_SDB;
2190 			qc->result_tf.status = fis[2];
2191 			qc->result_tf.error = fis[3];
2192 			qc->flags |= ATA_QCFLAG_RTF_FILLED;
2193 		}
2194 		done_mask &= ~(1ULL << tag);
2195 	}
2196 }
2197 
2198 static void ahci_freeze(struct ata_port *ap)
2199 {
2200 	void __iomem *port_mmio = ahci_port_base(ap);
2201 
2202 	/* turn IRQ off */
2203 	writel(0, port_mmio + PORT_IRQ_MASK);
2204 }
2205 
2206 static void ahci_thaw(struct ata_port *ap)
2207 {
2208 	struct ahci_host_priv *hpriv = ap->host->private_data;
2209 	void __iomem *mmio = hpriv->mmio;
2210 	void __iomem *port_mmio = ahci_port_base(ap);
2211 	u32 tmp;
2212 	struct ahci_port_priv *pp = ap->private_data;
2213 
2214 	/* clear IRQ */
2215 	tmp = readl(port_mmio + PORT_IRQ_STAT);
2216 	writel(tmp, port_mmio + PORT_IRQ_STAT);
2217 	writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2218 
2219 	/* turn IRQ back on */
2220 	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2221 }
2222 
2223 void ahci_error_handler(struct ata_port *ap)
2224 {
2225 	struct ahci_host_priv *hpriv = ap->host->private_data;
2226 
2227 	if (!ata_port_is_frozen(ap)) {
2228 		/* restart engine */
2229 		hpriv->stop_engine(ap);
2230 		hpriv->start_engine(ap);
2231 	}
2232 
2233 	sata_pmp_error_handler(ap);
2234 
2235 	if (!ata_dev_enabled(ap->link.device))
2236 		hpriv->stop_engine(ap);
2237 }
2238 EXPORT_SYMBOL_GPL(ahci_error_handler);
2239 
2240 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2241 {
2242 	struct ata_port *ap = qc->ap;
2243 
2244 	/* make DMA engine forget about the failed command */
2245 	if (qc->flags & ATA_QCFLAG_EH)
2246 		ahci_kick_engine(ap);
2247 }
2248 
2249 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2250 {
2251 	struct ahci_host_priv *hpriv = ap->host->private_data;
2252 	void __iomem *port_mmio = ahci_port_base(ap);
2253 	struct ata_device *dev = ap->link.device;
2254 	u32 devslp, dm, dito, mdat, deto, dito_conf;
2255 	int rc;
2256 	unsigned int err_mask;
2257 
2258 	devslp = readl(port_mmio + PORT_DEVSLP);
2259 	if (!(devslp & PORT_DEVSLP_DSP)) {
2260 		dev_info(ap->host->dev, "port does not support device sleep\n");
2261 		return;
2262 	}
2263 
2264 	/* disable device sleep */
2265 	if (!sleep) {
2266 		if (devslp & PORT_DEVSLP_ADSE) {
2267 			writel(devslp & ~PORT_DEVSLP_ADSE,
2268 			       port_mmio + PORT_DEVSLP);
2269 			err_mask = ata_dev_set_feature(dev,
2270 						       SETFEATURES_SATA_DISABLE,
2271 						       SATA_DEVSLP);
2272 			if (err_mask && err_mask != AC_ERR_DEV)
2273 				ata_dev_warn(dev, "failed to disable DEVSLP\n");
2274 		}
2275 		return;
2276 	}
2277 
2278 	dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2279 	dito = devslp_idle_timeout / (dm + 1);
2280 	if (dito > 0x3ff)
2281 		dito = 0x3ff;
2282 
2283 	dito_conf = (devslp >> PORT_DEVSLP_DITO_OFFSET) & 0x3FF;
2284 
2285 	/* device sleep was already enabled and same dito */
2286 	if ((devslp & PORT_DEVSLP_ADSE) && (dito_conf == dito))
2287 		return;
2288 
2289 	/* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2290 	rc = hpriv->stop_engine(ap);
2291 	if (rc)
2292 		return;
2293 
2294 	/* Use the nominal value 10 ms if the read MDAT is zero,
2295 	 * the nominal value of DETO is 20 ms.
2296 	 */
2297 	if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
2298 	    ATA_LOG_DEVSLP_VALID_MASK) {
2299 		mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
2300 		       ATA_LOG_DEVSLP_MDAT_MASK;
2301 		if (!mdat)
2302 			mdat = 10;
2303 		deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
2304 		if (!deto)
2305 			deto = 20;
2306 	} else {
2307 		mdat = 10;
2308 		deto = 20;
2309 	}
2310 
2311 	/* Make dito, mdat, deto bits to 0s */
2312 	devslp &= ~GENMASK_ULL(24, 2);
2313 	devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2314 		   (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2315 		   (deto << PORT_DEVSLP_DETO_OFFSET) |
2316 		   PORT_DEVSLP_ADSE);
2317 	writel(devslp, port_mmio + PORT_DEVSLP);
2318 
2319 	hpriv->start_engine(ap);
2320 
2321 	/* enable device sleep feature for the drive */
2322 	err_mask = ata_dev_set_feature(dev,
2323 				       SETFEATURES_SATA_ENABLE,
2324 				       SATA_DEVSLP);
2325 	if (err_mask && err_mask != AC_ERR_DEV)
2326 		ata_dev_warn(dev, "failed to enable DEVSLP\n");
2327 }
2328 
2329 static void ahci_enable_fbs(struct ata_port *ap)
2330 {
2331 	struct ahci_host_priv *hpriv = ap->host->private_data;
2332 	struct ahci_port_priv *pp = ap->private_data;
2333 	void __iomem *port_mmio = ahci_port_base(ap);
2334 	u32 fbs;
2335 	int rc;
2336 
2337 	if (!pp->fbs_supported)
2338 		return;
2339 
2340 	fbs = readl(port_mmio + PORT_FBS);
2341 	if (fbs & PORT_FBS_EN) {
2342 		pp->fbs_enabled = true;
2343 		pp->fbs_last_dev = -1; /* initialization */
2344 		return;
2345 	}
2346 
2347 	rc = hpriv->stop_engine(ap);
2348 	if (rc)
2349 		return;
2350 
2351 	writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2352 	fbs = readl(port_mmio + PORT_FBS);
2353 	if (fbs & PORT_FBS_EN) {
2354 		dev_info(ap->host->dev, "FBS is enabled\n");
2355 		pp->fbs_enabled = true;
2356 		pp->fbs_last_dev = -1; /* initialization */
2357 	} else
2358 		dev_err(ap->host->dev, "Failed to enable FBS\n");
2359 
2360 	hpriv->start_engine(ap);
2361 }
2362 
2363 static void ahci_disable_fbs(struct ata_port *ap)
2364 {
2365 	struct ahci_host_priv *hpriv = ap->host->private_data;
2366 	struct ahci_port_priv *pp = ap->private_data;
2367 	void __iomem *port_mmio = ahci_port_base(ap);
2368 	u32 fbs;
2369 	int rc;
2370 
2371 	if (!pp->fbs_supported)
2372 		return;
2373 
2374 	fbs = readl(port_mmio + PORT_FBS);
2375 	if ((fbs & PORT_FBS_EN) == 0) {
2376 		pp->fbs_enabled = false;
2377 		return;
2378 	}
2379 
2380 	rc = hpriv->stop_engine(ap);
2381 	if (rc)
2382 		return;
2383 
2384 	writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2385 	fbs = readl(port_mmio + PORT_FBS);
2386 	if (fbs & PORT_FBS_EN)
2387 		dev_err(ap->host->dev, "Failed to disable FBS\n");
2388 	else {
2389 		dev_info(ap->host->dev, "FBS is disabled\n");
2390 		pp->fbs_enabled = false;
2391 	}
2392 
2393 	hpriv->start_engine(ap);
2394 }
2395 
2396 static void ahci_pmp_attach(struct ata_port *ap)
2397 {
2398 	void __iomem *port_mmio = ahci_port_base(ap);
2399 	struct ahci_port_priv *pp = ap->private_data;
2400 	u32 cmd;
2401 
2402 	cmd = readl(port_mmio + PORT_CMD);
2403 	cmd |= PORT_CMD_PMP;
2404 	writel(cmd, port_mmio + PORT_CMD);
2405 
2406 	ahci_enable_fbs(ap);
2407 
2408 	pp->intr_mask |= PORT_IRQ_BAD_PMP;
2409 
2410 	/*
2411 	 * We must not change the port interrupt mask register if the
2412 	 * port is marked frozen, the value in pp->intr_mask will be
2413 	 * restored later when the port is thawed.
2414 	 *
2415 	 * Note that during initialization, the port is marked as
2416 	 * frozen since the irq handler is not yet registered.
2417 	 */
2418 	if (!ata_port_is_frozen(ap))
2419 		writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2420 }
2421 
2422 static void ahci_pmp_detach(struct ata_port *ap)
2423 {
2424 	void __iomem *port_mmio = ahci_port_base(ap);
2425 	struct ahci_port_priv *pp = ap->private_data;
2426 	u32 cmd;
2427 
2428 	ahci_disable_fbs(ap);
2429 
2430 	cmd = readl(port_mmio + PORT_CMD);
2431 	cmd &= ~PORT_CMD_PMP;
2432 	writel(cmd, port_mmio + PORT_CMD);
2433 
2434 	pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2435 
2436 	/* see comment above in ahci_pmp_attach() */
2437 	if (!ata_port_is_frozen(ap))
2438 		writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2439 }
2440 
2441 int ahci_port_resume(struct ata_port *ap)
2442 {
2443 	ahci_rpm_get_port(ap);
2444 
2445 	ahci_power_up(ap);
2446 	ahci_start_port(ap);
2447 
2448 	if (sata_pmp_attached(ap))
2449 		ahci_pmp_attach(ap);
2450 	else
2451 		ahci_pmp_detach(ap);
2452 
2453 	return 0;
2454 }
2455 EXPORT_SYMBOL_GPL(ahci_port_resume);
2456 
2457 #ifdef CONFIG_PM
2458 static void ahci_handle_s2idle(struct ata_port *ap)
2459 {
2460 	void __iomem *port_mmio = ahci_port_base(ap);
2461 	u32 devslp;
2462 
2463 	if (pm_suspend_via_firmware())
2464 		return;
2465 	devslp = readl(port_mmio + PORT_DEVSLP);
2466 	if ((devslp & PORT_DEVSLP_ADSE))
2467 		ata_msleep(ap, devslp_idle_timeout);
2468 }
2469 
2470 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2471 {
2472 	const char *emsg = NULL;
2473 	int rc;
2474 
2475 	rc = ahci_deinit_port(ap, &emsg);
2476 	if (rc == 0)
2477 		ahci_power_down(ap);
2478 	else {
2479 		ata_port_err(ap, "%s (%d)\n", emsg, rc);
2480 		ata_port_freeze(ap);
2481 	}
2482 
2483 	if (acpi_storage_d3(ap->host->dev))
2484 		ahci_handle_s2idle(ap);
2485 
2486 	ahci_rpm_put_port(ap);
2487 	return rc;
2488 }
2489 #endif
2490 
2491 static int ahci_port_start(struct ata_port *ap)
2492 {
2493 	struct ahci_host_priv *hpriv = ap->host->private_data;
2494 	struct device *dev = ap->host->dev;
2495 	struct ahci_port_priv *pp;
2496 	void *mem;
2497 	dma_addr_t mem_dma;
2498 	size_t dma_sz, rx_fis_sz;
2499 
2500 	pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2501 	if (!pp)
2502 		return -ENOMEM;
2503 
2504 	if (ap->host->n_ports > 1) {
2505 		pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2506 		if (!pp->irq_desc) {
2507 			devm_kfree(dev, pp);
2508 			return -ENOMEM;
2509 		}
2510 		snprintf(pp->irq_desc, 8,
2511 			 "%s%d", dev_driver_string(dev), ap->port_no);
2512 	}
2513 
2514 	/* check FBS capability */
2515 	if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2516 		void __iomem *port_mmio = ahci_port_base(ap);
2517 		u32 cmd = readl(port_mmio + PORT_CMD);
2518 		if (cmd & PORT_CMD_FBSCP)
2519 			pp->fbs_supported = true;
2520 		else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2521 			dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2522 				 ap->port_no);
2523 			pp->fbs_supported = true;
2524 		} else
2525 			dev_warn(dev, "port %d is not capable of FBS\n",
2526 				 ap->port_no);
2527 	}
2528 
2529 	if (pp->fbs_supported) {
2530 		dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2531 		rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2532 	} else {
2533 		dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2534 		rx_fis_sz = AHCI_RX_FIS_SZ;
2535 	}
2536 
2537 	mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2538 	if (!mem)
2539 		return -ENOMEM;
2540 
2541 	/*
2542 	 * First item in chunk of DMA memory: 32-slot command table,
2543 	 * 32 bytes each in size
2544 	 */
2545 	pp->cmd_slot = mem;
2546 	pp->cmd_slot_dma = mem_dma;
2547 
2548 	mem += AHCI_CMD_SLOT_SZ;
2549 	mem_dma += AHCI_CMD_SLOT_SZ;
2550 
2551 	/*
2552 	 * Second item: Received-FIS area
2553 	 */
2554 	pp->rx_fis = mem;
2555 	pp->rx_fis_dma = mem_dma;
2556 
2557 	mem += rx_fis_sz;
2558 	mem_dma += rx_fis_sz;
2559 
2560 	/*
2561 	 * Third item: data area for storing a single command
2562 	 * and its scatter-gather table
2563 	 */
2564 	pp->cmd_tbl = mem;
2565 	pp->cmd_tbl_dma = mem_dma;
2566 
2567 	/*
2568 	 * Save off initial list of interrupts to be enabled.
2569 	 * This could be changed later
2570 	 */
2571 	pp->intr_mask = DEF_PORT_IRQ;
2572 
2573 	/*
2574 	 * Switch to per-port locking in case each port has its own MSI vector.
2575 	 */
2576 	if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2577 		spin_lock_init(&pp->lock);
2578 		ap->lock = &pp->lock;
2579 	}
2580 
2581 	ap->private_data = pp;
2582 
2583 	/* engage engines, captain */
2584 	return ahci_port_resume(ap);
2585 }
2586 
2587 static void ahci_port_stop(struct ata_port *ap)
2588 {
2589 	const char *emsg = NULL;
2590 	struct ahci_host_priv *hpriv = ap->host->private_data;
2591 	void __iomem *host_mmio = hpriv->mmio;
2592 	int rc;
2593 
2594 	/* de-initialize port */
2595 	rc = ahci_deinit_port(ap, &emsg);
2596 	if (rc)
2597 		ata_port_warn(ap, "%s (%d)\n", emsg, rc);
2598 
2599 	/*
2600 	 * Clear GHC.IS to prevent stuck INTx after disabling MSI and
2601 	 * re-enabling INTx.
2602 	 */
2603 	writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT);
2604 
2605 	ahci_rpm_put_port(ap);
2606 }
2607 
2608 void ahci_print_info(struct ata_host *host, const char *scc_s)
2609 {
2610 	struct ahci_host_priv *hpriv = host->private_data;
2611 	u32 vers, cap, cap2, impl, speed;
2612 	const char *speed_s;
2613 
2614 	vers = hpriv->version;
2615 	cap = hpriv->cap;
2616 	cap2 = hpriv->cap2;
2617 	impl = hpriv->port_map;
2618 
2619 	speed = (cap >> 20) & 0xf;
2620 	if (speed == 1)
2621 		speed_s = "1.5";
2622 	else if (speed == 2)
2623 		speed_s = "3";
2624 	else if (speed == 3)
2625 		speed_s = "6";
2626 	else
2627 		speed_s = "?";
2628 
2629 	dev_info(host->dev,
2630 		"AHCI %02x%02x.%02x%02x "
2631 		"%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2632 		,
2633 
2634 		(vers >> 24) & 0xff,
2635 		(vers >> 16) & 0xff,
2636 		(vers >> 8) & 0xff,
2637 		vers & 0xff,
2638 
2639 		((cap >> 8) & 0x1f) + 1,
2640 		(cap & 0x1f) + 1,
2641 		speed_s,
2642 		impl,
2643 		scc_s);
2644 
2645 	dev_info(host->dev,
2646 		"flags: "
2647 		"%s%s%s%s%s%s%s"
2648 		"%s%s%s%s%s%s%s"
2649 		"%s%s%s%s%s%s%s"
2650 		"%s%s\n"
2651 		,
2652 
2653 		cap & HOST_CAP_64 ? "64bit " : "",
2654 		cap & HOST_CAP_NCQ ? "ncq " : "",
2655 		cap & HOST_CAP_SNTF ? "sntf " : "",
2656 		cap & HOST_CAP_MPS ? "ilck " : "",
2657 		cap & HOST_CAP_SSS ? "stag " : "",
2658 		cap & HOST_CAP_ALPM ? "pm " : "",
2659 		cap & HOST_CAP_LED ? "led " : "",
2660 		cap & HOST_CAP_CLO ? "clo " : "",
2661 		cap & HOST_CAP_ONLY ? "only " : "",
2662 		cap & HOST_CAP_PMP ? "pmp " : "",
2663 		cap & HOST_CAP_FBS ? "fbs " : "",
2664 		cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2665 		cap & HOST_CAP_SSC ? "slum " : "",
2666 		cap & HOST_CAP_PART ? "part " : "",
2667 		cap & HOST_CAP_CCC ? "ccc " : "",
2668 		cap & HOST_CAP_EMS ? "ems " : "",
2669 		cap & HOST_CAP_SXS ? "sxs " : "",
2670 		cap2 & HOST_CAP2_DESO ? "deso " : "",
2671 		cap2 & HOST_CAP2_SADM ? "sadm " : "",
2672 		cap2 & HOST_CAP2_SDS ? "sds " : "",
2673 		cap2 & HOST_CAP2_APST ? "apst " : "",
2674 		cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2675 		cap2 & HOST_CAP2_BOH ? "boh " : ""
2676 		);
2677 }
2678 EXPORT_SYMBOL_GPL(ahci_print_info);
2679 
2680 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2681 			  struct ata_port_info *pi)
2682 {
2683 	u8 messages;
2684 	void __iomem *mmio = hpriv->mmio;
2685 	u32 em_loc = readl(mmio + HOST_EM_LOC);
2686 	u32 em_ctl = readl(mmio + HOST_EM_CTL);
2687 
2688 	if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2689 		return;
2690 
2691 	messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2692 
2693 	if (messages) {
2694 		/* store em_loc */
2695 		hpriv->em_loc = ((em_loc >> 16) * 4);
2696 		hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2697 		hpriv->em_msg_type = messages;
2698 		pi->flags |= ATA_FLAG_EM;
2699 		if (!(em_ctl & EM_CTL_ALHD))
2700 			pi->flags |= ATA_FLAG_SW_ACTIVITY;
2701 	}
2702 }
2703 EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2704 
2705 static int ahci_host_activate_multi_irqs(struct ata_host *host,
2706 					 const struct scsi_host_template *sht)
2707 {
2708 	struct ahci_host_priv *hpriv = host->private_data;
2709 	int i, rc;
2710 
2711 	rc = ata_host_start(host);
2712 	if (rc)
2713 		return rc;
2714 	/*
2715 	 * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2716 	 * allocated. That is one MSI per port, starting from @irq.
2717 	 */
2718 	for (i = 0; i < host->n_ports; i++) {
2719 		struct ahci_port_priv *pp = host->ports[i]->private_data;
2720 		int irq = hpriv->get_irq_vector(host, i);
2721 
2722 		/* Do not receive interrupts sent by dummy ports */
2723 		if (!pp) {
2724 			disable_irq(irq);
2725 			continue;
2726 		}
2727 
2728 		rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard,
2729 				0, pp->irq_desc, host->ports[i]);
2730 
2731 		if (rc)
2732 			return rc;
2733 		ata_port_desc(host->ports[i], "irq %d", irq);
2734 	}
2735 
2736 	return ata_host_register(host, sht);
2737 }
2738 
2739 /**
2740  *	ahci_host_activate - start AHCI host, request IRQs and register it
2741  *	@host: target ATA host
2742  *	@sht: scsi_host_template to use when registering the host
2743  *
2744  *	LOCKING:
2745  *	Inherited from calling layer (may sleep).
2746  *
2747  *	RETURNS:
2748  *	0 on success, -errno otherwise.
2749  */
2750 int ahci_host_activate(struct ata_host *host, const struct scsi_host_template *sht)
2751 {
2752 	struct ahci_host_priv *hpriv = host->private_data;
2753 	int irq = hpriv->irq;
2754 	int rc;
2755 
2756 	if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2757 		if (hpriv->irq_handler &&
2758 		    hpriv->irq_handler != ahci_single_level_irq_intr)
2759 			dev_warn(host->dev,
2760 			         "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n");
2761 		if (!hpriv->get_irq_vector) {
2762 			dev_err(host->dev,
2763 				"AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n");
2764 			return -EIO;
2765 		}
2766 
2767 		rc = ahci_host_activate_multi_irqs(host, sht);
2768 	} else {
2769 		rc = ata_host_activate(host, irq, hpriv->irq_handler,
2770 				       IRQF_SHARED, sht);
2771 	}
2772 
2773 
2774 	return rc;
2775 }
2776 EXPORT_SYMBOL_GPL(ahci_host_activate);
2777 
2778 MODULE_AUTHOR("Jeff Garzik");
2779 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2780 MODULE_LICENSE("GPL");
2781