1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * libahci.c - Common AHCI SATA low-level routines 4 * 5 * Maintained by: Tejun Heo <tj@kernel.org> 6 * Please ALWAYS copy linux-ide@vger.kernel.org 7 * on emails. 8 * 9 * Copyright 2004-2005 Red Hat, Inc. 10 * 11 * libata documentation is available via 'make {ps|pdf}docs', 12 * as Documentation/driver-api/libata.rst 13 * 14 * AHCI hardware documentation: 15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 17 */ 18 19 #include <linux/bitops.h> 20 #include <linux/kernel.h> 21 #include <linux/gfp.h> 22 #include <linux/module.h> 23 #include <linux/nospec.h> 24 #include <linux/blkdev.h> 25 #include <linux/delay.h> 26 #include <linux/interrupt.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/device.h> 29 #include <scsi/scsi_host.h> 30 #include <scsi/scsi_cmnd.h> 31 #include <linux/libata.h> 32 #include <linux/pci.h> 33 #include "ahci.h" 34 #include "libata.h" 35 36 static int ahci_skip_host_reset; 37 int ahci_ignore_sss; 38 EXPORT_SYMBOL_GPL(ahci_ignore_sss); 39 40 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); 41 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); 42 43 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444); 44 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)"); 45 46 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 47 unsigned hints); 48 static ssize_t ahci_led_show(struct ata_port *ap, char *buf); 49 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 50 size_t size); 51 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 52 ssize_t size); 53 54 55 56 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); 57 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); 58 static void ahci_qc_fill_rtf(struct ata_queued_cmd *qc); 59 static void ahci_qc_ncq_fill_rtf(struct ata_port *ap, u64 done_mask); 60 static int ahci_port_start(struct ata_port *ap); 61 static void ahci_port_stop(struct ata_port *ap); 62 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc); 63 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc); 64 static void ahci_freeze(struct ata_port *ap); 65 static void ahci_thaw(struct ata_port *ap); 66 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep); 67 static void ahci_enable_fbs(struct ata_port *ap); 68 static void ahci_disable_fbs(struct ata_port *ap); 69 static void ahci_pmp_attach(struct ata_port *ap); 70 static void ahci_pmp_detach(struct ata_port *ap); 71 static int ahci_softreset(struct ata_link *link, unsigned int *class, 72 unsigned long deadline); 73 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class, 74 unsigned long deadline); 75 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 76 unsigned long deadline); 77 static void ahci_postreset(struct ata_link *link, unsigned int *class); 78 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); 79 static void ahci_dev_config(struct ata_device *dev); 80 #ifdef CONFIG_PM 81 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); 82 #endif 83 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf); 84 static ssize_t ahci_activity_store(struct ata_device *dev, 85 enum sw_activity val); 86 static void ahci_init_sw_activity(struct ata_link *link); 87 88 static ssize_t ahci_show_host_caps(struct device *dev, 89 struct device_attribute *attr, char *buf); 90 static ssize_t ahci_show_host_cap2(struct device *dev, 91 struct device_attribute *attr, char *buf); 92 static ssize_t ahci_show_host_version(struct device *dev, 93 struct device_attribute *attr, char *buf); 94 static ssize_t ahci_show_port_cmd(struct device *dev, 95 struct device_attribute *attr, char *buf); 96 static ssize_t ahci_read_em_buffer(struct device *dev, 97 struct device_attribute *attr, char *buf); 98 static ssize_t ahci_store_em_buffer(struct device *dev, 99 struct device_attribute *attr, 100 const char *buf, size_t size); 101 static ssize_t ahci_show_em_supported(struct device *dev, 102 struct device_attribute *attr, char *buf); 103 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance); 104 105 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL); 106 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL); 107 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL); 108 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL); 109 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO, 110 ahci_read_em_buffer, ahci_store_em_buffer); 111 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL); 112 113 static struct attribute *ahci_shost_attrs[] = { 114 &dev_attr_link_power_management_policy.attr, 115 &dev_attr_em_message_type.attr, 116 &dev_attr_em_message.attr, 117 &dev_attr_ahci_host_caps.attr, 118 &dev_attr_ahci_host_cap2.attr, 119 &dev_attr_ahci_host_version.attr, 120 &dev_attr_ahci_port_cmd.attr, 121 &dev_attr_em_buffer.attr, 122 &dev_attr_em_message_supported.attr, 123 NULL 124 }; 125 126 static const struct attribute_group ahci_shost_attr_group = { 127 .attrs = ahci_shost_attrs 128 }; 129 130 const struct attribute_group *ahci_shost_groups[] = { 131 &ahci_shost_attr_group, 132 NULL 133 }; 134 EXPORT_SYMBOL_GPL(ahci_shost_groups); 135 136 static struct attribute *ahci_sdev_attrs[] = { 137 &dev_attr_sw_activity.attr, 138 &dev_attr_unload_heads.attr, 139 &dev_attr_ncq_prio_supported.attr, 140 &dev_attr_ncq_prio_enable.attr, 141 NULL 142 }; 143 144 static const struct attribute_group ahci_sdev_attr_group = { 145 .attrs = ahci_sdev_attrs 146 }; 147 148 const struct attribute_group *ahci_sdev_groups[] = { 149 &ahci_sdev_attr_group, 150 NULL 151 }; 152 EXPORT_SYMBOL_GPL(ahci_sdev_groups); 153 154 struct ata_port_operations ahci_ops = { 155 .inherits = &sata_pmp_port_ops, 156 157 .qc_defer = ahci_pmp_qc_defer, 158 .qc_prep = ahci_qc_prep, 159 .qc_issue = ahci_qc_issue, 160 .qc_fill_rtf = ahci_qc_fill_rtf, 161 .qc_ncq_fill_rtf = ahci_qc_ncq_fill_rtf, 162 163 .freeze = ahci_freeze, 164 .thaw = ahci_thaw, 165 .softreset = ahci_softreset, 166 .hardreset = ahci_hardreset, 167 .postreset = ahci_postreset, 168 .pmp_softreset = ahci_softreset, 169 .error_handler = ahci_error_handler, 170 .post_internal_cmd = ahci_post_internal_cmd, 171 .dev_config = ahci_dev_config, 172 173 .scr_read = ahci_scr_read, 174 .scr_write = ahci_scr_write, 175 .pmp_attach = ahci_pmp_attach, 176 .pmp_detach = ahci_pmp_detach, 177 178 .set_lpm = ahci_set_lpm, 179 .em_show = ahci_led_show, 180 .em_store = ahci_led_store, 181 .sw_activity_show = ahci_activity_show, 182 .sw_activity_store = ahci_activity_store, 183 .transmit_led_message = ahci_transmit_led_message, 184 #ifdef CONFIG_PM 185 .port_suspend = ahci_port_suspend, 186 .port_resume = ahci_port_resume, 187 #endif 188 .port_start = ahci_port_start, 189 .port_stop = ahci_port_stop, 190 }; 191 EXPORT_SYMBOL_GPL(ahci_ops); 192 193 struct ata_port_operations ahci_pmp_retry_srst_ops = { 194 .inherits = &ahci_ops, 195 .softreset = ahci_pmp_retry_softreset, 196 }; 197 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops); 198 199 static bool ahci_em_messages __read_mostly = true; 200 module_param(ahci_em_messages, bool, 0444); 201 /* add other LED protocol types when they become supported */ 202 MODULE_PARM_DESC(ahci_em_messages, 203 "AHCI Enclosure Management Message control (0 = off, 1 = on)"); 204 205 /* device sleep idle timeout in ms */ 206 static int devslp_idle_timeout __read_mostly = 1000; 207 module_param(devslp_idle_timeout, int, 0644); 208 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout"); 209 210 static void ahci_enable_ahci(void __iomem *mmio) 211 { 212 int i; 213 u32 tmp; 214 215 /* turn on AHCI_EN */ 216 tmp = readl(mmio + HOST_CTL); 217 if (tmp & HOST_AHCI_EN) 218 return; 219 220 /* Some controllers need AHCI_EN to be written multiple times. 221 * Try a few times before giving up. 222 */ 223 for (i = 0; i < 5; i++) { 224 tmp |= HOST_AHCI_EN; 225 writel(tmp, mmio + HOST_CTL); 226 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ 227 if (tmp & HOST_AHCI_EN) 228 return; 229 msleep(10); 230 } 231 232 WARN_ON(1); 233 } 234 235 /** 236 * ahci_rpm_get_port - Make sure the port is powered on 237 * @ap: Port to power on 238 * 239 * Whenever there is need to access the AHCI host registers outside of 240 * normal execution paths, call this function to make sure the host is 241 * actually powered on. 242 */ 243 static int ahci_rpm_get_port(struct ata_port *ap) 244 { 245 return pm_runtime_get_sync(ap->dev); 246 } 247 248 /** 249 * ahci_rpm_put_port - Undoes ahci_rpm_get_port() 250 * @ap: Port to power down 251 * 252 * Undoes ahci_rpm_get_port() and possibly powers down the AHCI host 253 * if it has no more active users. 254 */ 255 static void ahci_rpm_put_port(struct ata_port *ap) 256 { 257 pm_runtime_put(ap->dev); 258 } 259 260 static ssize_t ahci_show_host_caps(struct device *dev, 261 struct device_attribute *attr, char *buf) 262 { 263 struct Scsi_Host *shost = class_to_shost(dev); 264 struct ata_port *ap = ata_shost_to_port(shost); 265 struct ahci_host_priv *hpriv = ap->host->private_data; 266 267 return sprintf(buf, "%x\n", hpriv->cap); 268 } 269 270 static ssize_t ahci_show_host_cap2(struct device *dev, 271 struct device_attribute *attr, char *buf) 272 { 273 struct Scsi_Host *shost = class_to_shost(dev); 274 struct ata_port *ap = ata_shost_to_port(shost); 275 struct ahci_host_priv *hpriv = ap->host->private_data; 276 277 return sprintf(buf, "%x\n", hpriv->cap2); 278 } 279 280 static ssize_t ahci_show_host_version(struct device *dev, 281 struct device_attribute *attr, char *buf) 282 { 283 struct Scsi_Host *shost = class_to_shost(dev); 284 struct ata_port *ap = ata_shost_to_port(shost); 285 struct ahci_host_priv *hpriv = ap->host->private_data; 286 287 return sprintf(buf, "%x\n", hpriv->version); 288 } 289 290 static ssize_t ahci_show_port_cmd(struct device *dev, 291 struct device_attribute *attr, char *buf) 292 { 293 struct Scsi_Host *shost = class_to_shost(dev); 294 struct ata_port *ap = ata_shost_to_port(shost); 295 void __iomem *port_mmio = ahci_port_base(ap); 296 ssize_t ret; 297 298 ahci_rpm_get_port(ap); 299 ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD)); 300 ahci_rpm_put_port(ap); 301 302 return ret; 303 } 304 305 static ssize_t ahci_read_em_buffer(struct device *dev, 306 struct device_attribute *attr, char *buf) 307 { 308 struct Scsi_Host *shost = class_to_shost(dev); 309 struct ata_port *ap = ata_shost_to_port(shost); 310 struct ahci_host_priv *hpriv = ap->host->private_data; 311 void __iomem *mmio = hpriv->mmio; 312 void __iomem *em_mmio = mmio + hpriv->em_loc; 313 u32 em_ctl, msg; 314 unsigned long flags; 315 size_t count; 316 int i; 317 318 ahci_rpm_get_port(ap); 319 spin_lock_irqsave(ap->lock, flags); 320 321 em_ctl = readl(mmio + HOST_EM_CTL); 322 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT || 323 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) { 324 spin_unlock_irqrestore(ap->lock, flags); 325 ahci_rpm_put_port(ap); 326 return -EINVAL; 327 } 328 329 if (!(em_ctl & EM_CTL_MR)) { 330 spin_unlock_irqrestore(ap->lock, flags); 331 ahci_rpm_put_port(ap); 332 return -EAGAIN; 333 } 334 335 if (!(em_ctl & EM_CTL_SMB)) 336 em_mmio += hpriv->em_buf_sz; 337 338 count = hpriv->em_buf_sz; 339 340 /* the count should not be larger than PAGE_SIZE */ 341 if (count > PAGE_SIZE) { 342 if (printk_ratelimit()) 343 ata_port_warn(ap, 344 "EM read buffer size too large: " 345 "buffer size %u, page size %lu\n", 346 hpriv->em_buf_sz, PAGE_SIZE); 347 count = PAGE_SIZE; 348 } 349 350 for (i = 0; i < count; i += 4) { 351 msg = readl(em_mmio + i); 352 buf[i] = msg & 0xff; 353 buf[i + 1] = (msg >> 8) & 0xff; 354 buf[i + 2] = (msg >> 16) & 0xff; 355 buf[i + 3] = (msg >> 24) & 0xff; 356 } 357 358 spin_unlock_irqrestore(ap->lock, flags); 359 ahci_rpm_put_port(ap); 360 361 return i; 362 } 363 364 static ssize_t ahci_store_em_buffer(struct device *dev, 365 struct device_attribute *attr, 366 const char *buf, size_t size) 367 { 368 struct Scsi_Host *shost = class_to_shost(dev); 369 struct ata_port *ap = ata_shost_to_port(shost); 370 struct ahci_host_priv *hpriv = ap->host->private_data; 371 void __iomem *mmio = hpriv->mmio; 372 void __iomem *em_mmio = mmio + hpriv->em_loc; 373 const unsigned char *msg_buf = buf; 374 u32 em_ctl, msg; 375 unsigned long flags; 376 int i; 377 378 /* check size validity */ 379 if (!(ap->flags & ATA_FLAG_EM) || 380 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) || 381 size % 4 || size > hpriv->em_buf_sz) 382 return -EINVAL; 383 384 ahci_rpm_get_port(ap); 385 spin_lock_irqsave(ap->lock, flags); 386 387 em_ctl = readl(mmio + HOST_EM_CTL); 388 if (em_ctl & EM_CTL_TM) { 389 spin_unlock_irqrestore(ap->lock, flags); 390 ahci_rpm_put_port(ap); 391 return -EBUSY; 392 } 393 394 for (i = 0; i < size; i += 4) { 395 msg = msg_buf[i] | msg_buf[i + 1] << 8 | 396 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24; 397 writel(msg, em_mmio + i); 398 } 399 400 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 401 402 spin_unlock_irqrestore(ap->lock, flags); 403 ahci_rpm_put_port(ap); 404 405 return size; 406 } 407 408 static ssize_t ahci_show_em_supported(struct device *dev, 409 struct device_attribute *attr, char *buf) 410 { 411 struct Scsi_Host *shost = class_to_shost(dev); 412 struct ata_port *ap = ata_shost_to_port(shost); 413 struct ahci_host_priv *hpriv = ap->host->private_data; 414 void __iomem *mmio = hpriv->mmio; 415 u32 em_ctl; 416 417 ahci_rpm_get_port(ap); 418 em_ctl = readl(mmio + HOST_EM_CTL); 419 ahci_rpm_put_port(ap); 420 421 return sprintf(buf, "%s%s%s%s\n", 422 em_ctl & EM_CTL_LED ? "led " : "", 423 em_ctl & EM_CTL_SAFTE ? "saf-te " : "", 424 em_ctl & EM_CTL_SES ? "ses-2 " : "", 425 em_ctl & EM_CTL_SGPIO ? "sgpio " : ""); 426 } 427 428 /** 429 * ahci_save_initial_config - Save and fixup initial config values 430 * @dev: target AHCI device 431 * @hpriv: host private area to store config values 432 * 433 * Some registers containing configuration info might be setup by 434 * BIOS and might be cleared on reset. This function saves the 435 * initial values of those registers into @hpriv such that they 436 * can be restored after controller reset. 437 * 438 * If inconsistent, config values are fixed up by this function. 439 * 440 * If it is not set already this function sets hpriv->start_engine to 441 * ahci_start_engine. 442 * 443 * LOCKING: 444 * None. 445 */ 446 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv) 447 { 448 void __iomem *mmio = hpriv->mmio; 449 void __iomem *port_mmio; 450 unsigned long port_map; 451 u32 cap, cap2, vers; 452 int i; 453 454 /* make sure AHCI mode is enabled before accessing CAP */ 455 ahci_enable_ahci(mmio); 456 457 /* 458 * Values prefixed with saved_ are written back to the HBA and ports 459 * registers after reset. Values without are used for driver operation. 460 */ 461 462 /* 463 * Override HW-init HBA capability fields with the platform-specific 464 * values. The rest of the HBA capabilities are defined as Read-only 465 * and can't be modified in CSR anyway. 466 */ 467 cap = readl(mmio + HOST_CAP); 468 if (hpriv->saved_cap) 469 cap = (cap & ~(HOST_CAP_SSS | HOST_CAP_MPS)) | hpriv->saved_cap; 470 hpriv->saved_cap = cap; 471 472 /* CAP2 register is only defined for AHCI 1.2 and later */ 473 vers = readl(mmio + HOST_VERSION); 474 if ((vers >> 16) > 1 || 475 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200)) 476 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2); 477 else 478 hpriv->saved_cap2 = cap2 = 0; 479 480 /* some chips have errata preventing 64bit use */ 481 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { 482 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n"); 483 cap &= ~HOST_CAP_64; 484 } 485 486 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { 487 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n"); 488 cap &= ~HOST_CAP_NCQ; 489 } 490 491 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) { 492 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n"); 493 cap |= HOST_CAP_NCQ; 494 } 495 496 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { 497 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n"); 498 cap &= ~HOST_CAP_PMP; 499 } 500 501 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) { 502 dev_info(dev, 503 "controller can't do SNTF, turning off CAP_SNTF\n"); 504 cap &= ~HOST_CAP_SNTF; 505 } 506 507 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) { 508 dev_info(dev, 509 "controller can't do DEVSLP, turning off\n"); 510 cap2 &= ~HOST_CAP2_SDS; 511 cap2 &= ~HOST_CAP2_SADM; 512 } 513 514 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) { 515 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n"); 516 cap |= HOST_CAP_FBS; 517 } 518 519 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) { 520 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n"); 521 cap &= ~HOST_CAP_FBS; 522 } 523 524 if (!(cap & HOST_CAP_ALPM) && (hpriv->flags & AHCI_HFLAG_YES_ALPM)) { 525 dev_info(dev, "controller can do ALPM, turning on CAP_ALPM\n"); 526 cap |= HOST_CAP_ALPM; 527 } 528 529 if ((cap & HOST_CAP_SXS) && (hpriv->flags & AHCI_HFLAG_NO_SXS)) { 530 dev_info(dev, "controller does not support SXS, disabling CAP_SXS\n"); 531 cap &= ~HOST_CAP_SXS; 532 } 533 534 /* Override the HBA ports mapping if the platform needs it */ 535 port_map = readl(mmio + HOST_PORTS_IMPL); 536 if (hpriv->saved_port_map && port_map != hpriv->saved_port_map) { 537 dev_info(dev, "forcing port_map 0x%lx -> 0x%x\n", 538 port_map, hpriv->saved_port_map); 539 port_map = hpriv->saved_port_map; 540 } else { 541 hpriv->saved_port_map = port_map; 542 } 543 544 if (hpriv->mask_port_map) { 545 dev_warn(dev, "masking port_map 0x%lx -> 0x%lx\n", 546 port_map, 547 port_map & hpriv->mask_port_map); 548 port_map &= hpriv->mask_port_map; 549 } 550 551 /* cross check port_map and cap.n_ports */ 552 if (port_map) { 553 int map_ports = 0; 554 555 for (i = 0; i < AHCI_MAX_PORTS; i++) 556 if (port_map & (1 << i)) 557 map_ports++; 558 559 /* If PI has more ports than n_ports, whine, clear 560 * port_map and let it be generated from n_ports. 561 */ 562 if (map_ports > ahci_nr_ports(cap)) { 563 dev_warn(dev, 564 "implemented port map (0x%lx) contains more ports than nr_ports (%u), using nr_ports\n", 565 port_map, ahci_nr_ports(cap)); 566 port_map = 0; 567 } 568 } 569 570 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */ 571 if (!port_map && vers < 0x10300) { 572 port_map = (1 << ahci_nr_ports(cap)) - 1; 573 dev_warn(dev, "forcing PORTS_IMPL to 0x%lx\n", port_map); 574 575 /* write the fixed up value to the PI register */ 576 hpriv->saved_port_map = port_map; 577 } 578 579 /* 580 * Preserve the ports capabilities defined by the platform. Note there 581 * is no need in storing the rest of the P#.CMD fields since they are 582 * volatile. 583 */ 584 for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) { 585 if (hpriv->saved_port_cap[i]) 586 continue; 587 588 port_mmio = __ahci_port_base(hpriv, i); 589 hpriv->saved_port_cap[i] = 590 readl(port_mmio + PORT_CMD) & PORT_CMD_CAP; 591 } 592 593 /* record values to use during operation */ 594 hpriv->cap = cap; 595 hpriv->cap2 = cap2; 596 hpriv->version = vers; 597 hpriv->port_map = port_map; 598 599 if (!hpriv->start_engine) 600 hpriv->start_engine = ahci_start_engine; 601 602 if (!hpriv->stop_engine) 603 hpriv->stop_engine = ahci_stop_engine; 604 605 if (!hpriv->irq_handler) 606 hpriv->irq_handler = ahci_single_level_irq_intr; 607 } 608 EXPORT_SYMBOL_GPL(ahci_save_initial_config); 609 610 /** 611 * ahci_restore_initial_config - Restore initial config 612 * @host: target ATA host 613 * 614 * Restore initial config stored by ahci_save_initial_config(). 615 * 616 * LOCKING: 617 * None. 618 */ 619 static void ahci_restore_initial_config(struct ata_host *host) 620 { 621 struct ahci_host_priv *hpriv = host->private_data; 622 unsigned long port_map = hpriv->port_map; 623 void __iomem *mmio = hpriv->mmio; 624 void __iomem *port_mmio; 625 int i; 626 627 writel(hpriv->saved_cap, mmio + HOST_CAP); 628 if (hpriv->saved_cap2) 629 writel(hpriv->saved_cap2, mmio + HOST_CAP2); 630 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); 631 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ 632 633 for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) { 634 port_mmio = __ahci_port_base(hpriv, i); 635 writel(hpriv->saved_port_cap[i], port_mmio + PORT_CMD); 636 } 637 } 638 639 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) 640 { 641 static const int offset[] = { 642 [SCR_STATUS] = PORT_SCR_STAT, 643 [SCR_CONTROL] = PORT_SCR_CTL, 644 [SCR_ERROR] = PORT_SCR_ERR, 645 [SCR_ACTIVE] = PORT_SCR_ACT, 646 [SCR_NOTIFICATION] = PORT_SCR_NTF, 647 }; 648 struct ahci_host_priv *hpriv = ap->host->private_data; 649 650 if (sc_reg < ARRAY_SIZE(offset) && 651 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) 652 return offset[sc_reg]; 653 return 0; 654 } 655 656 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) 657 { 658 void __iomem *port_mmio = ahci_port_base(link->ap); 659 int offset = ahci_scr_offset(link->ap, sc_reg); 660 661 if (offset) { 662 *val = readl(port_mmio + offset); 663 return 0; 664 } 665 return -EINVAL; 666 } 667 668 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) 669 { 670 void __iomem *port_mmio = ahci_port_base(link->ap); 671 int offset = ahci_scr_offset(link->ap, sc_reg); 672 673 if (offset) { 674 writel(val, port_mmio + offset); 675 return 0; 676 } 677 return -EINVAL; 678 } 679 680 void ahci_start_engine(struct ata_port *ap) 681 { 682 void __iomem *port_mmio = ahci_port_base(ap); 683 u32 tmp; 684 685 /* start DMA */ 686 tmp = readl(port_mmio + PORT_CMD); 687 tmp |= PORT_CMD_START; 688 writel(tmp, port_mmio + PORT_CMD); 689 readl(port_mmio + PORT_CMD); /* flush */ 690 } 691 EXPORT_SYMBOL_GPL(ahci_start_engine); 692 693 int ahci_stop_engine(struct ata_port *ap) 694 { 695 void __iomem *port_mmio = ahci_port_base(ap); 696 struct ahci_host_priv *hpriv = ap->host->private_data; 697 u32 tmp; 698 699 /* 700 * On some controllers, stopping a port's DMA engine while the port 701 * is in ALPM state (partial or slumber) results in failures on 702 * subsequent DMA engine starts. For those controllers, put the 703 * port back in active state before stopping its DMA engine. 704 */ 705 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) && 706 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) && 707 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) { 708 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n"); 709 return -EIO; 710 } 711 712 tmp = readl(port_mmio + PORT_CMD); 713 714 /* check if the HBA is idle */ 715 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) 716 return 0; 717 718 /* 719 * Don't try to issue commands but return with ENODEV if the 720 * AHCI controller not available anymore (e.g. due to PCIe hot 721 * unplugging). Otherwise a 500ms delay for each port is added. 722 */ 723 if (tmp == 0xffffffff) { 724 dev_err(ap->host->dev, "AHCI controller unavailable!\n"); 725 return -ENODEV; 726 } 727 728 /* setting HBA to idle */ 729 tmp &= ~PORT_CMD_START; 730 writel(tmp, port_mmio + PORT_CMD); 731 732 /* wait for engine to stop. This could be as long as 500 msec */ 733 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 734 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); 735 if (tmp & PORT_CMD_LIST_ON) 736 return -EIO; 737 738 return 0; 739 } 740 EXPORT_SYMBOL_GPL(ahci_stop_engine); 741 742 void ahci_start_fis_rx(struct ata_port *ap) 743 { 744 void __iomem *port_mmio = ahci_port_base(ap); 745 struct ahci_host_priv *hpriv = ap->host->private_data; 746 struct ahci_port_priv *pp = ap->private_data; 747 u32 tmp; 748 749 /* set FIS registers */ 750 if (hpriv->cap & HOST_CAP_64) 751 writel((pp->cmd_slot_dma >> 16) >> 16, 752 port_mmio + PORT_LST_ADDR_HI); 753 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); 754 755 if (hpriv->cap & HOST_CAP_64) 756 writel((pp->rx_fis_dma >> 16) >> 16, 757 port_mmio + PORT_FIS_ADDR_HI); 758 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); 759 760 /* enable FIS reception */ 761 tmp = readl(port_mmio + PORT_CMD); 762 tmp |= PORT_CMD_FIS_RX; 763 writel(tmp, port_mmio + PORT_CMD); 764 765 /* flush */ 766 readl(port_mmio + PORT_CMD); 767 } 768 EXPORT_SYMBOL_GPL(ahci_start_fis_rx); 769 770 static int ahci_stop_fis_rx(struct ata_port *ap) 771 { 772 void __iomem *port_mmio = ahci_port_base(ap); 773 u32 tmp; 774 775 /* disable FIS reception */ 776 tmp = readl(port_mmio + PORT_CMD); 777 tmp &= ~PORT_CMD_FIS_RX; 778 writel(tmp, port_mmio + PORT_CMD); 779 780 /* wait for completion, spec says 500ms, give it 1000 */ 781 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON, 782 PORT_CMD_FIS_ON, 10, 1000); 783 if (tmp & PORT_CMD_FIS_ON) 784 return -EBUSY; 785 786 return 0; 787 } 788 789 static void ahci_power_up(struct ata_port *ap) 790 { 791 struct ahci_host_priv *hpriv = ap->host->private_data; 792 void __iomem *port_mmio = ahci_port_base(ap); 793 u32 cmd; 794 795 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 796 797 /* spin up device */ 798 if (hpriv->cap & HOST_CAP_SSS) { 799 cmd |= PORT_CMD_SPIN_UP; 800 writel(cmd, port_mmio + PORT_CMD); 801 } 802 803 /* wake up link */ 804 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); 805 } 806 807 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 808 unsigned int hints) 809 { 810 struct ata_port *ap = link->ap; 811 struct ahci_host_priv *hpriv = ap->host->private_data; 812 struct ahci_port_priv *pp = ap->private_data; 813 void __iomem *port_mmio = ahci_port_base(ap); 814 815 if (policy != ATA_LPM_MAX_POWER) { 816 /* wakeup flag only applies to the max power policy */ 817 hints &= ~ATA_LPM_WAKE_ONLY; 818 819 /* 820 * Disable interrupts on Phy Ready. This keeps us from 821 * getting woken up due to spurious phy ready 822 * interrupts. 823 */ 824 pp->intr_mask &= ~PORT_IRQ_PHYRDY; 825 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 826 827 sata_link_scr_lpm(link, policy, false); 828 } 829 830 if (hpriv->cap & HOST_CAP_ALPM) { 831 u32 cmd = readl(port_mmio + PORT_CMD); 832 833 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) { 834 if (!(hints & ATA_LPM_WAKE_ONLY)) 835 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE); 836 cmd |= PORT_CMD_ICC_ACTIVE; 837 838 writel(cmd, port_mmio + PORT_CMD); 839 readl(port_mmio + PORT_CMD); 840 841 /* wait 10ms to be sure we've come out of LPM state */ 842 ata_msleep(ap, 10); 843 844 if (hints & ATA_LPM_WAKE_ONLY) 845 return 0; 846 } else { 847 cmd |= PORT_CMD_ALPE; 848 if (policy == ATA_LPM_MIN_POWER) 849 cmd |= PORT_CMD_ASP; 850 else if (policy == ATA_LPM_MIN_POWER_WITH_PARTIAL) 851 cmd &= ~PORT_CMD_ASP; 852 853 /* write out new cmd value */ 854 writel(cmd, port_mmio + PORT_CMD); 855 } 856 } 857 858 /* set aggressive device sleep */ 859 if ((hpriv->cap2 & HOST_CAP2_SDS) && 860 (hpriv->cap2 & HOST_CAP2_SADM) && 861 (link->device->flags & ATA_DFLAG_DEVSLP)) { 862 if (policy == ATA_LPM_MIN_POWER || 863 policy == ATA_LPM_MIN_POWER_WITH_PARTIAL) 864 ahci_set_aggressive_devslp(ap, true); 865 else 866 ahci_set_aggressive_devslp(ap, false); 867 } 868 869 if (policy == ATA_LPM_MAX_POWER) { 870 sata_link_scr_lpm(link, policy, false); 871 872 /* turn PHYRDY IRQ back on */ 873 pp->intr_mask |= PORT_IRQ_PHYRDY; 874 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 875 } 876 877 return 0; 878 } 879 880 #ifdef CONFIG_PM 881 static void ahci_power_down(struct ata_port *ap) 882 { 883 struct ahci_host_priv *hpriv = ap->host->private_data; 884 void __iomem *port_mmio = ahci_port_base(ap); 885 u32 cmd, scontrol; 886 887 if (!(hpriv->cap & HOST_CAP_SSS)) 888 return; 889 890 /* put device into listen mode, first set PxSCTL.DET to 0 */ 891 scontrol = readl(port_mmio + PORT_SCR_CTL); 892 scontrol &= ~0xf; 893 writel(scontrol, port_mmio + PORT_SCR_CTL); 894 895 /* then set PxCMD.SUD to 0 */ 896 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 897 cmd &= ~PORT_CMD_SPIN_UP; 898 writel(cmd, port_mmio + PORT_CMD); 899 } 900 #endif 901 902 static void ahci_start_port(struct ata_port *ap) 903 { 904 struct ahci_host_priv *hpriv = ap->host->private_data; 905 struct ahci_port_priv *pp = ap->private_data; 906 struct ata_link *link; 907 struct ahci_em_priv *emp; 908 ssize_t rc; 909 int i; 910 911 /* enable FIS reception */ 912 ahci_start_fis_rx(ap); 913 914 /* enable DMA */ 915 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE)) 916 hpriv->start_engine(ap); 917 918 /* turn on LEDs */ 919 if (ap->flags & ATA_FLAG_EM) { 920 ata_for_each_link(link, ap, EDGE) { 921 emp = &pp->em_priv[link->pmp]; 922 923 /* EM Transmit bit maybe busy during init */ 924 for (i = 0; i < EM_MAX_RETRY; i++) { 925 rc = ap->ops->transmit_led_message(ap, 926 emp->led_state, 927 4); 928 /* 929 * If busy, give a breather but do not 930 * release EH ownership by using msleep() 931 * instead of ata_msleep(). EM Transmit 932 * bit is busy for the whole host and 933 * releasing ownership will cause other 934 * ports to fail the same way. 935 */ 936 if (rc == -EBUSY) 937 msleep(1); 938 else 939 break; 940 } 941 } 942 } 943 944 if (ap->flags & ATA_FLAG_SW_ACTIVITY) 945 ata_for_each_link(link, ap, EDGE) 946 ahci_init_sw_activity(link); 947 948 } 949 950 static int ahci_deinit_port(struct ata_port *ap, const char **emsg) 951 { 952 int rc; 953 struct ahci_host_priv *hpriv = ap->host->private_data; 954 955 /* disable DMA */ 956 rc = hpriv->stop_engine(ap); 957 if (rc) { 958 *emsg = "failed to stop engine"; 959 return rc; 960 } 961 962 /* disable FIS reception */ 963 rc = ahci_stop_fis_rx(ap); 964 if (rc) { 965 *emsg = "failed stop FIS RX"; 966 return rc; 967 } 968 969 return 0; 970 } 971 972 int ahci_reset_controller(struct ata_host *host) 973 { 974 struct ahci_host_priv *hpriv = host->private_data; 975 void __iomem *mmio = hpriv->mmio; 976 u32 tmp; 977 978 /* we must be in AHCI mode, before using anything 979 * AHCI-specific, such as HOST_RESET. 980 */ 981 ahci_enable_ahci(mmio); 982 983 /* global controller reset */ 984 if (!ahci_skip_host_reset) { 985 tmp = readl(mmio + HOST_CTL); 986 if ((tmp & HOST_RESET) == 0) { 987 writel(tmp | HOST_RESET, mmio + HOST_CTL); 988 readl(mmio + HOST_CTL); /* flush */ 989 } 990 991 /* 992 * to perform host reset, OS should set HOST_RESET 993 * and poll until this bit is read to be "0". 994 * reset must complete within 1 second, or 995 * the hardware should be considered fried. 996 */ 997 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET, 998 HOST_RESET, 10, 1000); 999 1000 if (tmp & HOST_RESET) { 1001 dev_err(host->dev, "controller reset failed (0x%x)\n", 1002 tmp); 1003 return -EIO; 1004 } 1005 1006 /* turn on AHCI mode */ 1007 ahci_enable_ahci(mmio); 1008 1009 /* Some registers might be cleared on reset. Restore 1010 * initial values. 1011 */ 1012 if (!(hpriv->flags & AHCI_HFLAG_NO_WRITE_TO_RO)) 1013 ahci_restore_initial_config(host); 1014 } else 1015 dev_info(host->dev, "skipping global host reset\n"); 1016 1017 return 0; 1018 } 1019 EXPORT_SYMBOL_GPL(ahci_reset_controller); 1020 1021 static void ahci_sw_activity(struct ata_link *link) 1022 { 1023 struct ata_port *ap = link->ap; 1024 struct ahci_port_priv *pp = ap->private_data; 1025 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1026 1027 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY)) 1028 return; 1029 1030 emp->activity++; 1031 if (!timer_pending(&emp->timer)) 1032 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10)); 1033 } 1034 1035 static void ahci_sw_activity_blink(struct timer_list *t) 1036 { 1037 struct ahci_em_priv *emp = from_timer(emp, t, timer); 1038 struct ata_link *link = emp->link; 1039 struct ata_port *ap = link->ap; 1040 1041 unsigned long led_message = emp->led_state; 1042 u32 activity_led_state; 1043 unsigned long flags; 1044 1045 led_message &= EM_MSG_LED_VALUE; 1046 led_message |= ap->port_no | (link->pmp << 8); 1047 1048 /* check to see if we've had activity. If so, 1049 * toggle state of LED and reset timer. If not, 1050 * turn LED to desired idle state. 1051 */ 1052 spin_lock_irqsave(ap->lock, flags); 1053 if (emp->saved_activity != emp->activity) { 1054 emp->saved_activity = emp->activity; 1055 /* get the current LED state */ 1056 activity_led_state = led_message & EM_MSG_LED_VALUE_ON; 1057 1058 if (activity_led_state) 1059 activity_led_state = 0; 1060 else 1061 activity_led_state = 1; 1062 1063 /* clear old state */ 1064 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 1065 1066 /* toggle state */ 1067 led_message |= (activity_led_state << 16); 1068 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100)); 1069 } else { 1070 /* switch to idle */ 1071 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 1072 if (emp->blink_policy == BLINK_OFF) 1073 led_message |= (1 << 16); 1074 } 1075 spin_unlock_irqrestore(ap->lock, flags); 1076 ap->ops->transmit_led_message(ap, led_message, 4); 1077 } 1078 1079 static void ahci_init_sw_activity(struct ata_link *link) 1080 { 1081 struct ata_port *ap = link->ap; 1082 struct ahci_port_priv *pp = ap->private_data; 1083 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1084 1085 /* init activity stats, setup timer */ 1086 emp->saved_activity = emp->activity = 0; 1087 emp->link = link; 1088 timer_setup(&emp->timer, ahci_sw_activity_blink, 0); 1089 1090 /* check our blink policy and set flag for link if it's enabled */ 1091 if (emp->blink_policy) 1092 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1093 } 1094 1095 int ahci_reset_em(struct ata_host *host) 1096 { 1097 struct ahci_host_priv *hpriv = host->private_data; 1098 void __iomem *mmio = hpriv->mmio; 1099 u32 em_ctl; 1100 1101 em_ctl = readl(mmio + HOST_EM_CTL); 1102 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST)) 1103 return -EINVAL; 1104 1105 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL); 1106 return 0; 1107 } 1108 EXPORT_SYMBOL_GPL(ahci_reset_em); 1109 1110 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 1111 ssize_t size) 1112 { 1113 struct ahci_host_priv *hpriv = ap->host->private_data; 1114 struct ahci_port_priv *pp = ap->private_data; 1115 void __iomem *mmio = hpriv->mmio; 1116 u32 em_ctl; 1117 u32 message[] = {0, 0}; 1118 unsigned long flags; 1119 int pmp; 1120 struct ahci_em_priv *emp; 1121 1122 /* get the slot number from the message */ 1123 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1124 if (pmp < EM_MAX_SLOTS) 1125 emp = &pp->em_priv[pmp]; 1126 else 1127 return -EINVAL; 1128 1129 ahci_rpm_get_port(ap); 1130 spin_lock_irqsave(ap->lock, flags); 1131 1132 /* 1133 * if we are still busy transmitting a previous message, 1134 * do not allow 1135 */ 1136 em_ctl = readl(mmio + HOST_EM_CTL); 1137 if (em_ctl & EM_CTL_TM) { 1138 spin_unlock_irqrestore(ap->lock, flags); 1139 ahci_rpm_put_port(ap); 1140 return -EBUSY; 1141 } 1142 1143 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) { 1144 /* 1145 * create message header - this is all zero except for 1146 * the message size, which is 4 bytes. 1147 */ 1148 message[0] |= (4 << 8); 1149 1150 /* ignore 0:4 of byte zero, fill in port info yourself */ 1151 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no); 1152 1153 /* write message to EM_LOC */ 1154 writel(message[0], mmio + hpriv->em_loc); 1155 writel(message[1], mmio + hpriv->em_loc+4); 1156 1157 /* 1158 * tell hardware to transmit the message 1159 */ 1160 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 1161 } 1162 1163 /* save off new led state for port/slot */ 1164 emp->led_state = state; 1165 1166 spin_unlock_irqrestore(ap->lock, flags); 1167 ahci_rpm_put_port(ap); 1168 1169 return size; 1170 } 1171 1172 static ssize_t ahci_led_show(struct ata_port *ap, char *buf) 1173 { 1174 struct ahci_port_priv *pp = ap->private_data; 1175 struct ata_link *link; 1176 struct ahci_em_priv *emp; 1177 int rc = 0; 1178 1179 ata_for_each_link(link, ap, EDGE) { 1180 emp = &pp->em_priv[link->pmp]; 1181 rc += sprintf(buf, "%lx\n", emp->led_state); 1182 } 1183 return rc; 1184 } 1185 1186 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 1187 size_t size) 1188 { 1189 unsigned int state; 1190 int pmp; 1191 struct ahci_port_priv *pp = ap->private_data; 1192 struct ahci_em_priv *emp; 1193 1194 if (kstrtouint(buf, 0, &state) < 0) 1195 return -EINVAL; 1196 1197 /* get the slot number from the message */ 1198 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1199 if (pmp < EM_MAX_SLOTS) { 1200 pmp = array_index_nospec(pmp, EM_MAX_SLOTS); 1201 emp = &pp->em_priv[pmp]; 1202 } else { 1203 return -EINVAL; 1204 } 1205 1206 /* mask off the activity bits if we are in sw_activity 1207 * mode, user should turn off sw_activity before setting 1208 * activity led through em_message 1209 */ 1210 if (emp->blink_policy) 1211 state &= ~EM_MSG_LED_VALUE_ACTIVITY; 1212 1213 return ap->ops->transmit_led_message(ap, state, size); 1214 } 1215 1216 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val) 1217 { 1218 struct ata_link *link = dev->link; 1219 struct ata_port *ap = link->ap; 1220 struct ahci_port_priv *pp = ap->private_data; 1221 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1222 u32 port_led_state = emp->led_state; 1223 1224 /* save the desired Activity LED behavior */ 1225 if (val == OFF) { 1226 /* clear LFLAG */ 1227 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY); 1228 1229 /* set the LED to OFF */ 1230 port_led_state &= EM_MSG_LED_VALUE_OFF; 1231 port_led_state |= (ap->port_no | (link->pmp << 8)); 1232 ap->ops->transmit_led_message(ap, port_led_state, 4); 1233 } else { 1234 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1235 if (val == BLINK_OFF) { 1236 /* set LED to ON for idle */ 1237 port_led_state &= EM_MSG_LED_VALUE_OFF; 1238 port_led_state |= (ap->port_no | (link->pmp << 8)); 1239 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */ 1240 ap->ops->transmit_led_message(ap, port_led_state, 4); 1241 } 1242 } 1243 emp->blink_policy = val; 1244 return 0; 1245 } 1246 1247 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf) 1248 { 1249 struct ata_link *link = dev->link; 1250 struct ata_port *ap = link->ap; 1251 struct ahci_port_priv *pp = ap->private_data; 1252 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1253 1254 /* display the saved value of activity behavior for this 1255 * disk. 1256 */ 1257 return sprintf(buf, "%d\n", emp->blink_policy); 1258 } 1259 1260 static void ahci_port_init(struct device *dev, struct ata_port *ap, 1261 int port_no, void __iomem *mmio, 1262 void __iomem *port_mmio) 1263 { 1264 struct ahci_host_priv *hpriv = ap->host->private_data; 1265 const char *emsg = NULL; 1266 int rc; 1267 u32 tmp; 1268 1269 /* make sure port is not active */ 1270 rc = ahci_deinit_port(ap, &emsg); 1271 if (rc) 1272 dev_warn(dev, "%s (%d)\n", emsg, rc); 1273 1274 /* clear SError */ 1275 tmp = readl(port_mmio + PORT_SCR_ERR); 1276 dev_dbg(dev, "PORT_SCR_ERR 0x%x\n", tmp); 1277 writel(tmp, port_mmio + PORT_SCR_ERR); 1278 1279 /* clear port IRQ */ 1280 tmp = readl(port_mmio + PORT_IRQ_STAT); 1281 dev_dbg(dev, "PORT_IRQ_STAT 0x%x\n", tmp); 1282 if (tmp) 1283 writel(tmp, port_mmio + PORT_IRQ_STAT); 1284 1285 writel(1 << port_no, mmio + HOST_IRQ_STAT); 1286 1287 /* mark esata ports */ 1288 tmp = readl(port_mmio + PORT_CMD); 1289 if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS)) 1290 ap->pflags |= ATA_PFLAG_EXTERNAL; 1291 } 1292 1293 void ahci_init_controller(struct ata_host *host) 1294 { 1295 struct ahci_host_priv *hpriv = host->private_data; 1296 void __iomem *mmio = hpriv->mmio; 1297 int i; 1298 void __iomem *port_mmio; 1299 u32 tmp; 1300 1301 for (i = 0; i < host->n_ports; i++) { 1302 struct ata_port *ap = host->ports[i]; 1303 1304 port_mmio = ahci_port_base(ap); 1305 if (ata_port_is_dummy(ap)) 1306 continue; 1307 1308 ahci_port_init(host->dev, ap, i, mmio, port_mmio); 1309 } 1310 1311 tmp = readl(mmio + HOST_CTL); 1312 dev_dbg(host->dev, "HOST_CTL 0x%x\n", tmp); 1313 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); 1314 tmp = readl(mmio + HOST_CTL); 1315 dev_dbg(host->dev, "HOST_CTL 0x%x\n", tmp); 1316 } 1317 EXPORT_SYMBOL_GPL(ahci_init_controller); 1318 1319 static void ahci_dev_config(struct ata_device *dev) 1320 { 1321 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data; 1322 1323 if (hpriv->flags & AHCI_HFLAG_SECT255) { 1324 dev->max_sectors = 255; 1325 ata_dev_info(dev, 1326 "SB600 AHCI: limiting to 255 sectors per cmd\n"); 1327 } 1328 } 1329 1330 unsigned int ahci_dev_classify(struct ata_port *ap) 1331 { 1332 void __iomem *port_mmio = ahci_port_base(ap); 1333 struct ata_taskfile tf; 1334 u32 tmp; 1335 1336 tmp = readl(port_mmio + PORT_SIG); 1337 tf.lbah = (tmp >> 24) & 0xff; 1338 tf.lbam = (tmp >> 16) & 0xff; 1339 tf.lbal = (tmp >> 8) & 0xff; 1340 tf.nsect = (tmp) & 0xff; 1341 1342 return ata_port_classify(ap, &tf); 1343 } 1344 EXPORT_SYMBOL_GPL(ahci_dev_classify); 1345 1346 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 1347 u32 opts) 1348 { 1349 dma_addr_t cmd_tbl_dma; 1350 1351 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; 1352 1353 pp->cmd_slot[tag].opts = cpu_to_le32(opts); 1354 pp->cmd_slot[tag].status = 0; 1355 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); 1356 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); 1357 } 1358 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot); 1359 1360 int ahci_kick_engine(struct ata_port *ap) 1361 { 1362 void __iomem *port_mmio = ahci_port_base(ap); 1363 struct ahci_host_priv *hpriv = ap->host->private_data; 1364 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1365 u32 tmp; 1366 int busy, rc; 1367 1368 /* stop engine */ 1369 rc = hpriv->stop_engine(ap); 1370 if (rc) 1371 goto out_restart; 1372 1373 /* need to do CLO? 1374 * always do CLO if PMP is attached (AHCI-1.3 9.2) 1375 */ 1376 busy = status & (ATA_BUSY | ATA_DRQ); 1377 if (!busy && !sata_pmp_attached(ap)) { 1378 rc = 0; 1379 goto out_restart; 1380 } 1381 1382 if (!(hpriv->cap & HOST_CAP_CLO)) { 1383 rc = -EOPNOTSUPP; 1384 goto out_restart; 1385 } 1386 1387 /* perform CLO */ 1388 tmp = readl(port_mmio + PORT_CMD); 1389 tmp |= PORT_CMD_CLO; 1390 writel(tmp, port_mmio + PORT_CMD); 1391 1392 rc = 0; 1393 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 1394 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); 1395 if (tmp & PORT_CMD_CLO) 1396 rc = -EIO; 1397 1398 /* restart engine */ 1399 out_restart: 1400 hpriv->start_engine(ap); 1401 return rc; 1402 } 1403 EXPORT_SYMBOL_GPL(ahci_kick_engine); 1404 1405 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, 1406 struct ata_taskfile *tf, int is_cmd, u16 flags, 1407 unsigned long timeout_msec) 1408 { 1409 const u32 cmd_fis_len = 5; /* five dwords */ 1410 struct ahci_port_priv *pp = ap->private_data; 1411 void __iomem *port_mmio = ahci_port_base(ap); 1412 u8 *fis = pp->cmd_tbl; 1413 u32 tmp; 1414 1415 /* prep the command */ 1416 ata_tf_to_fis(tf, pmp, is_cmd, fis); 1417 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); 1418 1419 /* set port value for softreset of Port Multiplier */ 1420 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) { 1421 tmp = readl(port_mmio + PORT_FBS); 1422 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); 1423 tmp |= pmp << PORT_FBS_DEV_OFFSET; 1424 writel(tmp, port_mmio + PORT_FBS); 1425 pp->fbs_last_dev = pmp; 1426 } 1427 1428 /* issue & wait */ 1429 writel(1, port_mmio + PORT_CMD_ISSUE); 1430 1431 if (timeout_msec) { 1432 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE, 1433 0x1, 0x1, 1, timeout_msec); 1434 if (tmp & 0x1) { 1435 ahci_kick_engine(ap); 1436 return -EBUSY; 1437 } 1438 } else 1439 readl(port_mmio + PORT_CMD_ISSUE); /* flush */ 1440 1441 return 0; 1442 } 1443 1444 int ahci_do_softreset(struct ata_link *link, unsigned int *class, 1445 int pmp, unsigned long deadline, 1446 int (*check_ready)(struct ata_link *link)) 1447 { 1448 struct ata_port *ap = link->ap; 1449 struct ahci_host_priv *hpriv = ap->host->private_data; 1450 struct ahci_port_priv *pp = ap->private_data; 1451 const char *reason = NULL; 1452 unsigned long now, msecs; 1453 struct ata_taskfile tf; 1454 bool fbs_disabled = false; 1455 int rc; 1456 1457 /* prepare for SRST (AHCI-1.1 10.4.1) */ 1458 rc = ahci_kick_engine(ap); 1459 if (rc && rc != -EOPNOTSUPP) 1460 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc); 1461 1462 /* 1463 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall 1464 * clear PxFBS.EN to '0' prior to issuing software reset to devices 1465 * that is attached to port multiplier. 1466 */ 1467 if (!ata_is_host_link(link) && pp->fbs_enabled) { 1468 ahci_disable_fbs(ap); 1469 fbs_disabled = true; 1470 } 1471 1472 ata_tf_init(link->device, &tf); 1473 1474 /* issue the first H2D Register FIS */ 1475 msecs = 0; 1476 now = jiffies; 1477 if (time_after(deadline, now)) 1478 msecs = jiffies_to_msecs(deadline - now); 1479 1480 tf.ctl |= ATA_SRST; 1481 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, 1482 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { 1483 rc = -EIO; 1484 reason = "1st FIS failed"; 1485 goto fail; 1486 } 1487 1488 /* spec says at least 5us, but be generous and sleep for 1ms */ 1489 ata_msleep(ap, 1); 1490 1491 /* issue the second H2D Register FIS */ 1492 tf.ctl &= ~ATA_SRST; 1493 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); 1494 1495 /* wait for link to become ready */ 1496 rc = ata_wait_after_reset(link, deadline, check_ready); 1497 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) { 1498 /* 1499 * Workaround for cases where link online status can't 1500 * be trusted. Treat device readiness timeout as link 1501 * offline. 1502 */ 1503 ata_link_info(link, "device not ready, treating as offline\n"); 1504 *class = ATA_DEV_NONE; 1505 } else if (rc) { 1506 /* link occupied, -ENODEV too is an error */ 1507 reason = "device not ready"; 1508 goto fail; 1509 } else 1510 *class = ahci_dev_classify(ap); 1511 1512 /* re-enable FBS if disabled before */ 1513 if (fbs_disabled) 1514 ahci_enable_fbs(ap); 1515 1516 return 0; 1517 1518 fail: 1519 ata_link_err(link, "softreset failed (%s)\n", reason); 1520 return rc; 1521 } 1522 1523 int ahci_check_ready(struct ata_link *link) 1524 { 1525 void __iomem *port_mmio = ahci_port_base(link->ap); 1526 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1527 1528 return ata_check_ready(status); 1529 } 1530 EXPORT_SYMBOL_GPL(ahci_check_ready); 1531 1532 static int ahci_softreset(struct ata_link *link, unsigned int *class, 1533 unsigned long deadline) 1534 { 1535 int pmp = sata_srst_pmp(link); 1536 1537 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready); 1538 } 1539 EXPORT_SYMBOL_GPL(ahci_do_softreset); 1540 1541 static int ahci_bad_pmp_check_ready(struct ata_link *link) 1542 { 1543 void __iomem *port_mmio = ahci_port_base(link->ap); 1544 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1545 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT); 1546 1547 /* 1548 * There is no need to check TFDATA if BAD PMP is found due to HW bug, 1549 * which can save timeout delay. 1550 */ 1551 if (irq_status & PORT_IRQ_BAD_PMP) 1552 return -EIO; 1553 1554 return ata_check_ready(status); 1555 } 1556 1557 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class, 1558 unsigned long deadline) 1559 { 1560 struct ata_port *ap = link->ap; 1561 void __iomem *port_mmio = ahci_port_base(ap); 1562 int pmp = sata_srst_pmp(link); 1563 int rc; 1564 u32 irq_sts; 1565 1566 rc = ahci_do_softreset(link, class, pmp, deadline, 1567 ahci_bad_pmp_check_ready); 1568 1569 /* 1570 * Soft reset fails with IPMS set when PMP is enabled but 1571 * SATA HDD/ODD is connected to SATA port, do soft reset 1572 * again to port 0. 1573 */ 1574 if (rc == -EIO) { 1575 irq_sts = readl(port_mmio + PORT_IRQ_STAT); 1576 if (irq_sts & PORT_IRQ_BAD_PMP) { 1577 ata_link_warn(link, 1578 "applying PMP SRST workaround " 1579 "and retrying\n"); 1580 rc = ahci_do_softreset(link, class, 0, deadline, 1581 ahci_check_ready); 1582 } 1583 } 1584 1585 return rc; 1586 } 1587 1588 int ahci_do_hardreset(struct ata_link *link, unsigned int *class, 1589 unsigned long deadline, bool *online) 1590 { 1591 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 1592 struct ata_port *ap = link->ap; 1593 struct ahci_port_priv *pp = ap->private_data; 1594 struct ahci_host_priv *hpriv = ap->host->private_data; 1595 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 1596 struct ata_taskfile tf; 1597 int rc; 1598 1599 hpriv->stop_engine(ap); 1600 1601 /* clear D2H reception area to properly wait for D2H FIS */ 1602 ata_tf_init(link->device, &tf); 1603 tf.status = ATA_BUSY; 1604 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 1605 1606 rc = sata_link_hardreset(link, timing, deadline, online, 1607 ahci_check_ready); 1608 1609 hpriv->start_engine(ap); 1610 1611 if (*online) 1612 *class = ahci_dev_classify(ap); 1613 1614 return rc; 1615 } 1616 EXPORT_SYMBOL_GPL(ahci_do_hardreset); 1617 1618 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 1619 unsigned long deadline) 1620 { 1621 bool online; 1622 1623 return ahci_do_hardreset(link, class, deadline, &online); 1624 } 1625 1626 static void ahci_postreset(struct ata_link *link, unsigned int *class) 1627 { 1628 struct ata_port *ap = link->ap; 1629 void __iomem *port_mmio = ahci_port_base(ap); 1630 u32 new_tmp, tmp; 1631 1632 ata_std_postreset(link, class); 1633 1634 /* Make sure port's ATAPI bit is set appropriately */ 1635 new_tmp = tmp = readl(port_mmio + PORT_CMD); 1636 if (*class == ATA_DEV_ATAPI) 1637 new_tmp |= PORT_CMD_ATAPI; 1638 else 1639 new_tmp &= ~PORT_CMD_ATAPI; 1640 if (new_tmp != tmp) { 1641 writel(new_tmp, port_mmio + PORT_CMD); 1642 readl(port_mmio + PORT_CMD); /* flush */ 1643 } 1644 } 1645 1646 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) 1647 { 1648 struct scatterlist *sg; 1649 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; 1650 unsigned int si; 1651 1652 /* 1653 * Next, the S/G list. 1654 */ 1655 for_each_sg(qc->sg, sg, qc->n_elem, si) { 1656 dma_addr_t addr = sg_dma_address(sg); 1657 u32 sg_len = sg_dma_len(sg); 1658 1659 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); 1660 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); 1661 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); 1662 } 1663 1664 return si; 1665 } 1666 1667 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc) 1668 { 1669 struct ata_port *ap = qc->ap; 1670 struct ahci_port_priv *pp = ap->private_data; 1671 1672 if (!sata_pmp_attached(ap) || pp->fbs_enabled) 1673 return ata_std_qc_defer(qc); 1674 else 1675 return sata_pmp_qc_defer_cmd_switch(qc); 1676 } 1677 1678 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc) 1679 { 1680 struct ata_port *ap = qc->ap; 1681 struct ahci_port_priv *pp = ap->private_data; 1682 int is_atapi = ata_is_atapi(qc->tf.protocol); 1683 void *cmd_tbl; 1684 u32 opts; 1685 const u32 cmd_fis_len = 5; /* five dwords */ 1686 unsigned int n_elem; 1687 1688 /* 1689 * Fill in command table information. First, the header, 1690 * a SATA Register - Host to Device command FIS. 1691 */ 1692 cmd_tbl = pp->cmd_tbl + qc->hw_tag * AHCI_CMD_TBL_SZ; 1693 1694 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); 1695 if (is_atapi) { 1696 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); 1697 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); 1698 } 1699 1700 n_elem = 0; 1701 if (qc->flags & ATA_QCFLAG_DMAMAP) 1702 n_elem = ahci_fill_sg(qc, cmd_tbl); 1703 1704 /* 1705 * Fill in command slot information. 1706 */ 1707 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); 1708 if (qc->tf.flags & ATA_TFLAG_WRITE) 1709 opts |= AHCI_CMD_WRITE; 1710 if (is_atapi) 1711 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; 1712 1713 ahci_fill_cmd_slot(pp, qc->hw_tag, opts); 1714 1715 return AC_ERR_OK; 1716 } 1717 1718 static void ahci_fbs_dec_intr(struct ata_port *ap) 1719 { 1720 struct ahci_port_priv *pp = ap->private_data; 1721 void __iomem *port_mmio = ahci_port_base(ap); 1722 u32 fbs = readl(port_mmio + PORT_FBS); 1723 int retries = 3; 1724 1725 BUG_ON(!pp->fbs_enabled); 1726 1727 /* time to wait for DEC is not specified by AHCI spec, 1728 * add a retry loop for safety. 1729 */ 1730 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS); 1731 fbs = readl(port_mmio + PORT_FBS); 1732 while ((fbs & PORT_FBS_DEC) && retries--) { 1733 udelay(1); 1734 fbs = readl(port_mmio + PORT_FBS); 1735 } 1736 1737 if (fbs & PORT_FBS_DEC) 1738 dev_err(ap->host->dev, "failed to clear device error\n"); 1739 } 1740 1741 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) 1742 { 1743 struct ahci_host_priv *hpriv = ap->host->private_data; 1744 struct ahci_port_priv *pp = ap->private_data; 1745 struct ata_eh_info *host_ehi = &ap->link.eh_info; 1746 struct ata_link *link = NULL; 1747 struct ata_queued_cmd *active_qc; 1748 struct ata_eh_info *active_ehi; 1749 bool fbs_need_dec = false; 1750 u32 serror; 1751 1752 /* determine active link with error */ 1753 if (pp->fbs_enabled) { 1754 void __iomem *port_mmio = ahci_port_base(ap); 1755 u32 fbs = readl(port_mmio + PORT_FBS); 1756 int pmp = fbs >> PORT_FBS_DWE_OFFSET; 1757 1758 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) { 1759 link = &ap->pmp_link[pmp]; 1760 fbs_need_dec = true; 1761 } 1762 1763 } else 1764 ata_for_each_link(link, ap, EDGE) 1765 if (ata_link_active(link)) 1766 break; 1767 1768 if (!link) 1769 link = &ap->link; 1770 1771 active_qc = ata_qc_from_tag(ap, link->active_tag); 1772 active_ehi = &link->eh_info; 1773 1774 /* record irq stat */ 1775 ata_ehi_clear_desc(host_ehi); 1776 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); 1777 1778 /* AHCI needs SError cleared; otherwise, it might lock up */ 1779 ahci_scr_read(&ap->link, SCR_ERROR, &serror); 1780 ahci_scr_write(&ap->link, SCR_ERROR, serror); 1781 host_ehi->serror |= serror; 1782 1783 /* some controllers set IRQ_IF_ERR on device errors, ignore it */ 1784 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) 1785 irq_stat &= ~PORT_IRQ_IF_ERR; 1786 1787 if (irq_stat & PORT_IRQ_TF_ERR) { 1788 /* If qc is active, charge it; otherwise, the active 1789 * link. There's no active qc on NCQ errors. It will 1790 * be determined by EH by reading log page 10h. 1791 */ 1792 if (active_qc) 1793 active_qc->err_mask |= AC_ERR_DEV; 1794 else 1795 active_ehi->err_mask |= AC_ERR_DEV; 1796 1797 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) 1798 host_ehi->serror &= ~SERR_INTERNAL; 1799 } 1800 1801 if (irq_stat & PORT_IRQ_UNK_FIS) { 1802 u32 *unk = pp->rx_fis + RX_FIS_UNK; 1803 1804 active_ehi->err_mask |= AC_ERR_HSM; 1805 active_ehi->action |= ATA_EH_RESET; 1806 ata_ehi_push_desc(active_ehi, 1807 "unknown FIS %08x %08x %08x %08x" , 1808 unk[0], unk[1], unk[2], unk[3]); 1809 } 1810 1811 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) { 1812 active_ehi->err_mask |= AC_ERR_HSM; 1813 active_ehi->action |= ATA_EH_RESET; 1814 ata_ehi_push_desc(active_ehi, "incorrect PMP"); 1815 } 1816 1817 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { 1818 host_ehi->err_mask |= AC_ERR_HOST_BUS; 1819 host_ehi->action |= ATA_EH_RESET; 1820 ata_ehi_push_desc(host_ehi, "host bus error"); 1821 } 1822 1823 if (irq_stat & PORT_IRQ_IF_ERR) { 1824 if (fbs_need_dec) 1825 active_ehi->err_mask |= AC_ERR_DEV; 1826 else { 1827 host_ehi->err_mask |= AC_ERR_ATA_BUS; 1828 host_ehi->action |= ATA_EH_RESET; 1829 } 1830 1831 ata_ehi_push_desc(host_ehi, "interface fatal error"); 1832 } 1833 1834 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { 1835 ata_ehi_hotplugged(host_ehi); 1836 ata_ehi_push_desc(host_ehi, "%s", 1837 irq_stat & PORT_IRQ_CONNECT ? 1838 "connection status changed" : "PHY RDY changed"); 1839 } 1840 1841 /* okay, let's hand over to EH */ 1842 1843 if (irq_stat & PORT_IRQ_FREEZE) 1844 ata_port_freeze(ap); 1845 else if (fbs_need_dec) { 1846 ata_link_abort(link); 1847 ahci_fbs_dec_intr(ap); 1848 } else 1849 ata_port_abort(ap); 1850 } 1851 1852 static void ahci_qc_complete(struct ata_port *ap, void __iomem *port_mmio) 1853 { 1854 struct ata_eh_info *ehi = &ap->link.eh_info; 1855 struct ahci_port_priv *pp = ap->private_data; 1856 u32 qc_active = 0; 1857 int rc; 1858 1859 /* 1860 * pp->active_link is not reliable once FBS is enabled, both 1861 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because 1862 * NCQ and non-NCQ commands may be in flight at the same time. 1863 */ 1864 if (pp->fbs_enabled) { 1865 if (ap->qc_active) { 1866 qc_active = readl(port_mmio + PORT_SCR_ACT); 1867 qc_active |= readl(port_mmio + PORT_CMD_ISSUE); 1868 } 1869 } else { 1870 /* pp->active_link is valid iff any command is in flight */ 1871 if (ap->qc_active && pp->active_link->sactive) 1872 qc_active = readl(port_mmio + PORT_SCR_ACT); 1873 else 1874 qc_active = readl(port_mmio + PORT_CMD_ISSUE); 1875 } 1876 1877 rc = ata_qc_complete_multiple(ap, qc_active); 1878 if (unlikely(rc < 0 && !(ap->pflags & ATA_PFLAG_RESETTING))) { 1879 ehi->err_mask |= AC_ERR_HSM; 1880 ehi->action |= ATA_EH_RESET; 1881 ata_port_freeze(ap); 1882 } 1883 } 1884 1885 static void ahci_handle_port_interrupt(struct ata_port *ap, 1886 void __iomem *port_mmio, u32 status) 1887 { 1888 struct ahci_port_priv *pp = ap->private_data; 1889 struct ahci_host_priv *hpriv = ap->host->private_data; 1890 1891 /* ignore BAD_PMP while resetting */ 1892 if (unlikely(ap->pflags & ATA_PFLAG_RESETTING)) 1893 status &= ~PORT_IRQ_BAD_PMP; 1894 1895 if (sata_lpm_ignore_phy_events(&ap->link)) { 1896 status &= ~PORT_IRQ_PHYRDY; 1897 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG); 1898 } 1899 1900 if (unlikely(status & PORT_IRQ_ERROR)) { 1901 /* 1902 * Before getting the error notification, we may have 1903 * received SDB FISes notifying successful completions. 1904 * Handle these first and then handle the error. 1905 */ 1906 ahci_qc_complete(ap, port_mmio); 1907 ahci_error_intr(ap, status); 1908 return; 1909 } 1910 1911 if (status & PORT_IRQ_SDB_FIS) { 1912 /* If SNotification is available, leave notification 1913 * handling to sata_async_notification(). If not, 1914 * emulate it by snooping SDB FIS RX area. 1915 * 1916 * Snooping FIS RX area is probably cheaper than 1917 * poking SNotification but some constrollers which 1918 * implement SNotification, ICH9 for example, don't 1919 * store AN SDB FIS into receive area. 1920 */ 1921 if (hpriv->cap & HOST_CAP_SNTF) 1922 sata_async_notification(ap); 1923 else { 1924 /* If the 'N' bit in word 0 of the FIS is set, 1925 * we just received asynchronous notification. 1926 * Tell libata about it. 1927 * 1928 * Lack of SNotification should not appear in 1929 * ahci 1.2, so the workaround is unnecessary 1930 * when FBS is enabled. 1931 */ 1932 if (pp->fbs_enabled) 1933 WARN_ON_ONCE(1); 1934 else { 1935 const __le32 *f = pp->rx_fis + RX_FIS_SDB; 1936 u32 f0 = le32_to_cpu(f[0]); 1937 if (f0 & (1 << 15)) 1938 sata_async_notification(ap); 1939 } 1940 } 1941 } 1942 1943 /* Handle completed commands */ 1944 ahci_qc_complete(ap, port_mmio); 1945 } 1946 1947 static void ahci_port_intr(struct ata_port *ap) 1948 { 1949 void __iomem *port_mmio = ahci_port_base(ap); 1950 u32 status; 1951 1952 status = readl(port_mmio + PORT_IRQ_STAT); 1953 writel(status, port_mmio + PORT_IRQ_STAT); 1954 1955 ahci_handle_port_interrupt(ap, port_mmio, status); 1956 } 1957 1958 static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance) 1959 { 1960 struct ata_port *ap = dev_instance; 1961 void __iomem *port_mmio = ahci_port_base(ap); 1962 u32 status; 1963 1964 status = readl(port_mmio + PORT_IRQ_STAT); 1965 writel(status, port_mmio + PORT_IRQ_STAT); 1966 1967 spin_lock(ap->lock); 1968 ahci_handle_port_interrupt(ap, port_mmio, status); 1969 spin_unlock(ap->lock); 1970 1971 return IRQ_HANDLED; 1972 } 1973 1974 u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked) 1975 { 1976 unsigned int i, handled = 0; 1977 1978 for (i = 0; i < host->n_ports; i++) { 1979 struct ata_port *ap; 1980 1981 if (!(irq_masked & (1 << i))) 1982 continue; 1983 1984 ap = host->ports[i]; 1985 if (ap) { 1986 ahci_port_intr(ap); 1987 } else { 1988 if (ata_ratelimit()) 1989 dev_warn(host->dev, 1990 "interrupt on disabled port %u\n", i); 1991 } 1992 1993 handled = 1; 1994 } 1995 1996 return handled; 1997 } 1998 EXPORT_SYMBOL_GPL(ahci_handle_port_intr); 1999 2000 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance) 2001 { 2002 struct ata_host *host = dev_instance; 2003 struct ahci_host_priv *hpriv; 2004 unsigned int rc = 0; 2005 void __iomem *mmio; 2006 u32 irq_stat, irq_masked; 2007 2008 hpriv = host->private_data; 2009 mmio = hpriv->mmio; 2010 2011 /* sigh. 0xffffffff is a valid return from h/w */ 2012 irq_stat = readl(mmio + HOST_IRQ_STAT); 2013 if (!irq_stat) 2014 return IRQ_NONE; 2015 2016 irq_masked = irq_stat & hpriv->port_map; 2017 2018 spin_lock(&host->lock); 2019 2020 rc = ahci_handle_port_intr(host, irq_masked); 2021 2022 /* HOST_IRQ_STAT behaves as level triggered latch meaning that 2023 * it should be cleared after all the port events are cleared; 2024 * otherwise, it will raise a spurious interrupt after each 2025 * valid one. Please read section 10.6.2 of ahci 1.1 for more 2026 * information. 2027 * 2028 * Also, use the unmasked value to clear interrupt as spurious 2029 * pending event on a dummy port might cause screaming IRQ. 2030 */ 2031 writel(irq_stat, mmio + HOST_IRQ_STAT); 2032 2033 spin_unlock(&host->lock); 2034 2035 return IRQ_RETVAL(rc); 2036 } 2037 2038 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) 2039 { 2040 struct ata_port *ap = qc->ap; 2041 void __iomem *port_mmio = ahci_port_base(ap); 2042 struct ahci_port_priv *pp = ap->private_data; 2043 2044 /* Keep track of the currently active link. It will be used 2045 * in completion path to determine whether NCQ phase is in 2046 * progress. 2047 */ 2048 pp->active_link = qc->dev->link; 2049 2050 if (ata_is_ncq(qc->tf.protocol)) 2051 writel(1 << qc->hw_tag, port_mmio + PORT_SCR_ACT); 2052 2053 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) { 2054 u32 fbs = readl(port_mmio + PORT_FBS); 2055 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); 2056 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET; 2057 writel(fbs, port_mmio + PORT_FBS); 2058 pp->fbs_last_dev = qc->dev->link->pmp; 2059 } 2060 2061 writel(1 << qc->hw_tag, port_mmio + PORT_CMD_ISSUE); 2062 2063 ahci_sw_activity(qc->dev->link); 2064 2065 return 0; 2066 } 2067 EXPORT_SYMBOL_GPL(ahci_qc_issue); 2068 2069 static void ahci_qc_fill_rtf(struct ata_queued_cmd *qc) 2070 { 2071 struct ahci_port_priv *pp = qc->ap->private_data; 2072 u8 *rx_fis = pp->rx_fis; 2073 2074 /* 2075 * rtf may already be filled (e.g. for successful NCQ commands). 2076 * If that is the case, we have nothing to do. 2077 */ 2078 if (qc->flags & ATA_QCFLAG_RTF_FILLED) 2079 return; 2080 2081 if (pp->fbs_enabled) 2082 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ; 2083 2084 /* 2085 * After a successful execution of an ATA PIO data-in command, 2086 * the device doesn't send D2H Reg FIS to update the TF and 2087 * the host should take TF and E_Status from the preceding PIO 2088 * Setup FIS. 2089 */ 2090 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE && 2091 !(qc->flags & ATA_QCFLAG_EH)) { 2092 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf); 2093 qc->result_tf.status = (rx_fis + RX_FIS_PIO_SETUP)[15]; 2094 qc->flags |= ATA_QCFLAG_RTF_FILLED; 2095 return; 2096 } 2097 2098 /* 2099 * For NCQ commands, we never get a D2H FIS, so reading the D2H Register 2100 * FIS area of the Received FIS Structure (which contains a copy of the 2101 * last D2H FIS received) will contain an outdated status code. 2102 * For NCQ commands, we instead get a SDB FIS, so read the SDB FIS area 2103 * instead. However, the SDB FIS does not contain the LBA, so we can't 2104 * use the ata_tf_from_fis() helper. 2105 */ 2106 if (ata_is_ncq(qc->tf.protocol)) { 2107 const u8 *fis = rx_fis + RX_FIS_SDB; 2108 2109 /* 2110 * Successful NCQ commands have been filled already. 2111 * A failed NCQ command will read the status here. 2112 * (Note that a failed NCQ command will get a more specific 2113 * error when reading the NCQ Command Error log.) 2114 */ 2115 qc->result_tf.status = fis[2]; 2116 qc->result_tf.error = fis[3]; 2117 qc->flags |= ATA_QCFLAG_RTF_FILLED; 2118 return; 2119 } 2120 2121 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf); 2122 qc->flags |= ATA_QCFLAG_RTF_FILLED; 2123 } 2124 2125 static void ahci_qc_ncq_fill_rtf(struct ata_port *ap, u64 done_mask) 2126 { 2127 struct ahci_port_priv *pp = ap->private_data; 2128 const u8 *fis; 2129 2130 /* No outstanding commands. */ 2131 if (!ap->qc_active) 2132 return; 2133 2134 /* 2135 * FBS not enabled, so read status and error once, since they are shared 2136 * for all QCs. 2137 */ 2138 if (!pp->fbs_enabled) { 2139 u8 status, error; 2140 2141 /* No outstanding NCQ commands. */ 2142 if (!pp->active_link->sactive) 2143 return; 2144 2145 fis = pp->rx_fis + RX_FIS_SDB; 2146 status = fis[2]; 2147 error = fis[3]; 2148 2149 while (done_mask) { 2150 struct ata_queued_cmd *qc; 2151 unsigned int tag = __ffs64(done_mask); 2152 2153 qc = ata_qc_from_tag(ap, tag); 2154 if (qc && ata_is_ncq(qc->tf.protocol)) { 2155 qc->result_tf.status = status; 2156 qc->result_tf.error = error; 2157 qc->flags |= ATA_QCFLAG_RTF_FILLED; 2158 } 2159 done_mask &= ~(1ULL << tag); 2160 } 2161 2162 return; 2163 } 2164 2165 /* 2166 * FBS enabled, so read the status and error for each QC, since the QCs 2167 * can belong to different PMP links. (Each PMP link has its own FIS 2168 * Receive Area.) 2169 */ 2170 while (done_mask) { 2171 struct ata_queued_cmd *qc; 2172 unsigned int tag = __ffs64(done_mask); 2173 2174 qc = ata_qc_from_tag(ap, tag); 2175 if (qc && ata_is_ncq(qc->tf.protocol)) { 2176 fis = pp->rx_fis; 2177 fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ; 2178 fis += RX_FIS_SDB; 2179 qc->result_tf.status = fis[2]; 2180 qc->result_tf.error = fis[3]; 2181 qc->flags |= ATA_QCFLAG_RTF_FILLED; 2182 } 2183 done_mask &= ~(1ULL << tag); 2184 } 2185 } 2186 2187 static void ahci_freeze(struct ata_port *ap) 2188 { 2189 void __iomem *port_mmio = ahci_port_base(ap); 2190 2191 /* turn IRQ off */ 2192 writel(0, port_mmio + PORT_IRQ_MASK); 2193 } 2194 2195 static void ahci_thaw(struct ata_port *ap) 2196 { 2197 struct ahci_host_priv *hpriv = ap->host->private_data; 2198 void __iomem *mmio = hpriv->mmio; 2199 void __iomem *port_mmio = ahci_port_base(ap); 2200 u32 tmp; 2201 struct ahci_port_priv *pp = ap->private_data; 2202 2203 /* clear IRQ */ 2204 tmp = readl(port_mmio + PORT_IRQ_STAT); 2205 writel(tmp, port_mmio + PORT_IRQ_STAT); 2206 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); 2207 2208 /* turn IRQ back on */ 2209 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2210 } 2211 2212 void ahci_error_handler(struct ata_port *ap) 2213 { 2214 struct ahci_host_priv *hpriv = ap->host->private_data; 2215 2216 if (!ata_port_is_frozen(ap)) { 2217 /* restart engine */ 2218 hpriv->stop_engine(ap); 2219 hpriv->start_engine(ap); 2220 } 2221 2222 sata_pmp_error_handler(ap); 2223 2224 if (!ata_dev_enabled(ap->link.device)) 2225 hpriv->stop_engine(ap); 2226 } 2227 EXPORT_SYMBOL_GPL(ahci_error_handler); 2228 2229 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) 2230 { 2231 struct ata_port *ap = qc->ap; 2232 2233 /* make DMA engine forget about the failed command */ 2234 if (qc->flags & ATA_QCFLAG_EH) 2235 ahci_kick_engine(ap); 2236 } 2237 2238 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep) 2239 { 2240 struct ahci_host_priv *hpriv = ap->host->private_data; 2241 void __iomem *port_mmio = ahci_port_base(ap); 2242 struct ata_device *dev = ap->link.device; 2243 u32 devslp, dm, dito, mdat, deto, dito_conf; 2244 int rc; 2245 unsigned int err_mask; 2246 2247 devslp = readl(port_mmio + PORT_DEVSLP); 2248 if (!(devslp & PORT_DEVSLP_DSP)) { 2249 dev_info(ap->host->dev, "port does not support device sleep\n"); 2250 return; 2251 } 2252 2253 /* disable device sleep */ 2254 if (!sleep) { 2255 if (devslp & PORT_DEVSLP_ADSE) { 2256 writel(devslp & ~PORT_DEVSLP_ADSE, 2257 port_mmio + PORT_DEVSLP); 2258 err_mask = ata_dev_set_feature(dev, 2259 SETFEATURES_SATA_DISABLE, 2260 SATA_DEVSLP); 2261 if (err_mask && err_mask != AC_ERR_DEV) 2262 ata_dev_warn(dev, "failed to disable DEVSLP\n"); 2263 } 2264 return; 2265 } 2266 2267 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET; 2268 dito = devslp_idle_timeout / (dm + 1); 2269 if (dito > 0x3ff) 2270 dito = 0x3ff; 2271 2272 dito_conf = (devslp >> PORT_DEVSLP_DITO_OFFSET) & 0x3FF; 2273 2274 /* device sleep was already enabled and same dito */ 2275 if ((devslp & PORT_DEVSLP_ADSE) && (dito_conf == dito)) 2276 return; 2277 2278 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */ 2279 rc = hpriv->stop_engine(ap); 2280 if (rc) 2281 return; 2282 2283 /* Use the nominal value 10 ms if the read MDAT is zero, 2284 * the nominal value of DETO is 20 ms. 2285 */ 2286 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] & 2287 ATA_LOG_DEVSLP_VALID_MASK) { 2288 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] & 2289 ATA_LOG_DEVSLP_MDAT_MASK; 2290 if (!mdat) 2291 mdat = 10; 2292 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO]; 2293 if (!deto) 2294 deto = 20; 2295 } else { 2296 mdat = 10; 2297 deto = 20; 2298 } 2299 2300 /* Make dito, mdat, deto bits to 0s */ 2301 devslp &= ~GENMASK_ULL(24, 2); 2302 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) | 2303 (mdat << PORT_DEVSLP_MDAT_OFFSET) | 2304 (deto << PORT_DEVSLP_DETO_OFFSET) | 2305 PORT_DEVSLP_ADSE); 2306 writel(devslp, port_mmio + PORT_DEVSLP); 2307 2308 hpriv->start_engine(ap); 2309 2310 /* enable device sleep feature for the drive */ 2311 err_mask = ata_dev_set_feature(dev, 2312 SETFEATURES_SATA_ENABLE, 2313 SATA_DEVSLP); 2314 if (err_mask && err_mask != AC_ERR_DEV) 2315 ata_dev_warn(dev, "failed to enable DEVSLP\n"); 2316 } 2317 2318 static void ahci_enable_fbs(struct ata_port *ap) 2319 { 2320 struct ahci_host_priv *hpriv = ap->host->private_data; 2321 struct ahci_port_priv *pp = ap->private_data; 2322 void __iomem *port_mmio = ahci_port_base(ap); 2323 u32 fbs; 2324 int rc; 2325 2326 if (!pp->fbs_supported) 2327 return; 2328 2329 fbs = readl(port_mmio + PORT_FBS); 2330 if (fbs & PORT_FBS_EN) { 2331 pp->fbs_enabled = true; 2332 pp->fbs_last_dev = -1; /* initialization */ 2333 return; 2334 } 2335 2336 rc = hpriv->stop_engine(ap); 2337 if (rc) 2338 return; 2339 2340 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS); 2341 fbs = readl(port_mmio + PORT_FBS); 2342 if (fbs & PORT_FBS_EN) { 2343 dev_info(ap->host->dev, "FBS is enabled\n"); 2344 pp->fbs_enabled = true; 2345 pp->fbs_last_dev = -1; /* initialization */ 2346 } else 2347 dev_err(ap->host->dev, "Failed to enable FBS\n"); 2348 2349 hpriv->start_engine(ap); 2350 } 2351 2352 static void ahci_disable_fbs(struct ata_port *ap) 2353 { 2354 struct ahci_host_priv *hpriv = ap->host->private_data; 2355 struct ahci_port_priv *pp = ap->private_data; 2356 void __iomem *port_mmio = ahci_port_base(ap); 2357 u32 fbs; 2358 int rc; 2359 2360 if (!pp->fbs_supported) 2361 return; 2362 2363 fbs = readl(port_mmio + PORT_FBS); 2364 if ((fbs & PORT_FBS_EN) == 0) { 2365 pp->fbs_enabled = false; 2366 return; 2367 } 2368 2369 rc = hpriv->stop_engine(ap); 2370 if (rc) 2371 return; 2372 2373 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS); 2374 fbs = readl(port_mmio + PORT_FBS); 2375 if (fbs & PORT_FBS_EN) 2376 dev_err(ap->host->dev, "Failed to disable FBS\n"); 2377 else { 2378 dev_info(ap->host->dev, "FBS is disabled\n"); 2379 pp->fbs_enabled = false; 2380 } 2381 2382 hpriv->start_engine(ap); 2383 } 2384 2385 static void ahci_pmp_attach(struct ata_port *ap) 2386 { 2387 void __iomem *port_mmio = ahci_port_base(ap); 2388 struct ahci_port_priv *pp = ap->private_data; 2389 u32 cmd; 2390 2391 cmd = readl(port_mmio + PORT_CMD); 2392 cmd |= PORT_CMD_PMP; 2393 writel(cmd, port_mmio + PORT_CMD); 2394 2395 ahci_enable_fbs(ap); 2396 2397 pp->intr_mask |= PORT_IRQ_BAD_PMP; 2398 2399 /* 2400 * We must not change the port interrupt mask register if the 2401 * port is marked frozen, the value in pp->intr_mask will be 2402 * restored later when the port is thawed. 2403 * 2404 * Note that during initialization, the port is marked as 2405 * frozen since the irq handler is not yet registered. 2406 */ 2407 if (!ata_port_is_frozen(ap)) 2408 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2409 } 2410 2411 static void ahci_pmp_detach(struct ata_port *ap) 2412 { 2413 void __iomem *port_mmio = ahci_port_base(ap); 2414 struct ahci_port_priv *pp = ap->private_data; 2415 u32 cmd; 2416 2417 ahci_disable_fbs(ap); 2418 2419 cmd = readl(port_mmio + PORT_CMD); 2420 cmd &= ~PORT_CMD_PMP; 2421 writel(cmd, port_mmio + PORT_CMD); 2422 2423 pp->intr_mask &= ~PORT_IRQ_BAD_PMP; 2424 2425 /* see comment above in ahci_pmp_attach() */ 2426 if (!ata_port_is_frozen(ap)) 2427 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2428 } 2429 2430 int ahci_port_resume(struct ata_port *ap) 2431 { 2432 ahci_rpm_get_port(ap); 2433 2434 ahci_power_up(ap); 2435 ahci_start_port(ap); 2436 2437 if (sata_pmp_attached(ap)) 2438 ahci_pmp_attach(ap); 2439 else 2440 ahci_pmp_detach(ap); 2441 2442 return 0; 2443 } 2444 EXPORT_SYMBOL_GPL(ahci_port_resume); 2445 2446 #ifdef CONFIG_PM 2447 static void ahci_handle_s2idle(struct ata_port *ap) 2448 { 2449 void __iomem *port_mmio = ahci_port_base(ap); 2450 u32 devslp; 2451 2452 if (pm_suspend_via_firmware()) 2453 return; 2454 devslp = readl(port_mmio + PORT_DEVSLP); 2455 if ((devslp & PORT_DEVSLP_ADSE)) 2456 ata_msleep(ap, devslp_idle_timeout); 2457 } 2458 2459 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) 2460 { 2461 const char *emsg = NULL; 2462 int rc; 2463 2464 rc = ahci_deinit_port(ap, &emsg); 2465 if (rc == 0) 2466 ahci_power_down(ap); 2467 else { 2468 ata_port_err(ap, "%s (%d)\n", emsg, rc); 2469 ata_port_freeze(ap); 2470 } 2471 2472 if (acpi_storage_d3(ap->host->dev)) 2473 ahci_handle_s2idle(ap); 2474 2475 ahci_rpm_put_port(ap); 2476 return rc; 2477 } 2478 #endif 2479 2480 static int ahci_port_start(struct ata_port *ap) 2481 { 2482 struct ahci_host_priv *hpriv = ap->host->private_data; 2483 struct device *dev = ap->host->dev; 2484 struct ahci_port_priv *pp; 2485 void *mem; 2486 dma_addr_t mem_dma; 2487 size_t dma_sz, rx_fis_sz; 2488 2489 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 2490 if (!pp) 2491 return -ENOMEM; 2492 2493 if (ap->host->n_ports > 1) { 2494 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL); 2495 if (!pp->irq_desc) { 2496 devm_kfree(dev, pp); 2497 return -ENOMEM; 2498 } 2499 snprintf(pp->irq_desc, 8, 2500 "%s%d", dev_driver_string(dev), ap->port_no); 2501 } 2502 2503 /* check FBS capability */ 2504 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) { 2505 void __iomem *port_mmio = ahci_port_base(ap); 2506 u32 cmd = readl(port_mmio + PORT_CMD); 2507 if (cmd & PORT_CMD_FBSCP) 2508 pp->fbs_supported = true; 2509 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) { 2510 dev_info(dev, "port %d can do FBS, forcing FBSCP\n", 2511 ap->port_no); 2512 pp->fbs_supported = true; 2513 } else 2514 dev_warn(dev, "port %d is not capable of FBS\n", 2515 ap->port_no); 2516 } 2517 2518 if (pp->fbs_supported) { 2519 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ; 2520 rx_fis_sz = AHCI_RX_FIS_SZ * 16; 2521 } else { 2522 dma_sz = AHCI_PORT_PRIV_DMA_SZ; 2523 rx_fis_sz = AHCI_RX_FIS_SZ; 2524 } 2525 2526 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL); 2527 if (!mem) 2528 return -ENOMEM; 2529 2530 /* 2531 * First item in chunk of DMA memory: 32-slot command table, 2532 * 32 bytes each in size 2533 */ 2534 pp->cmd_slot = mem; 2535 pp->cmd_slot_dma = mem_dma; 2536 2537 mem += AHCI_CMD_SLOT_SZ; 2538 mem_dma += AHCI_CMD_SLOT_SZ; 2539 2540 /* 2541 * Second item: Received-FIS area 2542 */ 2543 pp->rx_fis = mem; 2544 pp->rx_fis_dma = mem_dma; 2545 2546 mem += rx_fis_sz; 2547 mem_dma += rx_fis_sz; 2548 2549 /* 2550 * Third item: data area for storing a single command 2551 * and its scatter-gather table 2552 */ 2553 pp->cmd_tbl = mem; 2554 pp->cmd_tbl_dma = mem_dma; 2555 2556 /* 2557 * Save off initial list of interrupts to be enabled. 2558 * This could be changed later 2559 */ 2560 pp->intr_mask = DEF_PORT_IRQ; 2561 2562 /* 2563 * Switch to per-port locking in case each port has its own MSI vector. 2564 */ 2565 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) { 2566 spin_lock_init(&pp->lock); 2567 ap->lock = &pp->lock; 2568 } 2569 2570 ap->private_data = pp; 2571 2572 /* engage engines, captain */ 2573 return ahci_port_resume(ap); 2574 } 2575 2576 static void ahci_port_stop(struct ata_port *ap) 2577 { 2578 const char *emsg = NULL; 2579 struct ahci_host_priv *hpriv = ap->host->private_data; 2580 void __iomem *host_mmio = hpriv->mmio; 2581 int rc; 2582 2583 /* de-initialize port */ 2584 rc = ahci_deinit_port(ap, &emsg); 2585 if (rc) 2586 ata_port_warn(ap, "%s (%d)\n", emsg, rc); 2587 2588 /* 2589 * Clear GHC.IS to prevent stuck INTx after disabling MSI and 2590 * re-enabling INTx. 2591 */ 2592 writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT); 2593 2594 ahci_rpm_put_port(ap); 2595 } 2596 2597 void ahci_print_info(struct ata_host *host, const char *scc_s) 2598 { 2599 struct ahci_host_priv *hpriv = host->private_data; 2600 u32 vers, cap, cap2, impl, speed; 2601 const char *speed_s; 2602 2603 vers = hpriv->version; 2604 cap = hpriv->cap; 2605 cap2 = hpriv->cap2; 2606 impl = hpriv->port_map; 2607 2608 speed = (cap >> 20) & 0xf; 2609 if (speed == 1) 2610 speed_s = "1.5"; 2611 else if (speed == 2) 2612 speed_s = "3"; 2613 else if (speed == 3) 2614 speed_s = "6"; 2615 else 2616 speed_s = "?"; 2617 2618 dev_info(host->dev, 2619 "AHCI %02x%02x.%02x%02x " 2620 "%u slots %u ports %s Gbps 0x%x impl %s mode\n" 2621 , 2622 2623 (vers >> 24) & 0xff, 2624 (vers >> 16) & 0xff, 2625 (vers >> 8) & 0xff, 2626 vers & 0xff, 2627 2628 ((cap >> 8) & 0x1f) + 1, 2629 (cap & 0x1f) + 1, 2630 speed_s, 2631 impl, 2632 scc_s); 2633 2634 dev_info(host->dev, 2635 "flags: " 2636 "%s%s%s%s%s%s%s" 2637 "%s%s%s%s%s%s%s" 2638 "%s%s%s%s%s%s%s" 2639 "%s%s\n" 2640 , 2641 2642 cap & HOST_CAP_64 ? "64bit " : "", 2643 cap & HOST_CAP_NCQ ? "ncq " : "", 2644 cap & HOST_CAP_SNTF ? "sntf " : "", 2645 cap & HOST_CAP_MPS ? "ilck " : "", 2646 cap & HOST_CAP_SSS ? "stag " : "", 2647 cap & HOST_CAP_ALPM ? "pm " : "", 2648 cap & HOST_CAP_LED ? "led " : "", 2649 cap & HOST_CAP_CLO ? "clo " : "", 2650 cap & HOST_CAP_ONLY ? "only " : "", 2651 cap & HOST_CAP_PMP ? "pmp " : "", 2652 cap & HOST_CAP_FBS ? "fbs " : "", 2653 cap & HOST_CAP_PIO_MULTI ? "pio " : "", 2654 cap & HOST_CAP_SSC ? "slum " : "", 2655 cap & HOST_CAP_PART ? "part " : "", 2656 cap & HOST_CAP_CCC ? "ccc " : "", 2657 cap & HOST_CAP_EMS ? "ems " : "", 2658 cap & HOST_CAP_SXS ? "sxs " : "", 2659 cap2 & HOST_CAP2_DESO ? "deso " : "", 2660 cap2 & HOST_CAP2_SADM ? "sadm " : "", 2661 cap2 & HOST_CAP2_SDS ? "sds " : "", 2662 cap2 & HOST_CAP2_APST ? "apst " : "", 2663 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "", 2664 cap2 & HOST_CAP2_BOH ? "boh " : "" 2665 ); 2666 } 2667 EXPORT_SYMBOL_GPL(ahci_print_info); 2668 2669 void ahci_set_em_messages(struct ahci_host_priv *hpriv, 2670 struct ata_port_info *pi) 2671 { 2672 u8 messages; 2673 void __iomem *mmio = hpriv->mmio; 2674 u32 em_loc = readl(mmio + HOST_EM_LOC); 2675 u32 em_ctl = readl(mmio + HOST_EM_CTL); 2676 2677 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS)) 2678 return; 2679 2680 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16; 2681 2682 if (messages) { 2683 /* store em_loc */ 2684 hpriv->em_loc = ((em_loc >> 16) * 4); 2685 hpriv->em_buf_sz = ((em_loc & 0xff) * 4); 2686 hpriv->em_msg_type = messages; 2687 pi->flags |= ATA_FLAG_EM; 2688 if (!(em_ctl & EM_CTL_ALHD)) 2689 pi->flags |= ATA_FLAG_SW_ACTIVITY; 2690 } 2691 } 2692 EXPORT_SYMBOL_GPL(ahci_set_em_messages); 2693 2694 static int ahci_host_activate_multi_irqs(struct ata_host *host, 2695 const struct scsi_host_template *sht) 2696 { 2697 struct ahci_host_priv *hpriv = host->private_data; 2698 int i, rc; 2699 2700 rc = ata_host_start(host); 2701 if (rc) 2702 return rc; 2703 /* 2704 * Requests IRQs according to AHCI-1.1 when multiple MSIs were 2705 * allocated. That is one MSI per port, starting from @irq. 2706 */ 2707 for (i = 0; i < host->n_ports; i++) { 2708 struct ahci_port_priv *pp = host->ports[i]->private_data; 2709 int irq = hpriv->get_irq_vector(host, i); 2710 2711 /* Do not receive interrupts sent by dummy ports */ 2712 if (!pp) { 2713 disable_irq(irq); 2714 continue; 2715 } 2716 2717 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard, 2718 0, pp->irq_desc, host->ports[i]); 2719 2720 if (rc) 2721 return rc; 2722 ata_port_desc(host->ports[i], "irq %d", irq); 2723 } 2724 2725 return ata_host_register(host, sht); 2726 } 2727 2728 /** 2729 * ahci_host_activate - start AHCI host, request IRQs and register it 2730 * @host: target ATA host 2731 * @sht: scsi_host_template to use when registering the host 2732 * 2733 * LOCKING: 2734 * Inherited from calling layer (may sleep). 2735 * 2736 * RETURNS: 2737 * 0 on success, -errno otherwise. 2738 */ 2739 int ahci_host_activate(struct ata_host *host, const struct scsi_host_template *sht) 2740 { 2741 struct ahci_host_priv *hpriv = host->private_data; 2742 int irq = hpriv->irq; 2743 int rc; 2744 2745 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) { 2746 if (hpriv->irq_handler && 2747 hpriv->irq_handler != ahci_single_level_irq_intr) 2748 dev_warn(host->dev, 2749 "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n"); 2750 if (!hpriv->get_irq_vector) { 2751 dev_err(host->dev, 2752 "AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n"); 2753 return -EIO; 2754 } 2755 2756 rc = ahci_host_activate_multi_irqs(host, sht); 2757 } else { 2758 rc = ata_host_activate(host, irq, hpriv->irq_handler, 2759 IRQF_SHARED, sht); 2760 } 2761 2762 2763 return rc; 2764 } 2765 EXPORT_SYMBOL_GPL(ahci_host_activate); 2766 2767 MODULE_AUTHOR("Jeff Garzik"); 2768 MODULE_DESCRIPTION("Common AHCI SATA low-level routines"); 2769 MODULE_LICENSE("GPL"); 2770