1 /* 2 * ata_piix.c - Intel PATA/SATA controllers 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * 9 * Copyright 2003-2005 Red Hat Inc 10 * Copyright 2003-2005 Jeff Garzik 11 * 12 * 13 * Copyright header from piix.c: 14 * 15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer 16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> 17 * Copyright (C) 2003 Red Hat Inc 18 * 19 * 20 * This program is free software; you can redistribute it and/or modify 21 * it under the terms of the GNU General Public License as published by 22 * the Free Software Foundation; either version 2, or (at your option) 23 * any later version. 24 * 25 * This program is distributed in the hope that it will be useful, 26 * but WITHOUT ANY WARRANTY; without even the implied warranty of 27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 28 * GNU General Public License for more details. 29 * 30 * You should have received a copy of the GNU General Public License 31 * along with this program; see the file COPYING. If not, write to 32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 33 * 34 * 35 * libata documentation is available via 'make {ps|pdf}docs', 36 * as Documentation/DocBook/libata.* 37 * 38 * Hardware documentation available at http://developer.intel.com/ 39 * 40 * Documentation 41 * Publically available from Intel web site. Errata documentation 42 * is also publically available. As an aide to anyone hacking on this 43 * driver the list of errata that are relevant is below, going back to 44 * PIIX4. Older device documentation is now a bit tricky to find. 45 * 46 * The chipsets all follow very much the same design. The orginal Triton 47 * series chipsets do _not_ support independant device timings, but this 48 * is fixed in Triton II. With the odd mobile exception the chips then 49 * change little except in gaining more modes until SATA arrives. This 50 * driver supports only the chips with independant timing (that is those 51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix 52 * for the early chip drivers. 53 * 54 * Errata of note: 55 * 56 * Unfixable 57 * PIIX4 errata #9 - Only on ultra obscure hw 58 * ICH3 errata #13 - Not observed to affect real hw 59 * by Intel 60 * 61 * Things we must deal with 62 * PIIX4 errata #10 - BM IDE hang with non UDMA 63 * (must stop/start dma to recover) 64 * 440MX errata #15 - As PIIX4 errata #10 65 * PIIX4 errata #15 - Must not read control registers 66 * during a PIO transfer 67 * 440MX errata #13 - As PIIX4 errata #15 68 * ICH2 errata #21 - DMA mode 0 doesn't work right 69 * ICH0/1 errata #55 - As ICH2 errata #21 70 * ICH2 spec c #9 - Extra operations needed to handle 71 * drive hotswap [NOT YET SUPPORTED] 72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary 73 * and must be dword aligned 74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 75 * 76 * Should have been BIOS fixed: 77 * 450NX: errata #19 - DMA hangs on old 450NX 78 * 450NX: errata #20 - DMA hangs on old 450NX 79 * 450NX: errata #25 - Corruption with DMA on old 450NX 80 * ICH3 errata #15 - IDE deadlock under high load 81 * (BIOS must set dev 31 fn 0 bit 23) 82 * ICH3 errata #18 - Don't use native mode 83 */ 84 85 #include <linux/kernel.h> 86 #include <linux/module.h> 87 #include <linux/pci.h> 88 #include <linux/init.h> 89 #include <linux/blkdev.h> 90 #include <linux/delay.h> 91 #include <linux/device.h> 92 #include <scsi/scsi_host.h> 93 #include <linux/libata.h> 94 #include <linux/dmi.h> 95 96 #define DRV_NAME "ata_piix" 97 #define DRV_VERSION "2.12" 98 99 enum { 100 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ 101 ICH5_PMR = 0x90, /* port mapping register */ 102 ICH5_PCS = 0x92, /* port control and status */ 103 PIIX_SIDPR_BAR = 5, 104 PIIX_SIDPR_LEN = 16, 105 PIIX_SIDPR_IDX = 0, 106 PIIX_SIDPR_DATA = 4, 107 108 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */ 109 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */ 110 111 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS, 112 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR, 113 114 PIIX_80C_PRI = (1 << 5) | (1 << 4), 115 PIIX_80C_SEC = (1 << 7) | (1 << 6), 116 117 /* constants for mapping table */ 118 P0 = 0, /* port 0 */ 119 P1 = 1, /* port 1 */ 120 P2 = 2, /* port 2 */ 121 P3 = 3, /* port 3 */ 122 IDE = -1, /* IDE */ 123 NA = -2, /* not avaliable */ 124 RV = -3, /* reserved */ 125 126 PIIX_AHCI_DEVICE = 6, 127 128 /* host->flags bits */ 129 PIIX_HOST_BROKEN_SUSPEND = (1 << 24), 130 }; 131 132 enum piix_controller_ids { 133 /* controller IDs */ 134 piix_pata_mwdma, /* PIIX3 MWDMA only */ 135 piix_pata_33, /* PIIX4 at 33Mhz */ 136 ich_pata_33, /* ICH up to UDMA 33 only */ 137 ich_pata_66, /* ICH up to 66 Mhz */ 138 ich_pata_100, /* ICH up to UDMA 100 */ 139 ich5_sata, 140 ich6_sata, 141 ich6m_sata, 142 ich8_sata, 143 ich8_2port_sata, 144 ich8m_apple_sata, /* locks up on second port enable */ 145 tolapai_sata, 146 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */ 147 }; 148 149 struct piix_map_db { 150 const u32 mask; 151 const u16 port_enable; 152 const int map[][4]; 153 }; 154 155 struct piix_host_priv { 156 const int *map; 157 u32 saved_iocfg; 158 void __iomem *sidpr; 159 }; 160 161 static int piix_init_one(struct pci_dev *pdev, 162 const struct pci_device_id *ent); 163 static void piix_remove_one(struct pci_dev *pdev); 164 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline); 165 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev); 166 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev); 167 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev); 168 static int ich_pata_cable_detect(struct ata_port *ap); 169 static u8 piix_vmw_bmdma_status(struct ata_port *ap); 170 static int piix_sidpr_scr_read(struct ata_link *link, 171 unsigned int reg, u32 *val); 172 static int piix_sidpr_scr_write(struct ata_link *link, 173 unsigned int reg, u32 val); 174 #ifdef CONFIG_PM 175 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); 176 static int piix_pci_device_resume(struct pci_dev *pdev); 177 #endif 178 179 static unsigned int in_module_init = 1; 180 181 static const struct pci_device_id piix_pci_tbl[] = { 182 /* Intel PIIX3 for the 430HX etc */ 183 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma }, 184 /* VMware ICH4 */ 185 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw }, 186 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */ 187 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */ 188 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 189 /* Intel PIIX4 */ 190 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 191 /* Intel PIIX4 */ 192 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 193 /* Intel PIIX */ 194 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 195 /* Intel ICH (i810, i815, i840) UDMA 66*/ 196 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 }, 197 /* Intel ICH0 : UDMA 33*/ 198 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 }, 199 /* Intel ICH2M */ 200 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 201 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */ 202 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 203 /* Intel ICH3M */ 204 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 205 /* Intel ICH3 (E7500/1) UDMA 100 */ 206 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 207 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */ 208 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 209 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 210 /* Intel ICH5 */ 211 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 212 /* C-ICH (i810E2) */ 213 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 214 /* ESB (855GME/875P + 6300ESB) UDMA 100 */ 215 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 216 /* ICH6 (and 6) (i915) UDMA 100 */ 217 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 218 /* ICH7/7-R (i945, i975) UDMA 100*/ 219 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 220 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 221 /* ICH8 Mobile PATA Controller */ 222 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 223 224 /* NOTE: The following PCI ids must be kept in sync with the 225 * list in drivers/pci/quirks.c. 226 */ 227 228 /* 82801EB (ICH5) */ 229 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 230 /* 82801EB (ICH5) */ 231 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 232 /* 6300ESB (ICH5 variant with broken PCS present bits) */ 233 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 234 /* 6300ESB pretending RAID */ 235 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 236 /* 82801FB/FW (ICH6/ICH6W) */ 237 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 238 /* 82801FR/FRW (ICH6R/ICH6RW) */ 239 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 240 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented). 241 * Attach iff the controller is in IDE mode. */ 242 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 243 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata }, 244 /* 82801GB/GR/GH (ICH7, identical to ICH6) */ 245 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 246 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */ 247 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata }, 248 /* Enterprise Southbridge 2 (631xESB/632xESB) */ 249 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 250 /* SATA Controller 1 IDE (ICH8) */ 251 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 252 /* SATA Controller 2 IDE (ICH8) */ 253 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 254 /* Mobile SATA Controller IDE (ICH8M), Apple */ 255 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata }, 256 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata }, 257 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata }, 258 /* Mobile SATA Controller IDE (ICH8M) */ 259 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 260 /* SATA Controller IDE (ICH9) */ 261 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 262 /* SATA Controller IDE (ICH9) */ 263 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 264 /* SATA Controller IDE (ICH9) */ 265 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 266 /* SATA Controller IDE (ICH9M) */ 267 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 268 /* SATA Controller IDE (ICH9M) */ 269 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 270 /* SATA Controller IDE (ICH9M) */ 271 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 272 /* SATA Controller IDE (Tolapai) */ 273 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata }, 274 /* SATA Controller IDE (ICH10) */ 275 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 276 /* SATA Controller IDE (ICH10) */ 277 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 278 /* SATA Controller IDE (ICH10) */ 279 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 280 /* SATA Controller IDE (ICH10) */ 281 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 282 /* SATA Controller IDE (PCH) */ 283 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 284 /* SATA Controller IDE (PCH) */ 285 { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 286 /* SATA Controller IDE (PCH) */ 287 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 288 /* SATA Controller IDE (PCH) */ 289 { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 290 /* SATA Controller IDE (PCH) */ 291 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 292 /* SATA Controller IDE (PCH) */ 293 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 294 { } /* terminate list */ 295 }; 296 297 static struct pci_driver piix_pci_driver = { 298 .name = DRV_NAME, 299 .id_table = piix_pci_tbl, 300 .probe = piix_init_one, 301 .remove = piix_remove_one, 302 #ifdef CONFIG_PM 303 .suspend = piix_pci_device_suspend, 304 .resume = piix_pci_device_resume, 305 #endif 306 }; 307 308 static struct scsi_host_template piix_sht = { 309 ATA_BMDMA_SHT(DRV_NAME), 310 }; 311 312 static struct ata_port_operations piix_pata_ops = { 313 .inherits = &ata_bmdma32_port_ops, 314 .cable_detect = ata_cable_40wire, 315 .set_piomode = piix_set_piomode, 316 .set_dmamode = piix_set_dmamode, 317 .prereset = piix_pata_prereset, 318 }; 319 320 static struct ata_port_operations piix_vmw_ops = { 321 .inherits = &piix_pata_ops, 322 .bmdma_status = piix_vmw_bmdma_status, 323 }; 324 325 static struct ata_port_operations ich_pata_ops = { 326 .inherits = &piix_pata_ops, 327 .cable_detect = ich_pata_cable_detect, 328 .set_dmamode = ich_set_dmamode, 329 }; 330 331 static struct ata_port_operations piix_sata_ops = { 332 .inherits = &ata_bmdma_port_ops, 333 }; 334 335 static struct ata_port_operations piix_sidpr_sata_ops = { 336 .inherits = &piix_sata_ops, 337 .hardreset = sata_std_hardreset, 338 .scr_read = piix_sidpr_scr_read, 339 .scr_write = piix_sidpr_scr_write, 340 }; 341 342 static const struct piix_map_db ich5_map_db = { 343 .mask = 0x7, 344 .port_enable = 0x3, 345 .map = { 346 /* PM PS SM SS MAP */ 347 { P0, NA, P1, NA }, /* 000b */ 348 { P1, NA, P0, NA }, /* 001b */ 349 { RV, RV, RV, RV }, 350 { RV, RV, RV, RV }, 351 { P0, P1, IDE, IDE }, /* 100b */ 352 { P1, P0, IDE, IDE }, /* 101b */ 353 { IDE, IDE, P0, P1 }, /* 110b */ 354 { IDE, IDE, P1, P0 }, /* 111b */ 355 }, 356 }; 357 358 static const struct piix_map_db ich6_map_db = { 359 .mask = 0x3, 360 .port_enable = 0xf, 361 .map = { 362 /* PM PS SM SS MAP */ 363 { P0, P2, P1, P3 }, /* 00b */ 364 { IDE, IDE, P1, P3 }, /* 01b */ 365 { P0, P2, IDE, IDE }, /* 10b */ 366 { RV, RV, RV, RV }, 367 }, 368 }; 369 370 static const struct piix_map_db ich6m_map_db = { 371 .mask = 0x3, 372 .port_enable = 0x5, 373 374 /* Map 01b isn't specified in the doc but some notebooks use 375 * it anyway. MAP 01b have been spotted on both ICH6M and 376 * ICH7M. 377 */ 378 .map = { 379 /* PM PS SM SS MAP */ 380 { P0, P2, NA, NA }, /* 00b */ 381 { IDE, IDE, P1, P3 }, /* 01b */ 382 { P0, P2, IDE, IDE }, /* 10b */ 383 { RV, RV, RV, RV }, 384 }, 385 }; 386 387 static const struct piix_map_db ich8_map_db = { 388 .mask = 0x3, 389 .port_enable = 0xf, 390 .map = { 391 /* PM PS SM SS MAP */ 392 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */ 393 { RV, RV, RV, RV }, 394 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */ 395 { RV, RV, RV, RV }, 396 }, 397 }; 398 399 static const struct piix_map_db ich8_2port_map_db = { 400 .mask = 0x3, 401 .port_enable = 0x3, 402 .map = { 403 /* PM PS SM SS MAP */ 404 { P0, NA, P1, NA }, /* 00b */ 405 { RV, RV, RV, RV }, /* 01b */ 406 { RV, RV, RV, RV }, /* 10b */ 407 { RV, RV, RV, RV }, 408 }, 409 }; 410 411 static const struct piix_map_db ich8m_apple_map_db = { 412 .mask = 0x3, 413 .port_enable = 0x1, 414 .map = { 415 /* PM PS SM SS MAP */ 416 { P0, NA, NA, NA }, /* 00b */ 417 { RV, RV, RV, RV }, 418 { P0, P2, IDE, IDE }, /* 10b */ 419 { RV, RV, RV, RV }, 420 }, 421 }; 422 423 static const struct piix_map_db tolapai_map_db = { 424 .mask = 0x3, 425 .port_enable = 0x3, 426 .map = { 427 /* PM PS SM SS MAP */ 428 { P0, NA, P1, NA }, /* 00b */ 429 { RV, RV, RV, RV }, /* 01b */ 430 { RV, RV, RV, RV }, /* 10b */ 431 { RV, RV, RV, RV }, 432 }, 433 }; 434 435 static const struct piix_map_db *piix_map_db_table[] = { 436 [ich5_sata] = &ich5_map_db, 437 [ich6_sata] = &ich6_map_db, 438 [ich6m_sata] = &ich6m_map_db, 439 [ich8_sata] = &ich8_map_db, 440 [ich8_2port_sata] = &ich8_2port_map_db, 441 [ich8m_apple_sata] = &ich8m_apple_map_db, 442 [tolapai_sata] = &tolapai_map_db, 443 }; 444 445 static struct ata_port_info piix_port_info[] = { 446 [piix_pata_mwdma] = /* PIIX3 MWDMA only */ 447 { 448 .flags = PIIX_PATA_FLAGS, 449 .pio_mask = ATA_PIO4, 450 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 451 .port_ops = &piix_pata_ops, 452 }, 453 454 [piix_pata_33] = /* PIIX4 at 33MHz */ 455 { 456 .flags = PIIX_PATA_FLAGS, 457 .pio_mask = ATA_PIO4, 458 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 459 .udma_mask = ATA_UDMA2, 460 .port_ops = &piix_pata_ops, 461 }, 462 463 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/ 464 { 465 .flags = PIIX_PATA_FLAGS, 466 .pio_mask = ATA_PIO4, 467 .mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */ 468 .udma_mask = ATA_UDMA2, 469 .port_ops = &ich_pata_ops, 470 }, 471 472 [ich_pata_66] = /* ICH controllers up to 66MHz */ 473 { 474 .flags = PIIX_PATA_FLAGS, 475 .pio_mask = ATA_PIO4, 476 .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */ 477 .udma_mask = ATA_UDMA4, 478 .port_ops = &ich_pata_ops, 479 }, 480 481 [ich_pata_100] = 482 { 483 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, 484 .pio_mask = ATA_PIO4, 485 .mwdma_mask = ATA_MWDMA12_ONLY, 486 .udma_mask = ATA_UDMA5, 487 .port_ops = &ich_pata_ops, 488 }, 489 490 [ich5_sata] = 491 { 492 .flags = PIIX_SATA_FLAGS, 493 .pio_mask = ATA_PIO4, 494 .mwdma_mask = ATA_MWDMA2, 495 .udma_mask = ATA_UDMA6, 496 .port_ops = &piix_sata_ops, 497 }, 498 499 [ich6_sata] = 500 { 501 .flags = PIIX_SATA_FLAGS, 502 .pio_mask = ATA_PIO4, 503 .mwdma_mask = ATA_MWDMA2, 504 .udma_mask = ATA_UDMA6, 505 .port_ops = &piix_sata_ops, 506 }, 507 508 [ich6m_sata] = 509 { 510 .flags = PIIX_SATA_FLAGS, 511 .pio_mask = ATA_PIO4, 512 .mwdma_mask = ATA_MWDMA2, 513 .udma_mask = ATA_UDMA6, 514 .port_ops = &piix_sata_ops, 515 }, 516 517 [ich8_sata] = 518 { 519 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, 520 .pio_mask = ATA_PIO4, 521 .mwdma_mask = ATA_MWDMA2, 522 .udma_mask = ATA_UDMA6, 523 .port_ops = &piix_sata_ops, 524 }, 525 526 [ich8_2port_sata] = 527 { 528 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, 529 .pio_mask = ATA_PIO4, 530 .mwdma_mask = ATA_MWDMA2, 531 .udma_mask = ATA_UDMA6, 532 .port_ops = &piix_sata_ops, 533 }, 534 535 [tolapai_sata] = 536 { 537 .flags = PIIX_SATA_FLAGS, 538 .pio_mask = ATA_PIO4, 539 .mwdma_mask = ATA_MWDMA2, 540 .udma_mask = ATA_UDMA6, 541 .port_ops = &piix_sata_ops, 542 }, 543 544 [ich8m_apple_sata] = 545 { 546 .flags = PIIX_SATA_FLAGS, 547 .pio_mask = ATA_PIO4, 548 .mwdma_mask = ATA_MWDMA2, 549 .udma_mask = ATA_UDMA6, 550 .port_ops = &piix_sata_ops, 551 }, 552 553 [piix_pata_vmw] = 554 { 555 .flags = PIIX_PATA_FLAGS, 556 .pio_mask = ATA_PIO4, 557 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 558 .udma_mask = ATA_UDMA2, 559 .port_ops = &piix_vmw_ops, 560 }, 561 562 }; 563 564 static struct pci_bits piix_enable_bits[] = { 565 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ 566 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ 567 }; 568 569 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik"); 570 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers"); 571 MODULE_LICENSE("GPL"); 572 MODULE_DEVICE_TABLE(pci, piix_pci_tbl); 573 MODULE_VERSION(DRV_VERSION); 574 575 struct ich_laptop { 576 u16 device; 577 u16 subvendor; 578 u16 subdevice; 579 }; 580 581 /* 582 * List of laptops that use short cables rather than 80 wire 583 */ 584 585 static const struct ich_laptop ich_laptop[] = { 586 /* devid, subvendor, subdev */ 587 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */ 588 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */ 589 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */ 590 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */ 591 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */ 592 { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */ 593 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */ 594 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */ 595 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */ 596 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */ 597 /* end marker */ 598 { 0, } 599 }; 600 601 /** 602 * ich_pata_cable_detect - Probe host controller cable detect info 603 * @ap: Port for which cable detect info is desired 604 * 605 * Read 80c cable indicator from ATA PCI device's PCI config 606 * register. This register is normally set by firmware (BIOS). 607 * 608 * LOCKING: 609 * None (inherited from caller). 610 */ 611 612 static int ich_pata_cable_detect(struct ata_port *ap) 613 { 614 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 615 struct piix_host_priv *hpriv = ap->host->private_data; 616 const struct ich_laptop *lap = &ich_laptop[0]; 617 u8 mask; 618 619 /* Check for specials - Acer Aspire 5602WLMi */ 620 while (lap->device) { 621 if (lap->device == pdev->device && 622 lap->subvendor == pdev->subsystem_vendor && 623 lap->subdevice == pdev->subsystem_device) 624 return ATA_CBL_PATA40_SHORT; 625 626 lap++; 627 } 628 629 /* check BIOS cable detect results */ 630 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; 631 if ((hpriv->saved_iocfg & mask) == 0) 632 return ATA_CBL_PATA40; 633 return ATA_CBL_PATA80; 634 } 635 636 /** 637 * piix_pata_prereset - prereset for PATA host controller 638 * @link: Target link 639 * @deadline: deadline jiffies for the operation 640 * 641 * LOCKING: 642 * None (inherited from caller). 643 */ 644 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline) 645 { 646 struct ata_port *ap = link->ap; 647 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 648 649 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) 650 return -ENOENT; 651 return ata_sff_prereset(link, deadline); 652 } 653 654 /** 655 * piix_set_piomode - Initialize host controller PATA PIO timings 656 * @ap: Port whose timings we are configuring 657 * @adev: um 658 * 659 * Set PIO mode for device, in host controller PCI config space. 660 * 661 * LOCKING: 662 * None (inherited from caller). 663 */ 664 665 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev) 666 { 667 unsigned int pio = adev->pio_mode - XFER_PIO_0; 668 struct pci_dev *dev = to_pci_dev(ap->host->dev); 669 unsigned int is_slave = (adev->devno != 0); 670 unsigned int master_port= ap->port_no ? 0x42 : 0x40; 671 unsigned int slave_port = 0x44; 672 u16 master_data; 673 u8 slave_data; 674 u8 udma_enable; 675 int control = 0; 676 677 /* 678 * See Intel Document 298600-004 for the timing programing rules 679 * for ICH controllers. 680 */ 681 682 static const /* ISP RTC */ 683 u8 timings[][2] = { { 0, 0 }, 684 { 0, 0 }, 685 { 1, 0 }, 686 { 2, 1 }, 687 { 2, 3 }, }; 688 689 if (pio >= 2) 690 control |= 1; /* TIME1 enable */ 691 if (ata_pio_need_iordy(adev)) 692 control |= 2; /* IE enable */ 693 694 /* Intel specifies that the PPE functionality is for disk only */ 695 if (adev->class == ATA_DEV_ATA) 696 control |= 4; /* PPE enable */ 697 698 /* PIO configuration clears DTE unconditionally. It will be 699 * programmed in set_dmamode which is guaranteed to be called 700 * after set_piomode if any DMA mode is available. 701 */ 702 pci_read_config_word(dev, master_port, &master_data); 703 if (is_slave) { 704 /* clear TIME1|IE1|PPE1|DTE1 */ 705 master_data &= 0xff0f; 706 /* Enable SITRE (separate slave timing register) */ 707 master_data |= 0x4000; 708 /* enable PPE1, IE1 and TIME1 as needed */ 709 master_data |= (control << 4); 710 pci_read_config_byte(dev, slave_port, &slave_data); 711 slave_data &= (ap->port_no ? 0x0f : 0xf0); 712 /* Load the timing nibble for this slave */ 713 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) 714 << (ap->port_no ? 4 : 0); 715 } else { 716 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */ 717 master_data &= 0xccf0; 718 /* Enable PPE, IE and TIME as appropriate */ 719 master_data |= control; 720 /* load ISP and RCT */ 721 master_data |= 722 (timings[pio][0] << 12) | 723 (timings[pio][1] << 8); 724 } 725 pci_write_config_word(dev, master_port, master_data); 726 if (is_slave) 727 pci_write_config_byte(dev, slave_port, slave_data); 728 729 /* Ensure the UDMA bit is off - it will be turned back on if 730 UDMA is selected */ 731 732 if (ap->udma_mask) { 733 pci_read_config_byte(dev, 0x48, &udma_enable); 734 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno)); 735 pci_write_config_byte(dev, 0x48, udma_enable); 736 } 737 } 738 739 /** 740 * do_pata_set_dmamode - Initialize host controller PATA PIO timings 741 * @ap: Port whose timings we are configuring 742 * @adev: Drive in question 743 * @isich: set if the chip is an ICH device 744 * 745 * Set UDMA mode for device, in host controller PCI config space. 746 * 747 * LOCKING: 748 * None (inherited from caller). 749 */ 750 751 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich) 752 { 753 struct pci_dev *dev = to_pci_dev(ap->host->dev); 754 u8 master_port = ap->port_no ? 0x42 : 0x40; 755 u16 master_data; 756 u8 speed = adev->dma_mode; 757 int devid = adev->devno + 2 * ap->port_no; 758 u8 udma_enable = 0; 759 760 static const /* ISP RTC */ 761 u8 timings[][2] = { { 0, 0 }, 762 { 0, 0 }, 763 { 1, 0 }, 764 { 2, 1 }, 765 { 2, 3 }, }; 766 767 pci_read_config_word(dev, master_port, &master_data); 768 if (ap->udma_mask) 769 pci_read_config_byte(dev, 0x48, &udma_enable); 770 771 if (speed >= XFER_UDMA_0) { 772 unsigned int udma = adev->dma_mode - XFER_UDMA_0; 773 u16 udma_timing; 774 u16 ideconf; 775 int u_clock, u_speed; 776 777 /* 778 * UDMA is handled by a combination of clock switching and 779 * selection of dividers 780 * 781 * Handy rule: Odd modes are UDMATIMx 01, even are 02 782 * except UDMA0 which is 00 783 */ 784 u_speed = min(2 - (udma & 1), udma); 785 if (udma == 5) 786 u_clock = 0x1000; /* 100Mhz */ 787 else if (udma > 2) 788 u_clock = 1; /* 66Mhz */ 789 else 790 u_clock = 0; /* 33Mhz */ 791 792 udma_enable |= (1 << devid); 793 794 /* Load the CT/RP selection */ 795 pci_read_config_word(dev, 0x4A, &udma_timing); 796 udma_timing &= ~(3 << (4 * devid)); 797 udma_timing |= u_speed << (4 * devid); 798 pci_write_config_word(dev, 0x4A, udma_timing); 799 800 if (isich) { 801 /* Select a 33/66/100Mhz clock */ 802 pci_read_config_word(dev, 0x54, &ideconf); 803 ideconf &= ~(0x1001 << devid); 804 ideconf |= u_clock << devid; 805 /* For ICH or later we should set bit 10 for better 806 performance (WR_PingPong_En) */ 807 pci_write_config_word(dev, 0x54, ideconf); 808 } 809 } else { 810 /* 811 * MWDMA is driven by the PIO timings. We must also enable 812 * IORDY unconditionally along with TIME1. PPE has already 813 * been set when the PIO timing was set. 814 */ 815 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; 816 unsigned int control; 817 u8 slave_data; 818 const unsigned int needed_pio[3] = { 819 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 820 }; 821 int pio = needed_pio[mwdma] - XFER_PIO_0; 822 823 control = 3; /* IORDY|TIME1 */ 824 825 /* If the drive MWDMA is faster than it can do PIO then 826 we must force PIO into PIO0 */ 827 828 if (adev->pio_mode < needed_pio[mwdma]) 829 /* Enable DMA timing only */ 830 control |= 8; /* PIO cycles in PIO0 */ 831 832 if (adev->devno) { /* Slave */ 833 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */ 834 master_data |= control << 4; 835 pci_read_config_byte(dev, 0x44, &slave_data); 836 slave_data &= (ap->port_no ? 0x0f : 0xf0); 837 /* Load the matching timing */ 838 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); 839 pci_write_config_byte(dev, 0x44, slave_data); 840 } else { /* Master */ 841 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY 842 and master timing bits */ 843 master_data |= control; 844 master_data |= 845 (timings[pio][0] << 12) | 846 (timings[pio][1] << 8); 847 } 848 849 if (ap->udma_mask) { 850 udma_enable &= ~(1 << devid); 851 pci_write_config_word(dev, master_port, master_data); 852 } 853 } 854 /* Don't scribble on 0x48 if the controller does not support UDMA */ 855 if (ap->udma_mask) 856 pci_write_config_byte(dev, 0x48, udma_enable); 857 } 858 859 /** 860 * piix_set_dmamode - Initialize host controller PATA DMA timings 861 * @ap: Port whose timings we are configuring 862 * @adev: um 863 * 864 * Set MW/UDMA mode for device, in host controller PCI config space. 865 * 866 * LOCKING: 867 * None (inherited from caller). 868 */ 869 870 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev) 871 { 872 do_pata_set_dmamode(ap, adev, 0); 873 } 874 875 /** 876 * ich_set_dmamode - Initialize host controller PATA DMA timings 877 * @ap: Port whose timings we are configuring 878 * @adev: um 879 * 880 * Set MW/UDMA mode for device, in host controller PCI config space. 881 * 882 * LOCKING: 883 * None (inherited from caller). 884 */ 885 886 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev) 887 { 888 do_pata_set_dmamode(ap, adev, 1); 889 } 890 891 /* 892 * Serial ATA Index/Data Pair Superset Registers access 893 * 894 * Beginning from ICH8, there's a sane way to access SCRs using index 895 * and data register pair located at BAR5 which means that we have 896 * separate SCRs for master and slave. This is handled using libata 897 * slave_link facility. 898 */ 899 static const int piix_sidx_map[] = { 900 [SCR_STATUS] = 0, 901 [SCR_ERROR] = 2, 902 [SCR_CONTROL] = 1, 903 }; 904 905 static void piix_sidpr_sel(struct ata_link *link, unsigned int reg) 906 { 907 struct ata_port *ap = link->ap; 908 struct piix_host_priv *hpriv = ap->host->private_data; 909 910 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg], 911 hpriv->sidpr + PIIX_SIDPR_IDX); 912 } 913 914 static int piix_sidpr_scr_read(struct ata_link *link, 915 unsigned int reg, u32 *val) 916 { 917 struct piix_host_priv *hpriv = link->ap->host->private_data; 918 919 if (reg >= ARRAY_SIZE(piix_sidx_map)) 920 return -EINVAL; 921 922 piix_sidpr_sel(link, reg); 923 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA); 924 return 0; 925 } 926 927 static int piix_sidpr_scr_write(struct ata_link *link, 928 unsigned int reg, u32 val) 929 { 930 struct piix_host_priv *hpriv = link->ap->host->private_data; 931 932 if (reg >= ARRAY_SIZE(piix_sidx_map)) 933 return -EINVAL; 934 935 piix_sidpr_sel(link, reg); 936 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA); 937 return 0; 938 } 939 940 #ifdef CONFIG_PM 941 static int piix_broken_suspend(void) 942 { 943 static const struct dmi_system_id sysids[] = { 944 { 945 .ident = "TECRA M3", 946 .matches = { 947 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 948 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"), 949 }, 950 }, 951 { 952 .ident = "TECRA M3", 953 .matches = { 954 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 955 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"), 956 }, 957 }, 958 { 959 .ident = "TECRA M4", 960 .matches = { 961 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 962 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"), 963 }, 964 }, 965 { 966 .ident = "TECRA M4", 967 .matches = { 968 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 969 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"), 970 }, 971 }, 972 { 973 .ident = "TECRA M5", 974 .matches = { 975 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 976 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"), 977 }, 978 }, 979 { 980 .ident = "TECRA M6", 981 .matches = { 982 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 983 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"), 984 }, 985 }, 986 { 987 .ident = "TECRA M7", 988 .matches = { 989 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 990 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"), 991 }, 992 }, 993 { 994 .ident = "TECRA A8", 995 .matches = { 996 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 997 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"), 998 }, 999 }, 1000 { 1001 .ident = "Satellite R20", 1002 .matches = { 1003 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1004 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"), 1005 }, 1006 }, 1007 { 1008 .ident = "Satellite R25", 1009 .matches = { 1010 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1011 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"), 1012 }, 1013 }, 1014 { 1015 .ident = "Satellite U200", 1016 .matches = { 1017 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1018 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"), 1019 }, 1020 }, 1021 { 1022 .ident = "Satellite U200", 1023 .matches = { 1024 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1025 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"), 1026 }, 1027 }, 1028 { 1029 .ident = "Satellite Pro U200", 1030 .matches = { 1031 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1032 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"), 1033 }, 1034 }, 1035 { 1036 .ident = "Satellite U205", 1037 .matches = { 1038 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1039 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"), 1040 }, 1041 }, 1042 { 1043 .ident = "SATELLITE U205", 1044 .matches = { 1045 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1046 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"), 1047 }, 1048 }, 1049 { 1050 .ident = "Portege M500", 1051 .matches = { 1052 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1053 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"), 1054 }, 1055 }, 1056 { 1057 .ident = "VGN-BX297XP", 1058 .matches = { 1059 DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"), 1060 DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"), 1061 }, 1062 }, 1063 1064 { } /* terminate list */ 1065 }; 1066 static const char *oemstrs[] = { 1067 "Tecra M3,", 1068 }; 1069 int i; 1070 1071 if (dmi_check_system(sysids)) 1072 return 1; 1073 1074 for (i = 0; i < ARRAY_SIZE(oemstrs); i++) 1075 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL)) 1076 return 1; 1077 1078 /* TECRA M4 sometimes forgets its identify and reports bogus 1079 * DMI information. As the bogus information is a bit 1080 * generic, match as many entries as possible. This manual 1081 * matching is necessary because dmi_system_id.matches is 1082 * limited to four entries. 1083 */ 1084 if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") && 1085 dmi_match(DMI_PRODUCT_NAME, "000000") && 1086 dmi_match(DMI_PRODUCT_VERSION, "000000") && 1087 dmi_match(DMI_PRODUCT_SERIAL, "000000") && 1088 dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") && 1089 dmi_match(DMI_BOARD_NAME, "Portable PC") && 1090 dmi_match(DMI_BOARD_VERSION, "Version A0")) 1091 return 1; 1092 1093 return 0; 1094 } 1095 1096 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) 1097 { 1098 struct ata_host *host = dev_get_drvdata(&pdev->dev); 1099 unsigned long flags; 1100 int rc = 0; 1101 1102 rc = ata_host_suspend(host, mesg); 1103 if (rc) 1104 return rc; 1105 1106 /* Some braindamaged ACPI suspend implementations expect the 1107 * controller to be awake on entry; otherwise, it burns cpu 1108 * cycles and power trying to do something to the sleeping 1109 * beauty. 1110 */ 1111 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) { 1112 pci_save_state(pdev); 1113 1114 /* mark its power state as "unknown", since we don't 1115 * know if e.g. the BIOS will change its device state 1116 * when we suspend. 1117 */ 1118 if (pdev->current_state == PCI_D0) 1119 pdev->current_state = PCI_UNKNOWN; 1120 1121 /* tell resume that it's waking up from broken suspend */ 1122 spin_lock_irqsave(&host->lock, flags); 1123 host->flags |= PIIX_HOST_BROKEN_SUSPEND; 1124 spin_unlock_irqrestore(&host->lock, flags); 1125 } else 1126 ata_pci_device_do_suspend(pdev, mesg); 1127 1128 return 0; 1129 } 1130 1131 static int piix_pci_device_resume(struct pci_dev *pdev) 1132 { 1133 struct ata_host *host = dev_get_drvdata(&pdev->dev); 1134 unsigned long flags; 1135 int rc; 1136 1137 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) { 1138 spin_lock_irqsave(&host->lock, flags); 1139 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND; 1140 spin_unlock_irqrestore(&host->lock, flags); 1141 1142 pci_set_power_state(pdev, PCI_D0); 1143 pci_restore_state(pdev); 1144 1145 /* PCI device wasn't disabled during suspend. Use 1146 * pci_reenable_device() to avoid affecting the enable 1147 * count. 1148 */ 1149 rc = pci_reenable_device(pdev); 1150 if (rc) 1151 dev_printk(KERN_ERR, &pdev->dev, "failed to enable " 1152 "device after resume (%d)\n", rc); 1153 } else 1154 rc = ata_pci_device_do_resume(pdev); 1155 1156 if (rc == 0) 1157 ata_host_resume(host); 1158 1159 return rc; 1160 } 1161 #endif 1162 1163 static u8 piix_vmw_bmdma_status(struct ata_port *ap) 1164 { 1165 return ata_bmdma_status(ap) & ~ATA_DMA_ERR; 1166 } 1167 1168 #define AHCI_PCI_BAR 5 1169 #define AHCI_GLOBAL_CTL 0x04 1170 #define AHCI_ENABLE (1 << 31) 1171 static int piix_disable_ahci(struct pci_dev *pdev) 1172 { 1173 void __iomem *mmio; 1174 u32 tmp; 1175 int rc = 0; 1176 1177 /* BUG: pci_enable_device has not yet been called. This 1178 * works because this device is usually set up by BIOS. 1179 */ 1180 1181 if (!pci_resource_start(pdev, AHCI_PCI_BAR) || 1182 !pci_resource_len(pdev, AHCI_PCI_BAR)) 1183 return 0; 1184 1185 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64); 1186 if (!mmio) 1187 return -ENOMEM; 1188 1189 tmp = ioread32(mmio + AHCI_GLOBAL_CTL); 1190 if (tmp & AHCI_ENABLE) { 1191 tmp &= ~AHCI_ENABLE; 1192 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL); 1193 1194 tmp = ioread32(mmio + AHCI_GLOBAL_CTL); 1195 if (tmp & AHCI_ENABLE) 1196 rc = -EIO; 1197 } 1198 1199 pci_iounmap(pdev, mmio); 1200 return rc; 1201 } 1202 1203 /** 1204 * piix_check_450nx_errata - Check for problem 450NX setup 1205 * @ata_dev: the PCI device to check 1206 * 1207 * Check for the present of 450NX errata #19 and errata #25. If 1208 * they are found return an error code so we can turn off DMA 1209 */ 1210 1211 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev) 1212 { 1213 struct pci_dev *pdev = NULL; 1214 u16 cfg; 1215 int no_piix_dma = 0; 1216 1217 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) { 1218 /* Look for 450NX PXB. Check for problem configurations 1219 A PCI quirk checks bit 6 already */ 1220 pci_read_config_word(pdev, 0x41, &cfg); 1221 /* Only on the original revision: IDE DMA can hang */ 1222 if (pdev->revision == 0x00) 1223 no_piix_dma = 1; 1224 /* On all revisions below 5 PXB bus lock must be disabled for IDE */ 1225 else if (cfg & (1<<14) && pdev->revision < 5) 1226 no_piix_dma = 2; 1227 } 1228 if (no_piix_dma) 1229 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n"); 1230 if (no_piix_dma == 2) 1231 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n"); 1232 return no_piix_dma; 1233 } 1234 1235 static void __devinit piix_init_pcs(struct ata_host *host, 1236 const struct piix_map_db *map_db) 1237 { 1238 struct pci_dev *pdev = to_pci_dev(host->dev); 1239 u16 pcs, new_pcs; 1240 1241 pci_read_config_word(pdev, ICH5_PCS, &pcs); 1242 1243 new_pcs = pcs | map_db->port_enable; 1244 1245 if (new_pcs != pcs) { 1246 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs); 1247 pci_write_config_word(pdev, ICH5_PCS, new_pcs); 1248 msleep(150); 1249 } 1250 } 1251 1252 static const int *__devinit piix_init_sata_map(struct pci_dev *pdev, 1253 struct ata_port_info *pinfo, 1254 const struct piix_map_db *map_db) 1255 { 1256 const int *map; 1257 int i, invalid_map = 0; 1258 u8 map_value; 1259 1260 pci_read_config_byte(pdev, ICH5_PMR, &map_value); 1261 1262 map = map_db->map[map_value & map_db->mask]; 1263 1264 dev_printk(KERN_INFO, &pdev->dev, "MAP ["); 1265 for (i = 0; i < 4; i++) { 1266 switch (map[i]) { 1267 case RV: 1268 invalid_map = 1; 1269 printk(" XX"); 1270 break; 1271 1272 case NA: 1273 printk(" --"); 1274 break; 1275 1276 case IDE: 1277 WARN_ON((i & 1) || map[i + 1] != IDE); 1278 pinfo[i / 2] = piix_port_info[ich_pata_100]; 1279 i++; 1280 printk(" IDE IDE"); 1281 break; 1282 1283 default: 1284 printk(" P%d", map[i]); 1285 if (i & 1) 1286 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS; 1287 break; 1288 } 1289 } 1290 printk(" ]\n"); 1291 1292 if (invalid_map) 1293 dev_printk(KERN_ERR, &pdev->dev, 1294 "invalid MAP value %u\n", map_value); 1295 1296 return map; 1297 } 1298 1299 static bool piix_no_sidpr(struct ata_host *host) 1300 { 1301 struct pci_dev *pdev = to_pci_dev(host->dev); 1302 1303 /* 1304 * Samsung DB-P70 only has three ATA ports exposed and 1305 * curiously the unconnected first port reports link online 1306 * while not responding to SRST protocol causing excessive 1307 * detection delay. 1308 * 1309 * Unfortunately, the system doesn't carry enough DMI 1310 * information to identify the machine but does have subsystem 1311 * vendor and device set. As it's unclear whether the 1312 * subsystem vendor/device is used only for this specific 1313 * board, the port can't be disabled solely with the 1314 * information; however, turning off SIDPR access works around 1315 * the problem. Turn it off. 1316 * 1317 * This problem is reported in bnc#441240. 1318 * 1319 * https://bugzilla.novell.com/show_bug.cgi?id=441420 1320 */ 1321 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 && 1322 pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG && 1323 pdev->subsystem_device == 0xb049) { 1324 dev_printk(KERN_WARNING, host->dev, 1325 "Samsung DB-P70 detected, disabling SIDPR\n"); 1326 return true; 1327 } 1328 1329 return false; 1330 } 1331 1332 static int __devinit piix_init_sidpr(struct ata_host *host) 1333 { 1334 struct pci_dev *pdev = to_pci_dev(host->dev); 1335 struct piix_host_priv *hpriv = host->private_data; 1336 struct ata_link *link0 = &host->ports[0]->link; 1337 u32 scontrol; 1338 int i, rc; 1339 1340 /* check for availability */ 1341 for (i = 0; i < 4; i++) 1342 if (hpriv->map[i] == IDE) 1343 return 0; 1344 1345 /* is it blacklisted? */ 1346 if (piix_no_sidpr(host)) 1347 return 0; 1348 1349 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR)) 1350 return 0; 1351 1352 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 || 1353 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN) 1354 return 0; 1355 1356 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME)) 1357 return 0; 1358 1359 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR]; 1360 1361 /* SCR access via SIDPR doesn't work on some configurations. 1362 * Give it a test drive by inhibiting power save modes which 1363 * we'll do anyway. 1364 */ 1365 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol); 1366 1367 /* if IPM is already 3, SCR access is probably working. Don't 1368 * un-inhibit power save modes as BIOS might have inhibited 1369 * them for a reason. 1370 */ 1371 if ((scontrol & 0xf00) != 0x300) { 1372 scontrol |= 0x300; 1373 piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol); 1374 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol); 1375 1376 if ((scontrol & 0xf00) != 0x300) { 1377 dev_printk(KERN_INFO, host->dev, "SCR access via " 1378 "SIDPR is available but doesn't work\n"); 1379 return 0; 1380 } 1381 } 1382 1383 /* okay, SCRs available, set ops and ask libata for slave_link */ 1384 for (i = 0; i < 2; i++) { 1385 struct ata_port *ap = host->ports[i]; 1386 1387 ap->ops = &piix_sidpr_sata_ops; 1388 1389 if (ap->flags & ATA_FLAG_SLAVE_POSS) { 1390 rc = ata_slave_link_init(ap); 1391 if (rc) 1392 return rc; 1393 } 1394 } 1395 1396 return 0; 1397 } 1398 1399 static void piix_iocfg_bit18_quirk(struct ata_host *host) 1400 { 1401 static const struct dmi_system_id sysids[] = { 1402 { 1403 /* Clevo M570U sets IOCFG bit 18 if the cdrom 1404 * isn't used to boot the system which 1405 * disables the channel. 1406 */ 1407 .ident = "M570U", 1408 .matches = { 1409 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."), 1410 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"), 1411 }, 1412 }, 1413 1414 { } /* terminate list */ 1415 }; 1416 struct pci_dev *pdev = to_pci_dev(host->dev); 1417 struct piix_host_priv *hpriv = host->private_data; 1418 1419 if (!dmi_check_system(sysids)) 1420 return; 1421 1422 /* The datasheet says that bit 18 is NOOP but certain systems 1423 * seem to use it to disable a channel. Clear the bit on the 1424 * affected systems. 1425 */ 1426 if (hpriv->saved_iocfg & (1 << 18)) { 1427 dev_printk(KERN_INFO, &pdev->dev, 1428 "applying IOCFG bit18 quirk\n"); 1429 pci_write_config_dword(pdev, PIIX_IOCFG, 1430 hpriv->saved_iocfg & ~(1 << 18)); 1431 } 1432 } 1433 1434 static bool piix_broken_system_poweroff(struct pci_dev *pdev) 1435 { 1436 static const struct dmi_system_id broken_systems[] = { 1437 { 1438 .ident = "HP Compaq 2510p", 1439 .matches = { 1440 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1441 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"), 1442 }, 1443 /* PCI slot number of the controller */ 1444 .driver_data = (void *)0x1FUL, 1445 }, 1446 1447 { } /* terminate list */ 1448 }; 1449 const struct dmi_system_id *dmi = dmi_first_match(broken_systems); 1450 1451 if (dmi) { 1452 unsigned long slot = (unsigned long)dmi->driver_data; 1453 /* apply the quirk only to on-board controllers */ 1454 return slot == PCI_SLOT(pdev->devfn); 1455 } 1456 1457 return false; 1458 } 1459 1460 /** 1461 * piix_init_one - Register PIIX ATA PCI device with kernel services 1462 * @pdev: PCI device to register 1463 * @ent: Entry in piix_pci_tbl matching with @pdev 1464 * 1465 * Called from kernel PCI layer. We probe for combined mode (sigh), 1466 * and then hand over control to libata, for it to do the rest. 1467 * 1468 * LOCKING: 1469 * Inherited from PCI layer (may sleep). 1470 * 1471 * RETURNS: 1472 * Zero on success, or -ERRNO value. 1473 */ 1474 1475 static int __devinit piix_init_one(struct pci_dev *pdev, 1476 const struct pci_device_id *ent) 1477 { 1478 static int printed_version; 1479 struct device *dev = &pdev->dev; 1480 struct ata_port_info port_info[2]; 1481 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] }; 1482 unsigned long port_flags; 1483 struct ata_host *host; 1484 struct piix_host_priv *hpriv; 1485 int rc; 1486 1487 if (!printed_version++) 1488 dev_printk(KERN_DEBUG, &pdev->dev, 1489 "version " DRV_VERSION "\n"); 1490 1491 /* no hotplugging support (FIXME) */ 1492 if (!in_module_init) 1493 return -ENODEV; 1494 1495 if (piix_broken_system_poweroff(pdev)) { 1496 piix_port_info[ent->driver_data].flags |= 1497 ATA_FLAG_NO_POWEROFF_SPINDOWN | 1498 ATA_FLAG_NO_HIBERNATE_SPINDOWN; 1499 dev_info(&pdev->dev, "quirky BIOS, skipping spindown " 1500 "on poweroff and hibernation\n"); 1501 } 1502 1503 port_info[0] = piix_port_info[ent->driver_data]; 1504 port_info[1] = piix_port_info[ent->driver_data]; 1505 1506 port_flags = port_info[0].flags; 1507 1508 /* enable device and prepare host */ 1509 rc = pcim_enable_device(pdev); 1510 if (rc) 1511 return rc; 1512 1513 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1514 if (!hpriv) 1515 return -ENOMEM; 1516 1517 /* Save IOCFG, this will be used for cable detection, quirk 1518 * detection and restoration on detach. This is necessary 1519 * because some ACPI implementations mess up cable related 1520 * bits on _STM. Reported on kernel bz#11879. 1521 */ 1522 pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg); 1523 1524 /* ICH6R may be driven by either ata_piix or ahci driver 1525 * regardless of BIOS configuration. Make sure AHCI mode is 1526 * off. 1527 */ 1528 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) { 1529 rc = piix_disable_ahci(pdev); 1530 if (rc) 1531 return rc; 1532 } 1533 1534 /* SATA map init can change port_info, do it before prepping host */ 1535 if (port_flags & ATA_FLAG_SATA) 1536 hpriv->map = piix_init_sata_map(pdev, port_info, 1537 piix_map_db_table[ent->driver_data]); 1538 1539 rc = ata_pci_sff_prepare_host(pdev, ppi, &host); 1540 if (rc) 1541 return rc; 1542 host->private_data = hpriv; 1543 1544 /* initialize controller */ 1545 if (port_flags & ATA_FLAG_SATA) { 1546 piix_init_pcs(host, piix_map_db_table[ent->driver_data]); 1547 rc = piix_init_sidpr(host); 1548 if (rc) 1549 return rc; 1550 } 1551 1552 /* apply IOCFG bit18 quirk */ 1553 piix_iocfg_bit18_quirk(host); 1554 1555 /* On ICH5, some BIOSen disable the interrupt using the 1556 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. 1557 * On ICH6, this bit has the same effect, but only when 1558 * MSI is disabled (and it is disabled, as we don't use 1559 * message-signalled interrupts currently). 1560 */ 1561 if (port_flags & PIIX_FLAG_CHECKINTR) 1562 pci_intx(pdev, 1); 1563 1564 if (piix_check_450nx_errata(pdev)) { 1565 /* This writes into the master table but it does not 1566 really matter for this errata as we will apply it to 1567 all the PIIX devices on the board */ 1568 host->ports[0]->mwdma_mask = 0; 1569 host->ports[0]->udma_mask = 0; 1570 host->ports[1]->mwdma_mask = 0; 1571 host->ports[1]->udma_mask = 0; 1572 } 1573 1574 pci_set_master(pdev); 1575 return ata_pci_sff_activate_host(host, ata_sff_interrupt, &piix_sht); 1576 } 1577 1578 static void piix_remove_one(struct pci_dev *pdev) 1579 { 1580 struct ata_host *host = dev_get_drvdata(&pdev->dev); 1581 struct piix_host_priv *hpriv = host->private_data; 1582 1583 pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg); 1584 1585 ata_pci_remove_one(pdev); 1586 } 1587 1588 static int __init piix_init(void) 1589 { 1590 int rc; 1591 1592 DPRINTK("pci_register_driver\n"); 1593 rc = pci_register_driver(&piix_pci_driver); 1594 if (rc) 1595 return rc; 1596 1597 in_module_init = 0; 1598 1599 DPRINTK("done\n"); 1600 return 0; 1601 } 1602 1603 static void __exit piix_exit(void) 1604 { 1605 pci_unregister_driver(&piix_pci_driver); 1606 } 1607 1608 module_init(piix_init); 1609 module_exit(piix_exit); 1610