1 /* 2 * ata_piix.c - Intel PATA/SATA controllers 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * 9 * Copyright 2003-2005 Red Hat Inc 10 * Copyright 2003-2005 Jeff Garzik 11 * 12 * 13 * Copyright header from piix.c: 14 * 15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer 16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> 17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com> 18 * 19 * 20 * This program is free software; you can redistribute it and/or modify 21 * it under the terms of the GNU General Public License as published by 22 * the Free Software Foundation; either version 2, or (at your option) 23 * any later version. 24 * 25 * This program is distributed in the hope that it will be useful, 26 * but WITHOUT ANY WARRANTY; without even the implied warranty of 27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 28 * GNU General Public License for more details. 29 * 30 * You should have received a copy of the GNU General Public License 31 * along with this program; see the file COPYING. If not, write to 32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 33 * 34 * 35 * libata documentation is available via 'make {ps|pdf}docs', 36 * as Documentation/DocBook/libata.* 37 * 38 * Hardware documentation available at http://developer.intel.com/ 39 * 40 * Documentation 41 * Publically available from Intel web site. Errata documentation 42 * is also publically available. As an aide to anyone hacking on this 43 * driver the list of errata that are relevant is below, going back to 44 * PIIX4. Older device documentation is now a bit tricky to find. 45 * 46 * The chipsets all follow very much the same design. The orginal Triton 47 * series chipsets do _not_ support independant device timings, but this 48 * is fixed in Triton II. With the odd mobile exception the chips then 49 * change little except in gaining more modes until SATA arrives. This 50 * driver supports only the chips with independant timing (that is those 51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix 52 * for the early chip drivers. 53 * 54 * Errata of note: 55 * 56 * Unfixable 57 * PIIX4 errata #9 - Only on ultra obscure hw 58 * ICH3 errata #13 - Not observed to affect real hw 59 * by Intel 60 * 61 * Things we must deal with 62 * PIIX4 errata #10 - BM IDE hang with non UDMA 63 * (must stop/start dma to recover) 64 * 440MX errata #15 - As PIIX4 errata #10 65 * PIIX4 errata #15 - Must not read control registers 66 * during a PIO transfer 67 * 440MX errata #13 - As PIIX4 errata #15 68 * ICH2 errata #21 - DMA mode 0 doesn't work right 69 * ICH0/1 errata #55 - As ICH2 errata #21 70 * ICH2 spec c #9 - Extra operations needed to handle 71 * drive hotswap [NOT YET SUPPORTED] 72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary 73 * and must be dword aligned 74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 75 * 76 * Should have been BIOS fixed: 77 * 450NX: errata #19 - DMA hangs on old 450NX 78 * 450NX: errata #20 - DMA hangs on old 450NX 79 * 450NX: errata #25 - Corruption with DMA on old 450NX 80 * ICH3 errata #15 - IDE deadlock under high load 81 * (BIOS must set dev 31 fn 0 bit 23) 82 * ICH3 errata #18 - Don't use native mode 83 */ 84 85 #include <linux/kernel.h> 86 #include <linux/module.h> 87 #include <linux/pci.h> 88 #include <linux/init.h> 89 #include <linux/blkdev.h> 90 #include <linux/delay.h> 91 #include <linux/device.h> 92 #include <scsi/scsi_host.h> 93 #include <linux/libata.h> 94 95 #define DRV_NAME "ata_piix" 96 #define DRV_VERSION "2.11" 97 98 enum { 99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ 100 ICH5_PMR = 0x90, /* port mapping register */ 101 ICH5_PCS = 0x92, /* port control and status */ 102 PIIX_SCC = 0x0A, /* sub-class code register */ 103 104 PIIX_FLAG_SCR = (1 << 26), /* SCR available */ 105 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */ 106 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */ 107 108 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS, 109 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR, 110 111 /* combined mode. if set, PATA is channel 0. 112 * if clear, PATA is channel 1. 113 */ 114 PIIX_PORT_ENABLED = (1 << 0), 115 PIIX_PORT_PRESENT = (1 << 4), 116 117 PIIX_80C_PRI = (1 << 5) | (1 << 4), 118 PIIX_80C_SEC = (1 << 7) | (1 << 6), 119 120 /* controller IDs */ 121 piix_pata_33 = 0, /* PIIX4 at 33Mhz */ 122 ich_pata_33 = 1, /* ICH up to UDMA 33 only */ 123 ich_pata_66 = 2, /* ICH up to 66 Mhz */ 124 ich_pata_100 = 3, /* ICH up to UDMA 100 */ 125 ich_pata_133 = 4, /* ICH up to UDMA 133 */ 126 ich5_sata = 5, 127 ich6_sata = 6, 128 ich6_sata_ahci = 7, 129 ich6m_sata_ahci = 8, 130 ich8_sata_ahci = 9, 131 piix_pata_mwdma = 10, /* PIIX3 MWDMA only */ 132 133 /* constants for mapping table */ 134 P0 = 0, /* port 0 */ 135 P1 = 1, /* port 1 */ 136 P2 = 2, /* port 2 */ 137 P3 = 3, /* port 3 */ 138 IDE = -1, /* IDE */ 139 NA = -2, /* not avaliable */ 140 RV = -3, /* reserved */ 141 142 PIIX_AHCI_DEVICE = 6, 143 }; 144 145 struct piix_map_db { 146 const u32 mask; 147 const u16 port_enable; 148 const int map[][4]; 149 }; 150 151 struct piix_host_priv { 152 const int *map; 153 }; 154 155 static int piix_init_one (struct pci_dev *pdev, 156 const struct pci_device_id *ent); 157 static void piix_pata_error_handler(struct ata_port *ap); 158 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev); 159 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev); 160 static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev); 161 static int ich_pata_cable_detect(struct ata_port *ap); 162 163 static unsigned int in_module_init = 1; 164 165 static const struct pci_device_id piix_pci_tbl[] = { 166 /* Intel PIIX3 for the 430HX etc */ 167 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma }, 168 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */ 169 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */ 170 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 171 /* Intel PIIX4 */ 172 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 173 /* Intel PIIX4 */ 174 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 175 /* Intel PIIX */ 176 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 177 /* Intel ICH (i810, i815, i840) UDMA 66*/ 178 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 }, 179 /* Intel ICH0 : UDMA 33*/ 180 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 }, 181 /* Intel ICH2M */ 182 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 183 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */ 184 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 185 /* Intel ICH3M */ 186 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 187 /* Intel ICH3 (E7500/1) UDMA 100 */ 188 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 189 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */ 190 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 191 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 192 /* Intel ICH5 */ 193 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 }, 194 /* C-ICH (i810E2) */ 195 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 196 /* ESB (855GME/875P + 6300ESB) UDMA 100 */ 197 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 198 /* ICH6 (and 6) (i915) UDMA 100 */ 199 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 200 /* ICH7/7-R (i945, i975) UDMA 100*/ 201 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 }, 202 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 203 /* ICH8 Mobile PATA Controller */ 204 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 205 206 /* NOTE: The following PCI ids must be kept in sync with the 207 * list in drivers/pci/quirks.c. 208 */ 209 210 /* 82801EB (ICH5) */ 211 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 212 /* 82801EB (ICH5) */ 213 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 214 /* 6300ESB (ICH5 variant with broken PCS present bits) */ 215 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 216 /* 6300ESB pretending RAID */ 217 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 218 /* 82801FB/FW (ICH6/ICH6W) */ 219 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 220 /* 82801FR/FRW (ICH6R/ICH6RW) */ 221 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, 222 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */ 223 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, 224 /* 82801GB/GR/GH (ICH7, identical to ICH6) */ 225 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, 226 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */ 227 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, 228 /* Enterprise Southbridge 2 (631xESB/632xESB) */ 229 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, 230 /* SATA Controller 1 IDE (ICH8) */ 231 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 232 /* SATA Controller 2 IDE (ICH8) */ 233 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 234 /* Mobile SATA Controller IDE (ICH8M) */ 235 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 236 /* SATA Controller IDE (ICH9) */ 237 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 238 /* SATA Controller IDE (ICH9) */ 239 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 240 /* SATA Controller IDE (ICH9) */ 241 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 242 /* SATA Controller IDE (ICH9M) */ 243 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 244 /* SATA Controller IDE (ICH9M) */ 245 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 246 /* SATA Controller IDE (ICH9M) */ 247 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 248 249 { } /* terminate list */ 250 }; 251 252 static struct pci_driver piix_pci_driver = { 253 .name = DRV_NAME, 254 .id_table = piix_pci_tbl, 255 .probe = piix_init_one, 256 .remove = ata_pci_remove_one, 257 #ifdef CONFIG_PM 258 .suspend = ata_pci_device_suspend, 259 .resume = ata_pci_device_resume, 260 #endif 261 }; 262 263 static struct scsi_host_template piix_sht = { 264 .module = THIS_MODULE, 265 .name = DRV_NAME, 266 .ioctl = ata_scsi_ioctl, 267 .queuecommand = ata_scsi_queuecmd, 268 .can_queue = ATA_DEF_QUEUE, 269 .this_id = ATA_SHT_THIS_ID, 270 .sg_tablesize = LIBATA_MAX_PRD, 271 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 272 .emulated = ATA_SHT_EMULATED, 273 .use_clustering = ATA_SHT_USE_CLUSTERING, 274 .proc_name = DRV_NAME, 275 .dma_boundary = ATA_DMA_BOUNDARY, 276 .slave_configure = ata_scsi_slave_config, 277 .slave_destroy = ata_scsi_slave_destroy, 278 .bios_param = ata_std_bios_param, 279 }; 280 281 static const struct ata_port_operations piix_pata_ops = { 282 .port_disable = ata_port_disable, 283 .set_piomode = piix_set_piomode, 284 .set_dmamode = piix_set_dmamode, 285 .mode_filter = ata_pci_default_filter, 286 287 .tf_load = ata_tf_load, 288 .tf_read = ata_tf_read, 289 .check_status = ata_check_status, 290 .exec_command = ata_exec_command, 291 .dev_select = ata_std_dev_select, 292 293 .bmdma_setup = ata_bmdma_setup, 294 .bmdma_start = ata_bmdma_start, 295 .bmdma_stop = ata_bmdma_stop, 296 .bmdma_status = ata_bmdma_status, 297 .qc_prep = ata_qc_prep, 298 .qc_issue = ata_qc_issue_prot, 299 .data_xfer = ata_data_xfer, 300 301 .freeze = ata_bmdma_freeze, 302 .thaw = ata_bmdma_thaw, 303 .error_handler = piix_pata_error_handler, 304 .post_internal_cmd = ata_bmdma_post_internal_cmd, 305 .cable_detect = ata_cable_40wire, 306 307 .irq_handler = ata_interrupt, 308 .irq_clear = ata_bmdma_irq_clear, 309 .irq_on = ata_irq_on, 310 .irq_ack = ata_irq_ack, 311 312 .port_start = ata_port_start, 313 }; 314 315 static const struct ata_port_operations ich_pata_ops = { 316 .port_disable = ata_port_disable, 317 .set_piomode = piix_set_piomode, 318 .set_dmamode = ich_set_dmamode, 319 .mode_filter = ata_pci_default_filter, 320 321 .tf_load = ata_tf_load, 322 .tf_read = ata_tf_read, 323 .check_status = ata_check_status, 324 .exec_command = ata_exec_command, 325 .dev_select = ata_std_dev_select, 326 327 .bmdma_setup = ata_bmdma_setup, 328 .bmdma_start = ata_bmdma_start, 329 .bmdma_stop = ata_bmdma_stop, 330 .bmdma_status = ata_bmdma_status, 331 .qc_prep = ata_qc_prep, 332 .qc_issue = ata_qc_issue_prot, 333 .data_xfer = ata_data_xfer, 334 335 .freeze = ata_bmdma_freeze, 336 .thaw = ata_bmdma_thaw, 337 .error_handler = piix_pata_error_handler, 338 .post_internal_cmd = ata_bmdma_post_internal_cmd, 339 .cable_detect = ich_pata_cable_detect, 340 341 .irq_handler = ata_interrupt, 342 .irq_clear = ata_bmdma_irq_clear, 343 .irq_on = ata_irq_on, 344 .irq_ack = ata_irq_ack, 345 346 .port_start = ata_port_start, 347 }; 348 349 static const struct ata_port_operations piix_sata_ops = { 350 .port_disable = ata_port_disable, 351 352 .tf_load = ata_tf_load, 353 .tf_read = ata_tf_read, 354 .check_status = ata_check_status, 355 .exec_command = ata_exec_command, 356 .dev_select = ata_std_dev_select, 357 358 .bmdma_setup = ata_bmdma_setup, 359 .bmdma_start = ata_bmdma_start, 360 .bmdma_stop = ata_bmdma_stop, 361 .bmdma_status = ata_bmdma_status, 362 .qc_prep = ata_qc_prep, 363 .qc_issue = ata_qc_issue_prot, 364 .data_xfer = ata_data_xfer, 365 366 .freeze = ata_bmdma_freeze, 367 .thaw = ata_bmdma_thaw, 368 .error_handler = ata_bmdma_error_handler, 369 .post_internal_cmd = ata_bmdma_post_internal_cmd, 370 371 .irq_handler = ata_interrupt, 372 .irq_clear = ata_bmdma_irq_clear, 373 .irq_on = ata_irq_on, 374 .irq_ack = ata_irq_ack, 375 376 .port_start = ata_port_start, 377 }; 378 379 static const struct piix_map_db ich5_map_db = { 380 .mask = 0x7, 381 .port_enable = 0x3, 382 .map = { 383 /* PM PS SM SS MAP */ 384 { P0, NA, P1, NA }, /* 000b */ 385 { P1, NA, P0, NA }, /* 001b */ 386 { RV, RV, RV, RV }, 387 { RV, RV, RV, RV }, 388 { P0, P1, IDE, IDE }, /* 100b */ 389 { P1, P0, IDE, IDE }, /* 101b */ 390 { IDE, IDE, P0, P1 }, /* 110b */ 391 { IDE, IDE, P1, P0 }, /* 111b */ 392 }, 393 }; 394 395 static const struct piix_map_db ich6_map_db = { 396 .mask = 0x3, 397 .port_enable = 0xf, 398 .map = { 399 /* PM PS SM SS MAP */ 400 { P0, P2, P1, P3 }, /* 00b */ 401 { IDE, IDE, P1, P3 }, /* 01b */ 402 { P0, P2, IDE, IDE }, /* 10b */ 403 { RV, RV, RV, RV }, 404 }, 405 }; 406 407 static const struct piix_map_db ich6m_map_db = { 408 .mask = 0x3, 409 .port_enable = 0x5, 410 411 /* Map 01b isn't specified in the doc but some notebooks use 412 * it anyway. MAP 01b have been spotted on both ICH6M and 413 * ICH7M. 414 */ 415 .map = { 416 /* PM PS SM SS MAP */ 417 { P0, P2, RV, RV }, /* 00b */ 418 { IDE, IDE, P1, P3 }, /* 01b */ 419 { P0, P2, IDE, IDE }, /* 10b */ 420 { RV, RV, RV, RV }, 421 }, 422 }; 423 424 static const struct piix_map_db ich8_map_db = { 425 .mask = 0x3, 426 .port_enable = 0x3, 427 .map = { 428 /* PM PS SM SS MAP */ 429 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */ 430 { RV, RV, RV, RV }, 431 { IDE, IDE, NA, NA }, /* 10b (IDE mode) */ 432 { RV, RV, RV, RV }, 433 }, 434 }; 435 436 static const struct piix_map_db *piix_map_db_table[] = { 437 [ich5_sata] = &ich5_map_db, 438 [ich6_sata] = &ich6_map_db, 439 [ich6_sata_ahci] = &ich6_map_db, 440 [ich6m_sata_ahci] = &ich6m_map_db, 441 [ich8_sata_ahci] = &ich8_map_db, 442 }; 443 444 static struct ata_port_info piix_port_info[] = { 445 /* piix_pata_33: 0: PIIX4 at 33MHz */ 446 { 447 .sht = &piix_sht, 448 .flags = PIIX_PATA_FLAGS, 449 .pio_mask = 0x1f, /* pio0-4 */ 450 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 451 .udma_mask = ATA_UDMA_MASK_40C, 452 .port_ops = &piix_pata_ops, 453 }, 454 455 /* ich_pata_33: 1 ICH0 - ICH at 33Mhz*/ 456 { 457 .sht = &piix_sht, 458 .flags = PIIX_PATA_FLAGS, 459 .pio_mask = 0x1f, /* pio 0-4 */ 460 .mwdma_mask = 0x06, /* Check: maybe 0x07 */ 461 .udma_mask = ATA_UDMA2, /* UDMA33 */ 462 .port_ops = &ich_pata_ops, 463 }, 464 /* ich_pata_66: 2 ICH controllers up to 66MHz */ 465 { 466 .sht = &piix_sht, 467 .flags = PIIX_PATA_FLAGS, 468 .pio_mask = 0x1f, /* pio 0-4 */ 469 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */ 470 .udma_mask = ATA_UDMA4, 471 .port_ops = &ich_pata_ops, 472 }, 473 474 /* ich_pata_100: 3 */ 475 { 476 .sht = &piix_sht, 477 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, 478 .pio_mask = 0x1f, /* pio0-4 */ 479 .mwdma_mask = 0x06, /* mwdma1-2 */ 480 .udma_mask = ATA_UDMA5, /* udma0-5 */ 481 .port_ops = &ich_pata_ops, 482 }, 483 484 /* ich_pata_133: 4 ICH with full UDMA6 */ 485 { 486 .sht = &piix_sht, 487 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, 488 .pio_mask = 0x1f, /* pio 0-4 */ 489 .mwdma_mask = 0x06, /* Check: maybe 0x07 */ 490 .udma_mask = ATA_UDMA6, /* UDMA133 */ 491 .port_ops = &ich_pata_ops, 492 }, 493 494 /* ich5_sata: 5 */ 495 { 496 .sht = &piix_sht, 497 .flags = PIIX_SATA_FLAGS, 498 .pio_mask = 0x1f, /* pio0-4 */ 499 .mwdma_mask = 0x07, /* mwdma0-2 */ 500 .udma_mask = ATA_UDMA6, 501 .port_ops = &piix_sata_ops, 502 }, 503 504 /* ich6_sata: 6 */ 505 { 506 .sht = &piix_sht, 507 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR, 508 .pio_mask = 0x1f, /* pio0-4 */ 509 .mwdma_mask = 0x07, /* mwdma0-2 */ 510 .udma_mask = ATA_UDMA6, 511 .port_ops = &piix_sata_ops, 512 }, 513 514 /* ich6_sata_ahci: 7 */ 515 { 516 .sht = &piix_sht, 517 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | 518 PIIX_FLAG_AHCI, 519 .pio_mask = 0x1f, /* pio0-4 */ 520 .mwdma_mask = 0x07, /* mwdma0-2 */ 521 .udma_mask = ATA_UDMA6, 522 .port_ops = &piix_sata_ops, 523 }, 524 525 /* ich6m_sata_ahci: 8 */ 526 { 527 .sht = &piix_sht, 528 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | 529 PIIX_FLAG_AHCI, 530 .pio_mask = 0x1f, /* pio0-4 */ 531 .mwdma_mask = 0x07, /* mwdma0-2 */ 532 .udma_mask = ATA_UDMA6, 533 .port_ops = &piix_sata_ops, 534 }, 535 536 /* ich8_sata_ahci: 9 */ 537 { 538 .sht = &piix_sht, 539 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | 540 PIIX_FLAG_AHCI, 541 .pio_mask = 0x1f, /* pio0-4 */ 542 .mwdma_mask = 0x07, /* mwdma0-2 */ 543 .udma_mask = ATA_UDMA6, 544 .port_ops = &piix_sata_ops, 545 }, 546 547 /* piix_pata_mwdma: 10: PIIX3 MWDMA only */ 548 { 549 .sht = &piix_sht, 550 .flags = PIIX_PATA_FLAGS, 551 .pio_mask = 0x1f, /* pio0-4 */ 552 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 553 .port_ops = &piix_pata_ops, 554 }, 555 }; 556 557 static struct pci_bits piix_enable_bits[] = { 558 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ 559 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ 560 }; 561 562 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik"); 563 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers"); 564 MODULE_LICENSE("GPL"); 565 MODULE_DEVICE_TABLE(pci, piix_pci_tbl); 566 MODULE_VERSION(DRV_VERSION); 567 568 struct ich_laptop { 569 u16 device; 570 u16 subvendor; 571 u16 subdevice; 572 }; 573 574 /* 575 * List of laptops that use short cables rather than 80 wire 576 */ 577 578 static const struct ich_laptop ich_laptop[] = { 579 /* devid, subvendor, subdev */ 580 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */ 581 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */ 582 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */ 583 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */ 584 /* end marker */ 585 { 0, } 586 }; 587 588 /** 589 * ich_pata_cable_detect - Probe host controller cable detect info 590 * @ap: Port for which cable detect info is desired 591 * 592 * Read 80c cable indicator from ATA PCI device's PCI config 593 * register. This register is normally set by firmware (BIOS). 594 * 595 * LOCKING: 596 * None (inherited from caller). 597 */ 598 599 static int ich_pata_cable_detect(struct ata_port *ap) 600 { 601 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 602 const struct ich_laptop *lap = &ich_laptop[0]; 603 u8 tmp, mask; 604 605 /* Check for specials - Acer Aspire 5602WLMi */ 606 while (lap->device) { 607 if (lap->device == pdev->device && 608 lap->subvendor == pdev->subsystem_vendor && 609 lap->subdevice == pdev->subsystem_device) { 610 return ATA_CBL_PATA40_SHORT; 611 } 612 lap++; 613 } 614 615 /* check BIOS cable detect results */ 616 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; 617 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp); 618 if ((tmp & mask) == 0) 619 return ATA_CBL_PATA40; 620 return ATA_CBL_PATA80; 621 } 622 623 /** 624 * piix_pata_prereset - prereset for PATA host controller 625 * @ap: Target port 626 * @deadline: deadline jiffies for the operation 627 * 628 * LOCKING: 629 * None (inherited from caller). 630 */ 631 static int piix_pata_prereset(struct ata_port *ap, unsigned long deadline) 632 { 633 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 634 635 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) 636 return -ENOENT; 637 return ata_std_prereset(ap, deadline); 638 } 639 640 static void piix_pata_error_handler(struct ata_port *ap) 641 { 642 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL, 643 ata_std_postreset); 644 } 645 646 /** 647 * piix_set_piomode - Initialize host controller PATA PIO timings 648 * @ap: Port whose timings we are configuring 649 * @adev: um 650 * 651 * Set PIO mode for device, in host controller PCI config space. 652 * 653 * LOCKING: 654 * None (inherited from caller). 655 */ 656 657 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev) 658 { 659 unsigned int pio = adev->pio_mode - XFER_PIO_0; 660 struct pci_dev *dev = to_pci_dev(ap->host->dev); 661 unsigned int is_slave = (adev->devno != 0); 662 unsigned int master_port= ap->port_no ? 0x42 : 0x40; 663 unsigned int slave_port = 0x44; 664 u16 master_data; 665 u8 slave_data; 666 u8 udma_enable; 667 int control = 0; 668 669 /* 670 * See Intel Document 298600-004 for the timing programing rules 671 * for ICH controllers. 672 */ 673 674 static const /* ISP RTC */ 675 u8 timings[][2] = { { 0, 0 }, 676 { 0, 0 }, 677 { 1, 0 }, 678 { 2, 1 }, 679 { 2, 3 }, }; 680 681 if (pio >= 2) 682 control |= 1; /* TIME1 enable */ 683 if (ata_pio_need_iordy(adev)) 684 control |= 2; /* IE enable */ 685 686 /* Intel specifies that the PPE functionality is for disk only */ 687 if (adev->class == ATA_DEV_ATA) 688 control |= 4; /* PPE enable */ 689 690 /* PIO configuration clears DTE unconditionally. It will be 691 * programmed in set_dmamode which is guaranteed to be called 692 * after set_piomode if any DMA mode is available. 693 */ 694 pci_read_config_word(dev, master_port, &master_data); 695 if (is_slave) { 696 /* clear TIME1|IE1|PPE1|DTE1 */ 697 master_data &= 0xff0f; 698 /* Enable SITRE (seperate slave timing register) */ 699 master_data |= 0x4000; 700 /* enable PPE1, IE1 and TIME1 as needed */ 701 master_data |= (control << 4); 702 pci_read_config_byte(dev, slave_port, &slave_data); 703 slave_data &= (ap->port_no ? 0x0f : 0xf0); 704 /* Load the timing nibble for this slave */ 705 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) 706 << (ap->port_no ? 4 : 0); 707 } else { 708 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */ 709 master_data &= 0xccf0; 710 /* Enable PPE, IE and TIME as appropriate */ 711 master_data |= control; 712 /* load ISP and RCT */ 713 master_data |= 714 (timings[pio][0] << 12) | 715 (timings[pio][1] << 8); 716 } 717 pci_write_config_word(dev, master_port, master_data); 718 if (is_slave) 719 pci_write_config_byte(dev, slave_port, slave_data); 720 721 /* Ensure the UDMA bit is off - it will be turned back on if 722 UDMA is selected */ 723 724 if (ap->udma_mask) { 725 pci_read_config_byte(dev, 0x48, &udma_enable); 726 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno)); 727 pci_write_config_byte(dev, 0x48, udma_enable); 728 } 729 } 730 731 /** 732 * do_pata_set_dmamode - Initialize host controller PATA PIO timings 733 * @ap: Port whose timings we are configuring 734 * @adev: Drive in question 735 * @udma: udma mode, 0 - 6 736 * @isich: set if the chip is an ICH device 737 * 738 * Set UDMA mode for device, in host controller PCI config space. 739 * 740 * LOCKING: 741 * None (inherited from caller). 742 */ 743 744 static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, int isich) 745 { 746 struct pci_dev *dev = to_pci_dev(ap->host->dev); 747 u8 master_port = ap->port_no ? 0x42 : 0x40; 748 u16 master_data; 749 u8 speed = adev->dma_mode; 750 int devid = adev->devno + 2 * ap->port_no; 751 u8 udma_enable = 0; 752 753 static const /* ISP RTC */ 754 u8 timings[][2] = { { 0, 0 }, 755 { 0, 0 }, 756 { 1, 0 }, 757 { 2, 1 }, 758 { 2, 3 }, }; 759 760 pci_read_config_word(dev, master_port, &master_data); 761 if (ap->udma_mask) 762 pci_read_config_byte(dev, 0x48, &udma_enable); 763 764 if (speed >= XFER_UDMA_0) { 765 unsigned int udma = adev->dma_mode - XFER_UDMA_0; 766 u16 udma_timing; 767 u16 ideconf; 768 int u_clock, u_speed; 769 770 /* 771 * UDMA is handled by a combination of clock switching and 772 * selection of dividers 773 * 774 * Handy rule: Odd modes are UDMATIMx 01, even are 02 775 * except UDMA0 which is 00 776 */ 777 u_speed = min(2 - (udma & 1), udma); 778 if (udma == 5) 779 u_clock = 0x1000; /* 100Mhz */ 780 else if (udma > 2) 781 u_clock = 1; /* 66Mhz */ 782 else 783 u_clock = 0; /* 33Mhz */ 784 785 udma_enable |= (1 << devid); 786 787 /* Load the CT/RP selection */ 788 pci_read_config_word(dev, 0x4A, &udma_timing); 789 udma_timing &= ~(3 << (4 * devid)); 790 udma_timing |= u_speed << (4 * devid); 791 pci_write_config_word(dev, 0x4A, udma_timing); 792 793 if (isich) { 794 /* Select a 33/66/100Mhz clock */ 795 pci_read_config_word(dev, 0x54, &ideconf); 796 ideconf &= ~(0x1001 << devid); 797 ideconf |= u_clock << devid; 798 /* For ICH or later we should set bit 10 for better 799 performance (WR_PingPong_En) */ 800 pci_write_config_word(dev, 0x54, ideconf); 801 } 802 } else { 803 /* 804 * MWDMA is driven by the PIO timings. We must also enable 805 * IORDY unconditionally along with TIME1. PPE has already 806 * been set when the PIO timing was set. 807 */ 808 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; 809 unsigned int control; 810 u8 slave_data; 811 const unsigned int needed_pio[3] = { 812 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 813 }; 814 int pio = needed_pio[mwdma] - XFER_PIO_0; 815 816 control = 3; /* IORDY|TIME1 */ 817 818 /* If the drive MWDMA is faster than it can do PIO then 819 we must force PIO into PIO0 */ 820 821 if (adev->pio_mode < needed_pio[mwdma]) 822 /* Enable DMA timing only */ 823 control |= 8; /* PIO cycles in PIO0 */ 824 825 if (adev->devno) { /* Slave */ 826 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */ 827 master_data |= control << 4; 828 pci_read_config_byte(dev, 0x44, &slave_data); 829 slave_data &= (ap->port_no ? 0x0f : 0xf0); 830 /* Load the matching timing */ 831 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); 832 pci_write_config_byte(dev, 0x44, slave_data); 833 } else { /* Master */ 834 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY 835 and master timing bits */ 836 master_data |= control; 837 master_data |= 838 (timings[pio][0] << 12) | 839 (timings[pio][1] << 8); 840 } 841 842 if (ap->udma_mask) { 843 udma_enable &= ~(1 << devid); 844 pci_write_config_word(dev, master_port, master_data); 845 } 846 } 847 /* Don't scribble on 0x48 if the controller does not support UDMA */ 848 if (ap->udma_mask) 849 pci_write_config_byte(dev, 0x48, udma_enable); 850 } 851 852 /** 853 * piix_set_dmamode - Initialize host controller PATA DMA timings 854 * @ap: Port whose timings we are configuring 855 * @adev: um 856 * 857 * Set MW/UDMA mode for device, in host controller PCI config space. 858 * 859 * LOCKING: 860 * None (inherited from caller). 861 */ 862 863 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev) 864 { 865 do_pata_set_dmamode(ap, adev, 0); 866 } 867 868 /** 869 * ich_set_dmamode - Initialize host controller PATA DMA timings 870 * @ap: Port whose timings we are configuring 871 * @adev: um 872 * 873 * Set MW/UDMA mode for device, in host controller PCI config space. 874 * 875 * LOCKING: 876 * None (inherited from caller). 877 */ 878 879 static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev) 880 { 881 do_pata_set_dmamode(ap, adev, 1); 882 } 883 884 #define AHCI_PCI_BAR 5 885 #define AHCI_GLOBAL_CTL 0x04 886 #define AHCI_ENABLE (1 << 31) 887 static int piix_disable_ahci(struct pci_dev *pdev) 888 { 889 void __iomem *mmio; 890 u32 tmp; 891 int rc = 0; 892 893 /* BUG: pci_enable_device has not yet been called. This 894 * works because this device is usually set up by BIOS. 895 */ 896 897 if (!pci_resource_start(pdev, AHCI_PCI_BAR) || 898 !pci_resource_len(pdev, AHCI_PCI_BAR)) 899 return 0; 900 901 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64); 902 if (!mmio) 903 return -ENOMEM; 904 905 tmp = readl(mmio + AHCI_GLOBAL_CTL); 906 if (tmp & AHCI_ENABLE) { 907 tmp &= ~AHCI_ENABLE; 908 writel(tmp, mmio + AHCI_GLOBAL_CTL); 909 910 tmp = readl(mmio + AHCI_GLOBAL_CTL); 911 if (tmp & AHCI_ENABLE) 912 rc = -EIO; 913 } 914 915 pci_iounmap(pdev, mmio); 916 return rc; 917 } 918 919 /** 920 * piix_check_450nx_errata - Check for problem 450NX setup 921 * @ata_dev: the PCI device to check 922 * 923 * Check for the present of 450NX errata #19 and errata #25. If 924 * they are found return an error code so we can turn off DMA 925 */ 926 927 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev) 928 { 929 struct pci_dev *pdev = NULL; 930 u16 cfg; 931 u8 rev; 932 int no_piix_dma = 0; 933 934 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) 935 { 936 /* Look for 450NX PXB. Check for problem configurations 937 A PCI quirk checks bit 6 already */ 938 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); 939 pci_read_config_word(pdev, 0x41, &cfg); 940 /* Only on the original revision: IDE DMA can hang */ 941 if (rev == 0x00) 942 no_piix_dma = 1; 943 /* On all revisions below 5 PXB bus lock must be disabled for IDE */ 944 else if (cfg & (1<<14) && rev < 5) 945 no_piix_dma = 2; 946 } 947 if (no_piix_dma) 948 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n"); 949 if (no_piix_dma == 2) 950 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n"); 951 return no_piix_dma; 952 } 953 954 static void __devinit piix_init_pcs(struct pci_dev *pdev, 955 struct ata_port_info *pinfo, 956 const struct piix_map_db *map_db) 957 { 958 u16 pcs, new_pcs; 959 960 pci_read_config_word(pdev, ICH5_PCS, &pcs); 961 962 new_pcs = pcs | map_db->port_enable; 963 964 if (new_pcs != pcs) { 965 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs); 966 pci_write_config_word(pdev, ICH5_PCS, new_pcs); 967 msleep(150); 968 } 969 } 970 971 static void __devinit piix_init_sata_map(struct pci_dev *pdev, 972 struct ata_port_info *pinfo, 973 const struct piix_map_db *map_db) 974 { 975 struct piix_host_priv *hpriv = pinfo[0].private_data; 976 const unsigned int *map; 977 int i, invalid_map = 0; 978 u8 map_value; 979 980 pci_read_config_byte(pdev, ICH5_PMR, &map_value); 981 982 map = map_db->map[map_value & map_db->mask]; 983 984 dev_printk(KERN_INFO, &pdev->dev, "MAP ["); 985 for (i = 0; i < 4; i++) { 986 switch (map[i]) { 987 case RV: 988 invalid_map = 1; 989 printk(" XX"); 990 break; 991 992 case NA: 993 printk(" --"); 994 break; 995 996 case IDE: 997 WARN_ON((i & 1) || map[i + 1] != IDE); 998 pinfo[i / 2] = piix_port_info[ich_pata_100]; 999 pinfo[i / 2].private_data = hpriv; 1000 i++; 1001 printk(" IDE IDE"); 1002 break; 1003 1004 default: 1005 printk(" P%d", map[i]); 1006 if (i & 1) 1007 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS; 1008 break; 1009 } 1010 } 1011 printk(" ]\n"); 1012 1013 if (invalid_map) 1014 dev_printk(KERN_ERR, &pdev->dev, 1015 "invalid MAP value %u\n", map_value); 1016 1017 hpriv->map = map; 1018 } 1019 1020 /** 1021 * piix_init_one - Register PIIX ATA PCI device with kernel services 1022 * @pdev: PCI device to register 1023 * @ent: Entry in piix_pci_tbl matching with @pdev 1024 * 1025 * Called from kernel PCI layer. We probe for combined mode (sigh), 1026 * and then hand over control to libata, for it to do the rest. 1027 * 1028 * LOCKING: 1029 * Inherited from PCI layer (may sleep). 1030 * 1031 * RETURNS: 1032 * Zero on success, or -ERRNO value. 1033 */ 1034 1035 static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 1036 { 1037 static int printed_version; 1038 struct device *dev = &pdev->dev; 1039 struct ata_port_info port_info[2]; 1040 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] }; 1041 struct piix_host_priv *hpriv; 1042 unsigned long port_flags; 1043 1044 if (!printed_version++) 1045 dev_printk(KERN_DEBUG, &pdev->dev, 1046 "version " DRV_VERSION "\n"); 1047 1048 /* no hotplugging support (FIXME) */ 1049 if (!in_module_init) 1050 return -ENODEV; 1051 1052 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1053 if (!hpriv) 1054 return -ENOMEM; 1055 1056 port_info[0] = piix_port_info[ent->driver_data]; 1057 port_info[1] = piix_port_info[ent->driver_data]; 1058 port_info[0].private_data = hpriv; 1059 port_info[1].private_data = hpriv; 1060 1061 port_flags = port_info[0].flags; 1062 1063 if (port_flags & PIIX_FLAG_AHCI) { 1064 u8 tmp; 1065 pci_read_config_byte(pdev, PIIX_SCC, &tmp); 1066 if (tmp == PIIX_AHCI_DEVICE) { 1067 int rc = piix_disable_ahci(pdev); 1068 if (rc) 1069 return rc; 1070 } 1071 } 1072 1073 /* Initialize SATA map */ 1074 if (port_flags & ATA_FLAG_SATA) { 1075 piix_init_sata_map(pdev, port_info, 1076 piix_map_db_table[ent->driver_data]); 1077 piix_init_pcs(pdev, port_info, 1078 piix_map_db_table[ent->driver_data]); 1079 } 1080 1081 /* On ICH5, some BIOSen disable the interrupt using the 1082 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. 1083 * On ICH6, this bit has the same effect, but only when 1084 * MSI is disabled (and it is disabled, as we don't use 1085 * message-signalled interrupts currently). 1086 */ 1087 if (port_flags & PIIX_FLAG_CHECKINTR) 1088 pci_intx(pdev, 1); 1089 1090 if (piix_check_450nx_errata(pdev)) { 1091 /* This writes into the master table but it does not 1092 really matter for this errata as we will apply it to 1093 all the PIIX devices on the board */ 1094 port_info[0].mwdma_mask = 0; 1095 port_info[0].udma_mask = 0; 1096 port_info[1].mwdma_mask = 0; 1097 port_info[1].udma_mask = 0; 1098 } 1099 return ata_pci_init_one(pdev, ppi); 1100 } 1101 1102 static int __init piix_init(void) 1103 { 1104 int rc; 1105 1106 DPRINTK("pci_register_driver\n"); 1107 rc = pci_register_driver(&piix_pci_driver); 1108 if (rc) 1109 return rc; 1110 1111 in_module_init = 0; 1112 1113 DPRINTK("done\n"); 1114 return 0; 1115 } 1116 1117 static void __exit piix_exit(void) 1118 { 1119 pci_unregister_driver(&piix_pci_driver); 1120 } 1121 1122 module_init(piix_init); 1123 module_exit(piix_exit); 1124