1 /* 2 * ata_piix.c - Intel PATA/SATA controllers 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * 9 * Copyright 2003-2005 Red Hat Inc 10 * Copyright 2003-2005 Jeff Garzik 11 * 12 * 13 * Copyright header from piix.c: 14 * 15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer 16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> 17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com> 18 * 19 * 20 * This program is free software; you can redistribute it and/or modify 21 * it under the terms of the GNU General Public License as published by 22 * the Free Software Foundation; either version 2, or (at your option) 23 * any later version. 24 * 25 * This program is distributed in the hope that it will be useful, 26 * but WITHOUT ANY WARRANTY; without even the implied warranty of 27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 28 * GNU General Public License for more details. 29 * 30 * You should have received a copy of the GNU General Public License 31 * along with this program; see the file COPYING. If not, write to 32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 33 * 34 * 35 * libata documentation is available via 'make {ps|pdf}docs', 36 * as Documentation/DocBook/libata.* 37 * 38 * Hardware documentation available at http://developer.intel.com/ 39 * 40 * Documentation 41 * Publically available from Intel web site. Errata documentation 42 * is also publically available. As an aide to anyone hacking on this 43 * driver the list of errata that are relevant is below, going back to 44 * PIIX4. Older device documentation is now a bit tricky to find. 45 * 46 * The chipsets all follow very much the same design. The orginal Triton 47 * series chipsets do _not_ support independant device timings, but this 48 * is fixed in Triton II. With the odd mobile exception the chips then 49 * change little except in gaining more modes until SATA arrives. This 50 * driver supports only the chips with independant timing (that is those 51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix 52 * for the early chip drivers. 53 * 54 * Errata of note: 55 * 56 * Unfixable 57 * PIIX4 errata #9 - Only on ultra obscure hw 58 * ICH3 errata #13 - Not observed to affect real hw 59 * by Intel 60 * 61 * Things we must deal with 62 * PIIX4 errata #10 - BM IDE hang with non UDMA 63 * (must stop/start dma to recover) 64 * 440MX errata #15 - As PIIX4 errata #10 65 * PIIX4 errata #15 - Must not read control registers 66 * during a PIO transfer 67 * 440MX errata #13 - As PIIX4 errata #15 68 * ICH2 errata #21 - DMA mode 0 doesn't work right 69 * ICH0/1 errata #55 - As ICH2 errata #21 70 * ICH2 spec c #9 - Extra operations needed to handle 71 * drive hotswap [NOT YET SUPPORTED] 72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary 73 * and must be dword aligned 74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 75 * 76 * Should have been BIOS fixed: 77 * 450NX: errata #19 - DMA hangs on old 450NX 78 * 450NX: errata #20 - DMA hangs on old 450NX 79 * 450NX: errata #25 - Corruption with DMA on old 450NX 80 * ICH3 errata #15 - IDE deadlock under high load 81 * (BIOS must set dev 31 fn 0 bit 23) 82 * ICH3 errata #18 - Don't use native mode 83 */ 84 85 #include <linux/kernel.h> 86 #include <linux/module.h> 87 #include <linux/pci.h> 88 #include <linux/init.h> 89 #include <linux/blkdev.h> 90 #include <linux/delay.h> 91 #include <linux/device.h> 92 #include <scsi/scsi_host.h> 93 #include <linux/libata.h> 94 #include <linux/dmi.h> 95 96 #define DRV_NAME "ata_piix" 97 #define DRV_VERSION "2.12" 98 99 enum { 100 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ 101 ICH5_PMR = 0x90, /* port mapping register */ 102 ICH5_PCS = 0x92, /* port control and status */ 103 PIIX_SIDPR_BAR = 5, 104 PIIX_SIDPR_LEN = 16, 105 PIIX_SIDPR_IDX = 0, 106 PIIX_SIDPR_DATA = 4, 107 108 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */ 109 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */ 110 111 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS, 112 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR, 113 114 PIIX_80C_PRI = (1 << 5) | (1 << 4), 115 PIIX_80C_SEC = (1 << 7) | (1 << 6), 116 117 /* constants for mapping table */ 118 P0 = 0, /* port 0 */ 119 P1 = 1, /* port 1 */ 120 P2 = 2, /* port 2 */ 121 P3 = 3, /* port 3 */ 122 IDE = -1, /* IDE */ 123 NA = -2, /* not avaliable */ 124 RV = -3, /* reserved */ 125 126 PIIX_AHCI_DEVICE = 6, 127 128 /* host->flags bits */ 129 PIIX_HOST_BROKEN_SUSPEND = (1 << 24), 130 }; 131 132 enum piix_controller_ids { 133 /* controller IDs */ 134 piix_pata_mwdma, /* PIIX3 MWDMA only */ 135 piix_pata_33, /* PIIX4 at 33Mhz */ 136 ich_pata_33, /* ICH up to UDMA 33 only */ 137 ich_pata_66, /* ICH up to 66 Mhz */ 138 ich_pata_100, /* ICH up to UDMA 100 */ 139 ich5_sata, 140 ich6_sata, 141 ich6m_sata, 142 ich8_sata, 143 ich8_2port_sata, 144 ich8m_apple_sata, /* locks up on second port enable */ 145 tolapai_sata, 146 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */ 147 }; 148 149 struct piix_map_db { 150 const u32 mask; 151 const u16 port_enable; 152 const int map[][4]; 153 }; 154 155 struct piix_host_priv { 156 const int *map; 157 void __iomem *sidpr; 158 }; 159 160 static int piix_init_one(struct pci_dev *pdev, 161 const struct pci_device_id *ent); 162 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline); 163 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev); 164 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev); 165 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev); 166 static int ich_pata_cable_detect(struct ata_port *ap); 167 static u8 piix_vmw_bmdma_status(struct ata_port *ap); 168 static int piix_sidpr_scr_read(struct ata_port *ap, unsigned int reg, u32 *val); 169 static int piix_sidpr_scr_write(struct ata_port *ap, unsigned int reg, u32 val); 170 #ifdef CONFIG_PM 171 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); 172 static int piix_pci_device_resume(struct pci_dev *pdev); 173 #endif 174 175 static unsigned int in_module_init = 1; 176 177 static const struct pci_device_id piix_pci_tbl[] = { 178 /* Intel PIIX3 for the 430HX etc */ 179 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma }, 180 /* VMware ICH4 */ 181 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw }, 182 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */ 183 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */ 184 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 185 /* Intel PIIX4 */ 186 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 187 /* Intel PIIX4 */ 188 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 189 /* Intel PIIX */ 190 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 191 /* Intel ICH (i810, i815, i840) UDMA 66*/ 192 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 }, 193 /* Intel ICH0 : UDMA 33*/ 194 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 }, 195 /* Intel ICH2M */ 196 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 197 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */ 198 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 199 /* Intel ICH3M */ 200 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 201 /* Intel ICH3 (E7500/1) UDMA 100 */ 202 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 203 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */ 204 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 205 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 206 /* Intel ICH5 */ 207 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 208 /* C-ICH (i810E2) */ 209 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 210 /* ESB (855GME/875P + 6300ESB) UDMA 100 */ 211 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 212 /* ICH6 (and 6) (i915) UDMA 100 */ 213 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 214 /* ICH7/7-R (i945, i975) UDMA 100*/ 215 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 216 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 217 /* ICH8 Mobile PATA Controller */ 218 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 219 220 /* NOTE: The following PCI ids must be kept in sync with the 221 * list in drivers/pci/quirks.c. 222 */ 223 224 /* 82801EB (ICH5) */ 225 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 226 /* 82801EB (ICH5) */ 227 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 228 /* 6300ESB (ICH5 variant with broken PCS present bits) */ 229 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 230 /* 6300ESB pretending RAID */ 231 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 232 /* 82801FB/FW (ICH6/ICH6W) */ 233 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 234 /* 82801FR/FRW (ICH6R/ICH6RW) */ 235 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 236 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented). 237 * Attach iff the controller is in IDE mode. */ 238 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 239 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata }, 240 /* 82801GB/GR/GH (ICH7, identical to ICH6) */ 241 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 242 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */ 243 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata }, 244 /* Enterprise Southbridge 2 (631xESB/632xESB) */ 245 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 246 /* SATA Controller 1 IDE (ICH8) */ 247 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 248 /* SATA Controller 2 IDE (ICH8) */ 249 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 250 /* Mobile SATA Controller IDE (ICH8M) */ 251 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 252 /* Mobile SATA Controller IDE (ICH8M), Apple */ 253 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata }, 254 /* SATA Controller IDE (ICH9) */ 255 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 256 /* SATA Controller IDE (ICH9) */ 257 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 258 /* SATA Controller IDE (ICH9) */ 259 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 260 /* SATA Controller IDE (ICH9M) */ 261 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 262 /* SATA Controller IDE (ICH9M) */ 263 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 264 /* SATA Controller IDE (ICH9M) */ 265 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 266 /* SATA Controller IDE (Tolapai) */ 267 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata }, 268 /* SATA Controller IDE (ICH10) */ 269 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 270 /* SATA Controller IDE (ICH10) */ 271 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 272 /* SATA Controller IDE (ICH10) */ 273 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 274 /* SATA Controller IDE (ICH10) */ 275 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 276 277 { } /* terminate list */ 278 }; 279 280 static struct pci_driver piix_pci_driver = { 281 .name = DRV_NAME, 282 .id_table = piix_pci_tbl, 283 .probe = piix_init_one, 284 .remove = ata_pci_remove_one, 285 #ifdef CONFIG_PM 286 .suspend = piix_pci_device_suspend, 287 .resume = piix_pci_device_resume, 288 #endif 289 }; 290 291 static struct scsi_host_template piix_sht = { 292 ATA_BMDMA_SHT(DRV_NAME), 293 }; 294 295 static struct ata_port_operations piix_pata_ops = { 296 .inherits = &ata_bmdma_port_ops, 297 .cable_detect = ata_cable_40wire, 298 .set_piomode = piix_set_piomode, 299 .set_dmamode = piix_set_dmamode, 300 .prereset = piix_pata_prereset, 301 }; 302 303 static struct ata_port_operations piix_vmw_ops = { 304 .inherits = &piix_pata_ops, 305 .bmdma_status = piix_vmw_bmdma_status, 306 }; 307 308 static struct ata_port_operations ich_pata_ops = { 309 .inherits = &piix_pata_ops, 310 .cable_detect = ich_pata_cable_detect, 311 .set_dmamode = ich_set_dmamode, 312 }; 313 314 static struct ata_port_operations piix_sata_ops = { 315 .inherits = &ata_bmdma_port_ops, 316 }; 317 318 static struct ata_port_operations piix_sidpr_sata_ops = { 319 .inherits = &piix_sata_ops, 320 .hardreset = sata_std_hardreset, 321 .scr_read = piix_sidpr_scr_read, 322 .scr_write = piix_sidpr_scr_write, 323 }; 324 325 static const struct piix_map_db ich5_map_db = { 326 .mask = 0x7, 327 .port_enable = 0x3, 328 .map = { 329 /* PM PS SM SS MAP */ 330 { P0, NA, P1, NA }, /* 000b */ 331 { P1, NA, P0, NA }, /* 001b */ 332 { RV, RV, RV, RV }, 333 { RV, RV, RV, RV }, 334 { P0, P1, IDE, IDE }, /* 100b */ 335 { P1, P0, IDE, IDE }, /* 101b */ 336 { IDE, IDE, P0, P1 }, /* 110b */ 337 { IDE, IDE, P1, P0 }, /* 111b */ 338 }, 339 }; 340 341 static const struct piix_map_db ich6_map_db = { 342 .mask = 0x3, 343 .port_enable = 0xf, 344 .map = { 345 /* PM PS SM SS MAP */ 346 { P0, P2, P1, P3 }, /* 00b */ 347 { IDE, IDE, P1, P3 }, /* 01b */ 348 { P0, P2, IDE, IDE }, /* 10b */ 349 { RV, RV, RV, RV }, 350 }, 351 }; 352 353 static const struct piix_map_db ich6m_map_db = { 354 .mask = 0x3, 355 .port_enable = 0x5, 356 357 /* Map 01b isn't specified in the doc but some notebooks use 358 * it anyway. MAP 01b have been spotted on both ICH6M and 359 * ICH7M. 360 */ 361 .map = { 362 /* PM PS SM SS MAP */ 363 { P0, P2, NA, NA }, /* 00b */ 364 { IDE, IDE, P1, P3 }, /* 01b */ 365 { P0, P2, IDE, IDE }, /* 10b */ 366 { RV, RV, RV, RV }, 367 }, 368 }; 369 370 static const struct piix_map_db ich8_map_db = { 371 .mask = 0x3, 372 .port_enable = 0xf, 373 .map = { 374 /* PM PS SM SS MAP */ 375 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */ 376 { RV, RV, RV, RV }, 377 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */ 378 { RV, RV, RV, RV }, 379 }, 380 }; 381 382 static const struct piix_map_db ich8_2port_map_db = { 383 .mask = 0x3, 384 .port_enable = 0x3, 385 .map = { 386 /* PM PS SM SS MAP */ 387 { P0, NA, P1, NA }, /* 00b */ 388 { RV, RV, RV, RV }, /* 01b */ 389 { RV, RV, RV, RV }, /* 10b */ 390 { RV, RV, RV, RV }, 391 }, 392 }; 393 394 static const struct piix_map_db ich8m_apple_map_db = { 395 .mask = 0x3, 396 .port_enable = 0x1, 397 .map = { 398 /* PM PS SM SS MAP */ 399 { P0, NA, NA, NA }, /* 00b */ 400 { RV, RV, RV, RV }, 401 { P0, P2, IDE, IDE }, /* 10b */ 402 { RV, RV, RV, RV }, 403 }, 404 }; 405 406 static const struct piix_map_db tolapai_map_db = { 407 .mask = 0x3, 408 .port_enable = 0x3, 409 .map = { 410 /* PM PS SM SS MAP */ 411 { P0, NA, P1, NA }, /* 00b */ 412 { RV, RV, RV, RV }, /* 01b */ 413 { RV, RV, RV, RV }, /* 10b */ 414 { RV, RV, RV, RV }, 415 }, 416 }; 417 418 static const struct piix_map_db *piix_map_db_table[] = { 419 [ich5_sata] = &ich5_map_db, 420 [ich6_sata] = &ich6_map_db, 421 [ich6m_sata] = &ich6m_map_db, 422 [ich8_sata] = &ich8_map_db, 423 [ich8_2port_sata] = &ich8_2port_map_db, 424 [ich8m_apple_sata] = &ich8m_apple_map_db, 425 [tolapai_sata] = &tolapai_map_db, 426 }; 427 428 static struct ata_port_info piix_port_info[] = { 429 [piix_pata_mwdma] = /* PIIX3 MWDMA only */ 430 { 431 .flags = PIIX_PATA_FLAGS, 432 .pio_mask = 0x1f, /* pio0-4 */ 433 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 434 .port_ops = &piix_pata_ops, 435 }, 436 437 [piix_pata_33] = /* PIIX4 at 33MHz */ 438 { 439 .flags = PIIX_PATA_FLAGS, 440 .pio_mask = 0x1f, /* pio0-4 */ 441 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 442 .udma_mask = ATA_UDMA_MASK_40C, 443 .port_ops = &piix_pata_ops, 444 }, 445 446 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/ 447 { 448 .flags = PIIX_PATA_FLAGS, 449 .pio_mask = 0x1f, /* pio 0-4 */ 450 .mwdma_mask = 0x06, /* Check: maybe 0x07 */ 451 .udma_mask = ATA_UDMA2, /* UDMA33 */ 452 .port_ops = &ich_pata_ops, 453 }, 454 455 [ich_pata_66] = /* ICH controllers up to 66MHz */ 456 { 457 .flags = PIIX_PATA_FLAGS, 458 .pio_mask = 0x1f, /* pio 0-4 */ 459 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */ 460 .udma_mask = ATA_UDMA4, 461 .port_ops = &ich_pata_ops, 462 }, 463 464 [ich_pata_100] = 465 { 466 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, 467 .pio_mask = 0x1f, /* pio0-4 */ 468 .mwdma_mask = 0x06, /* mwdma1-2 */ 469 .udma_mask = ATA_UDMA5, /* udma0-5 */ 470 .port_ops = &ich_pata_ops, 471 }, 472 473 [ich5_sata] = 474 { 475 .flags = PIIX_SATA_FLAGS, 476 .pio_mask = 0x1f, /* pio0-4 */ 477 .mwdma_mask = 0x07, /* mwdma0-2 */ 478 .udma_mask = ATA_UDMA6, 479 .port_ops = &piix_sata_ops, 480 }, 481 482 [ich6_sata] = 483 { 484 .flags = PIIX_SATA_FLAGS, 485 .pio_mask = 0x1f, /* pio0-4 */ 486 .mwdma_mask = 0x07, /* mwdma0-2 */ 487 .udma_mask = ATA_UDMA6, 488 .port_ops = &piix_sata_ops, 489 }, 490 491 [ich6m_sata] = 492 { 493 .flags = PIIX_SATA_FLAGS, 494 .pio_mask = 0x1f, /* pio0-4 */ 495 .mwdma_mask = 0x07, /* mwdma0-2 */ 496 .udma_mask = ATA_UDMA6, 497 .port_ops = &piix_sata_ops, 498 }, 499 500 [ich8_sata] = 501 { 502 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, 503 .pio_mask = 0x1f, /* pio0-4 */ 504 .mwdma_mask = 0x07, /* mwdma0-2 */ 505 .udma_mask = ATA_UDMA6, 506 .port_ops = &piix_sata_ops, 507 }, 508 509 [ich8_2port_sata] = 510 { 511 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, 512 .pio_mask = 0x1f, /* pio0-4 */ 513 .mwdma_mask = 0x07, /* mwdma0-2 */ 514 .udma_mask = ATA_UDMA6, 515 .port_ops = &piix_sata_ops, 516 }, 517 518 [tolapai_sata] = 519 { 520 .flags = PIIX_SATA_FLAGS, 521 .pio_mask = 0x1f, /* pio0-4 */ 522 .mwdma_mask = 0x07, /* mwdma0-2 */ 523 .udma_mask = ATA_UDMA6, 524 .port_ops = &piix_sata_ops, 525 }, 526 527 [ich8m_apple_sata] = 528 { 529 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, 530 .pio_mask = 0x1f, /* pio0-4 */ 531 .mwdma_mask = 0x07, /* mwdma0-2 */ 532 .udma_mask = ATA_UDMA6, 533 .port_ops = &piix_sata_ops, 534 }, 535 536 [piix_pata_vmw] = 537 { 538 .flags = PIIX_PATA_FLAGS, 539 .pio_mask = 0x1f, /* pio0-4 */ 540 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 541 .udma_mask = ATA_UDMA_MASK_40C, 542 .port_ops = &piix_vmw_ops, 543 }, 544 545 }; 546 547 static struct pci_bits piix_enable_bits[] = { 548 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ 549 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ 550 }; 551 552 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik"); 553 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers"); 554 MODULE_LICENSE("GPL"); 555 MODULE_DEVICE_TABLE(pci, piix_pci_tbl); 556 MODULE_VERSION(DRV_VERSION); 557 558 struct ich_laptop { 559 u16 device; 560 u16 subvendor; 561 u16 subdevice; 562 }; 563 564 /* 565 * List of laptops that use short cables rather than 80 wire 566 */ 567 568 static const struct ich_laptop ich_laptop[] = { 569 /* devid, subvendor, subdev */ 570 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */ 571 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */ 572 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */ 573 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */ 574 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */ 575 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */ 576 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */ 577 /* end marker */ 578 { 0, } 579 }; 580 581 /** 582 * ich_pata_cable_detect - Probe host controller cable detect info 583 * @ap: Port for which cable detect info is desired 584 * 585 * Read 80c cable indicator from ATA PCI device's PCI config 586 * register. This register is normally set by firmware (BIOS). 587 * 588 * LOCKING: 589 * None (inherited from caller). 590 */ 591 592 static int ich_pata_cable_detect(struct ata_port *ap) 593 { 594 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 595 const struct ich_laptop *lap = &ich_laptop[0]; 596 u8 tmp, mask; 597 598 /* Check for specials - Acer Aspire 5602WLMi */ 599 while (lap->device) { 600 if (lap->device == pdev->device && 601 lap->subvendor == pdev->subsystem_vendor && 602 lap->subdevice == pdev->subsystem_device) 603 return ATA_CBL_PATA40_SHORT; 604 605 lap++; 606 } 607 608 /* check BIOS cable detect results */ 609 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; 610 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp); 611 if ((tmp & mask) == 0) 612 return ATA_CBL_PATA40; 613 return ATA_CBL_PATA80; 614 } 615 616 /** 617 * piix_pata_prereset - prereset for PATA host controller 618 * @link: Target link 619 * @deadline: deadline jiffies for the operation 620 * 621 * LOCKING: 622 * None (inherited from caller). 623 */ 624 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline) 625 { 626 struct ata_port *ap = link->ap; 627 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 628 629 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) 630 return -ENOENT; 631 return ata_sff_prereset(link, deadline); 632 } 633 634 /** 635 * piix_set_piomode - Initialize host controller PATA PIO timings 636 * @ap: Port whose timings we are configuring 637 * @adev: um 638 * 639 * Set PIO mode for device, in host controller PCI config space. 640 * 641 * LOCKING: 642 * None (inherited from caller). 643 */ 644 645 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev) 646 { 647 unsigned int pio = adev->pio_mode - XFER_PIO_0; 648 struct pci_dev *dev = to_pci_dev(ap->host->dev); 649 unsigned int is_slave = (adev->devno != 0); 650 unsigned int master_port= ap->port_no ? 0x42 : 0x40; 651 unsigned int slave_port = 0x44; 652 u16 master_data; 653 u8 slave_data; 654 u8 udma_enable; 655 int control = 0; 656 657 /* 658 * See Intel Document 298600-004 for the timing programing rules 659 * for ICH controllers. 660 */ 661 662 static const /* ISP RTC */ 663 u8 timings[][2] = { { 0, 0 }, 664 { 0, 0 }, 665 { 1, 0 }, 666 { 2, 1 }, 667 { 2, 3 }, }; 668 669 if (pio >= 2) 670 control |= 1; /* TIME1 enable */ 671 if (ata_pio_need_iordy(adev)) 672 control |= 2; /* IE enable */ 673 674 /* Intel specifies that the PPE functionality is for disk only */ 675 if (adev->class == ATA_DEV_ATA) 676 control |= 4; /* PPE enable */ 677 678 /* PIO configuration clears DTE unconditionally. It will be 679 * programmed in set_dmamode which is guaranteed to be called 680 * after set_piomode if any DMA mode is available. 681 */ 682 pci_read_config_word(dev, master_port, &master_data); 683 if (is_slave) { 684 /* clear TIME1|IE1|PPE1|DTE1 */ 685 master_data &= 0xff0f; 686 /* Enable SITRE (separate slave timing register) */ 687 master_data |= 0x4000; 688 /* enable PPE1, IE1 and TIME1 as needed */ 689 master_data |= (control << 4); 690 pci_read_config_byte(dev, slave_port, &slave_data); 691 slave_data &= (ap->port_no ? 0x0f : 0xf0); 692 /* Load the timing nibble for this slave */ 693 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) 694 << (ap->port_no ? 4 : 0); 695 } else { 696 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */ 697 master_data &= 0xccf0; 698 /* Enable PPE, IE and TIME as appropriate */ 699 master_data |= control; 700 /* load ISP and RCT */ 701 master_data |= 702 (timings[pio][0] << 12) | 703 (timings[pio][1] << 8); 704 } 705 pci_write_config_word(dev, master_port, master_data); 706 if (is_slave) 707 pci_write_config_byte(dev, slave_port, slave_data); 708 709 /* Ensure the UDMA bit is off - it will be turned back on if 710 UDMA is selected */ 711 712 if (ap->udma_mask) { 713 pci_read_config_byte(dev, 0x48, &udma_enable); 714 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno)); 715 pci_write_config_byte(dev, 0x48, udma_enable); 716 } 717 } 718 719 /** 720 * do_pata_set_dmamode - Initialize host controller PATA PIO timings 721 * @ap: Port whose timings we are configuring 722 * @adev: Drive in question 723 * @udma: udma mode, 0 - 6 724 * @isich: set if the chip is an ICH device 725 * 726 * Set UDMA mode for device, in host controller PCI config space. 727 * 728 * LOCKING: 729 * None (inherited from caller). 730 */ 731 732 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich) 733 { 734 struct pci_dev *dev = to_pci_dev(ap->host->dev); 735 u8 master_port = ap->port_no ? 0x42 : 0x40; 736 u16 master_data; 737 u8 speed = adev->dma_mode; 738 int devid = adev->devno + 2 * ap->port_no; 739 u8 udma_enable = 0; 740 741 static const /* ISP RTC */ 742 u8 timings[][2] = { { 0, 0 }, 743 { 0, 0 }, 744 { 1, 0 }, 745 { 2, 1 }, 746 { 2, 3 }, }; 747 748 pci_read_config_word(dev, master_port, &master_data); 749 if (ap->udma_mask) 750 pci_read_config_byte(dev, 0x48, &udma_enable); 751 752 if (speed >= XFER_UDMA_0) { 753 unsigned int udma = adev->dma_mode - XFER_UDMA_0; 754 u16 udma_timing; 755 u16 ideconf; 756 int u_clock, u_speed; 757 758 /* 759 * UDMA is handled by a combination of clock switching and 760 * selection of dividers 761 * 762 * Handy rule: Odd modes are UDMATIMx 01, even are 02 763 * except UDMA0 which is 00 764 */ 765 u_speed = min(2 - (udma & 1), udma); 766 if (udma == 5) 767 u_clock = 0x1000; /* 100Mhz */ 768 else if (udma > 2) 769 u_clock = 1; /* 66Mhz */ 770 else 771 u_clock = 0; /* 33Mhz */ 772 773 udma_enable |= (1 << devid); 774 775 /* Load the CT/RP selection */ 776 pci_read_config_word(dev, 0x4A, &udma_timing); 777 udma_timing &= ~(3 << (4 * devid)); 778 udma_timing |= u_speed << (4 * devid); 779 pci_write_config_word(dev, 0x4A, udma_timing); 780 781 if (isich) { 782 /* Select a 33/66/100Mhz clock */ 783 pci_read_config_word(dev, 0x54, &ideconf); 784 ideconf &= ~(0x1001 << devid); 785 ideconf |= u_clock << devid; 786 /* For ICH or later we should set bit 10 for better 787 performance (WR_PingPong_En) */ 788 pci_write_config_word(dev, 0x54, ideconf); 789 } 790 } else { 791 /* 792 * MWDMA is driven by the PIO timings. We must also enable 793 * IORDY unconditionally along with TIME1. PPE has already 794 * been set when the PIO timing was set. 795 */ 796 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; 797 unsigned int control; 798 u8 slave_data; 799 const unsigned int needed_pio[3] = { 800 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 801 }; 802 int pio = needed_pio[mwdma] - XFER_PIO_0; 803 804 control = 3; /* IORDY|TIME1 */ 805 806 /* If the drive MWDMA is faster than it can do PIO then 807 we must force PIO into PIO0 */ 808 809 if (adev->pio_mode < needed_pio[mwdma]) 810 /* Enable DMA timing only */ 811 control |= 8; /* PIO cycles in PIO0 */ 812 813 if (adev->devno) { /* Slave */ 814 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */ 815 master_data |= control << 4; 816 pci_read_config_byte(dev, 0x44, &slave_data); 817 slave_data &= (ap->port_no ? 0x0f : 0xf0); 818 /* Load the matching timing */ 819 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); 820 pci_write_config_byte(dev, 0x44, slave_data); 821 } else { /* Master */ 822 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY 823 and master timing bits */ 824 master_data |= control; 825 master_data |= 826 (timings[pio][0] << 12) | 827 (timings[pio][1] << 8); 828 } 829 830 if (ap->udma_mask) { 831 udma_enable &= ~(1 << devid); 832 pci_write_config_word(dev, master_port, master_data); 833 } 834 } 835 /* Don't scribble on 0x48 if the controller does not support UDMA */ 836 if (ap->udma_mask) 837 pci_write_config_byte(dev, 0x48, udma_enable); 838 } 839 840 /** 841 * piix_set_dmamode - Initialize host controller PATA DMA timings 842 * @ap: Port whose timings we are configuring 843 * @adev: um 844 * 845 * Set MW/UDMA mode for device, in host controller PCI config space. 846 * 847 * LOCKING: 848 * None (inherited from caller). 849 */ 850 851 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev) 852 { 853 do_pata_set_dmamode(ap, adev, 0); 854 } 855 856 /** 857 * ich_set_dmamode - Initialize host controller PATA DMA timings 858 * @ap: Port whose timings we are configuring 859 * @adev: um 860 * 861 * Set MW/UDMA mode for device, in host controller PCI config space. 862 * 863 * LOCKING: 864 * None (inherited from caller). 865 */ 866 867 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev) 868 { 869 do_pata_set_dmamode(ap, adev, 1); 870 } 871 872 /* 873 * Serial ATA Index/Data Pair Superset Registers access 874 * 875 * Beginning from ICH8, there's a sane way to access SCRs using index 876 * and data register pair located at BAR5. This creates an 877 * interesting problem of mapping two SCRs to one port. 878 * 879 * Although they have separate SCRs, the master and slave aren't 880 * independent enough to be treated as separate links - e.g. softreset 881 * resets both. Also, there's no protocol defined for hard resetting 882 * singled device sharing the virtual port (no defined way to acquire 883 * device signature). This is worked around by merging the SCR values 884 * into one sensible value and requesting follow-up SRST after 885 * hardreset. 886 * 887 * SCR merging is perfomed in nibbles which is the unit contents in 888 * SCRs are organized. If two values are equal, the value is used. 889 * When they differ, merge table which lists precedence of possible 890 * values is consulted and the first match or the last entry when 891 * nothing matches is used. When there's no merge table for the 892 * specific nibble, value from the first port is used. 893 */ 894 static const int piix_sidx_map[] = { 895 [SCR_STATUS] = 0, 896 [SCR_ERROR] = 2, 897 [SCR_CONTROL] = 1, 898 }; 899 900 static void piix_sidpr_sel(struct ata_device *dev, unsigned int reg) 901 { 902 struct ata_port *ap = dev->link->ap; 903 struct piix_host_priv *hpriv = ap->host->private_data; 904 905 iowrite32(((ap->port_no * 2 + dev->devno) << 8) | piix_sidx_map[reg], 906 hpriv->sidpr + PIIX_SIDPR_IDX); 907 } 908 909 static int piix_sidpr_read(struct ata_device *dev, unsigned int reg) 910 { 911 struct piix_host_priv *hpriv = dev->link->ap->host->private_data; 912 913 piix_sidpr_sel(dev, reg); 914 return ioread32(hpriv->sidpr + PIIX_SIDPR_DATA); 915 } 916 917 static void piix_sidpr_write(struct ata_device *dev, unsigned int reg, u32 val) 918 { 919 struct piix_host_priv *hpriv = dev->link->ap->host->private_data; 920 921 piix_sidpr_sel(dev, reg); 922 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA); 923 } 924 925 static u32 piix_merge_scr(u32 val0, u32 val1, const int * const *merge_tbl) 926 { 927 u32 val = 0; 928 int i, mi; 929 930 for (i = 0, mi = 0; i < 32 / 4; i++) { 931 u8 c0 = (val0 >> (i * 4)) & 0xf; 932 u8 c1 = (val1 >> (i * 4)) & 0xf; 933 u8 merged = c0; 934 const int *cur; 935 936 /* if no merge preference, assume the first value */ 937 cur = merge_tbl[mi]; 938 if (!cur) 939 goto done; 940 mi++; 941 942 /* if two values equal, use it */ 943 if (c0 == c1) 944 goto done; 945 946 /* choose the first match or the last from the merge table */ 947 while (*cur != -1) { 948 if (c0 == *cur || c1 == *cur) 949 break; 950 cur++; 951 } 952 if (*cur == -1) 953 cur--; 954 merged = *cur; 955 done: 956 val |= merged << (i * 4); 957 } 958 959 return val; 960 } 961 962 static int piix_sidpr_scr_read(struct ata_port *ap, unsigned int reg, u32 *val) 963 { 964 const int * const sstatus_merge_tbl[] = { 965 /* DET */ (const int []){ 1, 3, 0, 4, 3, -1 }, 966 /* SPD */ (const int []){ 2, 1, 0, -1 }, 967 /* IPM */ (const int []){ 6, 2, 1, 0, -1 }, 968 NULL, 969 }; 970 const int * const scontrol_merge_tbl[] = { 971 /* DET */ (const int []){ 1, 0, 4, 0, -1 }, 972 /* SPD */ (const int []){ 0, 2, 1, 0, -1 }, 973 /* IPM */ (const int []){ 0, 1, 2, 3, 0, -1 }, 974 NULL, 975 }; 976 u32 v0, v1; 977 978 if (reg >= ARRAY_SIZE(piix_sidx_map)) 979 return -EINVAL; 980 981 if (!(ap->flags & ATA_FLAG_SLAVE_POSS)) { 982 *val = piix_sidpr_read(&ap->link.device[0], reg); 983 return 0; 984 } 985 986 v0 = piix_sidpr_read(&ap->link.device[0], reg); 987 v1 = piix_sidpr_read(&ap->link.device[1], reg); 988 989 switch (reg) { 990 case SCR_STATUS: 991 *val = piix_merge_scr(v0, v1, sstatus_merge_tbl); 992 break; 993 case SCR_ERROR: 994 *val = v0 | v1; 995 break; 996 case SCR_CONTROL: 997 *val = piix_merge_scr(v0, v1, scontrol_merge_tbl); 998 break; 999 } 1000 1001 return 0; 1002 } 1003 1004 static int piix_sidpr_scr_write(struct ata_port *ap, unsigned int reg, u32 val) 1005 { 1006 if (reg >= ARRAY_SIZE(piix_sidx_map)) 1007 return -EINVAL; 1008 1009 piix_sidpr_write(&ap->link.device[0], reg, val); 1010 1011 if (ap->flags & ATA_FLAG_SLAVE_POSS) 1012 piix_sidpr_write(&ap->link.device[1], reg, val); 1013 1014 return 0; 1015 } 1016 1017 #ifdef CONFIG_PM 1018 static int piix_broken_suspend(void) 1019 { 1020 static const struct dmi_system_id sysids[] = { 1021 { 1022 .ident = "TECRA M3", 1023 .matches = { 1024 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1025 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"), 1026 }, 1027 }, 1028 { 1029 .ident = "TECRA M3", 1030 .matches = { 1031 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1032 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"), 1033 }, 1034 }, 1035 { 1036 .ident = "TECRA M4", 1037 .matches = { 1038 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1039 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"), 1040 }, 1041 }, 1042 { 1043 .ident = "TECRA M5", 1044 .matches = { 1045 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1046 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"), 1047 }, 1048 }, 1049 { 1050 .ident = "TECRA M6", 1051 .matches = { 1052 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1053 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"), 1054 }, 1055 }, 1056 { 1057 .ident = "TECRA M7", 1058 .matches = { 1059 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1060 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"), 1061 }, 1062 }, 1063 { 1064 .ident = "TECRA A8", 1065 .matches = { 1066 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1067 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"), 1068 }, 1069 }, 1070 { 1071 .ident = "Satellite R20", 1072 .matches = { 1073 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1074 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"), 1075 }, 1076 }, 1077 { 1078 .ident = "Satellite R25", 1079 .matches = { 1080 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1081 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"), 1082 }, 1083 }, 1084 { 1085 .ident = "Satellite U200", 1086 .matches = { 1087 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1088 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"), 1089 }, 1090 }, 1091 { 1092 .ident = "Satellite U200", 1093 .matches = { 1094 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1095 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"), 1096 }, 1097 }, 1098 { 1099 .ident = "Satellite Pro U200", 1100 .matches = { 1101 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1102 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"), 1103 }, 1104 }, 1105 { 1106 .ident = "Satellite U205", 1107 .matches = { 1108 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1109 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"), 1110 }, 1111 }, 1112 { 1113 .ident = "SATELLITE U205", 1114 .matches = { 1115 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1116 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"), 1117 }, 1118 }, 1119 { 1120 .ident = "Portege M500", 1121 .matches = { 1122 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1123 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"), 1124 }, 1125 }, 1126 1127 { } /* terminate list */ 1128 }; 1129 static const char *oemstrs[] = { 1130 "Tecra M3,", 1131 }; 1132 int i; 1133 1134 if (dmi_check_system(sysids)) 1135 return 1; 1136 1137 for (i = 0; i < ARRAY_SIZE(oemstrs); i++) 1138 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL)) 1139 return 1; 1140 1141 return 0; 1142 } 1143 1144 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) 1145 { 1146 struct ata_host *host = dev_get_drvdata(&pdev->dev); 1147 unsigned long flags; 1148 int rc = 0; 1149 1150 rc = ata_host_suspend(host, mesg); 1151 if (rc) 1152 return rc; 1153 1154 /* Some braindamaged ACPI suspend implementations expect the 1155 * controller to be awake on entry; otherwise, it burns cpu 1156 * cycles and power trying to do something to the sleeping 1157 * beauty. 1158 */ 1159 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) { 1160 pci_save_state(pdev); 1161 1162 /* mark its power state as "unknown", since we don't 1163 * know if e.g. the BIOS will change its device state 1164 * when we suspend. 1165 */ 1166 if (pdev->current_state == PCI_D0) 1167 pdev->current_state = PCI_UNKNOWN; 1168 1169 /* tell resume that it's waking up from broken suspend */ 1170 spin_lock_irqsave(&host->lock, flags); 1171 host->flags |= PIIX_HOST_BROKEN_SUSPEND; 1172 spin_unlock_irqrestore(&host->lock, flags); 1173 } else 1174 ata_pci_device_do_suspend(pdev, mesg); 1175 1176 return 0; 1177 } 1178 1179 static int piix_pci_device_resume(struct pci_dev *pdev) 1180 { 1181 struct ata_host *host = dev_get_drvdata(&pdev->dev); 1182 unsigned long flags; 1183 int rc; 1184 1185 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) { 1186 spin_lock_irqsave(&host->lock, flags); 1187 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND; 1188 spin_unlock_irqrestore(&host->lock, flags); 1189 1190 pci_set_power_state(pdev, PCI_D0); 1191 pci_restore_state(pdev); 1192 1193 /* PCI device wasn't disabled during suspend. Use 1194 * pci_reenable_device() to avoid affecting the enable 1195 * count. 1196 */ 1197 rc = pci_reenable_device(pdev); 1198 if (rc) 1199 dev_printk(KERN_ERR, &pdev->dev, "failed to enable " 1200 "device after resume (%d)\n", rc); 1201 } else 1202 rc = ata_pci_device_do_resume(pdev); 1203 1204 if (rc == 0) 1205 ata_host_resume(host); 1206 1207 return rc; 1208 } 1209 #endif 1210 1211 static u8 piix_vmw_bmdma_status(struct ata_port *ap) 1212 { 1213 return ata_bmdma_status(ap) & ~ATA_DMA_ERR; 1214 } 1215 1216 #define AHCI_PCI_BAR 5 1217 #define AHCI_GLOBAL_CTL 0x04 1218 #define AHCI_ENABLE (1 << 31) 1219 static int piix_disable_ahci(struct pci_dev *pdev) 1220 { 1221 void __iomem *mmio; 1222 u32 tmp; 1223 int rc = 0; 1224 1225 /* BUG: pci_enable_device has not yet been called. This 1226 * works because this device is usually set up by BIOS. 1227 */ 1228 1229 if (!pci_resource_start(pdev, AHCI_PCI_BAR) || 1230 !pci_resource_len(pdev, AHCI_PCI_BAR)) 1231 return 0; 1232 1233 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64); 1234 if (!mmio) 1235 return -ENOMEM; 1236 1237 tmp = ioread32(mmio + AHCI_GLOBAL_CTL); 1238 if (tmp & AHCI_ENABLE) { 1239 tmp &= ~AHCI_ENABLE; 1240 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL); 1241 1242 tmp = ioread32(mmio + AHCI_GLOBAL_CTL); 1243 if (tmp & AHCI_ENABLE) 1244 rc = -EIO; 1245 } 1246 1247 pci_iounmap(pdev, mmio); 1248 return rc; 1249 } 1250 1251 /** 1252 * piix_check_450nx_errata - Check for problem 450NX setup 1253 * @ata_dev: the PCI device to check 1254 * 1255 * Check for the present of 450NX errata #19 and errata #25. If 1256 * they are found return an error code so we can turn off DMA 1257 */ 1258 1259 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev) 1260 { 1261 struct pci_dev *pdev = NULL; 1262 u16 cfg; 1263 int no_piix_dma = 0; 1264 1265 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) { 1266 /* Look for 450NX PXB. Check for problem configurations 1267 A PCI quirk checks bit 6 already */ 1268 pci_read_config_word(pdev, 0x41, &cfg); 1269 /* Only on the original revision: IDE DMA can hang */ 1270 if (pdev->revision == 0x00) 1271 no_piix_dma = 1; 1272 /* On all revisions below 5 PXB bus lock must be disabled for IDE */ 1273 else if (cfg & (1<<14) && pdev->revision < 5) 1274 no_piix_dma = 2; 1275 } 1276 if (no_piix_dma) 1277 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n"); 1278 if (no_piix_dma == 2) 1279 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n"); 1280 return no_piix_dma; 1281 } 1282 1283 static void __devinit piix_init_pcs(struct ata_host *host, 1284 const struct piix_map_db *map_db) 1285 { 1286 struct pci_dev *pdev = to_pci_dev(host->dev); 1287 u16 pcs, new_pcs; 1288 1289 pci_read_config_word(pdev, ICH5_PCS, &pcs); 1290 1291 new_pcs = pcs | map_db->port_enable; 1292 1293 if (new_pcs != pcs) { 1294 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs); 1295 pci_write_config_word(pdev, ICH5_PCS, new_pcs); 1296 msleep(150); 1297 } 1298 } 1299 1300 static const int *__devinit piix_init_sata_map(struct pci_dev *pdev, 1301 struct ata_port_info *pinfo, 1302 const struct piix_map_db *map_db) 1303 { 1304 const int *map; 1305 int i, invalid_map = 0; 1306 u8 map_value; 1307 1308 pci_read_config_byte(pdev, ICH5_PMR, &map_value); 1309 1310 map = map_db->map[map_value & map_db->mask]; 1311 1312 dev_printk(KERN_INFO, &pdev->dev, "MAP ["); 1313 for (i = 0; i < 4; i++) { 1314 switch (map[i]) { 1315 case RV: 1316 invalid_map = 1; 1317 printk(" XX"); 1318 break; 1319 1320 case NA: 1321 printk(" --"); 1322 break; 1323 1324 case IDE: 1325 WARN_ON((i & 1) || map[i + 1] != IDE); 1326 pinfo[i / 2] = piix_port_info[ich_pata_100]; 1327 i++; 1328 printk(" IDE IDE"); 1329 break; 1330 1331 default: 1332 printk(" P%d", map[i]); 1333 if (i & 1) 1334 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS; 1335 break; 1336 } 1337 } 1338 printk(" ]\n"); 1339 1340 if (invalid_map) 1341 dev_printk(KERN_ERR, &pdev->dev, 1342 "invalid MAP value %u\n", map_value); 1343 1344 return map; 1345 } 1346 1347 static void __devinit piix_init_sidpr(struct ata_host *host) 1348 { 1349 struct pci_dev *pdev = to_pci_dev(host->dev); 1350 struct piix_host_priv *hpriv = host->private_data; 1351 struct ata_device *dev0 = &host->ports[0]->link.device[0]; 1352 u32 scontrol; 1353 int i; 1354 1355 /* check for availability */ 1356 for (i = 0; i < 4; i++) 1357 if (hpriv->map[i] == IDE) 1358 return; 1359 1360 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR)) 1361 return; 1362 1363 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 || 1364 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN) 1365 return; 1366 1367 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME)) 1368 return; 1369 1370 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR]; 1371 1372 /* SCR access via SIDPR doesn't work on some configurations. 1373 * Give it a test drive by inhibiting power save modes which 1374 * we'll do anyway. 1375 */ 1376 scontrol = piix_sidpr_read(dev0, SCR_CONTROL); 1377 1378 /* if IPM is already 3, SCR access is probably working. Don't 1379 * un-inhibit power save modes as BIOS might have inhibited 1380 * them for a reason. 1381 */ 1382 if ((scontrol & 0xf00) != 0x300) { 1383 scontrol |= 0x300; 1384 piix_sidpr_write(dev0, SCR_CONTROL, scontrol); 1385 scontrol = piix_sidpr_read(dev0, SCR_CONTROL); 1386 1387 if ((scontrol & 0xf00) != 0x300) { 1388 dev_printk(KERN_INFO, host->dev, "SCR access via " 1389 "SIDPR is available but doesn't work\n"); 1390 return; 1391 } 1392 } 1393 1394 host->ports[0]->ops = &piix_sidpr_sata_ops; 1395 host->ports[1]->ops = &piix_sidpr_sata_ops; 1396 } 1397 1398 static void piix_iocfg_bit18_quirk(struct pci_dev *pdev) 1399 { 1400 static const struct dmi_system_id sysids[] = { 1401 { 1402 /* Clevo M570U sets IOCFG bit 18 if the cdrom 1403 * isn't used to boot the system which 1404 * disables the channel. 1405 */ 1406 .ident = "M570U", 1407 .matches = { 1408 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."), 1409 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"), 1410 }, 1411 }, 1412 1413 { } /* terminate list */ 1414 }; 1415 u32 iocfg; 1416 1417 if (!dmi_check_system(sysids)) 1418 return; 1419 1420 /* The datasheet says that bit 18 is NOOP but certain systems 1421 * seem to use it to disable a channel. Clear the bit on the 1422 * affected systems. 1423 */ 1424 pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg); 1425 if (iocfg & (1 << 18)) { 1426 dev_printk(KERN_INFO, &pdev->dev, 1427 "applying IOCFG bit18 quirk\n"); 1428 iocfg &= ~(1 << 18); 1429 pci_write_config_dword(pdev, PIIX_IOCFG, iocfg); 1430 } 1431 } 1432 1433 /** 1434 * piix_init_one - Register PIIX ATA PCI device with kernel services 1435 * @pdev: PCI device to register 1436 * @ent: Entry in piix_pci_tbl matching with @pdev 1437 * 1438 * Called from kernel PCI layer. We probe for combined mode (sigh), 1439 * and then hand over control to libata, for it to do the rest. 1440 * 1441 * LOCKING: 1442 * Inherited from PCI layer (may sleep). 1443 * 1444 * RETURNS: 1445 * Zero on success, or -ERRNO value. 1446 */ 1447 1448 static int __devinit piix_init_one(struct pci_dev *pdev, 1449 const struct pci_device_id *ent) 1450 { 1451 static int printed_version; 1452 struct device *dev = &pdev->dev; 1453 struct ata_port_info port_info[2]; 1454 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] }; 1455 unsigned long port_flags; 1456 struct ata_host *host; 1457 struct piix_host_priv *hpriv; 1458 int rc; 1459 1460 if (!printed_version++) 1461 dev_printk(KERN_DEBUG, &pdev->dev, 1462 "version " DRV_VERSION "\n"); 1463 1464 /* no hotplugging support (FIXME) */ 1465 if (!in_module_init) 1466 return -ENODEV; 1467 1468 port_info[0] = piix_port_info[ent->driver_data]; 1469 port_info[1] = piix_port_info[ent->driver_data]; 1470 1471 port_flags = port_info[0].flags; 1472 1473 /* enable device and prepare host */ 1474 rc = pcim_enable_device(pdev); 1475 if (rc) 1476 return rc; 1477 1478 /* ICH6R may be driven by either ata_piix or ahci driver 1479 * regardless of BIOS configuration. Make sure AHCI mode is 1480 * off. 1481 */ 1482 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) { 1483 int rc = piix_disable_ahci(pdev); 1484 if (rc) 1485 return rc; 1486 } 1487 1488 /* SATA map init can change port_info, do it before prepping host */ 1489 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1490 if (!hpriv) 1491 return -ENOMEM; 1492 1493 if (port_flags & ATA_FLAG_SATA) 1494 hpriv->map = piix_init_sata_map(pdev, port_info, 1495 piix_map_db_table[ent->driver_data]); 1496 1497 rc = ata_pci_sff_prepare_host(pdev, ppi, &host); 1498 if (rc) 1499 return rc; 1500 host->private_data = hpriv; 1501 1502 /* initialize controller */ 1503 if (port_flags & ATA_FLAG_SATA) { 1504 piix_init_pcs(host, piix_map_db_table[ent->driver_data]); 1505 piix_init_sidpr(host); 1506 } 1507 1508 /* apply IOCFG bit18 quirk */ 1509 piix_iocfg_bit18_quirk(pdev); 1510 1511 /* On ICH5, some BIOSen disable the interrupt using the 1512 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. 1513 * On ICH6, this bit has the same effect, but only when 1514 * MSI is disabled (and it is disabled, as we don't use 1515 * message-signalled interrupts currently). 1516 */ 1517 if (port_flags & PIIX_FLAG_CHECKINTR) 1518 pci_intx(pdev, 1); 1519 1520 if (piix_check_450nx_errata(pdev)) { 1521 /* This writes into the master table but it does not 1522 really matter for this errata as we will apply it to 1523 all the PIIX devices on the board */ 1524 host->ports[0]->mwdma_mask = 0; 1525 host->ports[0]->udma_mask = 0; 1526 host->ports[1]->mwdma_mask = 0; 1527 host->ports[1]->udma_mask = 0; 1528 } 1529 1530 pci_set_master(pdev); 1531 return ata_pci_sff_activate_host(host, ata_sff_interrupt, &piix_sht); 1532 } 1533 1534 static int __init piix_init(void) 1535 { 1536 int rc; 1537 1538 DPRINTK("pci_register_driver\n"); 1539 rc = pci_register_driver(&piix_pci_driver); 1540 if (rc) 1541 return rc; 1542 1543 in_module_init = 0; 1544 1545 DPRINTK("done\n"); 1546 return 0; 1547 } 1548 1549 static void __exit piix_exit(void) 1550 { 1551 pci_unregister_driver(&piix_pci_driver); 1552 } 1553 1554 module_init(piix_init); 1555 module_exit(piix_exit); 1556