xref: /openbmc/linux/drivers/ata/ahci_qoriq.c (revision 98ddec80)
1 /*
2  * Freescale QorIQ AHCI SATA platform driver
3  *
4  * Copyright 2015 Freescale, Inc.
5  *   Tang Yuantian <Yuantian.Tang@freescale.com>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2, or (at your option)
10  * any later version.
11  */
12 
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/pm.h>
16 #include <linux/ahci_platform.h>
17 #include <linux/device.h>
18 #include <linux/of_address.h>
19 #include <linux/of.h>
20 #include <linux/of_device.h>
21 #include <linux/platform_device.h>
22 #include <linux/libata.h>
23 #include "ahci.h"
24 
25 #define DRV_NAME "ahci-qoriq"
26 
27 /* port register definition */
28 #define PORT_PHY1	0xA8
29 #define PORT_PHY2	0xAC
30 #define PORT_PHY3	0xB0
31 #define PORT_PHY4	0xB4
32 #define PORT_PHY5	0xB8
33 #define PORT_AXICC	0xBC
34 #define PORT_TRANS	0xC8
35 
36 /* port register default value */
37 #define AHCI_PORT_PHY_1_CFG	0xa003fffe
38 #define AHCI_PORT_PHY2_CFG	0x28184d1f
39 #define AHCI_PORT_PHY3_CFG	0x0e081509
40 #define AHCI_PORT_TRANS_CFG	0x08000029
41 #define AHCI_PORT_AXICC_CFG	0x3fffffff
42 
43 /* for ls1021a */
44 #define LS1021A_PORT_PHY2	0x28183414
45 #define LS1021A_PORT_PHY3	0x0e080e06
46 #define LS1021A_PORT_PHY4	0x064a080b
47 #define LS1021A_PORT_PHY5	0x2aa86470
48 #define LS1021A_AXICC_ADDR	0xC0
49 
50 #define SATA_ECC_DISABLE	0x00020000
51 #define ECC_DIS_ARMV8_CH2	0x80000000
52 #define ECC_DIS_LS1088A		0x40000000
53 
54 enum ahci_qoriq_type {
55 	AHCI_LS1021A,
56 	AHCI_LS1043A,
57 	AHCI_LS2080A,
58 	AHCI_LS1046A,
59 	AHCI_LS1088A,
60 	AHCI_LS2088A,
61 };
62 
63 struct ahci_qoriq_priv {
64 	struct ccsr_ahci *reg_base;
65 	enum ahci_qoriq_type type;
66 	void __iomem *ecc_addr;
67 	bool is_dmacoherent;
68 };
69 
70 static const struct of_device_id ahci_qoriq_of_match[] = {
71 	{ .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
72 	{ .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
73 	{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
74 	{ .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
75 	{ .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
76 	{ .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
77 	{},
78 };
79 MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
80 
81 static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class,
82 			  unsigned long deadline)
83 {
84 	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
85 	void __iomem *port_mmio = ahci_port_base(link->ap);
86 	u32 px_cmd, px_is, px_val;
87 	struct ata_port *ap = link->ap;
88 	struct ahci_port_priv *pp = ap->private_data;
89 	struct ahci_host_priv *hpriv = ap->host->private_data;
90 	struct ahci_qoriq_priv *qoriq_priv = hpriv->plat_data;
91 	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
92 	struct ata_taskfile tf;
93 	bool online;
94 	int rc;
95 	bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A);
96 
97 	DPRINTK("ENTER\n");
98 
99 	hpriv->stop_engine(ap);
100 
101 	/*
102 	 * There is a errata on ls1021a Rev1.0 and Rev2.0 which is:
103 	 * A-009042: The device detection initialization sequence
104 	 * mistakenly resets some registers.
105 	 *
106 	 * Workaround for this is:
107 	 * The software should read and store PxCMD and PxIS values
108 	 * before issuing the device detection initialization sequence.
109 	 * After the sequence is complete, software should restore the
110 	 * PxCMD and PxIS with the stored values.
111 	 */
112 	if (ls1021a_workaround) {
113 		px_cmd = readl(port_mmio + PORT_CMD);
114 		px_is = readl(port_mmio + PORT_IRQ_STAT);
115 	}
116 
117 	/* clear D2H reception area to properly wait for D2H FIS */
118 	ata_tf_init(link->device, &tf);
119 	tf.command = ATA_BUSY;
120 	ata_tf_to_fis(&tf, 0, 0, d2h_fis);
121 
122 	rc = sata_link_hardreset(link, timing, deadline, &online,
123 				 ahci_check_ready);
124 
125 	/* restore the PxCMD and PxIS on ls1021 */
126 	if (ls1021a_workaround) {
127 		px_val = readl(port_mmio + PORT_CMD);
128 		if (px_val != px_cmd)
129 			writel(px_cmd, port_mmio + PORT_CMD);
130 
131 		px_val = readl(port_mmio + PORT_IRQ_STAT);
132 		if (px_val != px_is)
133 			writel(px_is, port_mmio + PORT_IRQ_STAT);
134 	}
135 
136 	hpriv->start_engine(ap);
137 
138 	if (online)
139 		*class = ahci_dev_classify(ap);
140 
141 	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
142 	return rc;
143 }
144 
145 static struct ata_port_operations ahci_qoriq_ops = {
146 	.inherits	= &ahci_ops,
147 	.hardreset	= ahci_qoriq_hardreset,
148 };
149 
150 static const struct ata_port_info ahci_qoriq_port_info = {
151 	.flags		= AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
152 	.pio_mask	= ATA_PIO4,
153 	.udma_mask	= ATA_UDMA6,
154 	.port_ops	= &ahci_qoriq_ops,
155 };
156 
157 static struct scsi_host_template ahci_qoriq_sht = {
158 	AHCI_SHT(DRV_NAME),
159 };
160 
161 static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
162 {
163 	struct ahci_qoriq_priv *qpriv = hpriv->plat_data;
164 	void __iomem *reg_base = hpriv->mmio;
165 
166 	switch (qpriv->type) {
167 	case AHCI_LS1021A:
168 		if (!qpriv->ecc_addr)
169 			return -EINVAL;
170 		writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
171 		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
172 		writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
173 		writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3);
174 		writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
175 		writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
176 		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
177 		if (qpriv->is_dmacoherent)
178 			writel(AHCI_PORT_AXICC_CFG,
179 					reg_base + LS1021A_AXICC_ADDR);
180 		break;
181 
182 	case AHCI_LS1043A:
183 		if (!qpriv->ecc_addr)
184 			return -EINVAL;
185 		writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
186 				qpriv->ecc_addr);
187 		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
188 		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
189 		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
190 		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
191 		if (qpriv->is_dmacoherent)
192 			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
193 		break;
194 
195 	case AHCI_LS2080A:
196 		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
197 		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
198 		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
199 		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
200 		if (qpriv->is_dmacoherent)
201 			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
202 		break;
203 
204 	case AHCI_LS1046A:
205 		if (!qpriv->ecc_addr)
206 			return -EINVAL;
207 		writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
208 				qpriv->ecc_addr);
209 		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
210 		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
211 		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
212 		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
213 		if (qpriv->is_dmacoherent)
214 			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
215 		break;
216 
217 	case AHCI_LS1088A:
218 		if (!qpriv->ecc_addr)
219 			return -EINVAL;
220 		writel(readl(qpriv->ecc_addr) | ECC_DIS_LS1088A,
221 		       qpriv->ecc_addr);
222 		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
223 		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
224 		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
225 		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
226 		if (qpriv->is_dmacoherent)
227 			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
228 		break;
229 
230 	case AHCI_LS2088A:
231 		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
232 		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
233 		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
234 		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
235 		if (qpriv->is_dmacoherent)
236 			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
237 		break;
238 	}
239 
240 	return 0;
241 }
242 
243 static int ahci_qoriq_probe(struct platform_device *pdev)
244 {
245 	struct device_node *np = pdev->dev.of_node;
246 	struct device *dev = &pdev->dev;
247 	struct ahci_host_priv *hpriv;
248 	struct ahci_qoriq_priv *qoriq_priv;
249 	const struct of_device_id *of_id;
250 	struct resource *res;
251 	int rc;
252 
253 	hpriv = ahci_platform_get_resources(pdev);
254 	if (IS_ERR(hpriv))
255 		return PTR_ERR(hpriv);
256 
257 	of_id = of_match_node(ahci_qoriq_of_match, np);
258 	if (!of_id)
259 		return -ENODEV;
260 
261 	qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL);
262 	if (!qoriq_priv)
263 		return -ENOMEM;
264 
265 	qoriq_priv->type = (enum ahci_qoriq_type)of_id->data;
266 
267 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
268 			"sata-ecc");
269 	if (res) {
270 		qoriq_priv->ecc_addr = devm_ioremap_resource(dev, res);
271 		if (IS_ERR(qoriq_priv->ecc_addr))
272 			return PTR_ERR(qoriq_priv->ecc_addr);
273 	}
274 	qoriq_priv->is_dmacoherent = of_dma_is_coherent(np);
275 
276 	rc = ahci_platform_enable_resources(hpriv);
277 	if (rc)
278 		return rc;
279 
280 	hpriv->plat_data = qoriq_priv;
281 	rc = ahci_qoriq_phy_init(hpriv);
282 	if (rc)
283 		goto disable_resources;
284 
285 	rc = ahci_platform_init_host(pdev, hpriv, &ahci_qoriq_port_info,
286 				     &ahci_qoriq_sht);
287 	if (rc)
288 		goto disable_resources;
289 
290 	return 0;
291 
292 disable_resources:
293 	ahci_platform_disable_resources(hpriv);
294 
295 	return rc;
296 }
297 
298 #ifdef CONFIG_PM_SLEEP
299 static int ahci_qoriq_resume(struct device *dev)
300 {
301 	struct ata_host *host = dev_get_drvdata(dev);
302 	struct ahci_host_priv *hpriv = host->private_data;
303 	int rc;
304 
305 	rc = ahci_platform_enable_resources(hpriv);
306 	if (rc)
307 		return rc;
308 
309 	rc = ahci_qoriq_phy_init(hpriv);
310 	if (rc)
311 		goto disable_resources;
312 
313 	rc = ahci_platform_resume_host(dev);
314 	if (rc)
315 		goto disable_resources;
316 
317 	/* We resumed so update PM runtime state */
318 	pm_runtime_disable(dev);
319 	pm_runtime_set_active(dev);
320 	pm_runtime_enable(dev);
321 
322 	return 0;
323 
324 disable_resources:
325 	ahci_platform_disable_resources(hpriv);
326 
327 	return rc;
328 }
329 #endif
330 
331 static SIMPLE_DEV_PM_OPS(ahci_qoriq_pm_ops, ahci_platform_suspend,
332 			 ahci_qoriq_resume);
333 
334 static struct platform_driver ahci_qoriq_driver = {
335 	.probe = ahci_qoriq_probe,
336 	.remove = ata_platform_remove_one,
337 	.driver = {
338 		.name = DRV_NAME,
339 		.of_match_table = ahci_qoriq_of_match,
340 		.pm = &ahci_qoriq_pm_ops,
341 	},
342 };
343 module_platform_driver(ahci_qoriq_driver);
344 
345 MODULE_DESCRIPTION("Freescale QorIQ AHCI SATA platform driver");
346 MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
347 MODULE_LICENSE("GPL");
348