1 /* 2 * copyright (c) 2013 Freescale Semiconductor, Inc. 3 * Freescale IMX AHCI SATA platform driver 4 * 5 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/platform_device.h> 23 #include <linux/regmap.h> 24 #include <linux/ahci_platform.h> 25 #include <linux/of_device.h> 26 #include <linux/mfd/syscon.h> 27 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 28 #include <linux/libata.h> 29 #include <linux/hwmon.h> 30 #include <linux/hwmon-sysfs.h> 31 #include <linux/thermal.h> 32 #include "ahci.h" 33 34 #define DRV_NAME "ahci-imx" 35 36 enum { 37 /* Timer 1-ms Register */ 38 IMX_TIMER1MS = 0x00e0, 39 /* Port0 PHY Control Register */ 40 IMX_P0PHYCR = 0x0178, 41 IMX_P0PHYCR_TEST_PDDQ = 1 << 20, 42 IMX_P0PHYCR_CR_READ = 1 << 19, 43 IMX_P0PHYCR_CR_WRITE = 1 << 18, 44 IMX_P0PHYCR_CR_CAP_DATA = 1 << 17, 45 IMX_P0PHYCR_CR_CAP_ADDR = 1 << 16, 46 /* Port0 PHY Status Register */ 47 IMX_P0PHYSR = 0x017c, 48 IMX_P0PHYSR_CR_ACK = 1 << 18, 49 IMX_P0PHYSR_CR_DATA_OUT = 0xffff << 0, 50 /* Lane0 Output Status Register */ 51 IMX_LANE0_OUT_STAT = 0x2003, 52 IMX_LANE0_OUT_STAT_RX_PLL_STATE = 1 << 1, 53 /* Clock Reset Register */ 54 IMX_CLOCK_RESET = 0x7f3f, 55 IMX_CLOCK_RESET_RESET = 1 << 0, 56 }; 57 58 enum ahci_imx_type { 59 AHCI_IMX53, 60 AHCI_IMX6Q, 61 }; 62 63 struct imx_ahci_priv { 64 struct platform_device *ahci_pdev; 65 enum ahci_imx_type type; 66 struct clk *sata_clk; 67 struct clk *sata_ref_clk; 68 struct clk *ahb_clk; 69 struct regmap *gpr; 70 bool no_device; 71 bool first_time; 72 u32 phy_params; 73 }; 74 75 static int ahci_imx_hotplug; 76 module_param_named(hotplug, ahci_imx_hotplug, int, 0644); 77 MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)"); 78 79 static void ahci_imx_host_stop(struct ata_host *host); 80 81 static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert) 82 { 83 int timeout = 10; 84 u32 crval; 85 u32 srval; 86 87 /* Assert or deassert the bit */ 88 crval = readl(mmio + IMX_P0PHYCR); 89 if (assert) 90 crval |= bit; 91 else 92 crval &= ~bit; 93 writel(crval, mmio + IMX_P0PHYCR); 94 95 /* Wait for the cr_ack signal */ 96 do { 97 srval = readl(mmio + IMX_P0PHYSR); 98 if ((assert ? srval : ~srval) & IMX_P0PHYSR_CR_ACK) 99 break; 100 usleep_range(100, 200); 101 } while (--timeout); 102 103 return timeout ? 0 : -ETIMEDOUT; 104 } 105 106 static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio) 107 { 108 u32 crval = addr; 109 int ret; 110 111 /* Supply the address on cr_data_in */ 112 writel(crval, mmio + IMX_P0PHYCR); 113 114 /* Assert the cr_cap_addr signal */ 115 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true); 116 if (ret) 117 return ret; 118 119 /* Deassert cr_cap_addr */ 120 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false); 121 if (ret) 122 return ret; 123 124 return 0; 125 } 126 127 static int imx_phy_reg_write(u16 val, void __iomem *mmio) 128 { 129 u32 crval = val; 130 int ret; 131 132 /* Supply the data on cr_data_in */ 133 writel(crval, mmio + IMX_P0PHYCR); 134 135 /* Assert the cr_cap_data signal */ 136 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, true); 137 if (ret) 138 return ret; 139 140 /* Deassert cr_cap_data */ 141 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, false); 142 if (ret) 143 return ret; 144 145 if (val & IMX_CLOCK_RESET_RESET) { 146 /* 147 * In case we're resetting the phy, it's unable to acknowledge, 148 * so we return immediately here. 149 */ 150 crval |= IMX_P0PHYCR_CR_WRITE; 151 writel(crval, mmio + IMX_P0PHYCR); 152 goto out; 153 } 154 155 /* Assert the cr_write signal */ 156 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, true); 157 if (ret) 158 return ret; 159 160 /* Deassert cr_write */ 161 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, false); 162 if (ret) 163 return ret; 164 165 out: 166 return 0; 167 } 168 169 static int imx_phy_reg_read(u16 *val, void __iomem *mmio) 170 { 171 int ret; 172 173 /* Assert the cr_read signal */ 174 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, true); 175 if (ret) 176 return ret; 177 178 /* Capture the data from cr_data_out[] */ 179 *val = readl(mmio + IMX_P0PHYSR) & IMX_P0PHYSR_CR_DATA_OUT; 180 181 /* Deassert cr_read */ 182 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, false); 183 if (ret) 184 return ret; 185 186 return 0; 187 } 188 189 static int imx_sata_phy_reset(struct ahci_host_priv *hpriv) 190 { 191 void __iomem *mmio = hpriv->mmio; 192 int timeout = 10; 193 u16 val; 194 int ret; 195 196 /* Reset SATA PHY by setting RESET bit of PHY register CLOCK_RESET */ 197 ret = imx_phy_reg_addressing(IMX_CLOCK_RESET, mmio); 198 if (ret) 199 return ret; 200 ret = imx_phy_reg_write(IMX_CLOCK_RESET_RESET, mmio); 201 if (ret) 202 return ret; 203 204 /* Wait for PHY RX_PLL to be stable */ 205 do { 206 usleep_range(100, 200); 207 ret = imx_phy_reg_addressing(IMX_LANE0_OUT_STAT, mmio); 208 if (ret) 209 return ret; 210 ret = imx_phy_reg_read(&val, mmio); 211 if (ret) 212 return ret; 213 if (val & IMX_LANE0_OUT_STAT_RX_PLL_STATE) 214 break; 215 } while (--timeout); 216 217 return timeout ? 0 : -ETIMEDOUT; 218 } 219 220 enum { 221 /* SATA PHY Register */ 222 SATA_PHY_CR_CLOCK_CRCMP_LT_LIMIT = 0x0001, 223 SATA_PHY_CR_CLOCK_DAC_CTL = 0x0008, 224 SATA_PHY_CR_CLOCK_RTUNE_CTL = 0x0009, 225 SATA_PHY_CR_CLOCK_ADC_OUT = 0x000A, 226 SATA_PHY_CR_CLOCK_MPLL_TST = 0x0017, 227 }; 228 229 static int read_adc_sum(void *dev, u16 rtune_ctl_reg, void __iomem * mmio) 230 { 231 u16 adc_out_reg, read_sum; 232 u32 index, read_attempt; 233 const u32 attempt_limit = 100; 234 235 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio); 236 imx_phy_reg_write(rtune_ctl_reg, mmio); 237 238 /* two dummy read */ 239 index = 0; 240 read_attempt = 0; 241 adc_out_reg = 0; 242 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_ADC_OUT, mmio); 243 while (index < 2) { 244 imx_phy_reg_read(&adc_out_reg, mmio); 245 /* check if valid */ 246 if (adc_out_reg & 0x400) 247 index++; 248 249 read_attempt++; 250 if (read_attempt > attempt_limit) { 251 dev_err(dev, "Read REG more than %d times!\n", 252 attempt_limit); 253 break; 254 } 255 } 256 257 index = 0; 258 read_attempt = 0; 259 read_sum = 0; 260 while (index < 80) { 261 imx_phy_reg_read(&adc_out_reg, mmio); 262 if (adc_out_reg & 0x400) { 263 read_sum = read_sum + (adc_out_reg & 0x3FF); 264 index++; 265 } 266 read_attempt++; 267 if (read_attempt > attempt_limit) { 268 dev_err(dev, "Read REG more than %d times!\n", 269 attempt_limit); 270 break; 271 } 272 } 273 274 /* Use the U32 to make 1000 precision */ 275 return (read_sum * 1000) / 80; 276 } 277 278 /* SATA AHCI temperature monitor */ 279 static int sata_ahci_read_temperature(void *dev, int *temp) 280 { 281 u16 mpll_test_reg, rtune_ctl_reg, dac_ctl_reg, read_sum; 282 u32 str1, str2, str3, str4; 283 int m1, m2, a; 284 struct ahci_host_priv *hpriv = dev_get_drvdata(dev); 285 void __iomem *mmio = hpriv->mmio; 286 287 /* check rd-wr to reg */ 288 read_sum = 0; 289 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_CRCMP_LT_LIMIT, mmio); 290 imx_phy_reg_write(read_sum, mmio); 291 imx_phy_reg_read(&read_sum, mmio); 292 if ((read_sum & 0xffff) != 0) 293 dev_err(dev, "Read/Write REG error, 0x%x!\n", read_sum); 294 295 imx_phy_reg_write(0x5A5A, mmio); 296 imx_phy_reg_read(&read_sum, mmio); 297 if ((read_sum & 0xffff) != 0x5A5A) 298 dev_err(dev, "Read/Write REG error, 0x%x!\n", read_sum); 299 300 imx_phy_reg_write(0x1234, mmio); 301 imx_phy_reg_read(&read_sum, mmio); 302 if ((read_sum & 0xffff) != 0x1234) 303 dev_err(dev, "Read/Write REG error, 0x%x!\n", read_sum); 304 305 /* start temperature test */ 306 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio); 307 imx_phy_reg_read(&mpll_test_reg, mmio); 308 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio); 309 imx_phy_reg_read(&rtune_ctl_reg, mmio); 310 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio); 311 imx_phy_reg_read(&dac_ctl_reg, mmio); 312 313 /* mpll_tst.meas_iv ([12:2]) */ 314 str1 = (mpll_test_reg >> 2) & 0x7FF; 315 /* rtune_ctl.mode ([1:0]) */ 316 str2 = (rtune_ctl_reg) & 0x3; 317 /* dac_ctl.dac_mode ([14:12]) */ 318 str3 = (dac_ctl_reg >> 12) & 0x7; 319 /* rtune_ctl.sel_atbp ([4]) */ 320 str4 = (rtune_ctl_reg >> 4); 321 322 /* Calculate the m1 */ 323 /* mpll_tst.meas_iv */ 324 mpll_test_reg = (mpll_test_reg & 0xE03) | (512) << 2; 325 /* rtune_ctl.mode */ 326 rtune_ctl_reg = (rtune_ctl_reg & 0xFFC) | (1); 327 /* dac_ctl.dac_mode */ 328 dac_ctl_reg = (dac_ctl_reg & 0x8FF) | (4) << 12; 329 /* rtune_ctl.sel_atbp */ 330 rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (0) << 4; 331 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio); 332 imx_phy_reg_write(mpll_test_reg, mmio); 333 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio); 334 imx_phy_reg_write(dac_ctl_reg, mmio); 335 m1 = read_adc_sum(dev, rtune_ctl_reg, mmio); 336 337 /* Calculate the m2 */ 338 /* rtune_ctl.sel_atbp */ 339 rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (1) << 4; 340 m2 = read_adc_sum(dev, rtune_ctl_reg, mmio); 341 342 /* restore the status */ 343 /* mpll_tst.meas_iv */ 344 mpll_test_reg = (mpll_test_reg & 0xE03) | (str1) << 2; 345 /* rtune_ctl.mode */ 346 rtune_ctl_reg = (rtune_ctl_reg & 0xFFC) | (str2); 347 /* dac_ctl.dac_mode */ 348 dac_ctl_reg = (dac_ctl_reg & 0x8FF) | (str3) << 12; 349 /* rtune_ctl.sel_atbp */ 350 rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (str4) << 4; 351 352 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio); 353 imx_phy_reg_write(mpll_test_reg, mmio); 354 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio); 355 imx_phy_reg_write(dac_ctl_reg, mmio); 356 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio); 357 imx_phy_reg_write(rtune_ctl_reg, mmio); 358 359 /* Compute temperature */ 360 if (!(m2 / 1000)) 361 m2 = 1000; 362 a = (m2 - m1) / (m2/1000); 363 *temp = ((-559) * a * a) / 1000 + (1379) * a + (-458000); 364 365 return 0; 366 } 367 368 static ssize_t sata_ahci_show_temp(struct device *dev, 369 struct device_attribute *da, 370 char *buf) 371 { 372 unsigned int temp = 0; 373 int err; 374 375 err = sata_ahci_read_temperature(dev, &temp); 376 if (err < 0) 377 return err; 378 379 return sprintf(buf, "%u\n", temp); 380 } 381 382 static const struct thermal_zone_of_device_ops fsl_sata_ahci_of_thermal_ops = { 383 .get_temp = sata_ahci_read_temperature, 384 }; 385 386 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, sata_ahci_show_temp, NULL, 0); 387 388 static struct attribute *fsl_sata_ahci_attrs[] = { 389 &sensor_dev_attr_temp1_input.dev_attr.attr, 390 NULL 391 }; 392 ATTRIBUTE_GROUPS(fsl_sata_ahci); 393 394 static int imx_sata_enable(struct ahci_host_priv *hpriv) 395 { 396 struct imx_ahci_priv *imxpriv = hpriv->plat_data; 397 struct device *dev = &imxpriv->ahci_pdev->dev; 398 int ret; 399 400 if (imxpriv->no_device) 401 return 0; 402 403 ret = ahci_platform_enable_regulators(hpriv); 404 if (ret) 405 return ret; 406 407 ret = clk_prepare_enable(imxpriv->sata_ref_clk); 408 if (ret < 0) 409 goto disable_regulator; 410 411 if (imxpriv->type == AHCI_IMX6Q) { 412 /* 413 * set PHY Paremeters, two steps to configure the GPR13, 414 * one write for rest of parameters, mask of first write 415 * is 0x07ffffff, and the other one write for setting 416 * the mpll_clk_en. 417 */ 418 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13, 419 IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK | 420 IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK | 421 IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK | 422 IMX6Q_GPR13_SATA_SPD_MODE_MASK | 423 IMX6Q_GPR13_SATA_MPLL_SS_EN | 424 IMX6Q_GPR13_SATA_TX_ATTEN_MASK | 425 IMX6Q_GPR13_SATA_TX_BOOST_MASK | 426 IMX6Q_GPR13_SATA_TX_LVL_MASK | 427 IMX6Q_GPR13_SATA_MPLL_CLK_EN | 428 IMX6Q_GPR13_SATA_TX_EDGE_RATE, 429 imxpriv->phy_params); 430 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13, 431 IMX6Q_GPR13_SATA_MPLL_CLK_EN, 432 IMX6Q_GPR13_SATA_MPLL_CLK_EN); 433 434 usleep_range(100, 200); 435 436 ret = imx_sata_phy_reset(hpriv); 437 if (ret) { 438 dev_err(dev, "failed to reset phy: %d\n", ret); 439 goto disable_clk; 440 } 441 } 442 443 usleep_range(1000, 2000); 444 445 return 0; 446 447 disable_clk: 448 clk_disable_unprepare(imxpriv->sata_ref_clk); 449 disable_regulator: 450 ahci_platform_disable_regulators(hpriv); 451 452 return ret; 453 } 454 455 static void imx_sata_disable(struct ahci_host_priv *hpriv) 456 { 457 struct imx_ahci_priv *imxpriv = hpriv->plat_data; 458 459 if (imxpriv->no_device) 460 return; 461 462 if (imxpriv->type == AHCI_IMX6Q) { 463 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13, 464 IMX6Q_GPR13_SATA_MPLL_CLK_EN, 465 !IMX6Q_GPR13_SATA_MPLL_CLK_EN); 466 } 467 468 clk_disable_unprepare(imxpriv->sata_ref_clk); 469 470 ahci_platform_disable_regulators(hpriv); 471 } 472 473 static void ahci_imx_error_handler(struct ata_port *ap) 474 { 475 u32 reg_val; 476 struct ata_device *dev; 477 struct ata_host *host = dev_get_drvdata(ap->dev); 478 struct ahci_host_priv *hpriv = host->private_data; 479 void __iomem *mmio = hpriv->mmio; 480 struct imx_ahci_priv *imxpriv = hpriv->plat_data; 481 482 ahci_error_handler(ap); 483 484 if (!(imxpriv->first_time) || ahci_imx_hotplug) 485 return; 486 487 imxpriv->first_time = false; 488 489 ata_for_each_dev(dev, &ap->link, ENABLED) 490 return; 491 /* 492 * Disable link to save power. An imx ahci port can't be recovered 493 * without full reset once the pddq mode is enabled making it 494 * impossible to use as part of libata LPM. 495 */ 496 reg_val = readl(mmio + IMX_P0PHYCR); 497 writel(reg_val | IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR); 498 imx_sata_disable(hpriv); 499 imxpriv->no_device = true; 500 501 dev_info(ap->dev, "no device found, disabling link.\n"); 502 dev_info(ap->dev, "pass " MODULE_PARAM_PREFIX ".hotplug=1 to enable hotplug\n"); 503 } 504 505 static int ahci_imx_softreset(struct ata_link *link, unsigned int *class, 506 unsigned long deadline) 507 { 508 struct ata_port *ap = link->ap; 509 struct ata_host *host = dev_get_drvdata(ap->dev); 510 struct ahci_host_priv *hpriv = host->private_data; 511 struct imx_ahci_priv *imxpriv = hpriv->plat_data; 512 int ret = -EIO; 513 514 if (imxpriv->type == AHCI_IMX53) 515 ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline); 516 else if (imxpriv->type == AHCI_IMX6Q) 517 ret = ahci_ops.softreset(link, class, deadline); 518 519 return ret; 520 } 521 522 static struct ata_port_operations ahci_imx_ops = { 523 .inherits = &ahci_ops, 524 .host_stop = ahci_imx_host_stop, 525 .error_handler = ahci_imx_error_handler, 526 .softreset = ahci_imx_softreset, 527 }; 528 529 static const struct ata_port_info ahci_imx_port_info = { 530 .flags = AHCI_FLAG_COMMON, 531 .pio_mask = ATA_PIO4, 532 .udma_mask = ATA_UDMA6, 533 .port_ops = &ahci_imx_ops, 534 }; 535 536 static const struct of_device_id imx_ahci_of_match[] = { 537 { .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 }, 538 { .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q }, 539 {}, 540 }; 541 MODULE_DEVICE_TABLE(of, imx_ahci_of_match); 542 543 struct reg_value { 544 u32 of_value; 545 u32 reg_value; 546 }; 547 548 struct reg_property { 549 const char *name; 550 const struct reg_value *values; 551 size_t num_values; 552 u32 def_value; 553 u32 set_value; 554 }; 555 556 static const struct reg_value gpr13_tx_level[] = { 557 { 937, IMX6Q_GPR13_SATA_TX_LVL_0_937_V }, 558 { 947, IMX6Q_GPR13_SATA_TX_LVL_0_947_V }, 559 { 957, IMX6Q_GPR13_SATA_TX_LVL_0_957_V }, 560 { 966, IMX6Q_GPR13_SATA_TX_LVL_0_966_V }, 561 { 976, IMX6Q_GPR13_SATA_TX_LVL_0_976_V }, 562 { 986, IMX6Q_GPR13_SATA_TX_LVL_0_986_V }, 563 { 996, IMX6Q_GPR13_SATA_TX_LVL_0_996_V }, 564 { 1005, IMX6Q_GPR13_SATA_TX_LVL_1_005_V }, 565 { 1015, IMX6Q_GPR13_SATA_TX_LVL_1_015_V }, 566 { 1025, IMX6Q_GPR13_SATA_TX_LVL_1_025_V }, 567 { 1035, IMX6Q_GPR13_SATA_TX_LVL_1_035_V }, 568 { 1045, IMX6Q_GPR13_SATA_TX_LVL_1_045_V }, 569 { 1054, IMX6Q_GPR13_SATA_TX_LVL_1_054_V }, 570 { 1064, IMX6Q_GPR13_SATA_TX_LVL_1_064_V }, 571 { 1074, IMX6Q_GPR13_SATA_TX_LVL_1_074_V }, 572 { 1084, IMX6Q_GPR13_SATA_TX_LVL_1_084_V }, 573 { 1094, IMX6Q_GPR13_SATA_TX_LVL_1_094_V }, 574 { 1104, IMX6Q_GPR13_SATA_TX_LVL_1_104_V }, 575 { 1113, IMX6Q_GPR13_SATA_TX_LVL_1_113_V }, 576 { 1123, IMX6Q_GPR13_SATA_TX_LVL_1_123_V }, 577 { 1133, IMX6Q_GPR13_SATA_TX_LVL_1_133_V }, 578 { 1143, IMX6Q_GPR13_SATA_TX_LVL_1_143_V }, 579 { 1152, IMX6Q_GPR13_SATA_TX_LVL_1_152_V }, 580 { 1162, IMX6Q_GPR13_SATA_TX_LVL_1_162_V }, 581 { 1172, IMX6Q_GPR13_SATA_TX_LVL_1_172_V }, 582 { 1182, IMX6Q_GPR13_SATA_TX_LVL_1_182_V }, 583 { 1191, IMX6Q_GPR13_SATA_TX_LVL_1_191_V }, 584 { 1201, IMX6Q_GPR13_SATA_TX_LVL_1_201_V }, 585 { 1211, IMX6Q_GPR13_SATA_TX_LVL_1_211_V }, 586 { 1221, IMX6Q_GPR13_SATA_TX_LVL_1_221_V }, 587 { 1230, IMX6Q_GPR13_SATA_TX_LVL_1_230_V }, 588 { 1240, IMX6Q_GPR13_SATA_TX_LVL_1_240_V } 589 }; 590 591 static const struct reg_value gpr13_tx_boost[] = { 592 { 0, IMX6Q_GPR13_SATA_TX_BOOST_0_00_DB }, 593 { 370, IMX6Q_GPR13_SATA_TX_BOOST_0_37_DB }, 594 { 740, IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB }, 595 { 1110, IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB }, 596 { 1480, IMX6Q_GPR13_SATA_TX_BOOST_1_48_DB }, 597 { 1850, IMX6Q_GPR13_SATA_TX_BOOST_1_85_DB }, 598 { 2220, IMX6Q_GPR13_SATA_TX_BOOST_2_22_DB }, 599 { 2590, IMX6Q_GPR13_SATA_TX_BOOST_2_59_DB }, 600 { 2960, IMX6Q_GPR13_SATA_TX_BOOST_2_96_DB }, 601 { 3330, IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB }, 602 { 3700, IMX6Q_GPR13_SATA_TX_BOOST_3_70_DB }, 603 { 4070, IMX6Q_GPR13_SATA_TX_BOOST_4_07_DB }, 604 { 4440, IMX6Q_GPR13_SATA_TX_BOOST_4_44_DB }, 605 { 4810, IMX6Q_GPR13_SATA_TX_BOOST_4_81_DB }, 606 { 5280, IMX6Q_GPR13_SATA_TX_BOOST_5_28_DB }, 607 { 5750, IMX6Q_GPR13_SATA_TX_BOOST_5_75_DB } 608 }; 609 610 static const struct reg_value gpr13_tx_atten[] = { 611 { 8, IMX6Q_GPR13_SATA_TX_ATTEN_8_16 }, 612 { 9, IMX6Q_GPR13_SATA_TX_ATTEN_9_16 }, 613 { 10, IMX6Q_GPR13_SATA_TX_ATTEN_10_16 }, 614 { 12, IMX6Q_GPR13_SATA_TX_ATTEN_12_16 }, 615 { 14, IMX6Q_GPR13_SATA_TX_ATTEN_14_16 }, 616 { 16, IMX6Q_GPR13_SATA_TX_ATTEN_16_16 }, 617 }; 618 619 static const struct reg_value gpr13_rx_eq[] = { 620 { 500, IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB }, 621 { 1000, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB }, 622 { 1500, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB }, 623 { 2000, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB }, 624 { 2500, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB }, 625 { 3000, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB }, 626 { 3500, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB }, 627 { 4000, IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB }, 628 }; 629 630 static const struct reg_property gpr13_props[] = { 631 { 632 .name = "fsl,transmit-level-mV", 633 .values = gpr13_tx_level, 634 .num_values = ARRAY_SIZE(gpr13_tx_level), 635 .def_value = IMX6Q_GPR13_SATA_TX_LVL_1_025_V, 636 }, { 637 .name = "fsl,transmit-boost-mdB", 638 .values = gpr13_tx_boost, 639 .num_values = ARRAY_SIZE(gpr13_tx_boost), 640 .def_value = IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB, 641 }, { 642 .name = "fsl,transmit-atten-16ths", 643 .values = gpr13_tx_atten, 644 .num_values = ARRAY_SIZE(gpr13_tx_atten), 645 .def_value = IMX6Q_GPR13_SATA_TX_ATTEN_9_16, 646 }, { 647 .name = "fsl,receive-eq-mdB", 648 .values = gpr13_rx_eq, 649 .num_values = ARRAY_SIZE(gpr13_rx_eq), 650 .def_value = IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB, 651 }, { 652 .name = "fsl,no-spread-spectrum", 653 .def_value = IMX6Q_GPR13_SATA_MPLL_SS_EN, 654 .set_value = 0, 655 }, 656 }; 657 658 static u32 imx_ahci_parse_props(struct device *dev, 659 const struct reg_property *prop, size_t num) 660 { 661 struct device_node *np = dev->of_node; 662 u32 reg_value = 0; 663 int i, j; 664 665 for (i = 0; i < num; i++, prop++) { 666 u32 of_val; 667 668 if (prop->num_values == 0) { 669 if (of_property_read_bool(np, prop->name)) 670 reg_value |= prop->set_value; 671 else 672 reg_value |= prop->def_value; 673 continue; 674 } 675 676 if (of_property_read_u32(np, prop->name, &of_val)) { 677 dev_info(dev, "%s not specified, using %08x\n", 678 prop->name, prop->def_value); 679 reg_value |= prop->def_value; 680 continue; 681 } 682 683 for (j = 0; j < prop->num_values; j++) { 684 if (prop->values[j].of_value == of_val) { 685 dev_info(dev, "%s value %u, using %08x\n", 686 prop->name, of_val, prop->values[j].reg_value); 687 reg_value |= prop->values[j].reg_value; 688 break; 689 } 690 } 691 692 if (j == prop->num_values) { 693 dev_err(dev, "DT property %s is not a valid value\n", 694 prop->name); 695 reg_value |= prop->def_value; 696 } 697 } 698 699 return reg_value; 700 } 701 702 static struct scsi_host_template ahci_platform_sht = { 703 AHCI_SHT(DRV_NAME), 704 }; 705 706 static int imx_ahci_probe(struct platform_device *pdev) 707 { 708 struct device *dev = &pdev->dev; 709 const struct of_device_id *of_id; 710 struct ahci_host_priv *hpriv; 711 struct imx_ahci_priv *imxpriv; 712 unsigned int reg_val; 713 int ret; 714 715 of_id = of_match_device(imx_ahci_of_match, dev); 716 if (!of_id) 717 return -EINVAL; 718 719 imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL); 720 if (!imxpriv) 721 return -ENOMEM; 722 723 imxpriv->ahci_pdev = pdev; 724 imxpriv->no_device = false; 725 imxpriv->first_time = true; 726 imxpriv->type = (enum ahci_imx_type)of_id->data; 727 728 imxpriv->sata_clk = devm_clk_get(dev, "sata"); 729 if (IS_ERR(imxpriv->sata_clk)) { 730 dev_err(dev, "can't get sata clock.\n"); 731 return PTR_ERR(imxpriv->sata_clk); 732 } 733 734 imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref"); 735 if (IS_ERR(imxpriv->sata_ref_clk)) { 736 dev_err(dev, "can't get sata_ref clock.\n"); 737 return PTR_ERR(imxpriv->sata_ref_clk); 738 } 739 740 imxpriv->ahb_clk = devm_clk_get(dev, "ahb"); 741 if (IS_ERR(imxpriv->ahb_clk)) { 742 dev_err(dev, "can't get ahb clock.\n"); 743 return PTR_ERR(imxpriv->ahb_clk); 744 } 745 746 if (imxpriv->type == AHCI_IMX6Q) { 747 u32 reg_value; 748 749 imxpriv->gpr = syscon_regmap_lookup_by_compatible( 750 "fsl,imx6q-iomuxc-gpr"); 751 if (IS_ERR(imxpriv->gpr)) { 752 dev_err(dev, 753 "failed to find fsl,imx6q-iomux-gpr regmap\n"); 754 return PTR_ERR(imxpriv->gpr); 755 } 756 757 reg_value = imx_ahci_parse_props(dev, gpr13_props, 758 ARRAY_SIZE(gpr13_props)); 759 760 imxpriv->phy_params = 761 IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M | 762 IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F | 763 IMX6Q_GPR13_SATA_SPD_MODE_3P0G | 764 reg_value; 765 } 766 767 hpriv = ahci_platform_get_resources(pdev); 768 if (IS_ERR(hpriv)) 769 return PTR_ERR(hpriv); 770 771 hpriv->plat_data = imxpriv; 772 773 ret = clk_prepare_enable(imxpriv->sata_clk); 774 if (ret) 775 return ret; 776 777 if (imxpriv->type == AHCI_IMX53 && 778 IS_ENABLED(CONFIG_HWMON)) { 779 /* Add the temperature monitor */ 780 struct device *hwmon_dev; 781 782 hwmon_dev = 783 devm_hwmon_device_register_with_groups(dev, 784 "sata_ahci", 785 hpriv, 786 fsl_sata_ahci_groups); 787 if (IS_ERR(hwmon_dev)) { 788 ret = PTR_ERR(hwmon_dev); 789 goto disable_clk; 790 } 791 devm_thermal_zone_of_sensor_register(hwmon_dev, 0, hwmon_dev, 792 &fsl_sata_ahci_of_thermal_ops); 793 dev_info(dev, "%s: sensor 'sata_ahci'\n", dev_name(hwmon_dev)); 794 } 795 796 ret = imx_sata_enable(hpriv); 797 if (ret) 798 goto disable_clk; 799 800 /* 801 * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL, 802 * and IP vendor specific register IMX_TIMER1MS. 803 * Configure CAP_SSS (support stagered spin up). 804 * Implement the port0. 805 * Get the ahb clock rate, and configure the TIMER1MS register. 806 */ 807 reg_val = readl(hpriv->mmio + HOST_CAP); 808 if (!(reg_val & HOST_CAP_SSS)) { 809 reg_val |= HOST_CAP_SSS; 810 writel(reg_val, hpriv->mmio + HOST_CAP); 811 } 812 reg_val = readl(hpriv->mmio + HOST_PORTS_IMPL); 813 if (!(reg_val & 0x1)) { 814 reg_val |= 0x1; 815 writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL); 816 } 817 818 reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000; 819 writel(reg_val, hpriv->mmio + IMX_TIMER1MS); 820 821 ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info, 822 &ahci_platform_sht); 823 if (ret) 824 goto disable_sata; 825 826 return 0; 827 828 disable_sata: 829 imx_sata_disable(hpriv); 830 disable_clk: 831 clk_disable_unprepare(imxpriv->sata_clk); 832 return ret; 833 } 834 835 static void ahci_imx_host_stop(struct ata_host *host) 836 { 837 struct ahci_host_priv *hpriv = host->private_data; 838 struct imx_ahci_priv *imxpriv = hpriv->plat_data; 839 840 imx_sata_disable(hpriv); 841 clk_disable_unprepare(imxpriv->sata_clk); 842 } 843 844 #ifdef CONFIG_PM_SLEEP 845 static int imx_ahci_suspend(struct device *dev) 846 { 847 struct ata_host *host = dev_get_drvdata(dev); 848 struct ahci_host_priv *hpriv = host->private_data; 849 int ret; 850 851 ret = ahci_platform_suspend_host(dev); 852 if (ret) 853 return ret; 854 855 imx_sata_disable(hpriv); 856 857 return 0; 858 } 859 860 static int imx_ahci_resume(struct device *dev) 861 { 862 struct ata_host *host = dev_get_drvdata(dev); 863 struct ahci_host_priv *hpriv = host->private_data; 864 int ret; 865 866 ret = imx_sata_enable(hpriv); 867 if (ret) 868 return ret; 869 870 return ahci_platform_resume_host(dev); 871 } 872 #endif 873 874 static SIMPLE_DEV_PM_OPS(ahci_imx_pm_ops, imx_ahci_suspend, imx_ahci_resume); 875 876 static struct platform_driver imx_ahci_driver = { 877 .probe = imx_ahci_probe, 878 .remove = ata_platform_remove_one, 879 .driver = { 880 .name = DRV_NAME, 881 .of_match_table = imx_ahci_of_match, 882 .pm = &ahci_imx_pm_ops, 883 }, 884 }; 885 module_platform_driver(imx_ahci_driver); 886 887 MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver"); 888 MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>"); 889 MODULE_LICENSE("GPL"); 890 MODULE_ALIAS("ahci:imx"); 891