1 /* 2 * copyright (c) 2013 Freescale Semiconductor, Inc. 3 * Freescale IMX AHCI SATA platform driver 4 * 5 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/platform_device.h> 23 #include <linux/regmap.h> 24 #include <linux/ahci_platform.h> 25 #include <linux/of_device.h> 26 #include <linux/mfd/syscon.h> 27 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 28 #include <linux/libata.h> 29 #include "ahci.h" 30 31 enum { 32 /* Timer 1-ms Register */ 33 IMX_TIMER1MS = 0x00e0, 34 /* Port0 PHY Control Register */ 35 IMX_P0PHYCR = 0x0178, 36 IMX_P0PHYCR_TEST_PDDQ = 1 << 20, 37 IMX_P0PHYCR_CR_READ = 1 << 19, 38 IMX_P0PHYCR_CR_WRITE = 1 << 18, 39 IMX_P0PHYCR_CR_CAP_DATA = 1 << 17, 40 IMX_P0PHYCR_CR_CAP_ADDR = 1 << 16, 41 /* Port0 PHY Status Register */ 42 IMX_P0PHYSR = 0x017c, 43 IMX_P0PHYSR_CR_ACK = 1 << 18, 44 IMX_P0PHYSR_CR_DATA_OUT = 0xffff << 0, 45 /* Lane0 Output Status Register */ 46 IMX_LANE0_OUT_STAT = 0x2003, 47 IMX_LANE0_OUT_STAT_RX_PLL_STATE = 1 << 1, 48 /* Clock Reset Register */ 49 IMX_CLOCK_RESET = 0x7f3f, 50 IMX_CLOCK_RESET_RESET = 1 << 0, 51 }; 52 53 enum ahci_imx_type { 54 AHCI_IMX53, 55 AHCI_IMX6Q, 56 }; 57 58 struct imx_ahci_priv { 59 struct platform_device *ahci_pdev; 60 enum ahci_imx_type type; 61 struct clk *ahb_clk; 62 struct regmap *gpr; 63 bool no_device; 64 bool first_time; 65 }; 66 67 static int ahci_imx_hotplug; 68 module_param_named(hotplug, ahci_imx_hotplug, int, 0644); 69 MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)"); 70 71 static void ahci_imx_host_stop(struct ata_host *host); 72 73 static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert) 74 { 75 int timeout = 10; 76 u32 crval; 77 u32 srval; 78 79 /* Assert or deassert the bit */ 80 crval = readl(mmio + IMX_P0PHYCR); 81 if (assert) 82 crval |= bit; 83 else 84 crval &= ~bit; 85 writel(crval, mmio + IMX_P0PHYCR); 86 87 /* Wait for the cr_ack signal */ 88 do { 89 srval = readl(mmio + IMX_P0PHYSR); 90 if ((assert ? srval : ~srval) & IMX_P0PHYSR_CR_ACK) 91 break; 92 usleep_range(100, 200); 93 } while (--timeout); 94 95 return timeout ? 0 : -ETIMEDOUT; 96 } 97 98 static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio) 99 { 100 u32 crval = addr; 101 int ret; 102 103 /* Supply the address on cr_data_in */ 104 writel(crval, mmio + IMX_P0PHYCR); 105 106 /* Assert the cr_cap_addr signal */ 107 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true); 108 if (ret) 109 return ret; 110 111 /* Deassert cr_cap_addr */ 112 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false); 113 if (ret) 114 return ret; 115 116 return 0; 117 } 118 119 static int imx_phy_reg_write(u16 val, void __iomem *mmio) 120 { 121 u32 crval = val; 122 int ret; 123 124 /* Supply the data on cr_data_in */ 125 writel(crval, mmio + IMX_P0PHYCR); 126 127 /* Assert the cr_cap_data signal */ 128 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, true); 129 if (ret) 130 return ret; 131 132 /* Deassert cr_cap_data */ 133 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, false); 134 if (ret) 135 return ret; 136 137 if (val & IMX_CLOCK_RESET_RESET) { 138 /* 139 * In case we're resetting the phy, it's unable to acknowledge, 140 * so we return immediately here. 141 */ 142 crval |= IMX_P0PHYCR_CR_WRITE; 143 writel(crval, mmio + IMX_P0PHYCR); 144 goto out; 145 } 146 147 /* Assert the cr_write signal */ 148 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, true); 149 if (ret) 150 return ret; 151 152 /* Deassert cr_write */ 153 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, false); 154 if (ret) 155 return ret; 156 157 out: 158 return 0; 159 } 160 161 static int imx_phy_reg_read(u16 *val, void __iomem *mmio) 162 { 163 int ret; 164 165 /* Assert the cr_read signal */ 166 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, true); 167 if (ret) 168 return ret; 169 170 /* Capture the data from cr_data_out[] */ 171 *val = readl(mmio + IMX_P0PHYSR) & IMX_P0PHYSR_CR_DATA_OUT; 172 173 /* Deassert cr_read */ 174 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, false); 175 if (ret) 176 return ret; 177 178 return 0; 179 } 180 181 static int imx_sata_phy_reset(struct ahci_host_priv *hpriv) 182 { 183 void __iomem *mmio = hpriv->mmio; 184 int timeout = 10; 185 u16 val; 186 int ret; 187 188 /* Reset SATA PHY by setting RESET bit of PHY register CLOCK_RESET */ 189 ret = imx_phy_reg_addressing(IMX_CLOCK_RESET, mmio); 190 if (ret) 191 return ret; 192 ret = imx_phy_reg_write(IMX_CLOCK_RESET_RESET, mmio); 193 if (ret) 194 return ret; 195 196 /* Wait for PHY RX_PLL to be stable */ 197 do { 198 usleep_range(100, 200); 199 ret = imx_phy_reg_addressing(IMX_LANE0_OUT_STAT, mmio); 200 if (ret) 201 return ret; 202 ret = imx_phy_reg_read(&val, mmio); 203 if (ret) 204 return ret; 205 if (val & IMX_LANE0_OUT_STAT_RX_PLL_STATE) 206 break; 207 } while (--timeout); 208 209 return timeout ? 0 : -ETIMEDOUT; 210 } 211 212 static int imx_sata_enable(struct ahci_host_priv *hpriv) 213 { 214 struct imx_ahci_priv *imxpriv = hpriv->plat_data; 215 struct device *dev = &imxpriv->ahci_pdev->dev; 216 int ret; 217 218 if (imxpriv->no_device) 219 return 0; 220 221 if (hpriv->target_pwr) { 222 ret = regulator_enable(hpriv->target_pwr); 223 if (ret) 224 return ret; 225 } 226 227 ret = ahci_platform_enable_clks(hpriv); 228 if (ret < 0) 229 goto disable_regulator; 230 231 if (imxpriv->type == AHCI_IMX6Q) { 232 /* 233 * set PHY Paremeters, two steps to configure the GPR13, 234 * one write for rest of parameters, mask of first write 235 * is 0x07ffffff, and the other one write for setting 236 * the mpll_clk_en. 237 */ 238 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13, 239 IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK | 240 IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK | 241 IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK | 242 IMX6Q_GPR13_SATA_SPD_MODE_MASK | 243 IMX6Q_GPR13_SATA_MPLL_SS_EN | 244 IMX6Q_GPR13_SATA_TX_ATTEN_MASK | 245 IMX6Q_GPR13_SATA_TX_BOOST_MASK | 246 IMX6Q_GPR13_SATA_TX_LVL_MASK | 247 IMX6Q_GPR13_SATA_MPLL_CLK_EN | 248 IMX6Q_GPR13_SATA_TX_EDGE_RATE, 249 IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB | 250 IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M | 251 IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F | 252 IMX6Q_GPR13_SATA_SPD_MODE_3P0G | 253 IMX6Q_GPR13_SATA_MPLL_SS_EN | 254 IMX6Q_GPR13_SATA_TX_ATTEN_9_16 | 255 IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB | 256 IMX6Q_GPR13_SATA_TX_LVL_1_025_V); 257 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13, 258 IMX6Q_GPR13_SATA_MPLL_CLK_EN, 259 IMX6Q_GPR13_SATA_MPLL_CLK_EN); 260 261 usleep_range(100, 200); 262 263 ret = imx_sata_phy_reset(hpriv); 264 if (ret) { 265 dev_err(dev, "failed to reset phy: %d\n", ret); 266 goto disable_regulator; 267 } 268 } 269 270 usleep_range(1000, 2000); 271 272 return 0; 273 274 disable_regulator: 275 if (hpriv->target_pwr) 276 regulator_disable(hpriv->target_pwr); 277 278 return ret; 279 } 280 281 static void imx_sata_disable(struct ahci_host_priv *hpriv) 282 { 283 struct imx_ahci_priv *imxpriv = hpriv->plat_data; 284 285 if (imxpriv->no_device) 286 return; 287 288 if (imxpriv->type == AHCI_IMX6Q) { 289 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13, 290 IMX6Q_GPR13_SATA_MPLL_CLK_EN, 291 !IMX6Q_GPR13_SATA_MPLL_CLK_EN); 292 } 293 294 ahci_platform_disable_clks(hpriv); 295 296 if (hpriv->target_pwr) 297 regulator_disable(hpriv->target_pwr); 298 } 299 300 static void ahci_imx_error_handler(struct ata_port *ap) 301 { 302 u32 reg_val; 303 struct ata_device *dev; 304 struct ata_host *host = dev_get_drvdata(ap->dev); 305 struct ahci_host_priv *hpriv = host->private_data; 306 void __iomem *mmio = hpriv->mmio; 307 struct imx_ahci_priv *imxpriv = hpriv->plat_data; 308 309 ahci_error_handler(ap); 310 311 if (!(imxpriv->first_time) || ahci_imx_hotplug) 312 return; 313 314 imxpriv->first_time = false; 315 316 ata_for_each_dev(dev, &ap->link, ENABLED) 317 return; 318 /* 319 * Disable link to save power. An imx ahci port can't be recovered 320 * without full reset once the pddq mode is enabled making it 321 * impossible to use as part of libata LPM. 322 */ 323 reg_val = readl(mmio + IMX_P0PHYCR); 324 writel(reg_val | IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR); 325 imx_sata_disable(hpriv); 326 imxpriv->no_device = true; 327 } 328 329 static int ahci_imx_softreset(struct ata_link *link, unsigned int *class, 330 unsigned long deadline) 331 { 332 struct ata_port *ap = link->ap; 333 struct ata_host *host = dev_get_drvdata(ap->dev); 334 struct ahci_host_priv *hpriv = host->private_data; 335 struct imx_ahci_priv *imxpriv = hpriv->plat_data; 336 int ret = -EIO; 337 338 if (imxpriv->type == AHCI_IMX53) 339 ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline); 340 else if (imxpriv->type == AHCI_IMX6Q) 341 ret = ahci_ops.softreset(link, class, deadline); 342 343 return ret; 344 } 345 346 static struct ata_port_operations ahci_imx_ops = { 347 .inherits = &ahci_ops, 348 .host_stop = ahci_imx_host_stop, 349 .error_handler = ahci_imx_error_handler, 350 .softreset = ahci_imx_softreset, 351 }; 352 353 static const struct ata_port_info ahci_imx_port_info = { 354 .flags = AHCI_FLAG_COMMON, 355 .pio_mask = ATA_PIO4, 356 .udma_mask = ATA_UDMA6, 357 .port_ops = &ahci_imx_ops, 358 }; 359 360 static const struct of_device_id imx_ahci_of_match[] = { 361 { .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 }, 362 { .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q }, 363 {}, 364 }; 365 MODULE_DEVICE_TABLE(of, imx_ahci_of_match); 366 367 static int imx_ahci_probe(struct platform_device *pdev) 368 { 369 struct device *dev = &pdev->dev; 370 const struct of_device_id *of_id; 371 struct ahci_host_priv *hpriv; 372 struct imx_ahci_priv *imxpriv; 373 unsigned int reg_val; 374 int ret; 375 376 of_id = of_match_device(imx_ahci_of_match, dev); 377 if (!of_id) 378 return -EINVAL; 379 380 imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL); 381 if (!imxpriv) 382 return -ENOMEM; 383 384 imxpriv->ahci_pdev = pdev; 385 imxpriv->no_device = false; 386 imxpriv->first_time = true; 387 imxpriv->type = (enum ahci_imx_type)of_id->data; 388 imxpriv->ahb_clk = devm_clk_get(dev, "ahb"); 389 if (IS_ERR(imxpriv->ahb_clk)) { 390 dev_err(dev, "can't get ahb clock.\n"); 391 return PTR_ERR(imxpriv->ahb_clk); 392 } 393 394 if (imxpriv->type == AHCI_IMX6Q) { 395 imxpriv->gpr = syscon_regmap_lookup_by_compatible( 396 "fsl,imx6q-iomuxc-gpr"); 397 if (IS_ERR(imxpriv->gpr)) { 398 dev_err(dev, 399 "failed to find fsl,imx6q-iomux-gpr regmap\n"); 400 return PTR_ERR(imxpriv->gpr); 401 } 402 } 403 404 hpriv = ahci_platform_get_resources(pdev); 405 if (IS_ERR(hpriv)) 406 return PTR_ERR(hpriv); 407 408 hpriv->plat_data = imxpriv; 409 410 ret = imx_sata_enable(hpriv); 411 if (ret) 412 return ret; 413 414 /* 415 * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL, 416 * and IP vendor specific register IMX_TIMER1MS. 417 * Configure CAP_SSS (support stagered spin up). 418 * Implement the port0. 419 * Get the ahb clock rate, and configure the TIMER1MS register. 420 */ 421 reg_val = readl(hpriv->mmio + HOST_CAP); 422 if (!(reg_val & HOST_CAP_SSS)) { 423 reg_val |= HOST_CAP_SSS; 424 writel(reg_val, hpriv->mmio + HOST_CAP); 425 } 426 reg_val = readl(hpriv->mmio + HOST_PORTS_IMPL); 427 if (!(reg_val & 0x1)) { 428 reg_val |= 0x1; 429 writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL); 430 } 431 432 reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000; 433 writel(reg_val, hpriv->mmio + IMX_TIMER1MS); 434 435 ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info, 436 0, 0, 0); 437 if (ret) 438 imx_sata_disable(hpriv); 439 440 return ret; 441 } 442 443 static void ahci_imx_host_stop(struct ata_host *host) 444 { 445 struct ahci_host_priv *hpriv = host->private_data; 446 447 imx_sata_disable(hpriv); 448 } 449 450 #ifdef CONFIG_PM_SLEEP 451 static int imx_ahci_suspend(struct device *dev) 452 { 453 struct ata_host *host = dev_get_drvdata(dev); 454 struct ahci_host_priv *hpriv = host->private_data; 455 int ret; 456 457 ret = ahci_platform_suspend_host(dev); 458 if (ret) 459 return ret; 460 461 imx_sata_disable(hpriv); 462 463 return 0; 464 } 465 466 static int imx_ahci_resume(struct device *dev) 467 { 468 struct ata_host *host = dev_get_drvdata(dev); 469 struct ahci_host_priv *hpriv = host->private_data; 470 int ret; 471 472 ret = imx_sata_enable(hpriv); 473 if (ret) 474 return ret; 475 476 return ahci_platform_resume_host(dev); 477 } 478 #endif 479 480 static SIMPLE_DEV_PM_OPS(ahci_imx_pm_ops, imx_ahci_suspend, imx_ahci_resume); 481 482 static struct platform_driver imx_ahci_driver = { 483 .probe = imx_ahci_probe, 484 .remove = ata_platform_remove_one, 485 .driver = { 486 .name = "ahci-imx", 487 .owner = THIS_MODULE, 488 .of_match_table = imx_ahci_of_match, 489 .pm = &ahci_imx_pm_ops, 490 }, 491 }; 492 module_platform_driver(imx_ahci_driver); 493 494 MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver"); 495 MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>"); 496 MODULE_LICENSE("GPL"); 497 MODULE_ALIAS("ahci:imx"); 498