1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Xilinx, Inc. 4 * CEVA AHCI SATA platform driver 5 * 6 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov 7 */ 8 9 #include <linux/ahci_platform.h> 10 #include <linux/kernel.h> 11 #include <linux/libata.h> 12 #include <linux/module.h> 13 #include <linux/of_device.h> 14 #include <linux/platform_device.h> 15 #include <linux/reset.h> 16 #include "ahci.h" 17 18 /* Vendor Specific Register Offsets */ 19 #define AHCI_VEND_PCFG 0xA4 20 #define AHCI_VEND_PPCFG 0xA8 21 #define AHCI_VEND_PP2C 0xAC 22 #define AHCI_VEND_PP3C 0xB0 23 #define AHCI_VEND_PP4C 0xB4 24 #define AHCI_VEND_PP5C 0xB8 25 #define AHCI_VEND_AXICC 0xBC 26 #define AHCI_VEND_PAXIC 0xC0 27 #define AHCI_VEND_PTC 0xC8 28 29 /* Vendor Specific Register bit definitions */ 30 #define PAXIC_ADBW_BW64 0x1 31 #define PAXIC_MAWID(i) (((i) * 2) << 4) 32 #define PAXIC_MARID(i) (((i) * 2) << 12) 33 #define PAXIC_MARIDD(i) ((((i) * 2) + 1) << 16) 34 #define PAXIC_MAWIDD(i) ((((i) * 2) + 1) << 8) 35 #define PAXIC_OTL (0x4 << 20) 36 37 /* Register bit definitions for cache control */ 38 #define AXICC_ARCA_VAL (0xF << 0) 39 #define AXICC_ARCF_VAL (0xF << 4) 40 #define AXICC_ARCH_VAL (0xF << 8) 41 #define AXICC_ARCP_VAL (0xF << 12) 42 #define AXICC_AWCFD_VAL (0xF << 16) 43 #define AXICC_AWCD_VAL (0xF << 20) 44 #define AXICC_AWCF_VAL (0xF << 24) 45 46 #define PCFG_TPSS_VAL (0x32 << 16) 47 #define PCFG_TPRS_VAL (0x2 << 12) 48 #define PCFG_PAD_VAL 0x2 49 50 #define PPCFG_TTA 0x1FFFE 51 #define PPCFG_PSSO_EN (1 << 28) 52 #define PPCFG_PSS_EN (1 << 29) 53 #define PPCFG_ESDF_EN (1 << 31) 54 55 #define PP5C_RIT 0x60216 56 #define PP5C_RCT (0x7f0 << 20) 57 58 #define PTC_RX_WM_VAL 0x40 59 #define PTC_RSVD (1 << 27) 60 61 #define PORT0_BASE 0x100 62 #define PORT1_BASE 0x180 63 64 /* Port Control Register Bit Definitions */ 65 #define PORT_SCTL_SPD_GEN3 (0x3 << 4) 66 #define PORT_SCTL_SPD_GEN2 (0x2 << 4) 67 #define PORT_SCTL_SPD_GEN1 (0x1 << 4) 68 #define PORT_SCTL_IPM (0x3 << 8) 69 70 #define PORT_BASE 0x100 71 #define PORT_OFFSET 0x80 72 #define NR_PORTS 2 73 #define DRV_NAME "ahci-ceva" 74 #define CEVA_FLAG_BROKEN_GEN2 1 75 76 static unsigned int rx_watermark = PTC_RX_WM_VAL; 77 module_param(rx_watermark, uint, 0644); 78 MODULE_PARM_DESC(rx_watermark, "RxWaterMark value (0 - 0x80)"); 79 80 struct ceva_ahci_priv { 81 struct platform_device *ahci_pdev; 82 /* Port Phy2Cfg Register */ 83 u32 pp2c[NR_PORTS]; 84 u32 pp3c[NR_PORTS]; 85 u32 pp4c[NR_PORTS]; 86 u32 pp5c[NR_PORTS]; 87 /* Axi Cache Control Register */ 88 u32 axicc; 89 bool is_cci_enabled; 90 int flags; 91 struct reset_control *rst; 92 }; 93 94 static unsigned int ceva_ahci_read_id(struct ata_device *dev, 95 struct ata_taskfile *tf, u16 *id) 96 { 97 __le16 *__id = (__le16 *)id; 98 u32 err_mask; 99 100 err_mask = ata_do_dev_read_id(dev, tf, id); 101 if (err_mask) 102 return err_mask; 103 /* 104 * Since CEVA controller does not support device sleep feature, we 105 * need to clear DEVSLP (bit 8) in word78 of the IDENTIFY DEVICE data. 106 */ 107 __id[ATA_ID_FEATURE_SUPP] &= cpu_to_le16(~(1 << 8)); 108 109 return 0; 110 } 111 112 static struct ata_port_operations ahci_ceva_ops = { 113 .inherits = &ahci_platform_ops, 114 .read_id = ceva_ahci_read_id, 115 }; 116 117 static const struct ata_port_info ahci_ceva_port_info = { 118 .flags = AHCI_FLAG_COMMON, 119 .pio_mask = ATA_PIO4, 120 .udma_mask = ATA_UDMA6, 121 .port_ops = &ahci_ceva_ops, 122 }; 123 124 static void ahci_ceva_setup(struct ahci_host_priv *hpriv) 125 { 126 void __iomem *mmio = hpriv->mmio; 127 struct ceva_ahci_priv *cevapriv = hpriv->plat_data; 128 u32 tmp; 129 int i; 130 131 /* Set AHCI Enable */ 132 tmp = readl(mmio + HOST_CTL); 133 tmp |= HOST_AHCI_EN; 134 writel(tmp, mmio + HOST_CTL); 135 136 for (i = 0; i < NR_PORTS; i++) { 137 /* TPSS TPRS scalars, CISE and Port Addr */ 138 tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i); 139 writel(tmp, mmio + AHCI_VEND_PCFG); 140 141 /* 142 * AXI Data bus width to 64 143 * Set Mem Addr Read, Write ID for data transfers 144 * Set Mem Addr Read ID, Write ID for non-data transfers 145 * Transfer limit to 72 DWord 146 */ 147 tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD(i) | PAXIC_MARIDD(i) | 148 PAXIC_MAWID(i) | PAXIC_MARID(i) | PAXIC_OTL; 149 writel(tmp, mmio + AHCI_VEND_PAXIC); 150 151 /* Set AXI cache control register if CCi is enabled */ 152 if (cevapriv->is_cci_enabled) { 153 tmp = readl(mmio + AHCI_VEND_AXICC); 154 tmp |= AXICC_ARCA_VAL | AXICC_ARCF_VAL | 155 AXICC_ARCH_VAL | AXICC_ARCP_VAL | 156 AXICC_AWCFD_VAL | AXICC_AWCD_VAL | 157 AXICC_AWCF_VAL; 158 writel(tmp, mmio + AHCI_VEND_AXICC); 159 } 160 161 /* Port Phy Cfg register enables */ 162 tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN; 163 writel(tmp, mmio + AHCI_VEND_PPCFG); 164 165 /* Phy Control OOB timing parameters COMINIT */ 166 writel(cevapriv->pp2c[i], mmio + AHCI_VEND_PP2C); 167 168 /* Phy Control OOB timing parameters COMWAKE */ 169 writel(cevapriv->pp3c[i], mmio + AHCI_VEND_PP3C); 170 171 /* Phy Control Burst timing setting */ 172 writel(cevapriv->pp4c[i], mmio + AHCI_VEND_PP4C); 173 174 /* Rate Change Timer and Retry Interval Timer setting */ 175 writel(cevapriv->pp5c[i], mmio + AHCI_VEND_PP5C); 176 177 /* Rx Watermark setting */ 178 tmp = rx_watermark | PTC_RSVD; 179 writel(tmp, mmio + AHCI_VEND_PTC); 180 181 /* Default to Gen 3 Speed and Gen 1 if Gen2 is broken */ 182 tmp = PORT_SCTL_SPD_GEN3 | PORT_SCTL_IPM; 183 if (cevapriv->flags & CEVA_FLAG_BROKEN_GEN2) 184 tmp = PORT_SCTL_SPD_GEN1 | PORT_SCTL_IPM; 185 writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i); 186 } 187 } 188 189 static struct scsi_host_template ahci_platform_sht = { 190 AHCI_SHT(DRV_NAME), 191 }; 192 193 static int ceva_ahci_probe(struct platform_device *pdev) 194 { 195 struct device_node *np = pdev->dev.of_node; 196 struct device *dev = &pdev->dev; 197 struct ahci_host_priv *hpriv; 198 struct ceva_ahci_priv *cevapriv; 199 enum dev_dma_attr attr; 200 int rc; 201 202 cevapriv = devm_kzalloc(dev, sizeof(*cevapriv), GFP_KERNEL); 203 if (!cevapriv) 204 return -ENOMEM; 205 206 cevapriv->ahci_pdev = pdev; 207 208 cevapriv->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, 209 NULL); 210 if (IS_ERR(cevapriv->rst)) 211 dev_err_probe(&pdev->dev, PTR_ERR(cevapriv->rst), 212 "failed to get reset\n"); 213 214 hpriv = ahci_platform_get_resources(pdev, 0); 215 if (IS_ERR(hpriv)) 216 return PTR_ERR(hpriv); 217 218 if (!cevapriv->rst) { 219 rc = ahci_platform_enable_resources(hpriv); 220 if (rc) 221 return rc; 222 } else { 223 int i; 224 225 rc = ahci_platform_enable_clks(hpriv); 226 if (rc) 227 return rc; 228 /* Assert the controller reset */ 229 reset_control_assert(cevapriv->rst); 230 231 for (i = 0; i < hpriv->nports; i++) { 232 rc = phy_init(hpriv->phys[i]); 233 if (rc) 234 return rc; 235 } 236 237 /* De-assert the controller reset */ 238 reset_control_deassert(cevapriv->rst); 239 240 for (i = 0; i < hpriv->nports; i++) { 241 rc = phy_power_on(hpriv->phys[i]); 242 if (rc) { 243 phy_exit(hpriv->phys[i]); 244 return rc; 245 } 246 } 247 } 248 249 if (of_property_read_bool(np, "ceva,broken-gen2")) 250 cevapriv->flags = CEVA_FLAG_BROKEN_GEN2; 251 252 /* Read OOB timing value for COMINIT from device-tree */ 253 if (of_property_read_u8_array(np, "ceva,p0-cominit-params", 254 (u8 *)&cevapriv->pp2c[0], 4) < 0) { 255 dev_warn(dev, "ceva,p0-cominit-params property not defined\n"); 256 return -EINVAL; 257 } 258 259 if (of_property_read_u8_array(np, "ceva,p1-cominit-params", 260 (u8 *)&cevapriv->pp2c[1], 4) < 0) { 261 dev_warn(dev, "ceva,p1-cominit-params property not defined\n"); 262 return -EINVAL; 263 } 264 265 /* Read OOB timing value for COMWAKE from device-tree*/ 266 if (of_property_read_u8_array(np, "ceva,p0-comwake-params", 267 (u8 *)&cevapriv->pp3c[0], 4) < 0) { 268 dev_warn(dev, "ceva,p0-comwake-params property not defined\n"); 269 return -EINVAL; 270 } 271 272 if (of_property_read_u8_array(np, "ceva,p1-comwake-params", 273 (u8 *)&cevapriv->pp3c[1], 4) < 0) { 274 dev_warn(dev, "ceva,p1-comwake-params property not defined\n"); 275 return -EINVAL; 276 } 277 278 /* Read phy BURST timing value from device-tree */ 279 if (of_property_read_u8_array(np, "ceva,p0-burst-params", 280 (u8 *)&cevapriv->pp4c[0], 4) < 0) { 281 dev_warn(dev, "ceva,p0-burst-params property not defined\n"); 282 return -EINVAL; 283 } 284 285 if (of_property_read_u8_array(np, "ceva,p1-burst-params", 286 (u8 *)&cevapriv->pp4c[1], 4) < 0) { 287 dev_warn(dev, "ceva,p1-burst-params property not defined\n"); 288 return -EINVAL; 289 } 290 291 /* Read phy RETRY interval timing value from device-tree */ 292 if (of_property_read_u16_array(np, "ceva,p0-retry-params", 293 (u16 *)&cevapriv->pp5c[0], 2) < 0) { 294 dev_warn(dev, "ceva,p0-retry-params property not defined\n"); 295 return -EINVAL; 296 } 297 298 if (of_property_read_u16_array(np, "ceva,p1-retry-params", 299 (u16 *)&cevapriv->pp5c[1], 2) < 0) { 300 dev_warn(dev, "ceva,p1-retry-params property not defined\n"); 301 return -EINVAL; 302 } 303 304 /* 305 * Check if CCI is enabled for SATA. The DEV_DMA_COHERENT is returned 306 * if CCI is enabled, so check for DEV_DMA_COHERENT. 307 */ 308 attr = device_get_dma_attr(dev); 309 cevapriv->is_cci_enabled = (attr == DEV_DMA_COHERENT); 310 311 hpriv->plat_data = cevapriv; 312 313 /* CEVA specific initialization */ 314 ahci_ceva_setup(hpriv); 315 316 rc = ahci_platform_init_host(pdev, hpriv, &ahci_ceva_port_info, 317 &ahci_platform_sht); 318 if (rc) 319 goto disable_resources; 320 321 return 0; 322 323 disable_resources: 324 ahci_platform_disable_resources(hpriv); 325 return rc; 326 } 327 328 static int __maybe_unused ceva_ahci_suspend(struct device *dev) 329 { 330 return ahci_platform_suspend(dev); 331 } 332 333 static int __maybe_unused ceva_ahci_resume(struct device *dev) 334 { 335 struct ata_host *host = dev_get_drvdata(dev); 336 struct ahci_host_priv *hpriv = host->private_data; 337 int rc; 338 339 rc = ahci_platform_enable_resources(hpriv); 340 if (rc) 341 return rc; 342 343 /* Configure CEVA specific config before resuming HBA */ 344 ahci_ceva_setup(hpriv); 345 346 rc = ahci_platform_resume_host(dev); 347 if (rc) 348 goto disable_resources; 349 350 /* We resumed so update PM runtime state */ 351 pm_runtime_disable(dev); 352 pm_runtime_set_active(dev); 353 pm_runtime_enable(dev); 354 355 return 0; 356 357 disable_resources: 358 ahci_platform_disable_resources(hpriv); 359 360 return rc; 361 } 362 363 static SIMPLE_DEV_PM_OPS(ahci_ceva_pm_ops, ceva_ahci_suspend, ceva_ahci_resume); 364 365 static const struct of_device_id ceva_ahci_of_match[] = { 366 { .compatible = "ceva,ahci-1v84" }, 367 {}, 368 }; 369 MODULE_DEVICE_TABLE(of, ceva_ahci_of_match); 370 371 static struct platform_driver ceva_ahci_driver = { 372 .probe = ceva_ahci_probe, 373 .remove = ata_platform_remove_one, 374 .driver = { 375 .name = DRV_NAME, 376 .of_match_table = ceva_ahci_of_match, 377 .pm = &ahci_ceva_pm_ops, 378 }, 379 }; 380 module_platform_driver(ceva_ahci_driver); 381 382 MODULE_DESCRIPTION("CEVA AHCI SATA platform driver"); 383 MODULE_AUTHOR("Xilinx Inc."); 384 MODULE_LICENSE("GPL v2"); 385