1 /* 2 * Broadcom SATA3 AHCI Controller Driver 3 * 4 * Copyright © 2009-2015 Broadcom Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2, or (at your option) 9 * any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include <linux/ahci_platform.h> 18 #include <linux/compiler.h> 19 #include <linux/device.h> 20 #include <linux/init.h> 21 #include <linux/interrupt.h> 22 #include <linux/io.h> 23 #include <linux/kernel.h> 24 #include <linux/libata.h> 25 #include <linux/module.h> 26 #include <linux/of.h> 27 #include <linux/platform_device.h> 28 #include <linux/string.h> 29 30 #include "ahci.h" 31 32 #define DRV_NAME "brcm-ahci" 33 34 #define SATA_TOP_CTRL_VERSION 0x0 35 #define SATA_TOP_CTRL_BUS_CTRL 0x4 36 #define MMIO_ENDIAN_SHIFT 0 /* CPU->AHCI */ 37 #define DMADESC_ENDIAN_SHIFT 2 /* AHCI->DDR */ 38 #define DMADATA_ENDIAN_SHIFT 4 /* AHCI->DDR */ 39 #define PIODATA_ENDIAN_SHIFT 6 40 #define ENDIAN_SWAP_NONE 0 41 #define ENDIAN_SWAP_FULL 2 42 #define OVERRIDE_HWINIT BIT(16) 43 #define SATA_TOP_CTRL_TP_CTRL 0x8 44 #define SATA_TOP_CTRL_PHY_CTRL 0xc 45 #define SATA_TOP_CTRL_PHY_CTRL_1 0x0 46 #define SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE BIT(14) 47 #define SATA_TOP_CTRL_PHY_CTRL_2 0x4 48 #define SATA_TOP_CTRL_2_SW_RST_MDIOREG BIT(0) 49 #define SATA_TOP_CTRL_2_SW_RST_OOB BIT(1) 50 #define SATA_TOP_CTRL_2_SW_RST_RX BIT(2) 51 #define SATA_TOP_CTRL_2_SW_RST_TX BIT(3) 52 #define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET BIT(14) 53 #define SATA_TOP_CTRL_PHY_OFFS 0x8 54 #define SATA_TOP_MAX_PHYS 2 55 56 #define SATA_FIRST_PORT_CTRL 0x700 57 #define SATA_NEXT_PORT_CTRL_OFFSET 0x80 58 #define SATA_PORT_PCTRL6(reg_base) (reg_base + 0x18) 59 60 /* On big-endian MIPS, buses are reversed to big endian, so switch them back */ 61 #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN) 62 #define DATA_ENDIAN 2 /* AHCI->DDR inbound accesses */ 63 #define MMIO_ENDIAN 2 /* CPU->AHCI outbound accesses */ 64 #else 65 #define DATA_ENDIAN 0 66 #define MMIO_ENDIAN 0 67 #endif 68 69 #define BUS_CTRL_ENDIAN_CONF \ 70 ((DATA_ENDIAN << DMADATA_ENDIAN_SHIFT) | \ 71 (DATA_ENDIAN << DMADESC_ENDIAN_SHIFT) | \ 72 (MMIO_ENDIAN << MMIO_ENDIAN_SHIFT)) 73 74 enum brcm_ahci_version { 75 BRCM_SATA_BCM7425 = 1, 76 BRCM_SATA_BCM7445, 77 BRCM_SATA_NSP, 78 }; 79 80 enum brcm_ahci_quirks { 81 BRCM_AHCI_QUIRK_NO_NCQ = BIT(0), 82 BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE = BIT(1), 83 }; 84 85 struct brcm_ahci_priv { 86 struct device *dev; 87 void __iomem *top_ctrl; 88 u32 port_mask; 89 u32 quirks; 90 enum brcm_ahci_version version; 91 }; 92 93 static const struct ata_port_info ahci_brcm_port_info = { 94 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM, 95 .link_flags = ATA_LFLAG_NO_DB_DELAY, 96 .pio_mask = ATA_PIO4, 97 .udma_mask = ATA_UDMA6, 98 .port_ops = &ahci_platform_ops, 99 }; 100 101 static inline u32 brcm_sata_readreg(void __iomem *addr) 102 { 103 /* 104 * MIPS endianness is configured by boot strap, which also reverses all 105 * bus endianness (i.e., big-endian CPU + big endian bus ==> native 106 * endian I/O). 107 * 108 * Other architectures (e.g., ARM) either do not support big endian, or 109 * else leave I/O in little endian mode. 110 */ 111 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 112 return __raw_readl(addr); 113 else 114 return readl_relaxed(addr); 115 } 116 117 static inline void brcm_sata_writereg(u32 val, void __iomem *addr) 118 { 119 /* See brcm_sata_readreg() comments */ 120 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 121 __raw_writel(val, addr); 122 else 123 writel_relaxed(val, addr); 124 } 125 126 static void brcm_sata_alpm_init(struct ahci_host_priv *hpriv) 127 { 128 struct brcm_ahci_priv *priv = hpriv->plat_data; 129 u32 bus_ctrl, port_ctrl, host_caps; 130 int i; 131 132 /* Enable support for ALPM */ 133 bus_ctrl = brcm_sata_readreg(priv->top_ctrl + 134 SATA_TOP_CTRL_BUS_CTRL); 135 brcm_sata_writereg(bus_ctrl | OVERRIDE_HWINIT, 136 priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL); 137 host_caps = readl(hpriv->mmio + HOST_CAP); 138 writel(host_caps | HOST_CAP_ALPM, hpriv->mmio); 139 brcm_sata_writereg(bus_ctrl, priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL); 140 141 /* 142 * Adjust timeout to allow PLL sufficient time to lock while waking 143 * up from slumber mode. 144 */ 145 for (i = 0, port_ctrl = SATA_FIRST_PORT_CTRL; 146 i < SATA_TOP_MAX_PHYS; 147 i++, port_ctrl += SATA_NEXT_PORT_CTRL_OFFSET) { 148 if (priv->port_mask & BIT(i)) 149 writel(0xff1003fc, 150 hpriv->mmio + SATA_PORT_PCTRL6(port_ctrl)); 151 } 152 } 153 154 static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port) 155 { 156 void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL + 157 (port * SATA_TOP_CTRL_PHY_OFFS); 158 void __iomem *p; 159 u32 reg; 160 161 if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE) 162 return; 163 164 /* clear PHY_DEFAULT_POWER_STATE */ 165 p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1; 166 reg = brcm_sata_readreg(p); 167 reg &= ~SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE; 168 brcm_sata_writereg(reg, p); 169 170 /* reset the PHY digital logic */ 171 p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2; 172 reg = brcm_sata_readreg(p); 173 reg &= ~(SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB | 174 SATA_TOP_CTRL_2_SW_RST_RX); 175 reg |= SATA_TOP_CTRL_2_SW_RST_TX; 176 brcm_sata_writereg(reg, p); 177 reg = brcm_sata_readreg(p); 178 reg |= SATA_TOP_CTRL_2_PHY_GLOBAL_RESET; 179 brcm_sata_writereg(reg, p); 180 reg = brcm_sata_readreg(p); 181 reg &= ~SATA_TOP_CTRL_2_PHY_GLOBAL_RESET; 182 brcm_sata_writereg(reg, p); 183 (void)brcm_sata_readreg(p); 184 } 185 186 static void brcm_sata_phy_disable(struct brcm_ahci_priv *priv, int port) 187 { 188 void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL + 189 (port * SATA_TOP_CTRL_PHY_OFFS); 190 void __iomem *p; 191 u32 reg; 192 193 if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE) 194 return; 195 196 /* power-off the PHY digital logic */ 197 p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2; 198 reg = brcm_sata_readreg(p); 199 reg |= (SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB | 200 SATA_TOP_CTRL_2_SW_RST_RX | SATA_TOP_CTRL_2_SW_RST_TX | 201 SATA_TOP_CTRL_2_PHY_GLOBAL_RESET); 202 brcm_sata_writereg(reg, p); 203 204 /* set PHY_DEFAULT_POWER_STATE */ 205 p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1; 206 reg = brcm_sata_readreg(p); 207 reg |= SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE; 208 brcm_sata_writereg(reg, p); 209 } 210 211 static void brcm_sata_phys_enable(struct brcm_ahci_priv *priv) 212 { 213 int i; 214 215 for (i = 0; i < SATA_TOP_MAX_PHYS; i++) 216 if (priv->port_mask & BIT(i)) 217 brcm_sata_phy_enable(priv, i); 218 } 219 220 static void brcm_sata_phys_disable(struct brcm_ahci_priv *priv) 221 { 222 int i; 223 224 for (i = 0; i < SATA_TOP_MAX_PHYS; i++) 225 if (priv->port_mask & BIT(i)) 226 brcm_sata_phy_disable(priv, i); 227 } 228 229 static u32 brcm_ahci_get_portmask(struct platform_device *pdev, 230 struct brcm_ahci_priv *priv) 231 { 232 void __iomem *ahci; 233 struct resource *res; 234 u32 impl; 235 236 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ahci"); 237 ahci = devm_ioremap_resource(&pdev->dev, res); 238 if (IS_ERR(ahci)) 239 return 0; 240 241 impl = readl(ahci + HOST_PORTS_IMPL); 242 243 if (fls(impl) > SATA_TOP_MAX_PHYS) 244 dev_warn(priv->dev, "warning: more ports than PHYs (%#x)\n", 245 impl); 246 else if (!impl) 247 dev_info(priv->dev, "no ports found\n"); 248 249 devm_iounmap(&pdev->dev, ahci); 250 devm_release_mem_region(&pdev->dev, res->start, resource_size(res)); 251 252 return impl; 253 } 254 255 static void brcm_sata_init(struct brcm_ahci_priv *priv) 256 { 257 void __iomem *ctrl = priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL; 258 259 /* Configure endianness */ 260 if (priv->version == BRCM_SATA_NSP) { 261 u32 data = brcm_sata_readreg(ctrl); 262 263 data &= ~((0x03 << DMADATA_ENDIAN_SHIFT) | 264 (0x03 << DMADESC_ENDIAN_SHIFT)); 265 data |= (0x02 << DMADATA_ENDIAN_SHIFT) | 266 (0x02 << DMADESC_ENDIAN_SHIFT); 267 brcm_sata_writereg(data, ctrl); 268 } else 269 brcm_sata_writereg(BUS_CTRL_ENDIAN_CONF, ctrl); 270 } 271 272 #ifdef CONFIG_PM_SLEEP 273 static int brcm_ahci_suspend(struct device *dev) 274 { 275 struct ata_host *host = dev_get_drvdata(dev); 276 struct ahci_host_priv *hpriv = host->private_data; 277 struct brcm_ahci_priv *priv = hpriv->plat_data; 278 int ret; 279 280 ret = ahci_platform_suspend(dev); 281 brcm_sata_phys_disable(priv); 282 return ret; 283 } 284 285 static int brcm_ahci_resume(struct device *dev) 286 { 287 struct ata_host *host = dev_get_drvdata(dev); 288 struct ahci_host_priv *hpriv = host->private_data; 289 struct brcm_ahci_priv *priv = hpriv->plat_data; 290 291 brcm_sata_init(priv); 292 brcm_sata_phys_enable(priv); 293 brcm_sata_alpm_init(hpriv); 294 return ahci_platform_resume(dev); 295 } 296 #endif 297 298 static struct scsi_host_template ahci_platform_sht = { 299 AHCI_SHT(DRV_NAME), 300 }; 301 302 static const struct of_device_id ahci_of_match[] = { 303 {.compatible = "brcm,bcm7425-ahci", .data = (void *)BRCM_SATA_BCM7425}, 304 {.compatible = "brcm,bcm7445-ahci", .data = (void *)BRCM_SATA_BCM7445}, 305 {.compatible = "brcm,bcm-nsp-ahci", .data = (void *)BRCM_SATA_NSP}, 306 {}, 307 }; 308 MODULE_DEVICE_TABLE(of, ahci_of_match); 309 310 static int brcm_ahci_probe(struct platform_device *pdev) 311 { 312 const struct of_device_id *of_id; 313 struct device *dev = &pdev->dev; 314 struct brcm_ahci_priv *priv; 315 struct ahci_host_priv *hpriv; 316 struct resource *res; 317 int ret; 318 319 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 320 if (!priv) 321 return -ENOMEM; 322 323 of_id = of_match_node(ahci_of_match, pdev->dev.of_node); 324 if (!of_id) 325 return -ENODEV; 326 327 priv->version = (enum brcm_ahci_version)of_id->data; 328 priv->dev = dev; 329 330 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "top-ctrl"); 331 priv->top_ctrl = devm_ioremap_resource(dev, res); 332 if (IS_ERR(priv->top_ctrl)) 333 return PTR_ERR(priv->top_ctrl); 334 335 if ((priv->version == BRCM_SATA_BCM7425) || 336 (priv->version == BRCM_SATA_NSP)) { 337 priv->quirks |= BRCM_AHCI_QUIRK_NO_NCQ; 338 priv->quirks |= BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE; 339 } 340 341 brcm_sata_init(priv); 342 343 priv->port_mask = brcm_ahci_get_portmask(pdev, priv); 344 if (!priv->port_mask) 345 return -ENODEV; 346 347 brcm_sata_phys_enable(priv); 348 349 hpriv = ahci_platform_get_resources(pdev); 350 if (IS_ERR(hpriv)) 351 return PTR_ERR(hpriv); 352 hpriv->plat_data = priv; 353 hpriv->flags = AHCI_HFLAG_WAKE_BEFORE_STOP; 354 355 brcm_sata_alpm_init(hpriv); 356 357 ret = ahci_platform_enable_resources(hpriv); 358 if (ret) 359 return ret; 360 361 if (priv->quirks & BRCM_AHCI_QUIRK_NO_NCQ) 362 hpriv->flags |= AHCI_HFLAG_NO_NCQ; 363 364 ret = ahci_platform_init_host(pdev, hpriv, &ahci_brcm_port_info, 365 &ahci_platform_sht); 366 if (ret) 367 return ret; 368 369 dev_info(dev, "Broadcom AHCI SATA3 registered\n"); 370 371 return 0; 372 } 373 374 static int brcm_ahci_remove(struct platform_device *pdev) 375 { 376 struct ata_host *host = dev_get_drvdata(&pdev->dev); 377 struct ahci_host_priv *hpriv = host->private_data; 378 struct brcm_ahci_priv *priv = hpriv->plat_data; 379 int ret; 380 381 ret = ata_platform_remove_one(pdev); 382 if (ret) 383 return ret; 384 385 brcm_sata_phys_disable(priv); 386 387 return 0; 388 } 389 390 static SIMPLE_DEV_PM_OPS(ahci_brcm_pm_ops, brcm_ahci_suspend, brcm_ahci_resume); 391 392 static struct platform_driver brcm_ahci_driver = { 393 .probe = brcm_ahci_probe, 394 .remove = brcm_ahci_remove, 395 .driver = { 396 .name = DRV_NAME, 397 .of_match_table = ahci_of_match, 398 .pm = &ahci_brcm_pm_ops, 399 }, 400 }; 401 module_platform_driver(brcm_ahci_driver); 402 403 MODULE_DESCRIPTION("Broadcom SATA3 AHCI Controller Driver"); 404 MODULE_AUTHOR("Brian Norris"); 405 MODULE_LICENSE("GPL"); 406 MODULE_ALIAS("platform:sata-brcmstb"); 407