1 /* 2 * ahci.h - Common AHCI SATA definitions and declarations 3 * 4 * Maintained by: Tejun Heo <tj@kernel.org> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2004-2005 Red Hat, Inc. 9 * 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; see the file COPYING. If not, write to 23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * 26 * libata documentation is available via 'make {ps|pdf}docs', 27 * as Documentation/DocBook/libata.* 28 * 29 * AHCI hardware documentation: 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 32 * 33 */ 34 35 #ifndef _AHCI_H 36 #define _AHCI_H 37 38 #include <linux/pci.h> 39 #include <linux/clk.h> 40 #include <linux/libata.h> 41 #include <linux/phy/phy.h> 42 #include <linux/regulator/consumer.h> 43 44 /* Enclosure Management Control */ 45 #define EM_CTRL_MSG_TYPE 0x000f0000 46 47 /* Enclosure Management LED Message Type */ 48 #define EM_MSG_LED_HBA_PORT 0x0000000f 49 #define EM_MSG_LED_PMP_SLOT 0x0000ff00 50 #define EM_MSG_LED_VALUE 0xffff0000 51 #define EM_MSG_LED_VALUE_ACTIVITY 0x00070000 52 #define EM_MSG_LED_VALUE_OFF 0xfff80000 53 #define EM_MSG_LED_VALUE_ON 0x00010000 54 55 enum { 56 AHCI_MAX_PORTS = 32, 57 AHCI_MAX_CLKS = 5, 58 AHCI_MAX_SG = 168, /* hardware max is 64K */ 59 AHCI_DMA_BOUNDARY = 0xffffffff, 60 AHCI_MAX_CMDS = 32, 61 AHCI_CMD_SZ = 32, 62 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, 63 AHCI_RX_FIS_SZ = 256, 64 AHCI_CMD_TBL_CDB = 0x40, 65 AHCI_CMD_TBL_HDR_SZ = 0x80, 66 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), 67 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, 68 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + 69 AHCI_RX_FIS_SZ, 70 AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ + 71 AHCI_CMD_TBL_AR_SZ + 72 (AHCI_RX_FIS_SZ * 16), 73 AHCI_IRQ_ON_SG = (1 << 31), 74 AHCI_CMD_ATAPI = (1 << 5), 75 AHCI_CMD_WRITE = (1 << 6), 76 AHCI_CMD_PREFETCH = (1 << 7), 77 AHCI_CMD_RESET = (1 << 8), 78 AHCI_CMD_CLR_BUSY = (1 << 10), 79 80 RX_FIS_PIO_SETUP = 0x20, /* offset of PIO Setup FIS data */ 81 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ 82 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */ 83 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ 84 85 /* global controller registers */ 86 HOST_CAP = 0x00, /* host capabilities */ 87 HOST_CTL = 0x04, /* global host control */ 88 HOST_IRQ_STAT = 0x08, /* interrupt status */ 89 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ 90 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ 91 HOST_EM_LOC = 0x1c, /* Enclosure Management location */ 92 HOST_EM_CTL = 0x20, /* Enclosure Management Control */ 93 HOST_CAP2 = 0x24, /* host capabilities, extended */ 94 95 /* HOST_CTL bits */ 96 HOST_RESET = (1 << 0), /* reset controller; self-clear */ 97 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ 98 HOST_MRSM = (1 << 2), /* MSI Revert to Single Message */ 99 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ 100 101 /* HOST_CAP bits */ 102 HOST_CAP_SXS = (1 << 5), /* Supports External SATA */ 103 HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */ 104 HOST_CAP_CCC = (1 << 7), /* Command Completion Coalescing */ 105 HOST_CAP_PART = (1 << 13), /* Partial state capable */ 106 HOST_CAP_SSC = (1 << 14), /* Slumber state capable */ 107 HOST_CAP_PIO_MULTI = (1 << 15), /* PIO multiple DRQ support */ 108 HOST_CAP_FBS = (1 << 16), /* FIS-based switching support */ 109 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */ 110 HOST_CAP_ONLY = (1 << 18), /* Supports AHCI mode only */ 111 HOST_CAP_CLO = (1 << 24), /* Command List Override support */ 112 HOST_CAP_LED = (1 << 25), /* Supports activity LED */ 113 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */ 114 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ 115 HOST_CAP_MPS = (1 << 28), /* Mechanical presence switch */ 116 HOST_CAP_SNTF = (1 << 29), /* SNotification register */ 117 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ 118 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ 119 120 /* HOST_CAP2 bits */ 121 HOST_CAP2_BOH = (1 << 0), /* BIOS/OS handoff supported */ 122 HOST_CAP2_NVMHCI = (1 << 1), /* NVMHCI supported */ 123 HOST_CAP2_APST = (1 << 2), /* Automatic partial to slumber */ 124 HOST_CAP2_SDS = (1 << 3), /* Support device sleep */ 125 HOST_CAP2_SADM = (1 << 4), /* Support aggressive DevSlp */ 126 HOST_CAP2_DESO = (1 << 5), /* DevSlp from slumber only */ 127 128 /* registers for each SATA port */ 129 PORT_LST_ADDR = 0x00, /* command list DMA addr */ 130 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ 131 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ 132 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ 133 PORT_IRQ_STAT = 0x10, /* interrupt status */ 134 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ 135 PORT_CMD = 0x18, /* port command */ 136 PORT_TFDATA = 0x20, /* taskfile data */ 137 PORT_SIG = 0x24, /* device TF signature */ 138 PORT_CMD_ISSUE = 0x38, /* command issue */ 139 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ 140 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ 141 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ 142 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ 143 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */ 144 PORT_FBS = 0x40, /* FIS-based Switching */ 145 PORT_DEVSLP = 0x44, /* device sleep */ 146 147 /* PORT_IRQ_{STAT,MASK} bits */ 148 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ 149 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ 150 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ 151 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ 152 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ 153 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ 154 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ 155 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ 156 157 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ 158 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ 159 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ 160 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ 161 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ 162 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ 163 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ 164 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ 165 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ 166 167 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | 168 PORT_IRQ_IF_ERR | 169 PORT_IRQ_CONNECT | 170 PORT_IRQ_PHYRDY | 171 PORT_IRQ_UNK_FIS | 172 PORT_IRQ_BAD_PMP, 173 PORT_IRQ_ERROR = PORT_IRQ_FREEZE | 174 PORT_IRQ_TF_ERR | 175 PORT_IRQ_HBUS_DATA_ERR, 176 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | 177 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | 178 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, 179 180 /* PORT_CMD bits */ 181 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */ 182 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */ 183 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ 184 PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */ 185 PORT_CMD_ESP = (1 << 21), /* External Sata Port */ 186 PORT_CMD_HPCP = (1 << 18), /* HotPlug Capable Port */ 187 PORT_CMD_PMP = (1 << 17), /* PMP attached */ 188 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ 189 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ 190 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ 191 PORT_CMD_CLO = (1 << 3), /* Command list override */ 192 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ 193 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ 194 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ 195 196 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ 197 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ 198 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ 199 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ 200 201 /* PORT_FBS bits */ 202 PORT_FBS_DWE_OFFSET = 16, /* FBS device with error offset */ 203 PORT_FBS_ADO_OFFSET = 12, /* FBS active dev optimization offset */ 204 PORT_FBS_DEV_OFFSET = 8, /* FBS device to issue offset */ 205 PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET), /* FBS.DEV */ 206 PORT_FBS_SDE = (1 << 2), /* FBS single device error */ 207 PORT_FBS_DEC = (1 << 1), /* FBS device error clear */ 208 PORT_FBS_EN = (1 << 0), /* Enable FBS */ 209 210 /* PORT_DEVSLP bits */ 211 PORT_DEVSLP_DM_OFFSET = 25, /* DITO multiplier offset */ 212 PORT_DEVSLP_DM_MASK = (0xf << 25), /* DITO multiplier mask */ 213 PORT_DEVSLP_DITO_OFFSET = 15, /* DITO offset */ 214 PORT_DEVSLP_MDAT_OFFSET = 10, /* Minimum assertion time */ 215 PORT_DEVSLP_DETO_OFFSET = 2, /* DevSlp exit timeout */ 216 PORT_DEVSLP_DSP = (1 << 1), /* DevSlp present */ 217 PORT_DEVSLP_ADSE = (1 << 0), /* Aggressive DevSlp enable */ 218 219 /* hpriv->flags bits */ 220 221 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags) 222 223 AHCI_HFLAG_NO_NCQ = (1 << 0), 224 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */ 225 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */ 226 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */ 227 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */ 228 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */ 229 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */ 230 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */ 231 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */ 232 AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */ 233 AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as 234 link offline */ 235 AHCI_HFLAG_NO_SNTF = (1 << 12), /* no sntf */ 236 AHCI_HFLAG_NO_FPDMA_AA = (1 << 13), /* no FPDMA AA */ 237 AHCI_HFLAG_YES_FBS = (1 << 14), /* force FBS cap on */ 238 AHCI_HFLAG_DELAY_ENGINE = (1 << 15), /* do not start engine on 239 port start (wait until 240 error-handling stage) */ 241 AHCI_HFLAG_NO_DEVSLP = (1 << 17), /* no device sleep */ 242 AHCI_HFLAG_NO_FBS = (1 << 18), /* no FBS */ 243 AHCI_HFLAG_EDGE_IRQ = (1 << 19), /* HOST_IRQ_STAT behaves as 244 Edge Triggered */ 245 #ifdef CONFIG_PCI_MSI 246 AHCI_HFLAG_MULTI_MSI = (1 << 20), /* multiple PCI MSIs */ 247 AHCI_HFLAG_MULTI_MSIX = (1 << 21), /* per-port MSI-X */ 248 #else 249 /* compile out MSI infrastructure */ 250 AHCI_HFLAG_MULTI_MSI = 0, 251 AHCI_HFLAG_MULTI_MSIX = 0, 252 #endif 253 254 /* ap->flags bits */ 255 256 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA | 257 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN, 258 259 ICH_MAP = 0x90, /* ICH MAP register */ 260 261 /* em constants */ 262 EM_MAX_SLOTS = 8, 263 EM_MAX_RETRY = 5, 264 265 /* em_ctl bits */ 266 EM_CTL_RST = (1 << 9), /* Reset */ 267 EM_CTL_TM = (1 << 8), /* Transmit Message */ 268 EM_CTL_MR = (1 << 0), /* Message Received */ 269 EM_CTL_ALHD = (1 << 26), /* Activity LED */ 270 EM_CTL_XMT = (1 << 25), /* Transmit Only */ 271 EM_CTL_SMB = (1 << 24), /* Single Message Buffer */ 272 EM_CTL_SGPIO = (1 << 19), /* SGPIO messages supported */ 273 EM_CTL_SES = (1 << 18), /* SES-2 messages supported */ 274 EM_CTL_SAFTE = (1 << 17), /* SAF-TE messages supported */ 275 EM_CTL_LED = (1 << 16), /* LED messages supported */ 276 277 /* em message type */ 278 EM_MSG_TYPE_LED = (1 << 0), /* LED */ 279 EM_MSG_TYPE_SAFTE = (1 << 1), /* SAF-TE */ 280 EM_MSG_TYPE_SES2 = (1 << 2), /* SES-2 */ 281 EM_MSG_TYPE_SGPIO = (1 << 3), /* SGPIO */ 282 }; 283 284 struct ahci_cmd_hdr { 285 __le32 opts; 286 __le32 status; 287 __le32 tbl_addr; 288 __le32 tbl_addr_hi; 289 __le32 reserved[4]; 290 }; 291 292 struct ahci_sg { 293 __le32 addr; 294 __le32 addr_hi; 295 __le32 reserved; 296 __le32 flags_size; 297 }; 298 299 struct ahci_em_priv { 300 enum sw_activity blink_policy; 301 struct timer_list timer; 302 unsigned long saved_activity; 303 unsigned long activity; 304 unsigned long led_state; 305 }; 306 307 struct ahci_port_priv { 308 struct ata_link *active_link; 309 struct ahci_cmd_hdr *cmd_slot; 310 dma_addr_t cmd_slot_dma; 311 void *cmd_tbl; 312 dma_addr_t cmd_tbl_dma; 313 void *rx_fis; 314 dma_addr_t rx_fis_dma; 315 /* for NCQ spurious interrupt analysis */ 316 unsigned int ncq_saw_d2h:1; 317 unsigned int ncq_saw_dmas:1; 318 unsigned int ncq_saw_sdb:1; 319 spinlock_t lock; /* protects parent ata_port */ 320 u32 intr_mask; /* interrupts to enable */ 321 bool fbs_supported; /* set iff FBS is supported */ 322 bool fbs_enabled; /* set iff FBS is enabled */ 323 int fbs_last_dev; /* save FBS.DEV of last FIS */ 324 /* enclosure management info per PM slot */ 325 struct ahci_em_priv em_priv[EM_MAX_SLOTS]; 326 char *irq_desc; /* desc in /proc/interrupts */ 327 }; 328 329 struct ahci_host_priv { 330 /* Input fields */ 331 unsigned int flags; /* AHCI_HFLAG_* */ 332 u32 force_port_map; /* force port map */ 333 u32 mask_port_map; /* mask out particular bits */ 334 335 void __iomem * mmio; /* bus-independent mem map */ 336 u32 cap; /* cap to use */ 337 u32 cap2; /* cap2 to use */ 338 u32 port_map; /* port map to use */ 339 u32 saved_cap; /* saved initial cap */ 340 u32 saved_cap2; /* saved initial cap2 */ 341 u32 saved_port_map; /* saved initial port_map */ 342 u32 em_loc; /* enclosure management location */ 343 u32 em_buf_sz; /* EM buffer size in byte */ 344 u32 em_msg_type; /* EM message type */ 345 bool got_runtime_pm; /* Did we do pm_runtime_get? */ 346 struct clk *clks[AHCI_MAX_CLKS]; /* Optional */ 347 struct regulator **target_pwrs; /* Optional */ 348 /* 349 * If platform uses PHYs. There is a 1:1 relation between the port number and 350 * the PHY position in this array. 351 */ 352 struct phy **phys; 353 struct msix_entry *msix; /* Optional MSI-X support */ 354 unsigned nports; /* Number of ports */ 355 void *plat_data; /* Other platform data */ 356 unsigned int irq; /* interrupt line */ 357 /* 358 * Optional ahci_start_engine override, if not set this gets set to the 359 * default ahci_start_engine during ahci_save_initial_config, this can 360 * be overridden anytime before the host is activated. 361 */ 362 void (*start_engine)(struct ata_port *ap); 363 }; 364 365 #ifdef CONFIG_PCI_MSI 366 static inline int ahci_irq_vector(struct ahci_host_priv *hpriv, int port) 367 { 368 if (hpriv->flags & AHCI_HFLAG_MULTI_MSIX) 369 return hpriv->msix[port].vector; 370 else 371 return hpriv->irq + port; 372 } 373 #else 374 static inline int ahci_irq_vector(struct ahci_host_priv *hpriv, int port) 375 { 376 return hpriv->irq; 377 } 378 #endif 379 380 extern int ahci_ignore_sss; 381 382 extern struct device_attribute *ahci_shost_attrs[]; 383 extern struct device_attribute *ahci_sdev_attrs[]; 384 385 /* 386 * This must be instantiated by the edge drivers. Read the comments 387 * for ATA_BASE_SHT 388 */ 389 #define AHCI_SHT(drv_name) \ 390 ATA_NCQ_SHT(drv_name), \ 391 .can_queue = AHCI_MAX_CMDS - 1, \ 392 .sg_tablesize = AHCI_MAX_SG, \ 393 .dma_boundary = AHCI_DMA_BOUNDARY, \ 394 .shost_attrs = ahci_shost_attrs, \ 395 .sdev_attrs = ahci_sdev_attrs 396 397 extern struct ata_port_operations ahci_ops; 398 extern struct ata_port_operations ahci_platform_ops; 399 extern struct ata_port_operations ahci_pmp_retry_srst_ops; 400 401 unsigned int ahci_dev_classify(struct ata_port *ap); 402 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 403 u32 opts); 404 void ahci_save_initial_config(struct device *dev, 405 struct ahci_host_priv *hpriv); 406 void ahci_init_controller(struct ata_host *host); 407 int ahci_reset_controller(struct ata_host *host); 408 409 int ahci_do_softreset(struct ata_link *link, unsigned int *class, 410 int pmp, unsigned long deadline, 411 int (*check_ready)(struct ata_link *link)); 412 413 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); 414 int ahci_stop_engine(struct ata_port *ap); 415 void ahci_start_fis_rx(struct ata_port *ap); 416 void ahci_start_engine(struct ata_port *ap); 417 int ahci_check_ready(struct ata_link *link); 418 int ahci_kick_engine(struct ata_port *ap); 419 int ahci_port_resume(struct ata_port *ap); 420 void ahci_set_em_messages(struct ahci_host_priv *hpriv, 421 struct ata_port_info *pi); 422 int ahci_reset_em(struct ata_host *host); 423 void ahci_print_info(struct ata_host *host, const char *scc_s); 424 int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht); 425 void ahci_error_handler(struct ata_port *ap); 426 427 static inline void __iomem *__ahci_port_base(struct ata_host *host, 428 unsigned int port_no) 429 { 430 struct ahci_host_priv *hpriv = host->private_data; 431 void __iomem *mmio = hpriv->mmio; 432 433 return mmio + 0x100 + (port_no * 0x80); 434 } 435 436 static inline void __iomem *ahci_port_base(struct ata_port *ap) 437 { 438 return __ahci_port_base(ap->host, ap->port_no); 439 } 440 441 static inline int ahci_nr_ports(u32 cap) 442 { 443 return (cap & 0x1f) + 1; 444 } 445 446 #endif /* _AHCI_H */ 447