1 /* 2 * ahci.h - Common AHCI SATA definitions and declarations 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2004-2005 Red Hat, Inc. 9 * 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; see the file COPYING. If not, write to 23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * 26 * libata documentation is available via 'make {ps|pdf}docs', 27 * as Documentation/DocBook/libata.* 28 * 29 * AHCI hardware documentation: 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 32 * 33 */ 34 35 #ifndef _AHCI_H 36 #define _AHCI_H 37 38 #include <linux/clk.h> 39 #include <linux/libata.h> 40 41 /* Enclosure Management Control */ 42 #define EM_CTRL_MSG_TYPE 0x000f0000 43 44 /* Enclosure Management LED Message Type */ 45 #define EM_MSG_LED_HBA_PORT 0x0000000f 46 #define EM_MSG_LED_PMP_SLOT 0x0000ff00 47 #define EM_MSG_LED_VALUE 0xffff0000 48 #define EM_MSG_LED_VALUE_ACTIVITY 0x00070000 49 #define EM_MSG_LED_VALUE_OFF 0xfff80000 50 #define EM_MSG_LED_VALUE_ON 0x00010000 51 52 enum { 53 AHCI_MAX_PORTS = 32, 54 AHCI_MAX_SG = 168, /* hardware max is 64K */ 55 AHCI_DMA_BOUNDARY = 0xffffffff, 56 AHCI_MAX_CMDS = 32, 57 AHCI_CMD_SZ = 32, 58 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, 59 AHCI_RX_FIS_SZ = 256, 60 AHCI_CMD_TBL_CDB = 0x40, 61 AHCI_CMD_TBL_HDR_SZ = 0x80, 62 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), 63 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, 64 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + 65 AHCI_RX_FIS_SZ, 66 AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ + 67 AHCI_CMD_TBL_AR_SZ + 68 (AHCI_RX_FIS_SZ * 16), 69 AHCI_IRQ_ON_SG = (1 << 31), 70 AHCI_CMD_ATAPI = (1 << 5), 71 AHCI_CMD_WRITE = (1 << 6), 72 AHCI_CMD_PREFETCH = (1 << 7), 73 AHCI_CMD_RESET = (1 << 8), 74 AHCI_CMD_CLR_BUSY = (1 << 10), 75 76 RX_FIS_PIO_SETUP = 0x20, /* offset of PIO Setup FIS data */ 77 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ 78 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */ 79 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ 80 81 /* global controller registers */ 82 HOST_CAP = 0x00, /* host capabilities */ 83 HOST_CTL = 0x04, /* global host control */ 84 HOST_IRQ_STAT = 0x08, /* interrupt status */ 85 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ 86 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ 87 HOST_EM_LOC = 0x1c, /* Enclosure Management location */ 88 HOST_EM_CTL = 0x20, /* Enclosure Management Control */ 89 HOST_CAP2 = 0x24, /* host capabilities, extended */ 90 91 /* HOST_CTL bits */ 92 HOST_RESET = (1 << 0), /* reset controller; self-clear */ 93 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ 94 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ 95 96 /* HOST_CAP bits */ 97 HOST_CAP_SXS = (1 << 5), /* Supports External SATA */ 98 HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */ 99 HOST_CAP_CCC = (1 << 7), /* Command Completion Coalescing */ 100 HOST_CAP_PART = (1 << 13), /* Partial state capable */ 101 HOST_CAP_SSC = (1 << 14), /* Slumber state capable */ 102 HOST_CAP_PIO_MULTI = (1 << 15), /* PIO multiple DRQ support */ 103 HOST_CAP_FBS = (1 << 16), /* FIS-based switching support */ 104 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */ 105 HOST_CAP_ONLY = (1 << 18), /* Supports AHCI mode only */ 106 HOST_CAP_CLO = (1 << 24), /* Command List Override support */ 107 HOST_CAP_LED = (1 << 25), /* Supports activity LED */ 108 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */ 109 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ 110 HOST_CAP_MPS = (1 << 28), /* Mechanical presence switch */ 111 HOST_CAP_SNTF = (1 << 29), /* SNotification register */ 112 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ 113 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ 114 115 /* HOST_CAP2 bits */ 116 HOST_CAP2_BOH = (1 << 0), /* BIOS/OS handoff supported */ 117 HOST_CAP2_NVMHCI = (1 << 1), /* NVMHCI supported */ 118 HOST_CAP2_APST = (1 << 2), /* Automatic partial to slumber */ 119 HOST_CAP2_SDS = (1 << 3), /* Support device sleep */ 120 HOST_CAP2_SADM = (1 << 4), /* Support aggressive DevSlp */ 121 HOST_CAP2_DESO = (1 << 5), /* DevSlp from slumber only */ 122 123 /* registers for each SATA port */ 124 PORT_LST_ADDR = 0x00, /* command list DMA addr */ 125 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ 126 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ 127 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ 128 PORT_IRQ_STAT = 0x10, /* interrupt status */ 129 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ 130 PORT_CMD = 0x18, /* port command */ 131 PORT_TFDATA = 0x20, /* taskfile data */ 132 PORT_SIG = 0x24, /* device TF signature */ 133 PORT_CMD_ISSUE = 0x38, /* command issue */ 134 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ 135 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ 136 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ 137 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ 138 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */ 139 PORT_FBS = 0x40, /* FIS-based Switching */ 140 PORT_DEVSLP = 0x44, /* device sleep */ 141 142 /* PORT_IRQ_{STAT,MASK} bits */ 143 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ 144 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ 145 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ 146 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ 147 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ 148 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ 149 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ 150 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ 151 152 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ 153 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ 154 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ 155 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ 156 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ 157 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ 158 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ 159 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ 160 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ 161 162 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | 163 PORT_IRQ_IF_ERR | 164 PORT_IRQ_CONNECT | 165 PORT_IRQ_PHYRDY | 166 PORT_IRQ_UNK_FIS | 167 PORT_IRQ_BAD_PMP, 168 PORT_IRQ_ERROR = PORT_IRQ_FREEZE | 169 PORT_IRQ_TF_ERR | 170 PORT_IRQ_HBUS_DATA_ERR, 171 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | 172 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | 173 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, 174 175 /* PORT_CMD bits */ 176 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */ 177 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */ 178 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ 179 PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */ 180 PORT_CMD_PMP = (1 << 17), /* PMP attached */ 181 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ 182 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ 183 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ 184 PORT_CMD_CLO = (1 << 3), /* Command list override */ 185 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ 186 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ 187 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ 188 189 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ 190 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ 191 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ 192 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ 193 194 /* PORT_FBS bits */ 195 PORT_FBS_DWE_OFFSET = 16, /* FBS device with error offset */ 196 PORT_FBS_ADO_OFFSET = 12, /* FBS active dev optimization offset */ 197 PORT_FBS_DEV_OFFSET = 8, /* FBS device to issue offset */ 198 PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET), /* FBS.DEV */ 199 PORT_FBS_SDE = (1 << 2), /* FBS single device error */ 200 PORT_FBS_DEC = (1 << 1), /* FBS device error clear */ 201 PORT_FBS_EN = (1 << 0), /* Enable FBS */ 202 203 /* PORT_DEVSLP bits */ 204 PORT_DEVSLP_DM_OFFSET = 25, /* DITO multiplier offset */ 205 PORT_DEVSLP_DM_MASK = (0xf << 25), /* DITO multiplier mask */ 206 PORT_DEVSLP_DITO_OFFSET = 15, /* DITO offset */ 207 PORT_DEVSLP_MDAT_OFFSET = 10, /* Minimum assertion time */ 208 PORT_DEVSLP_DETO_OFFSET = 2, /* DevSlp exit timeout */ 209 PORT_DEVSLP_DSP = (1 << 1), /* DevSlp present */ 210 PORT_DEVSLP_ADSE = (1 << 0), /* Aggressive DevSlp enable */ 211 212 /* hpriv->flags bits */ 213 214 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags) 215 216 AHCI_HFLAG_NO_NCQ = (1 << 0), 217 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */ 218 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */ 219 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */ 220 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */ 221 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */ 222 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */ 223 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */ 224 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */ 225 AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */ 226 AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as 227 link offline */ 228 AHCI_HFLAG_NO_SNTF = (1 << 12), /* no sntf */ 229 AHCI_HFLAG_NO_FPDMA_AA = (1 << 13), /* no FPDMA AA */ 230 AHCI_HFLAG_YES_FBS = (1 << 14), /* force FBS cap on */ 231 AHCI_HFLAG_DELAY_ENGINE = (1 << 15), /* do not start engine on 232 port start (wait until 233 error-handling stage) */ 234 AHCI_HFLAG_MULTI_MSI = (1 << 16), /* multiple PCI MSIs */ 235 236 /* ap->flags bits */ 237 238 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA | 239 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN, 240 241 ICH_MAP = 0x90, /* ICH MAP register */ 242 243 /* em constants */ 244 EM_MAX_SLOTS = 8, 245 EM_MAX_RETRY = 5, 246 247 /* em_ctl bits */ 248 EM_CTL_RST = (1 << 9), /* Reset */ 249 EM_CTL_TM = (1 << 8), /* Transmit Message */ 250 EM_CTL_MR = (1 << 0), /* Message Received */ 251 EM_CTL_ALHD = (1 << 26), /* Activity LED */ 252 EM_CTL_XMT = (1 << 25), /* Transmit Only */ 253 EM_CTL_SMB = (1 << 24), /* Single Message Buffer */ 254 EM_CTL_SGPIO = (1 << 19), /* SGPIO messages supported */ 255 EM_CTL_SES = (1 << 18), /* SES-2 messages supported */ 256 EM_CTL_SAFTE = (1 << 17), /* SAF-TE messages supported */ 257 EM_CTL_LED = (1 << 16), /* LED messages supported */ 258 259 /* em message type */ 260 EM_MSG_TYPE_LED = (1 << 0), /* LED */ 261 EM_MSG_TYPE_SAFTE = (1 << 1), /* SAF-TE */ 262 EM_MSG_TYPE_SES2 = (1 << 2), /* SES-2 */ 263 EM_MSG_TYPE_SGPIO = (1 << 3), /* SGPIO */ 264 }; 265 266 struct ahci_cmd_hdr { 267 __le32 opts; 268 __le32 status; 269 __le32 tbl_addr; 270 __le32 tbl_addr_hi; 271 __le32 reserved[4]; 272 }; 273 274 struct ahci_sg { 275 __le32 addr; 276 __le32 addr_hi; 277 __le32 reserved; 278 __le32 flags_size; 279 }; 280 281 struct ahci_em_priv { 282 enum sw_activity blink_policy; 283 struct timer_list timer; 284 unsigned long saved_activity; 285 unsigned long activity; 286 unsigned long led_state; 287 }; 288 289 struct ahci_port_priv { 290 struct ata_link *active_link; 291 struct ahci_cmd_hdr *cmd_slot; 292 dma_addr_t cmd_slot_dma; 293 void *cmd_tbl; 294 dma_addr_t cmd_tbl_dma; 295 void *rx_fis; 296 dma_addr_t rx_fis_dma; 297 /* for NCQ spurious interrupt analysis */ 298 unsigned int ncq_saw_d2h:1; 299 unsigned int ncq_saw_dmas:1; 300 unsigned int ncq_saw_sdb:1; 301 u32 intr_status; /* interrupts to handle */ 302 spinlock_t lock; /* protects parent ata_port */ 303 u32 intr_mask; /* interrupts to enable */ 304 bool fbs_supported; /* set iff FBS is supported */ 305 bool fbs_enabled; /* set iff FBS is enabled */ 306 int fbs_last_dev; /* save FBS.DEV of last FIS */ 307 /* enclosure management info per PM slot */ 308 struct ahci_em_priv em_priv[EM_MAX_SLOTS]; 309 }; 310 311 struct ahci_host_priv { 312 void __iomem * mmio; /* bus-independent mem map */ 313 unsigned int flags; /* AHCI_HFLAG_* */ 314 u32 cap; /* cap to use */ 315 u32 cap2; /* cap2 to use */ 316 u32 port_map; /* port map to use */ 317 u32 saved_cap; /* saved initial cap */ 318 u32 saved_cap2; /* saved initial cap2 */ 319 u32 saved_port_map; /* saved initial port_map */ 320 u32 em_loc; /* enclosure management location */ 321 u32 em_buf_sz; /* EM buffer size in byte */ 322 u32 em_msg_type; /* EM message type */ 323 struct clk *clk; /* Only for platforms supporting clk */ 324 }; 325 326 extern int ahci_ignore_sss; 327 328 extern struct device_attribute *ahci_shost_attrs[]; 329 extern struct device_attribute *ahci_sdev_attrs[]; 330 331 #define AHCI_SHT(drv_name) \ 332 ATA_NCQ_SHT(drv_name), \ 333 .can_queue = AHCI_MAX_CMDS - 1, \ 334 .sg_tablesize = AHCI_MAX_SG, \ 335 .dma_boundary = AHCI_DMA_BOUNDARY, \ 336 .shost_attrs = ahci_shost_attrs, \ 337 .sdev_attrs = ahci_sdev_attrs 338 339 extern struct ata_port_operations ahci_ops; 340 extern struct ata_port_operations ahci_pmp_retry_srst_ops; 341 342 unsigned int ahci_dev_classify(struct ata_port *ap); 343 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 344 u32 opts); 345 void ahci_save_initial_config(struct device *dev, 346 struct ahci_host_priv *hpriv, 347 unsigned int force_port_map, 348 unsigned int mask_port_map); 349 void ahci_init_controller(struct ata_host *host); 350 int ahci_reset_controller(struct ata_host *host); 351 352 int ahci_do_softreset(struct ata_link *link, unsigned int *class, 353 int pmp, unsigned long deadline, 354 int (*check_ready)(struct ata_link *link)); 355 356 int ahci_stop_engine(struct ata_port *ap); 357 void ahci_start_engine(struct ata_port *ap); 358 int ahci_check_ready(struct ata_link *link); 359 int ahci_kick_engine(struct ata_port *ap); 360 int ahci_port_resume(struct ata_port *ap); 361 void ahci_set_em_messages(struct ahci_host_priv *hpriv, 362 struct ata_port_info *pi); 363 int ahci_reset_em(struct ata_host *host); 364 irqreturn_t ahci_interrupt(int irq, void *dev_instance); 365 irqreturn_t ahci_hw_interrupt(int irq, void *dev_instance); 366 irqreturn_t ahci_thread_fn(int irq, void *dev_instance); 367 void ahci_print_info(struct ata_host *host, const char *scc_s); 368 int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis); 369 370 static inline void __iomem *__ahci_port_base(struct ata_host *host, 371 unsigned int port_no) 372 { 373 struct ahci_host_priv *hpriv = host->private_data; 374 void __iomem *mmio = hpriv->mmio; 375 376 return mmio + 0x100 + (port_no * 0x80); 377 } 378 379 static inline void __iomem *ahci_port_base(struct ata_port *ap) 380 { 381 return __ahci_port_base(ap->host, ap->port_no); 382 } 383 384 static inline int ahci_nr_ports(u32 cap) 385 { 386 return (cap & 0x1f) + 1; 387 } 388 389 #endif /* _AHCI_H */ 390