1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ahci.c - AHCI SATA support 4 * 5 * Maintained by: Tejun Heo <tj@kernel.org> 6 * Please ALWAYS copy linux-ide@vger.kernel.org 7 * on emails. 8 * 9 * Copyright 2004-2005 Red Hat, Inc. 10 * 11 * libata documentation is available via 'make {ps|pdf}docs', 12 * as Documentation/driver-api/libata.rst 13 * 14 * AHCI hardware documentation: 15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/blkdev.h> 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/device.h> 27 #include <linux/dmi.h> 28 #include <linux/gfp.h> 29 #include <linux/msi.h> 30 #include <scsi/scsi_host.h> 31 #include <scsi/scsi_cmnd.h> 32 #include <linux/libata.h> 33 #include <linux/ahci-remap.h> 34 #include <linux/io-64-nonatomic-lo-hi.h> 35 #include "ahci.h" 36 37 #define DRV_NAME "ahci" 38 #define DRV_VERSION "3.0" 39 40 enum { 41 AHCI_PCI_BAR_STA2X11 = 0, 42 AHCI_PCI_BAR_CAVIUM = 0, 43 AHCI_PCI_BAR_LOONGSON = 0, 44 AHCI_PCI_BAR_ENMOTUS = 2, 45 AHCI_PCI_BAR_CAVIUM_GEN5 = 4, 46 AHCI_PCI_BAR_STANDARD = 5, 47 }; 48 49 enum board_ids { 50 /* board IDs by feature in alphabetical order */ 51 board_ahci, 52 board_ahci_ign_iferr, 53 board_ahci_mobile, 54 board_ahci_nomsi, 55 board_ahci_noncq, 56 board_ahci_nosntf, 57 board_ahci_yes_fbs, 58 59 /* board IDs for specific chipsets in alphabetical order */ 60 board_ahci_al, 61 board_ahci_avn, 62 board_ahci_mcp65, 63 board_ahci_mcp77, 64 board_ahci_mcp89, 65 board_ahci_mv, 66 board_ahci_sb600, 67 board_ahci_sb700, /* for SB700 and SB800 */ 68 board_ahci_vt8251, 69 70 /* 71 * board IDs for Intel chipsets that support more than 6 ports 72 * *and* end up needing the PCS quirk. 73 */ 74 board_ahci_pcs7, 75 76 /* aliases */ 77 board_ahci_mcp_linux = board_ahci_mcp65, 78 board_ahci_mcp67 = board_ahci_mcp65, 79 board_ahci_mcp73 = board_ahci_mcp65, 80 board_ahci_mcp79 = board_ahci_mcp77, 81 }; 82 83 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 84 static void ahci_remove_one(struct pci_dev *dev); 85 static void ahci_shutdown_one(struct pci_dev *dev); 86 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 87 unsigned long deadline); 88 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 89 unsigned long deadline); 90 static void ahci_mcp89_apple_enable(struct pci_dev *pdev); 91 static bool is_mcp89_apple(struct pci_dev *pdev); 92 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 93 unsigned long deadline); 94 #ifdef CONFIG_PM 95 static int ahci_pci_device_runtime_suspend(struct device *dev); 96 static int ahci_pci_device_runtime_resume(struct device *dev); 97 #ifdef CONFIG_PM_SLEEP 98 static int ahci_pci_device_suspend(struct device *dev); 99 static int ahci_pci_device_resume(struct device *dev); 100 #endif 101 #endif /* CONFIG_PM */ 102 103 static struct scsi_host_template ahci_sht = { 104 AHCI_SHT("ahci"), 105 }; 106 107 static struct ata_port_operations ahci_vt8251_ops = { 108 .inherits = &ahci_ops, 109 .hardreset = ahci_vt8251_hardreset, 110 }; 111 112 static struct ata_port_operations ahci_p5wdh_ops = { 113 .inherits = &ahci_ops, 114 .hardreset = ahci_p5wdh_hardreset, 115 }; 116 117 static struct ata_port_operations ahci_avn_ops = { 118 .inherits = &ahci_ops, 119 .hardreset = ahci_avn_hardreset, 120 }; 121 122 static const struct ata_port_info ahci_port_info[] = { 123 /* by features */ 124 [board_ahci] = { 125 .flags = AHCI_FLAG_COMMON, 126 .pio_mask = ATA_PIO4, 127 .udma_mask = ATA_UDMA6, 128 .port_ops = &ahci_ops, 129 }, 130 [board_ahci_ign_iferr] = { 131 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), 132 .flags = AHCI_FLAG_COMMON, 133 .pio_mask = ATA_PIO4, 134 .udma_mask = ATA_UDMA6, 135 .port_ops = &ahci_ops, 136 }, 137 [board_ahci_mobile] = { 138 AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE), 139 .flags = AHCI_FLAG_COMMON, 140 .pio_mask = ATA_PIO4, 141 .udma_mask = ATA_UDMA6, 142 .port_ops = &ahci_ops, 143 }, 144 [board_ahci_nomsi] = { 145 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI), 146 .flags = AHCI_FLAG_COMMON, 147 .pio_mask = ATA_PIO4, 148 .udma_mask = ATA_UDMA6, 149 .port_ops = &ahci_ops, 150 }, 151 [board_ahci_noncq] = { 152 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ), 153 .flags = AHCI_FLAG_COMMON, 154 .pio_mask = ATA_PIO4, 155 .udma_mask = ATA_UDMA6, 156 .port_ops = &ahci_ops, 157 }, 158 [board_ahci_nosntf] = { 159 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF), 160 .flags = AHCI_FLAG_COMMON, 161 .pio_mask = ATA_PIO4, 162 .udma_mask = ATA_UDMA6, 163 .port_ops = &ahci_ops, 164 }, 165 [board_ahci_yes_fbs] = { 166 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS), 167 .flags = AHCI_FLAG_COMMON, 168 .pio_mask = ATA_PIO4, 169 .udma_mask = ATA_UDMA6, 170 .port_ops = &ahci_ops, 171 }, 172 /* by chipsets */ 173 [board_ahci_al] = { 174 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI), 175 .flags = AHCI_FLAG_COMMON, 176 .pio_mask = ATA_PIO4, 177 .udma_mask = ATA_UDMA6, 178 .port_ops = &ahci_ops, 179 }, 180 [board_ahci_avn] = { 181 .flags = AHCI_FLAG_COMMON, 182 .pio_mask = ATA_PIO4, 183 .udma_mask = ATA_UDMA6, 184 .port_ops = &ahci_avn_ops, 185 }, 186 [board_ahci_mcp65] = { 187 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP | 188 AHCI_HFLAG_YES_NCQ), 189 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM, 190 .pio_mask = ATA_PIO4, 191 .udma_mask = ATA_UDMA6, 192 .port_ops = &ahci_ops, 193 }, 194 [board_ahci_mcp77] = { 195 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP), 196 .flags = AHCI_FLAG_COMMON, 197 .pio_mask = ATA_PIO4, 198 .udma_mask = ATA_UDMA6, 199 .port_ops = &ahci_ops, 200 }, 201 [board_ahci_mcp89] = { 202 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA), 203 .flags = AHCI_FLAG_COMMON, 204 .pio_mask = ATA_PIO4, 205 .udma_mask = ATA_UDMA6, 206 .port_ops = &ahci_ops, 207 }, 208 [board_ahci_mv] = { 209 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | 210 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP), 211 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, 212 .pio_mask = ATA_PIO4, 213 .udma_mask = ATA_UDMA6, 214 .port_ops = &ahci_ops, 215 }, 216 [board_ahci_sb600] = { 217 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | 218 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 | 219 AHCI_HFLAG_32BIT_ONLY), 220 .flags = AHCI_FLAG_COMMON, 221 .pio_mask = ATA_PIO4, 222 .udma_mask = ATA_UDMA6, 223 .port_ops = &ahci_pmp_retry_srst_ops, 224 }, 225 [board_ahci_sb700] = { /* for SB700 and SB800 */ 226 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL), 227 .flags = AHCI_FLAG_COMMON, 228 .pio_mask = ATA_PIO4, 229 .udma_mask = ATA_UDMA6, 230 .port_ops = &ahci_pmp_retry_srst_ops, 231 }, 232 [board_ahci_vt8251] = { 233 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), 234 .flags = AHCI_FLAG_COMMON, 235 .pio_mask = ATA_PIO4, 236 .udma_mask = ATA_UDMA6, 237 .port_ops = &ahci_vt8251_ops, 238 }, 239 [board_ahci_pcs7] = { 240 .flags = AHCI_FLAG_COMMON, 241 .pio_mask = ATA_PIO4, 242 .udma_mask = ATA_UDMA6, 243 .port_ops = &ahci_ops, 244 }, 245 }; 246 247 static const struct pci_device_id ahci_pci_tbl[] = { 248 /* Intel */ 249 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */ 250 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ 251 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ 252 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ 253 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ 254 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ 255 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ 256 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ 257 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ 258 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ 259 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ 260 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ 261 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */ 262 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ 263 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ 264 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ 265 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ 266 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ 267 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ 268 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ 269 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ 270 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */ 271 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */ 272 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */ 273 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */ 274 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */ 275 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ 276 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */ 277 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ 278 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ 279 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */ 280 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */ 281 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */ 282 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */ 283 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */ 284 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */ 285 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */ 286 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */ 287 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */ 288 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */ 289 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */ 290 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */ 291 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */ 292 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */ 293 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */ 294 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */ 295 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */ 296 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */ 297 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */ 298 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */ 299 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */ 300 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */ 301 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */ 302 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */ 303 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */ 304 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */ 305 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */ 306 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */ 307 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */ 308 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */ 309 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */ 310 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */ 311 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */ 312 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */ 313 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */ 314 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */ 315 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */ 316 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */ 317 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */ 318 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */ 319 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */ 320 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */ 321 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */ 322 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */ 323 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */ 324 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */ 325 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */ 326 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */ 327 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */ 328 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */ 329 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */ 330 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */ 331 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */ 332 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */ 333 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */ 334 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */ 335 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */ 336 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */ 337 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */ 338 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */ 339 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */ 340 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */ 341 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */ 342 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */ 343 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */ 344 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */ 345 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */ 346 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */ 347 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */ 348 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */ 349 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */ 350 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */ 351 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */ 352 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */ 353 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */ 354 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */ 355 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */ 356 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */ 357 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */ 358 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */ 359 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */ 360 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */ 361 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */ 362 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */ 363 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */ 364 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */ 365 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */ 366 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */ 367 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */ 368 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */ 369 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */ 370 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */ 371 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */ 372 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */ 373 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */ 374 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */ 375 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */ 376 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */ 377 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */ 378 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */ 379 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */ 380 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */ 381 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */ 382 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */ 383 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */ 384 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */ 385 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */ 386 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */ 387 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */ 388 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */ 389 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */ 390 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */ 391 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */ 392 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */ 393 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/ 394 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/ 395 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/ 396 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/ 397 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/ 398 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/ 399 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/ 400 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/ 401 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/ 402 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/ 403 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/ 404 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/ 405 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */ 406 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */ 407 { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */ 408 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */ 409 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */ 410 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */ 411 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */ 412 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */ 413 { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_mobile }, /* Comet Lake PCH-U AHCI */ 414 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_mobile }, /* Comet Lake PCH RAID */ 415 416 /* JMicron 360/1/3/5/6, match class to avoid IDE function */ 417 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 418 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, 419 /* JMicron 362B and 362C have an AHCI function with IDE class code */ 420 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr }, 421 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr }, 422 /* May need to update quirk_jmicron_async_suspend() for additions */ 423 424 /* ATI */ 425 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ 426 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ 427 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ 428 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ 429 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ 430 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ 431 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ 432 433 /* Amazon's Annapurna Labs support */ 434 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031), 435 .class = PCI_CLASS_STORAGE_SATA_AHCI, 436 .class_mask = 0xffffff, 437 board_ahci_al }, 438 /* AMD */ 439 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */ 440 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */ 441 /* AMD is using RAID class only for ahci controllers */ 442 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 443 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci }, 444 445 /* VIA */ 446 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ 447 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ 448 449 /* NVIDIA */ 450 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */ 451 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */ 452 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */ 453 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */ 454 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */ 455 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */ 456 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */ 457 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */ 458 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */ 459 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */ 460 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */ 461 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */ 462 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */ 463 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */ 464 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */ 465 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */ 466 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */ 467 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */ 468 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */ 469 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */ 470 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */ 471 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */ 472 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */ 473 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */ 474 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */ 475 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */ 476 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */ 477 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */ 478 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */ 479 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */ 480 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */ 481 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */ 482 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */ 483 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */ 484 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */ 485 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */ 486 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */ 487 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */ 488 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */ 489 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */ 490 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */ 491 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */ 492 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */ 493 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */ 494 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */ 495 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */ 496 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */ 497 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */ 498 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */ 499 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */ 500 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */ 501 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */ 502 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */ 503 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */ 504 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */ 505 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */ 506 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */ 507 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */ 508 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */ 509 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */ 510 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */ 511 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */ 512 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */ 513 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */ 514 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */ 515 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */ 516 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */ 517 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */ 518 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */ 519 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */ 520 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */ 521 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */ 522 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */ 523 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */ 524 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */ 525 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */ 526 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */ 527 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */ 528 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */ 529 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */ 530 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */ 531 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */ 532 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */ 533 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */ 534 535 /* SiS */ 536 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ 537 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */ 538 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ 539 540 /* ST Microelectronics */ 541 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */ 542 543 /* Marvell */ 544 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ 545 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ 546 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123), 547 .class = PCI_CLASS_STORAGE_SATA_AHCI, 548 .class_mask = 0xffffff, 549 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */ 550 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125), 551 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */ 552 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178, 553 PCI_VENDOR_ID_MARVELL_EXT, 0x9170), 554 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */ 555 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a), 556 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 557 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172), 558 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */ 559 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182), 560 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 561 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192), 562 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */ 563 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0), 564 .driver_data = board_ahci_yes_fbs }, 565 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */ 566 .driver_data = board_ahci_yes_fbs }, 567 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3), 568 .driver_data = board_ahci_yes_fbs }, 569 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230), 570 .driver_data = board_ahci_yes_fbs }, 571 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */ 572 .driver_data = board_ahci_yes_fbs }, 573 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */ 574 .driver_data = board_ahci_yes_fbs }, 575 576 /* Promise */ 577 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */ 578 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */ 579 580 /* Asmedia */ 581 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */ 582 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */ 583 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */ 584 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */ 585 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */ 586 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */ 587 588 /* 589 * Samsung SSDs found on some macbooks. NCQ times out if MSI is 590 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731 591 */ 592 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi }, 593 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi }, 594 595 /* Enmotus */ 596 { PCI_DEVICE(0x1c44, 0x8000), board_ahci }, 597 598 /* Loongson */ 599 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci }, 600 601 /* Generic, PCI class code for AHCI */ 602 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 603 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, 604 605 { } /* terminate list */ 606 }; 607 608 static const struct dev_pm_ops ahci_pci_pm_ops = { 609 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume) 610 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend, 611 ahci_pci_device_runtime_resume, NULL) 612 }; 613 614 static struct pci_driver ahci_pci_driver = { 615 .name = DRV_NAME, 616 .id_table = ahci_pci_tbl, 617 .probe = ahci_init_one, 618 .remove = ahci_remove_one, 619 .shutdown = ahci_shutdown_one, 620 .driver = { 621 .pm = &ahci_pci_pm_ops, 622 }, 623 }; 624 625 #if IS_ENABLED(CONFIG_PATA_MARVELL) 626 static int marvell_enable; 627 #else 628 static int marvell_enable = 1; 629 #endif 630 module_param(marvell_enable, int, 0644); 631 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)"); 632 633 static int mobile_lpm_policy = -1; 634 module_param(mobile_lpm_policy, int, 0644); 635 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets"); 636 637 static void ahci_pci_save_initial_config(struct pci_dev *pdev, 638 struct ahci_host_priv *hpriv) 639 { 640 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) { 641 dev_info(&pdev->dev, "JMB361 has only one port\n"); 642 hpriv->force_port_map = 1; 643 } 644 645 /* 646 * Temporary Marvell 6145 hack: PATA port presence 647 * is asserted through the standard AHCI port 648 * presence register, as bit 4 (counting from 0) 649 */ 650 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 651 if (pdev->device == 0x6121) 652 hpriv->mask_port_map = 0x3; 653 else 654 hpriv->mask_port_map = 0xf; 655 dev_info(&pdev->dev, 656 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n"); 657 } 658 659 ahci_save_initial_config(&pdev->dev, hpriv); 660 } 661 662 static void ahci_pci_init_controller(struct ata_host *host) 663 { 664 struct ahci_host_priv *hpriv = host->private_data; 665 struct pci_dev *pdev = to_pci_dev(host->dev); 666 void __iomem *port_mmio; 667 u32 tmp; 668 int mv; 669 670 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 671 if (pdev->device == 0x6121) 672 mv = 2; 673 else 674 mv = 4; 675 port_mmio = __ahci_port_base(host, mv); 676 677 writel(0, port_mmio + PORT_IRQ_MASK); 678 679 /* clear port IRQ */ 680 tmp = readl(port_mmio + PORT_IRQ_STAT); 681 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 682 if (tmp) 683 writel(tmp, port_mmio + PORT_IRQ_STAT); 684 } 685 686 ahci_init_controller(host); 687 } 688 689 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 690 unsigned long deadline) 691 { 692 struct ata_port *ap = link->ap; 693 struct ahci_host_priv *hpriv = ap->host->private_data; 694 bool online; 695 int rc; 696 697 DPRINTK("ENTER\n"); 698 699 hpriv->stop_engine(ap); 700 701 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 702 deadline, &online, NULL); 703 704 hpriv->start_engine(ap); 705 706 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 707 708 /* vt8251 doesn't clear BSY on signature FIS reception, 709 * request follow-up softreset. 710 */ 711 return online ? -EAGAIN : rc; 712 } 713 714 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 715 unsigned long deadline) 716 { 717 struct ata_port *ap = link->ap; 718 struct ahci_port_priv *pp = ap->private_data; 719 struct ahci_host_priv *hpriv = ap->host->private_data; 720 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 721 struct ata_taskfile tf; 722 bool online; 723 int rc; 724 725 hpriv->stop_engine(ap); 726 727 /* clear D2H reception area to properly wait for D2H FIS */ 728 ata_tf_init(link->device, &tf); 729 tf.command = ATA_BUSY; 730 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 731 732 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 733 deadline, &online, NULL); 734 735 hpriv->start_engine(ap); 736 737 /* The pseudo configuration device on SIMG4726 attached to 738 * ASUS P5W-DH Deluxe doesn't send signature FIS after 739 * hardreset if no device is attached to the first downstream 740 * port && the pseudo device locks up on SRST w/ PMP==0. To 741 * work around this, wait for !BSY only briefly. If BSY isn't 742 * cleared, perform CLO and proceed to IDENTIFY (achieved by 743 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). 744 * 745 * Wait for two seconds. Devices attached to downstream port 746 * which can't process the following IDENTIFY after this will 747 * have to be reset again. For most cases, this should 748 * suffice while making probing snappish enough. 749 */ 750 if (online) { 751 rc = ata_wait_after_reset(link, jiffies + 2 * HZ, 752 ahci_check_ready); 753 if (rc) 754 ahci_kick_engine(ap); 755 } 756 return rc; 757 } 758 759 /* 760 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports. 761 * 762 * It has been observed with some SSDs that the timing of events in the 763 * link synchronization phase can leave the port in a state that can not 764 * be recovered by a SATA-hard-reset alone. The failing signature is 765 * SStatus.DET stuck at 1 ("Device presence detected but Phy 766 * communication not established"). It was found that unloading and 767 * reloading the driver when this problem occurs allows the drive 768 * connection to be recovered (DET advanced to 0x3). The critical 769 * component of reloading the driver is that the port state machines are 770 * reset by bouncing "port enable" in the AHCI PCS configuration 771 * register. So, reproduce that effect by bouncing a port whenever we 772 * see DET==1 after a reset. 773 */ 774 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 775 unsigned long deadline) 776 { 777 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 778 struct ata_port *ap = link->ap; 779 struct ahci_port_priv *pp = ap->private_data; 780 struct ahci_host_priv *hpriv = ap->host->private_data; 781 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 782 unsigned long tmo = deadline - jiffies; 783 struct ata_taskfile tf; 784 bool online; 785 int rc, i; 786 787 DPRINTK("ENTER\n"); 788 789 hpriv->stop_engine(ap); 790 791 for (i = 0; i < 2; i++) { 792 u16 val; 793 u32 sstatus; 794 int port = ap->port_no; 795 struct ata_host *host = ap->host; 796 struct pci_dev *pdev = to_pci_dev(host->dev); 797 798 /* clear D2H reception area to properly wait for D2H FIS */ 799 ata_tf_init(link->device, &tf); 800 tf.command = ATA_BUSY; 801 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 802 803 rc = sata_link_hardreset(link, timing, deadline, &online, 804 ahci_check_ready); 805 806 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 || 807 (sstatus & 0xf) != 1) 808 break; 809 810 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n", 811 port); 812 813 pci_read_config_word(pdev, 0x92, &val); 814 val &= ~(1 << port); 815 pci_write_config_word(pdev, 0x92, val); 816 ata_msleep(ap, 1000); 817 val |= 1 << port; 818 pci_write_config_word(pdev, 0x92, val); 819 deadline += tmo; 820 } 821 822 hpriv->start_engine(ap); 823 824 if (online) 825 *class = ahci_dev_classify(ap); 826 827 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 828 return rc; 829 } 830 831 832 #ifdef CONFIG_PM 833 static void ahci_pci_disable_interrupts(struct ata_host *host) 834 { 835 struct ahci_host_priv *hpriv = host->private_data; 836 void __iomem *mmio = hpriv->mmio; 837 u32 ctl; 838 839 /* AHCI spec rev1.1 section 8.3.3: 840 * Software must disable interrupts prior to requesting a 841 * transition of the HBA to D3 state. 842 */ 843 ctl = readl(mmio + HOST_CTL); 844 ctl &= ~HOST_IRQ_EN; 845 writel(ctl, mmio + HOST_CTL); 846 readl(mmio + HOST_CTL); /* flush */ 847 } 848 849 static int ahci_pci_device_runtime_suspend(struct device *dev) 850 { 851 struct pci_dev *pdev = to_pci_dev(dev); 852 struct ata_host *host = pci_get_drvdata(pdev); 853 854 ahci_pci_disable_interrupts(host); 855 return 0; 856 } 857 858 static int ahci_pci_device_runtime_resume(struct device *dev) 859 { 860 struct pci_dev *pdev = to_pci_dev(dev); 861 struct ata_host *host = pci_get_drvdata(pdev); 862 int rc; 863 864 rc = ahci_reset_controller(host); 865 if (rc) 866 return rc; 867 ahci_pci_init_controller(host); 868 return 0; 869 } 870 871 #ifdef CONFIG_PM_SLEEP 872 static int ahci_pci_device_suspend(struct device *dev) 873 { 874 struct pci_dev *pdev = to_pci_dev(dev); 875 struct ata_host *host = pci_get_drvdata(pdev); 876 struct ahci_host_priv *hpriv = host->private_data; 877 878 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { 879 dev_err(&pdev->dev, 880 "BIOS update required for suspend/resume\n"); 881 return -EIO; 882 } 883 884 ahci_pci_disable_interrupts(host); 885 return ata_host_suspend(host, PMSG_SUSPEND); 886 } 887 888 static int ahci_pci_device_resume(struct device *dev) 889 { 890 struct pci_dev *pdev = to_pci_dev(dev); 891 struct ata_host *host = pci_get_drvdata(pdev); 892 int rc; 893 894 /* Apple BIOS helpfully mangles the registers on resume */ 895 if (is_mcp89_apple(pdev)) 896 ahci_mcp89_apple_enable(pdev); 897 898 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { 899 rc = ahci_reset_controller(host); 900 if (rc) 901 return rc; 902 903 ahci_pci_init_controller(host); 904 } 905 906 ata_host_resume(host); 907 908 return 0; 909 } 910 #endif 911 912 #endif /* CONFIG_PM */ 913 914 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) 915 { 916 const int dma_bits = using_dac ? 64 : 32; 917 int rc; 918 919 /* 920 * If the device fixup already set the dma_mask to some non-standard 921 * value, don't extend it here. This happens on STA2X11, for example. 922 * 923 * XXX: manipulating the DMA mask from platform code is completely 924 * bogus, platform code should use dev->bus_dma_limit instead.. 925 */ 926 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32)) 927 return 0; 928 929 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits)); 930 if (rc) 931 dev_err(&pdev->dev, "DMA enable failed\n"); 932 return rc; 933 } 934 935 static void ahci_pci_print_info(struct ata_host *host) 936 { 937 struct pci_dev *pdev = to_pci_dev(host->dev); 938 u16 cc; 939 const char *scc_s; 940 941 pci_read_config_word(pdev, 0x0a, &cc); 942 if (cc == PCI_CLASS_STORAGE_IDE) 943 scc_s = "IDE"; 944 else if (cc == PCI_CLASS_STORAGE_SATA) 945 scc_s = "SATA"; 946 else if (cc == PCI_CLASS_STORAGE_RAID) 947 scc_s = "RAID"; 948 else 949 scc_s = "unknown"; 950 951 ahci_print_info(host, scc_s); 952 } 953 954 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is 955 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't 956 * support PMP and the 4726 either directly exports the device 957 * attached to the first downstream port or acts as a hardware storage 958 * controller and emulate a single ATA device (can be RAID 0/1 or some 959 * other configuration). 960 * 961 * When there's no device attached to the first downstream port of the 962 * 4726, "Config Disk" appears, which is a pseudo ATA device to 963 * configure the 4726. However, ATA emulation of the device is very 964 * lame. It doesn't send signature D2H Reg FIS after the initial 965 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. 966 * 967 * The following function works around the problem by always using 968 * hardreset on the port and not depending on receiving signature FIS 969 * afterward. If signature FIS isn't received soon, ATA class is 970 * assumed without follow-up softreset. 971 */ 972 static void ahci_p5wdh_workaround(struct ata_host *host) 973 { 974 static const struct dmi_system_id sysids[] = { 975 { 976 .ident = "P5W DH Deluxe", 977 .matches = { 978 DMI_MATCH(DMI_SYS_VENDOR, 979 "ASUSTEK COMPUTER INC"), 980 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), 981 }, 982 }, 983 { } 984 }; 985 struct pci_dev *pdev = to_pci_dev(host->dev); 986 987 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && 988 dmi_check_system(sysids)) { 989 struct ata_port *ap = host->ports[1]; 990 991 dev_info(&pdev->dev, 992 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n"); 993 994 ap->ops = &ahci_p5wdh_ops; 995 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; 996 } 997 } 998 999 /* 1000 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when 1001 * booting in BIOS compatibility mode. We restore the registers but not ID. 1002 */ 1003 static void ahci_mcp89_apple_enable(struct pci_dev *pdev) 1004 { 1005 u32 val; 1006 1007 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n"); 1008 1009 pci_read_config_dword(pdev, 0xf8, &val); 1010 val |= 1 << 0x1b; 1011 /* the following changes the device ID, but appears not to affect function */ 1012 /* val = (val & ~0xf0000000) | 0x80000000; */ 1013 pci_write_config_dword(pdev, 0xf8, val); 1014 1015 pci_read_config_dword(pdev, 0x54c, &val); 1016 val |= 1 << 0xc; 1017 pci_write_config_dword(pdev, 0x54c, val); 1018 1019 pci_read_config_dword(pdev, 0x4a4, &val); 1020 val &= 0xff; 1021 val |= 0x01060100; 1022 pci_write_config_dword(pdev, 0x4a4, val); 1023 1024 pci_read_config_dword(pdev, 0x54c, &val); 1025 val &= ~(1 << 0xc); 1026 pci_write_config_dword(pdev, 0x54c, val); 1027 1028 pci_read_config_dword(pdev, 0xf8, &val); 1029 val &= ~(1 << 0x1b); 1030 pci_write_config_dword(pdev, 0xf8, val); 1031 } 1032 1033 static bool is_mcp89_apple(struct pci_dev *pdev) 1034 { 1035 return pdev->vendor == PCI_VENDOR_ID_NVIDIA && 1036 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA && 1037 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 1038 pdev->subsystem_device == 0xcb89; 1039 } 1040 1041 /* only some SB600 ahci controllers can do 64bit DMA */ 1042 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev) 1043 { 1044 static const struct dmi_system_id sysids[] = { 1045 /* 1046 * The oldest version known to be broken is 0901 and 1047 * working is 1501 which was released on 2007-10-26. 1048 * Enable 64bit DMA on 1501 and anything newer. 1049 * 1050 * Please read bko#9412 for more info. 1051 */ 1052 { 1053 .ident = "ASUS M2A-VM", 1054 .matches = { 1055 DMI_MATCH(DMI_BOARD_VENDOR, 1056 "ASUSTeK Computer INC."), 1057 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"), 1058 }, 1059 .driver_data = "20071026", /* yyyymmdd */ 1060 }, 1061 /* 1062 * All BIOS versions for the MSI K9A2 Platinum (MS-7376) 1063 * support 64bit DMA. 1064 * 1065 * BIOS versions earlier than 1.5 had the Manufacturer DMI 1066 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD". 1067 * This spelling mistake was fixed in BIOS version 1.5, so 1068 * 1.5 and later have the Manufacturer as 1069 * "MICRO-STAR INTERNATIONAL CO.,LTD". 1070 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER". 1071 * 1072 * BIOS versions earlier than 1.9 had a Board Product Name 1073 * DMI field of "MS-7376". This was changed to be 1074 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still 1075 * match on DMI_BOARD_NAME of "MS-7376". 1076 */ 1077 { 1078 .ident = "MSI K9A2 Platinum", 1079 .matches = { 1080 DMI_MATCH(DMI_BOARD_VENDOR, 1081 "MICRO-STAR INTER"), 1082 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"), 1083 }, 1084 }, 1085 /* 1086 * All BIOS versions for the MSI K9AGM2 (MS-7327) support 1087 * 64bit DMA. 1088 * 1089 * This board also had the typo mentioned above in the 1090 * Manufacturer DMI field (fixed in BIOS version 1.5), so 1091 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again. 1092 */ 1093 { 1094 .ident = "MSI K9AGM2", 1095 .matches = { 1096 DMI_MATCH(DMI_BOARD_VENDOR, 1097 "MICRO-STAR INTER"), 1098 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"), 1099 }, 1100 }, 1101 /* 1102 * All BIOS versions for the Asus M3A support 64bit DMA. 1103 * (all release versions from 0301 to 1206 were tested) 1104 */ 1105 { 1106 .ident = "ASUS M3A", 1107 .matches = { 1108 DMI_MATCH(DMI_BOARD_VENDOR, 1109 "ASUSTeK Computer INC."), 1110 DMI_MATCH(DMI_BOARD_NAME, "M3A"), 1111 }, 1112 }, 1113 { } 1114 }; 1115 const struct dmi_system_id *match; 1116 int year, month, date; 1117 char buf[9]; 1118 1119 match = dmi_first_match(sysids); 1120 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) || 1121 !match) 1122 return false; 1123 1124 if (!match->driver_data) 1125 goto enable_64bit; 1126 1127 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1128 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1129 1130 if (strcmp(buf, match->driver_data) >= 0) 1131 goto enable_64bit; 1132 else { 1133 dev_warn(&pdev->dev, 1134 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n", 1135 match->ident); 1136 return false; 1137 } 1138 1139 enable_64bit: 1140 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident); 1141 return true; 1142 } 1143 1144 static bool ahci_broken_system_poweroff(struct pci_dev *pdev) 1145 { 1146 static const struct dmi_system_id broken_systems[] = { 1147 { 1148 .ident = "HP Compaq nx6310", 1149 .matches = { 1150 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1151 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"), 1152 }, 1153 /* PCI slot number of the controller */ 1154 .driver_data = (void *)0x1FUL, 1155 }, 1156 { 1157 .ident = "HP Compaq 6720s", 1158 .matches = { 1159 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1160 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"), 1161 }, 1162 /* PCI slot number of the controller */ 1163 .driver_data = (void *)0x1FUL, 1164 }, 1165 1166 { } /* terminate list */ 1167 }; 1168 const struct dmi_system_id *dmi = dmi_first_match(broken_systems); 1169 1170 if (dmi) { 1171 unsigned long slot = (unsigned long)dmi->driver_data; 1172 /* apply the quirk only to on-board controllers */ 1173 return slot == PCI_SLOT(pdev->devfn); 1174 } 1175 1176 return false; 1177 } 1178 1179 static bool ahci_broken_suspend(struct pci_dev *pdev) 1180 { 1181 static const struct dmi_system_id sysids[] = { 1182 /* 1183 * On HP dv[4-6] and HDX18 with earlier BIOSen, link 1184 * to the harddisk doesn't become online after 1185 * resuming from STR. Warn and fail suspend. 1186 * 1187 * http://bugzilla.kernel.org/show_bug.cgi?id=12276 1188 * 1189 * Use dates instead of versions to match as HP is 1190 * apparently recycling both product and version 1191 * strings. 1192 * 1193 * http://bugzilla.kernel.org/show_bug.cgi?id=15462 1194 */ 1195 { 1196 .ident = "dv4", 1197 .matches = { 1198 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1199 DMI_MATCH(DMI_PRODUCT_NAME, 1200 "HP Pavilion dv4 Notebook PC"), 1201 }, 1202 .driver_data = "20090105", /* F.30 */ 1203 }, 1204 { 1205 .ident = "dv5", 1206 .matches = { 1207 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1208 DMI_MATCH(DMI_PRODUCT_NAME, 1209 "HP Pavilion dv5 Notebook PC"), 1210 }, 1211 .driver_data = "20090506", /* F.16 */ 1212 }, 1213 { 1214 .ident = "dv6", 1215 .matches = { 1216 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1217 DMI_MATCH(DMI_PRODUCT_NAME, 1218 "HP Pavilion dv6 Notebook PC"), 1219 }, 1220 .driver_data = "20090423", /* F.21 */ 1221 }, 1222 { 1223 .ident = "HDX18", 1224 .matches = { 1225 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1226 DMI_MATCH(DMI_PRODUCT_NAME, 1227 "HP HDX18 Notebook PC"), 1228 }, 1229 .driver_data = "20090430", /* F.23 */ 1230 }, 1231 /* 1232 * Acer eMachines G725 has the same problem. BIOS 1233 * V1.03 is known to be broken. V3.04 is known to 1234 * work. Between, there are V1.06, V2.06 and V3.03 1235 * that we don't have much idea about. For now, 1236 * blacklist anything older than V3.04. 1237 * 1238 * http://bugzilla.kernel.org/show_bug.cgi?id=15104 1239 */ 1240 { 1241 .ident = "G725", 1242 .matches = { 1243 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"), 1244 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"), 1245 }, 1246 .driver_data = "20091216", /* V3.04 */ 1247 }, 1248 { } /* terminate list */ 1249 }; 1250 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1251 int year, month, date; 1252 char buf[9]; 1253 1254 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2)) 1255 return false; 1256 1257 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1258 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1259 1260 return strcmp(buf, dmi->driver_data) < 0; 1261 } 1262 1263 static bool ahci_broken_lpm(struct pci_dev *pdev) 1264 { 1265 static const struct dmi_system_id sysids[] = { 1266 /* Various Lenovo 50 series have LPM issues with older BIOSen */ 1267 { 1268 .matches = { 1269 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1270 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"), 1271 }, 1272 .driver_data = "20180406", /* 1.31 */ 1273 }, 1274 { 1275 .matches = { 1276 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1277 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"), 1278 }, 1279 .driver_data = "20180420", /* 1.28 */ 1280 }, 1281 { 1282 .matches = { 1283 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1284 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"), 1285 }, 1286 .driver_data = "20180315", /* 1.33 */ 1287 }, 1288 { 1289 .matches = { 1290 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1291 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"), 1292 }, 1293 /* 1294 * Note date based on release notes, 2.35 has been 1295 * reported to be good, but I've been unable to get 1296 * a hold of the reporter to get the DMI BIOS date. 1297 * TODO: fix this. 1298 */ 1299 .driver_data = "20180310", /* 2.35 */ 1300 }, 1301 { } /* terminate list */ 1302 }; 1303 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1304 int year, month, date; 1305 char buf[9]; 1306 1307 if (!dmi) 1308 return false; 1309 1310 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1311 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1312 1313 return strcmp(buf, dmi->driver_data) < 0; 1314 } 1315 1316 static bool ahci_broken_online(struct pci_dev *pdev) 1317 { 1318 #define ENCODE_BUSDEVFN(bus, slot, func) \ 1319 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func))) 1320 static const struct dmi_system_id sysids[] = { 1321 /* 1322 * There are several gigabyte boards which use 1323 * SIMG5723s configured as hardware RAID. Certain 1324 * 5723 firmware revisions shipped there keep the link 1325 * online but fail to answer properly to SRST or 1326 * IDENTIFY when no device is attached downstream 1327 * causing libata to retry quite a few times leading 1328 * to excessive detection delay. 1329 * 1330 * As these firmwares respond to the second reset try 1331 * with invalid device signature, considering unknown 1332 * sig as offline works around the problem acceptably. 1333 */ 1334 { 1335 .ident = "EP45-DQ6", 1336 .matches = { 1337 DMI_MATCH(DMI_BOARD_VENDOR, 1338 "Gigabyte Technology Co., Ltd."), 1339 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"), 1340 }, 1341 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0), 1342 }, 1343 { 1344 .ident = "EP45-DS5", 1345 .matches = { 1346 DMI_MATCH(DMI_BOARD_VENDOR, 1347 "Gigabyte Technology Co., Ltd."), 1348 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"), 1349 }, 1350 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0), 1351 }, 1352 { } /* terminate list */ 1353 }; 1354 #undef ENCODE_BUSDEVFN 1355 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1356 unsigned int val; 1357 1358 if (!dmi) 1359 return false; 1360 1361 val = (unsigned long)dmi->driver_data; 1362 1363 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff); 1364 } 1365 1366 static bool ahci_broken_devslp(struct pci_dev *pdev) 1367 { 1368 /* device with broken DEVSLP but still showing SDS capability */ 1369 static const struct pci_device_id ids[] = { 1370 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */ 1371 {} 1372 }; 1373 1374 return pci_match_id(ids, pdev); 1375 } 1376 1377 #ifdef CONFIG_ATA_ACPI 1378 static void ahci_gtf_filter_workaround(struct ata_host *host) 1379 { 1380 static const struct dmi_system_id sysids[] = { 1381 /* 1382 * Aspire 3810T issues a bunch of SATA enable commands 1383 * via _GTF including an invalid one and one which is 1384 * rejected by the device. Among the successful ones 1385 * is FPDMA non-zero offset enable which when enabled 1386 * only on the drive side leads to NCQ command 1387 * failures. Filter it out. 1388 */ 1389 { 1390 .ident = "Aspire 3810T", 1391 .matches = { 1392 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1393 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"), 1394 }, 1395 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET, 1396 }, 1397 { } 1398 }; 1399 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1400 unsigned int filter; 1401 int i; 1402 1403 if (!dmi) 1404 return; 1405 1406 filter = (unsigned long)dmi->driver_data; 1407 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n", 1408 filter, dmi->ident); 1409 1410 for (i = 0; i < host->n_ports; i++) { 1411 struct ata_port *ap = host->ports[i]; 1412 struct ata_link *link; 1413 struct ata_device *dev; 1414 1415 ata_for_each_link(link, ap, EDGE) 1416 ata_for_each_dev(dev, link, ALL) 1417 dev->gtf_filter |= filter; 1418 } 1419 } 1420 #else 1421 static inline void ahci_gtf_filter_workaround(struct ata_host *host) 1422 {} 1423 #endif 1424 1425 /* 1426 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected 1427 * as DUMMY, or detected but eventually get a "link down" and never get up 1428 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the 1429 * port_map may hold a value of 0x00. 1430 * 1431 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports 1432 * and can significantly reduce the occurrence of the problem. 1433 * 1434 * https://bugzilla.kernel.org/show_bug.cgi?id=189471 1435 */ 1436 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv, 1437 struct pci_dev *pdev) 1438 { 1439 static const struct dmi_system_id sysids[] = { 1440 { 1441 .ident = "Acer Switch Alpha 12", 1442 .matches = { 1443 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1444 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271") 1445 }, 1446 }, 1447 { } 1448 }; 1449 1450 if (dmi_check_system(sysids)) { 1451 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n"); 1452 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) { 1453 hpriv->port_map = 0x7; 1454 hpriv->cap = 0xC734FF02; 1455 } 1456 } 1457 } 1458 1459 #ifdef CONFIG_ARM64 1460 /* 1461 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently. 1462 * Workaround is to make sure all pending IRQs are served before leaving 1463 * handler. 1464 */ 1465 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance) 1466 { 1467 struct ata_host *host = dev_instance; 1468 struct ahci_host_priv *hpriv; 1469 unsigned int rc = 0; 1470 void __iomem *mmio; 1471 u32 irq_stat, irq_masked; 1472 unsigned int handled = 1; 1473 1474 VPRINTK("ENTER\n"); 1475 hpriv = host->private_data; 1476 mmio = hpriv->mmio; 1477 irq_stat = readl(mmio + HOST_IRQ_STAT); 1478 if (!irq_stat) 1479 return IRQ_NONE; 1480 1481 do { 1482 irq_masked = irq_stat & hpriv->port_map; 1483 spin_lock(&host->lock); 1484 rc = ahci_handle_port_intr(host, irq_masked); 1485 if (!rc) 1486 handled = 0; 1487 writel(irq_stat, mmio + HOST_IRQ_STAT); 1488 irq_stat = readl(mmio + HOST_IRQ_STAT); 1489 spin_unlock(&host->lock); 1490 } while (irq_stat); 1491 VPRINTK("EXIT\n"); 1492 1493 return IRQ_RETVAL(handled); 1494 } 1495 #endif 1496 1497 static void ahci_remap_check(struct pci_dev *pdev, int bar, 1498 struct ahci_host_priv *hpriv) 1499 { 1500 int i; 1501 u32 cap; 1502 1503 /* 1504 * Check if this device might have remapped nvme devices. 1505 */ 1506 if (pdev->vendor != PCI_VENDOR_ID_INTEL || 1507 pci_resource_len(pdev, bar) < SZ_512K || 1508 bar != AHCI_PCI_BAR_STANDARD || 1509 !(readl(hpriv->mmio + AHCI_VSCAP) & 1)) 1510 return; 1511 1512 cap = readq(hpriv->mmio + AHCI_REMAP_CAP); 1513 for (i = 0; i < AHCI_MAX_REMAP; i++) { 1514 if ((cap & (1 << i)) == 0) 1515 continue; 1516 if (readl(hpriv->mmio + ahci_remap_dcc(i)) 1517 != PCI_CLASS_STORAGE_EXPRESS) 1518 continue; 1519 1520 /* We've found a remapped device */ 1521 hpriv->remapped_nvme++; 1522 } 1523 1524 if (!hpriv->remapped_nvme) 1525 return; 1526 1527 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n", 1528 hpriv->remapped_nvme); 1529 dev_warn(&pdev->dev, 1530 "Switch your BIOS from RAID to AHCI mode to use them.\n"); 1531 1532 /* 1533 * Don't rely on the msi-x capability in the remap case, 1534 * share the legacy interrupt across ahci and remapped devices. 1535 */ 1536 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1537 } 1538 1539 static int ahci_get_irq_vector(struct ata_host *host, int port) 1540 { 1541 return pci_irq_vector(to_pci_dev(host->dev), port); 1542 } 1543 1544 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports, 1545 struct ahci_host_priv *hpriv) 1546 { 1547 int nvec; 1548 1549 if (hpriv->flags & AHCI_HFLAG_NO_MSI) 1550 return -ENODEV; 1551 1552 /* 1553 * If number of MSIs is less than number of ports then Sharing Last 1554 * Message mode could be enforced. In this case assume that advantage 1555 * of multipe MSIs is negated and use single MSI mode instead. 1556 */ 1557 if (n_ports > 1) { 1558 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX, 1559 PCI_IRQ_MSIX | PCI_IRQ_MSI); 1560 if (nvec > 0) { 1561 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) { 1562 hpriv->get_irq_vector = ahci_get_irq_vector; 1563 hpriv->flags |= AHCI_HFLAG_MULTI_MSI; 1564 return nvec; 1565 } 1566 1567 /* 1568 * Fallback to single MSI mode if the controller 1569 * enforced MRSM mode. 1570 */ 1571 printk(KERN_INFO 1572 "ahci: MRSM is on, fallback to single MSI\n"); 1573 pci_free_irq_vectors(pdev); 1574 } 1575 } 1576 1577 /* 1578 * If the host is not capable of supporting per-port vectors, fall 1579 * back to single MSI before finally attempting single MSI-X. 1580 */ 1581 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 1582 if (nvec == 1) 1583 return nvec; 1584 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX); 1585 } 1586 1587 static void ahci_update_initial_lpm_policy(struct ata_port *ap, 1588 struct ahci_host_priv *hpriv) 1589 { 1590 int policy = CONFIG_SATA_MOBILE_LPM_POLICY; 1591 1592 1593 /* Ignore processing for non mobile platforms */ 1594 if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE)) 1595 return; 1596 1597 /* user modified policy via module param */ 1598 if (mobile_lpm_policy != -1) { 1599 policy = mobile_lpm_policy; 1600 goto update_policy; 1601 } 1602 1603 #ifdef CONFIG_ACPI 1604 if (policy > ATA_LPM_MED_POWER && 1605 (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) { 1606 if (hpriv->cap & HOST_CAP_PART) 1607 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL; 1608 else if (hpriv->cap & HOST_CAP_SSC) 1609 policy = ATA_LPM_MIN_POWER; 1610 } 1611 #endif 1612 1613 update_policy: 1614 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER) 1615 ap->target_lpm_policy = policy; 1616 } 1617 1618 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv) 1619 { 1620 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev); 1621 u16 tmp16; 1622 1623 /* 1624 * Only apply the 6-port PCS quirk for known legacy platforms. 1625 */ 1626 if (!id || id->vendor != PCI_VENDOR_ID_INTEL) 1627 return; 1628 1629 /* Skip applying the quirk on Denverton and beyond */ 1630 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7) 1631 return; 1632 1633 /* 1634 * port_map is determined from PORTS_IMPL PCI register which is 1635 * implemented as write or write-once register. If the register 1636 * isn't programmed, ahci automatically generates it from number 1637 * of ports, which is good enough for PCS programming. It is 1638 * otherwise expected that platform firmware enables the ports 1639 * before the OS boots. 1640 */ 1641 pci_read_config_word(pdev, PCS_6, &tmp16); 1642 if ((tmp16 & hpriv->port_map) != hpriv->port_map) { 1643 tmp16 |= hpriv->port_map; 1644 pci_write_config_word(pdev, PCS_6, tmp16); 1645 } 1646 } 1647 1648 static ssize_t remapped_nvme_show(struct device *dev, 1649 struct device_attribute *attr, 1650 char *buf) 1651 { 1652 struct ata_host *host = dev_get_drvdata(dev); 1653 struct ahci_host_priv *hpriv = host->private_data; 1654 1655 return sprintf(buf, "%u\n", hpriv->remapped_nvme); 1656 } 1657 1658 static DEVICE_ATTR_RO(remapped_nvme); 1659 1660 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1661 { 1662 unsigned int board_id = ent->driver_data; 1663 struct ata_port_info pi = ahci_port_info[board_id]; 1664 const struct ata_port_info *ppi[] = { &pi, NULL }; 1665 struct device *dev = &pdev->dev; 1666 struct ahci_host_priv *hpriv; 1667 struct ata_host *host; 1668 int n_ports, i, rc; 1669 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD; 1670 1671 VPRINTK("ENTER\n"); 1672 1673 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS); 1674 1675 ata_print_version_once(&pdev->dev, DRV_VERSION); 1676 1677 /* The AHCI driver can only drive the SATA ports, the PATA driver 1678 can drive them all so if both drivers are selected make sure 1679 AHCI stays out of the way */ 1680 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable) 1681 return -ENODEV; 1682 1683 /* Apple BIOS on MCP89 prevents us using AHCI */ 1684 if (is_mcp89_apple(pdev)) 1685 ahci_mcp89_apple_enable(pdev); 1686 1687 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode. 1688 * At the moment, we can only use the AHCI mode. Let the users know 1689 * that for SAS drives they're out of luck. 1690 */ 1691 if (pdev->vendor == PCI_VENDOR_ID_PROMISE) 1692 dev_info(&pdev->dev, 1693 "PDC42819 can only drive SATA devices with this driver\n"); 1694 1695 /* Some devices use non-standard BARs */ 1696 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06) 1697 ahci_pci_bar = AHCI_PCI_BAR_STA2X11; 1698 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000) 1699 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS; 1700 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) { 1701 if (pdev->device == 0xa01c) 1702 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM; 1703 if (pdev->device == 0xa084) 1704 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5; 1705 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) { 1706 if (pdev->device == 0x7a08) 1707 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON; 1708 } 1709 1710 /* acquire resources */ 1711 rc = pcim_enable_device(pdev); 1712 if (rc) 1713 return rc; 1714 1715 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 1716 (pdev->device == 0x2652 || pdev->device == 0x2653)) { 1717 u8 map; 1718 1719 /* ICH6s share the same PCI ID for both piix and ahci 1720 * modes. Enabling ahci mode while MAP indicates 1721 * combined mode is a bad idea. Yield to ata_piix. 1722 */ 1723 pci_read_config_byte(pdev, ICH_MAP, &map); 1724 if (map & 0x3) { 1725 dev_info(&pdev->dev, 1726 "controller is in combined mode, can't enable AHCI mode\n"); 1727 return -ENODEV; 1728 } 1729 } 1730 1731 /* AHCI controllers often implement SFF compatible interface. 1732 * Grab all PCI BARs just in case. 1733 */ 1734 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME); 1735 if (rc == -EBUSY) 1736 pcim_pin_device(pdev); 1737 if (rc) 1738 return rc; 1739 1740 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1741 if (!hpriv) 1742 return -ENOMEM; 1743 hpriv->flags |= (unsigned long)pi.private_data; 1744 1745 /* MCP65 revision A1 and A2 can't do MSI */ 1746 if (board_id == board_ahci_mcp65 && 1747 (pdev->revision == 0xa1 || pdev->revision == 0xa2)) 1748 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1749 1750 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */ 1751 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40) 1752 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL; 1753 1754 /* only some SB600s can do 64bit DMA */ 1755 if (ahci_sb600_enable_64bit(pdev)) 1756 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY; 1757 1758 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar]; 1759 1760 /* detect remapped nvme devices */ 1761 ahci_remap_check(pdev, ahci_pci_bar, hpriv); 1762 1763 sysfs_add_file_to_group(&pdev->dev.kobj, 1764 &dev_attr_remapped_nvme.attr, 1765 NULL); 1766 1767 /* must set flag prior to save config in order to take effect */ 1768 if (ahci_broken_devslp(pdev)) 1769 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP; 1770 1771 #ifdef CONFIG_ARM64 1772 if (pdev->vendor == 0x177d && pdev->device == 0xa01c) 1773 hpriv->irq_handler = ahci_thunderx_irq_handler; 1774 #endif 1775 1776 /* save initial config */ 1777 ahci_pci_save_initial_config(pdev, hpriv); 1778 1779 /* 1780 * If platform firmware failed to enable ports, try to enable 1781 * them here. 1782 */ 1783 ahci_intel_pcs_quirk(pdev, hpriv); 1784 1785 /* prepare host */ 1786 if (hpriv->cap & HOST_CAP_NCQ) { 1787 pi.flags |= ATA_FLAG_NCQ; 1788 /* 1789 * Auto-activate optimization is supposed to be 1790 * supported on all AHCI controllers indicating NCQ 1791 * capability, but it seems to be broken on some 1792 * chipsets including NVIDIAs. 1793 */ 1794 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA)) 1795 pi.flags |= ATA_FLAG_FPDMA_AA; 1796 1797 /* 1798 * All AHCI controllers should be forward-compatible 1799 * with the new auxiliary field. This code should be 1800 * conditionalized if any buggy AHCI controllers are 1801 * encountered. 1802 */ 1803 pi.flags |= ATA_FLAG_FPDMA_AUX; 1804 } 1805 1806 if (hpriv->cap & HOST_CAP_PMP) 1807 pi.flags |= ATA_FLAG_PMP; 1808 1809 ahci_set_em_messages(hpriv, &pi); 1810 1811 if (ahci_broken_system_poweroff(pdev)) { 1812 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN; 1813 dev_info(&pdev->dev, 1814 "quirky BIOS, skipping spindown on poweroff\n"); 1815 } 1816 1817 if (ahci_broken_lpm(pdev)) { 1818 pi.flags |= ATA_FLAG_NO_LPM; 1819 dev_warn(&pdev->dev, 1820 "BIOS update required for Link Power Management support\n"); 1821 } 1822 1823 if (ahci_broken_suspend(pdev)) { 1824 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND; 1825 dev_warn(&pdev->dev, 1826 "BIOS update required for suspend/resume\n"); 1827 } 1828 1829 if (ahci_broken_online(pdev)) { 1830 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE; 1831 dev_info(&pdev->dev, 1832 "online status unreliable, applying workaround\n"); 1833 } 1834 1835 1836 /* Acer SA5-271 workaround modifies private_data */ 1837 acer_sa5_271_workaround(hpriv, pdev); 1838 1839 /* CAP.NP sometimes indicate the index of the last enabled 1840 * port, at other times, that of the last possible port, so 1841 * determining the maximum port number requires looking at 1842 * both CAP.NP and port_map. 1843 */ 1844 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); 1845 1846 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 1847 if (!host) 1848 return -ENOMEM; 1849 host->private_data = hpriv; 1850 1851 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) { 1852 /* legacy intx interrupts */ 1853 pci_intx(pdev, 1); 1854 } 1855 hpriv->irq = pci_irq_vector(pdev, 0); 1856 1857 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) 1858 host->flags |= ATA_HOST_PARALLEL_SCAN; 1859 else 1860 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n"); 1861 1862 if (pi.flags & ATA_FLAG_EM) 1863 ahci_reset_em(host); 1864 1865 for (i = 0; i < host->n_ports; i++) { 1866 struct ata_port *ap = host->ports[i]; 1867 1868 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar"); 1869 ata_port_pbar_desc(ap, ahci_pci_bar, 1870 0x100 + ap->port_no * 0x80, "port"); 1871 1872 /* set enclosure management message type */ 1873 if (ap->flags & ATA_FLAG_EM) 1874 ap->em_message_type = hpriv->em_msg_type; 1875 1876 ahci_update_initial_lpm_policy(ap, hpriv); 1877 1878 /* disabled/not-implemented port */ 1879 if (!(hpriv->port_map & (1 << i))) 1880 ap->ops = &ata_dummy_port_ops; 1881 } 1882 1883 /* apply workaround for ASUS P5W DH Deluxe mainboard */ 1884 ahci_p5wdh_workaround(host); 1885 1886 /* apply gtf filter quirk */ 1887 ahci_gtf_filter_workaround(host); 1888 1889 /* initialize adapter */ 1890 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); 1891 if (rc) 1892 return rc; 1893 1894 rc = ahci_reset_controller(host); 1895 if (rc) 1896 return rc; 1897 1898 ahci_pci_init_controller(host); 1899 ahci_pci_print_info(host); 1900 1901 pci_set_master(pdev); 1902 1903 rc = ahci_host_activate(host, &ahci_sht); 1904 if (rc) 1905 return rc; 1906 1907 pm_runtime_put_noidle(&pdev->dev); 1908 return 0; 1909 } 1910 1911 static void ahci_shutdown_one(struct pci_dev *pdev) 1912 { 1913 ata_pci_shutdown_one(pdev); 1914 } 1915 1916 static void ahci_remove_one(struct pci_dev *pdev) 1917 { 1918 sysfs_remove_file_from_group(&pdev->dev.kobj, 1919 &dev_attr_remapped_nvme.attr, 1920 NULL); 1921 pm_runtime_get_noresume(&pdev->dev); 1922 ata_pci_remove_one(pdev); 1923 } 1924 1925 module_pci_driver(ahci_pci_driver); 1926 1927 MODULE_AUTHOR("Jeff Garzik"); 1928 MODULE_DESCRIPTION("AHCI SATA low-level driver"); 1929 MODULE_LICENSE("GPL"); 1930 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); 1931 MODULE_VERSION(DRV_VERSION); 1932