1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ahci.c - AHCI SATA support 4 * 5 * Maintained by: Tejun Heo <tj@kernel.org> 6 * Please ALWAYS copy linux-ide@vger.kernel.org 7 * on emails. 8 * 9 * Copyright 2004-2005 Red Hat, Inc. 10 * 11 * libata documentation is available via 'make {ps|pdf}docs', 12 * as Documentation/driver-api/libata.rst 13 * 14 * AHCI hardware documentation: 15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/blkdev.h> 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/device.h> 27 #include <linux/dmi.h> 28 #include <linux/gfp.h> 29 #include <scsi/scsi_host.h> 30 #include <scsi/scsi_cmnd.h> 31 #include <linux/libata.h> 32 #include <linux/ahci-remap.h> 33 #include <linux/io-64-nonatomic-lo-hi.h> 34 #include "ahci.h" 35 36 #define DRV_NAME "ahci" 37 #define DRV_VERSION "3.0" 38 39 enum { 40 AHCI_PCI_BAR_STA2X11 = 0, 41 AHCI_PCI_BAR_CAVIUM = 0, 42 AHCI_PCI_BAR_LOONGSON = 0, 43 AHCI_PCI_BAR_ENMOTUS = 2, 44 AHCI_PCI_BAR_CAVIUM_GEN5 = 4, 45 AHCI_PCI_BAR_STANDARD = 5, 46 }; 47 48 enum board_ids { 49 /* board IDs by feature in alphabetical order */ 50 board_ahci, 51 board_ahci_ign_iferr, 52 board_ahci_low_power, 53 board_ahci_no_debounce_delay, 54 board_ahci_nomsi, 55 board_ahci_noncq, 56 board_ahci_nosntf, 57 board_ahci_yes_fbs, 58 59 /* board IDs for specific chipsets in alphabetical order */ 60 board_ahci_al, 61 board_ahci_avn, 62 board_ahci_mcp65, 63 board_ahci_mcp77, 64 board_ahci_mcp89, 65 board_ahci_mv, 66 board_ahci_sb600, 67 board_ahci_sb700, /* for SB700 and SB800 */ 68 board_ahci_vt8251, 69 70 /* 71 * board IDs for Intel chipsets that support more than 6 ports 72 * *and* end up needing the PCS quirk. 73 */ 74 board_ahci_pcs7, 75 76 /* aliases */ 77 board_ahci_mcp_linux = board_ahci_mcp65, 78 board_ahci_mcp67 = board_ahci_mcp65, 79 board_ahci_mcp73 = board_ahci_mcp65, 80 board_ahci_mcp79 = board_ahci_mcp77, 81 }; 82 83 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 84 static void ahci_remove_one(struct pci_dev *dev); 85 static void ahci_shutdown_one(struct pci_dev *dev); 86 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv); 87 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 88 unsigned long deadline); 89 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 90 unsigned long deadline); 91 static void ahci_mcp89_apple_enable(struct pci_dev *pdev); 92 static bool is_mcp89_apple(struct pci_dev *pdev); 93 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 94 unsigned long deadline); 95 #ifdef CONFIG_PM 96 static int ahci_pci_device_runtime_suspend(struct device *dev); 97 static int ahci_pci_device_runtime_resume(struct device *dev); 98 #ifdef CONFIG_PM_SLEEP 99 static int ahci_pci_device_suspend(struct device *dev); 100 static int ahci_pci_device_resume(struct device *dev); 101 #endif 102 #endif /* CONFIG_PM */ 103 104 static const struct scsi_host_template ahci_sht = { 105 AHCI_SHT("ahci"), 106 }; 107 108 static struct ata_port_operations ahci_vt8251_ops = { 109 .inherits = &ahci_ops, 110 .hardreset = ahci_vt8251_hardreset, 111 }; 112 113 static struct ata_port_operations ahci_p5wdh_ops = { 114 .inherits = &ahci_ops, 115 .hardreset = ahci_p5wdh_hardreset, 116 }; 117 118 static struct ata_port_operations ahci_avn_ops = { 119 .inherits = &ahci_ops, 120 .hardreset = ahci_avn_hardreset, 121 }; 122 123 static const struct ata_port_info ahci_port_info[] = { 124 /* by features */ 125 [board_ahci] = { 126 .flags = AHCI_FLAG_COMMON, 127 .pio_mask = ATA_PIO4, 128 .udma_mask = ATA_UDMA6, 129 .port_ops = &ahci_ops, 130 }, 131 [board_ahci_ign_iferr] = { 132 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), 133 .flags = AHCI_FLAG_COMMON, 134 .pio_mask = ATA_PIO4, 135 .udma_mask = ATA_UDMA6, 136 .port_ops = &ahci_ops, 137 }, 138 [board_ahci_low_power] = { 139 AHCI_HFLAGS (AHCI_HFLAG_USE_LPM_POLICY), 140 .flags = AHCI_FLAG_COMMON, 141 .pio_mask = ATA_PIO4, 142 .udma_mask = ATA_UDMA6, 143 .port_ops = &ahci_ops, 144 }, 145 [board_ahci_no_debounce_delay] = { 146 .flags = AHCI_FLAG_COMMON, 147 .link_flags = ATA_LFLAG_NO_DEBOUNCE_DELAY, 148 .pio_mask = ATA_PIO4, 149 .udma_mask = ATA_UDMA6, 150 .port_ops = &ahci_ops, 151 }, 152 [board_ahci_nomsi] = { 153 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI), 154 .flags = AHCI_FLAG_COMMON, 155 .pio_mask = ATA_PIO4, 156 .udma_mask = ATA_UDMA6, 157 .port_ops = &ahci_ops, 158 }, 159 [board_ahci_noncq] = { 160 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ), 161 .flags = AHCI_FLAG_COMMON, 162 .pio_mask = ATA_PIO4, 163 .udma_mask = ATA_UDMA6, 164 .port_ops = &ahci_ops, 165 }, 166 [board_ahci_nosntf] = { 167 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF), 168 .flags = AHCI_FLAG_COMMON, 169 .pio_mask = ATA_PIO4, 170 .udma_mask = ATA_UDMA6, 171 .port_ops = &ahci_ops, 172 }, 173 [board_ahci_yes_fbs] = { 174 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS), 175 .flags = AHCI_FLAG_COMMON, 176 .pio_mask = ATA_PIO4, 177 .udma_mask = ATA_UDMA6, 178 .port_ops = &ahci_ops, 179 }, 180 /* by chipsets */ 181 [board_ahci_al] = { 182 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI), 183 .flags = AHCI_FLAG_COMMON, 184 .pio_mask = ATA_PIO4, 185 .udma_mask = ATA_UDMA6, 186 .port_ops = &ahci_ops, 187 }, 188 [board_ahci_avn] = { 189 .flags = AHCI_FLAG_COMMON, 190 .pio_mask = ATA_PIO4, 191 .udma_mask = ATA_UDMA6, 192 .port_ops = &ahci_avn_ops, 193 }, 194 [board_ahci_mcp65] = { 195 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP | 196 AHCI_HFLAG_YES_NCQ), 197 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM, 198 .pio_mask = ATA_PIO4, 199 .udma_mask = ATA_UDMA6, 200 .port_ops = &ahci_ops, 201 }, 202 [board_ahci_mcp77] = { 203 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP), 204 .flags = AHCI_FLAG_COMMON, 205 .pio_mask = ATA_PIO4, 206 .udma_mask = ATA_UDMA6, 207 .port_ops = &ahci_ops, 208 }, 209 [board_ahci_mcp89] = { 210 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA), 211 .flags = AHCI_FLAG_COMMON, 212 .pio_mask = ATA_PIO4, 213 .udma_mask = ATA_UDMA6, 214 .port_ops = &ahci_ops, 215 }, 216 [board_ahci_mv] = { 217 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | 218 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP), 219 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, 220 .pio_mask = ATA_PIO4, 221 .udma_mask = ATA_UDMA6, 222 .port_ops = &ahci_ops, 223 }, 224 [board_ahci_sb600] = { 225 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | 226 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 | 227 AHCI_HFLAG_32BIT_ONLY), 228 .flags = AHCI_FLAG_COMMON, 229 .pio_mask = ATA_PIO4, 230 .udma_mask = ATA_UDMA6, 231 .port_ops = &ahci_pmp_retry_srst_ops, 232 }, 233 [board_ahci_sb700] = { /* for SB700 and SB800 */ 234 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL), 235 .flags = AHCI_FLAG_COMMON, 236 .pio_mask = ATA_PIO4, 237 .udma_mask = ATA_UDMA6, 238 .port_ops = &ahci_pmp_retry_srst_ops, 239 }, 240 [board_ahci_vt8251] = { 241 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), 242 .flags = AHCI_FLAG_COMMON, 243 .pio_mask = ATA_PIO4, 244 .udma_mask = ATA_UDMA6, 245 .port_ops = &ahci_vt8251_ops, 246 }, 247 [board_ahci_pcs7] = { 248 .flags = AHCI_FLAG_COMMON, 249 .pio_mask = ATA_PIO4, 250 .udma_mask = ATA_UDMA6, 251 .port_ops = &ahci_ops, 252 }, 253 }; 254 255 static const struct pci_device_id ahci_pci_tbl[] = { 256 /* Intel */ 257 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */ 258 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ 259 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ 260 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ 261 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ 262 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ 263 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ 264 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ 265 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ 266 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ 267 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ 268 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ 269 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8/Lewisburg RAID*/ 270 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ 271 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ 272 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ 273 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ 274 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ 275 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ 276 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ 277 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ 278 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_low_power }, /* ICH9M */ 279 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_low_power }, /* ICH9M */ 280 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_low_power }, /* ICH9M */ 281 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_low_power }, /* ICH9M */ 282 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_low_power }, /* ICH9M */ 283 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ 284 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_low_power }, /* ICH9M */ 285 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ 286 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ 287 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */ 288 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */ 289 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */ 290 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */ 291 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */ 292 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */ 293 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */ 294 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_low_power }, /* PCH M AHCI */ 295 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */ 296 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_low_power }, /* PCH M RAID */ 297 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */ 298 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */ 299 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */ 300 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */ 301 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */ 302 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */ 303 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */ 304 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */ 305 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */ 306 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */ 307 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */ 308 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */ 309 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */ 310 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */ 311 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */ 312 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */ 313 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */ 314 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */ 315 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */ 316 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */ 317 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */ 318 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */ 319 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_low_power }, /* CPT M AHCI */ 320 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */ 321 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_low_power }, /* CPT M RAID */ 322 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */ 323 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */ 324 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */ 325 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */ 326 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */ 327 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */ 328 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */ 329 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_low_power }, /* Panther M AHCI */ 330 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */ 331 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */ 332 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */ 333 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_low_power }, /* Panther M RAID */ 334 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */ 335 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */ 336 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_low_power }, /* Lynx M AHCI */ 337 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */ 338 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_low_power }, /* Lynx M RAID */ 339 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */ 340 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_low_power }, /* Lynx M RAID */ 341 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */ 342 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_low_power }, /* Lynx M RAID */ 343 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_low_power }, /* Lynx LP AHCI */ 344 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_low_power }, /* Lynx LP AHCI */ 345 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_low_power }, /* Lynx LP RAID */ 346 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_low_power }, /* Lynx LP RAID */ 347 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_low_power }, /* Lynx LP RAID */ 348 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_low_power }, /* Lynx LP RAID */ 349 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_low_power }, /* Lynx LP RAID */ 350 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_low_power }, /* Lynx LP RAID */ 351 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_low_power }, /* Cannon Lake PCH-LP AHCI */ 352 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */ 353 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */ 354 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */ 355 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */ 356 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */ 357 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */ 358 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */ 359 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */ 360 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */ 361 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */ 362 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */ 363 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */ 364 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */ 365 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */ 366 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */ 367 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */ 368 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg/Lewisburg AHCI*/ 369 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* *burg SATA0 'RAID' */ 370 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* *burg SATA1 'RAID' */ 371 { PCI_VDEVICE(INTEL, 0x282f), board_ahci }, /* *burg SATA2 'RAID' */ 372 { PCI_VDEVICE(INTEL, 0x43d4), board_ahci }, /* Rocket Lake PCH-H RAID */ 373 { PCI_VDEVICE(INTEL, 0x43d5), board_ahci }, /* Rocket Lake PCH-H RAID */ 374 { PCI_VDEVICE(INTEL, 0x43d6), board_ahci }, /* Rocket Lake PCH-H RAID */ 375 { PCI_VDEVICE(INTEL, 0x43d7), board_ahci }, /* Rocket Lake PCH-H RAID */ 376 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */ 377 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */ 378 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */ 379 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */ 380 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */ 381 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */ 382 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */ 383 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */ 384 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */ 385 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_low_power }, /* Wildcat LP AHCI */ 386 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_low_power }, /* Wildcat LP RAID */ 387 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_low_power }, /* Wildcat LP RAID */ 388 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_low_power }, /* Wildcat LP RAID */ 389 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */ 390 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_low_power }, /* 9 Series M AHCI */ 391 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */ 392 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_low_power }, /* 9 Series M RAID */ 393 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */ 394 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_low_power }, /* 9 Series M RAID */ 395 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */ 396 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_low_power }, /* 9 Series M RAID */ 397 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_low_power }, /* Sunrise LP AHCI */ 398 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_low_power }, /* Sunrise LP RAID */ 399 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_low_power }, /* Sunrise LP RAID */ 400 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */ 401 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_low_power }, /* Sunrise M AHCI */ 402 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */ 403 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */ 404 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_low_power }, /* Sunrise M RAID */ 405 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */ 406 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/ 407 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/ 408 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/ 409 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/ 410 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/ 411 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/ 412 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/ 413 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/ 414 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */ 415 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */ 416 { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */ 417 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_low_power }, /* Bay Trail AHCI */ 418 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_low_power }, /* Bay Trail AHCI */ 419 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_low_power }, /* Cherry Tr. AHCI */ 420 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_low_power }, /* ApolloLake AHCI */ 421 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_low_power }, /* Ice Lake LP AHCI */ 422 { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_low_power }, /* Comet Lake PCH-U AHCI */ 423 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_low_power }, /* Comet Lake PCH RAID */ 424 425 /* JMicron 360/1/3/5/6, match class to avoid IDE function */ 426 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 427 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, 428 /* JMicron 362B and 362C have an AHCI function with IDE class code */ 429 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr }, 430 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr }, 431 /* May need to update quirk_jmicron_async_suspend() for additions */ 432 433 /* ATI */ 434 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ 435 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ 436 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ 437 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ 438 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ 439 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ 440 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ 441 442 /* Amazon's Annapurna Labs support */ 443 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031), 444 .class = PCI_CLASS_STORAGE_SATA_AHCI, 445 .class_mask = 0xffffff, 446 board_ahci_al }, 447 /* AMD */ 448 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */ 449 { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */ 450 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */ 451 { PCI_VDEVICE(AMD, 0x7901), board_ahci_low_power }, /* AMD Green Sardine */ 452 /* AMD is using RAID class only for ahci controllers */ 453 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 454 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci }, 455 456 /* Dell S140/S150 */ 457 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID, 458 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci }, 459 460 /* VIA */ 461 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ 462 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ 463 464 /* NVIDIA */ 465 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */ 466 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */ 467 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */ 468 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */ 469 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */ 470 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */ 471 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */ 472 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */ 473 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */ 474 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */ 475 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */ 476 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */ 477 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */ 478 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */ 479 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */ 480 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */ 481 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */ 482 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */ 483 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */ 484 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */ 485 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */ 486 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */ 487 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */ 488 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */ 489 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */ 490 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */ 491 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */ 492 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */ 493 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */ 494 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */ 495 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */ 496 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */ 497 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */ 498 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */ 499 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */ 500 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */ 501 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */ 502 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */ 503 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */ 504 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */ 505 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */ 506 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */ 507 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */ 508 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */ 509 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */ 510 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */ 511 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */ 512 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */ 513 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */ 514 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */ 515 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */ 516 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */ 517 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */ 518 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */ 519 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */ 520 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */ 521 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */ 522 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */ 523 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */ 524 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */ 525 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */ 526 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */ 527 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */ 528 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */ 529 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */ 530 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */ 531 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */ 532 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */ 533 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */ 534 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */ 535 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */ 536 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */ 537 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */ 538 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */ 539 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */ 540 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */ 541 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */ 542 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */ 543 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */ 544 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */ 545 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */ 546 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */ 547 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */ 548 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */ 549 550 /* SiS */ 551 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ 552 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */ 553 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ 554 555 /* ST Microelectronics */ 556 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */ 557 558 /* Marvell */ 559 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ 560 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ 561 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123), 562 .class = PCI_CLASS_STORAGE_SATA_AHCI, 563 .class_mask = 0xffffff, 564 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */ 565 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125), 566 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */ 567 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178, 568 PCI_VENDOR_ID_MARVELL_EXT, 0x9170), 569 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */ 570 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a), 571 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 572 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172), 573 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */ 574 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182), 575 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 576 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192), 577 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */ 578 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0), 579 .driver_data = board_ahci_yes_fbs }, 580 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */ 581 .driver_data = board_ahci_yes_fbs }, 582 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3), 583 .driver_data = board_ahci_yes_fbs }, 584 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230), 585 .driver_data = board_ahci_yes_fbs }, 586 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9235), 587 .driver_data = board_ahci_no_debounce_delay }, 588 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */ 589 .driver_data = board_ahci_yes_fbs }, 590 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */ 591 .driver_data = board_ahci_yes_fbs }, 592 593 /* Promise */ 594 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */ 595 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */ 596 597 /* Asmedia */ 598 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */ 599 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */ 600 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */ 601 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */ 602 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */ 603 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */ 604 { PCI_VDEVICE(ASMEDIA, 0x0624), board_ahci }, /* ASM1062+JMB575 */ 605 606 /* 607 * Samsung SSDs found on some macbooks. NCQ times out if MSI is 608 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731 609 */ 610 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi }, 611 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi }, 612 613 /* Enmotus */ 614 { PCI_DEVICE(0x1c44, 0x8000), board_ahci }, 615 616 /* Loongson */ 617 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci }, 618 619 /* Generic, PCI class code for AHCI */ 620 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 621 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, 622 623 { } /* terminate list */ 624 }; 625 626 static const struct dev_pm_ops ahci_pci_pm_ops = { 627 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume) 628 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend, 629 ahci_pci_device_runtime_resume, NULL) 630 }; 631 632 static struct pci_driver ahci_pci_driver = { 633 .name = DRV_NAME, 634 .id_table = ahci_pci_tbl, 635 .probe = ahci_init_one, 636 .remove = ahci_remove_one, 637 .shutdown = ahci_shutdown_one, 638 .driver = { 639 .pm = &ahci_pci_pm_ops, 640 }, 641 }; 642 643 #if IS_ENABLED(CONFIG_PATA_MARVELL) 644 static int marvell_enable; 645 #else 646 static int marvell_enable = 1; 647 #endif 648 module_param(marvell_enable, int, 0644); 649 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)"); 650 651 static int mobile_lpm_policy = -1; 652 module_param(mobile_lpm_policy, int, 0644); 653 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets"); 654 655 static void ahci_pci_save_initial_config(struct pci_dev *pdev, 656 struct ahci_host_priv *hpriv) 657 { 658 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) { 659 dev_info(&pdev->dev, "JMB361 has only one port\n"); 660 hpriv->saved_port_map = 1; 661 } 662 663 /* 664 * Temporary Marvell 6145 hack: PATA port presence 665 * is asserted through the standard AHCI port 666 * presence register, as bit 4 (counting from 0) 667 */ 668 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 669 if (pdev->device == 0x6121) 670 hpriv->mask_port_map = 0x3; 671 else 672 hpriv->mask_port_map = 0xf; 673 dev_info(&pdev->dev, 674 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n"); 675 } 676 677 ahci_save_initial_config(&pdev->dev, hpriv); 678 } 679 680 static int ahci_pci_reset_controller(struct ata_host *host) 681 { 682 struct pci_dev *pdev = to_pci_dev(host->dev); 683 struct ahci_host_priv *hpriv = host->private_data; 684 int rc; 685 686 rc = ahci_reset_controller(host); 687 if (rc) 688 return rc; 689 690 /* 691 * If platform firmware failed to enable ports, try to enable 692 * them here. 693 */ 694 ahci_intel_pcs_quirk(pdev, hpriv); 695 696 return 0; 697 } 698 699 static void ahci_pci_init_controller(struct ata_host *host) 700 { 701 struct ahci_host_priv *hpriv = host->private_data; 702 struct pci_dev *pdev = to_pci_dev(host->dev); 703 void __iomem *port_mmio; 704 u32 tmp; 705 int mv; 706 707 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 708 if (pdev->device == 0x6121) 709 mv = 2; 710 else 711 mv = 4; 712 port_mmio = __ahci_port_base(hpriv, mv); 713 714 writel(0, port_mmio + PORT_IRQ_MASK); 715 716 /* clear port IRQ */ 717 tmp = readl(port_mmio + PORT_IRQ_STAT); 718 dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp); 719 if (tmp) 720 writel(tmp, port_mmio + PORT_IRQ_STAT); 721 } 722 723 ahci_init_controller(host); 724 } 725 726 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 727 unsigned long deadline) 728 { 729 struct ata_port *ap = link->ap; 730 struct ahci_host_priv *hpriv = ap->host->private_data; 731 bool online; 732 int rc; 733 734 hpriv->stop_engine(ap); 735 736 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 737 deadline, &online, NULL); 738 739 hpriv->start_engine(ap); 740 741 /* vt8251 doesn't clear BSY on signature FIS reception, 742 * request follow-up softreset. 743 */ 744 return online ? -EAGAIN : rc; 745 } 746 747 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 748 unsigned long deadline) 749 { 750 struct ata_port *ap = link->ap; 751 struct ahci_port_priv *pp = ap->private_data; 752 struct ahci_host_priv *hpriv = ap->host->private_data; 753 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 754 struct ata_taskfile tf; 755 bool online; 756 int rc; 757 758 hpriv->stop_engine(ap); 759 760 /* clear D2H reception area to properly wait for D2H FIS */ 761 ata_tf_init(link->device, &tf); 762 tf.status = ATA_BUSY; 763 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 764 765 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 766 deadline, &online, NULL); 767 768 hpriv->start_engine(ap); 769 770 /* The pseudo configuration device on SIMG4726 attached to 771 * ASUS P5W-DH Deluxe doesn't send signature FIS after 772 * hardreset if no device is attached to the first downstream 773 * port && the pseudo device locks up on SRST w/ PMP==0. To 774 * work around this, wait for !BSY only briefly. If BSY isn't 775 * cleared, perform CLO and proceed to IDENTIFY (achieved by 776 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). 777 * 778 * Wait for two seconds. Devices attached to downstream port 779 * which can't process the following IDENTIFY after this will 780 * have to be reset again. For most cases, this should 781 * suffice while making probing snappish enough. 782 */ 783 if (online) { 784 rc = ata_wait_after_reset(link, jiffies + 2 * HZ, 785 ahci_check_ready); 786 if (rc) 787 ahci_kick_engine(ap); 788 } 789 return rc; 790 } 791 792 /* 793 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports. 794 * 795 * It has been observed with some SSDs that the timing of events in the 796 * link synchronization phase can leave the port in a state that can not 797 * be recovered by a SATA-hard-reset alone. The failing signature is 798 * SStatus.DET stuck at 1 ("Device presence detected but Phy 799 * communication not established"). It was found that unloading and 800 * reloading the driver when this problem occurs allows the drive 801 * connection to be recovered (DET advanced to 0x3). The critical 802 * component of reloading the driver is that the port state machines are 803 * reset by bouncing "port enable" in the AHCI PCS configuration 804 * register. So, reproduce that effect by bouncing a port whenever we 805 * see DET==1 after a reset. 806 */ 807 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 808 unsigned long deadline) 809 { 810 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 811 struct ata_port *ap = link->ap; 812 struct ahci_port_priv *pp = ap->private_data; 813 struct ahci_host_priv *hpriv = ap->host->private_data; 814 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 815 unsigned long tmo = deadline - jiffies; 816 struct ata_taskfile tf; 817 bool online; 818 int rc, i; 819 820 hpriv->stop_engine(ap); 821 822 for (i = 0; i < 2; i++) { 823 u16 val; 824 u32 sstatus; 825 int port = ap->port_no; 826 struct ata_host *host = ap->host; 827 struct pci_dev *pdev = to_pci_dev(host->dev); 828 829 /* clear D2H reception area to properly wait for D2H FIS */ 830 ata_tf_init(link->device, &tf); 831 tf.status = ATA_BUSY; 832 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 833 834 rc = sata_link_hardreset(link, timing, deadline, &online, 835 ahci_check_ready); 836 837 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 || 838 (sstatus & 0xf) != 1) 839 break; 840 841 ata_link_info(link, "avn bounce port%d\n", port); 842 843 pci_read_config_word(pdev, 0x92, &val); 844 val &= ~(1 << port); 845 pci_write_config_word(pdev, 0x92, val); 846 ata_msleep(ap, 1000); 847 val |= 1 << port; 848 pci_write_config_word(pdev, 0x92, val); 849 deadline += tmo; 850 } 851 852 hpriv->start_engine(ap); 853 854 if (online) 855 *class = ahci_dev_classify(ap); 856 857 return rc; 858 } 859 860 861 #ifdef CONFIG_PM 862 static void ahci_pci_disable_interrupts(struct ata_host *host) 863 { 864 struct ahci_host_priv *hpriv = host->private_data; 865 void __iomem *mmio = hpriv->mmio; 866 u32 ctl; 867 868 /* AHCI spec rev1.1 section 8.3.3: 869 * Software must disable interrupts prior to requesting a 870 * transition of the HBA to D3 state. 871 */ 872 ctl = readl(mmio + HOST_CTL); 873 ctl &= ~HOST_IRQ_EN; 874 writel(ctl, mmio + HOST_CTL); 875 readl(mmio + HOST_CTL); /* flush */ 876 } 877 878 static int ahci_pci_device_runtime_suspend(struct device *dev) 879 { 880 struct pci_dev *pdev = to_pci_dev(dev); 881 struct ata_host *host = pci_get_drvdata(pdev); 882 883 ahci_pci_disable_interrupts(host); 884 return 0; 885 } 886 887 static int ahci_pci_device_runtime_resume(struct device *dev) 888 { 889 struct pci_dev *pdev = to_pci_dev(dev); 890 struct ata_host *host = pci_get_drvdata(pdev); 891 int rc; 892 893 rc = ahci_pci_reset_controller(host); 894 if (rc) 895 return rc; 896 ahci_pci_init_controller(host); 897 return 0; 898 } 899 900 #ifdef CONFIG_PM_SLEEP 901 static int ahci_pci_device_suspend(struct device *dev) 902 { 903 struct pci_dev *pdev = to_pci_dev(dev); 904 struct ata_host *host = pci_get_drvdata(pdev); 905 struct ahci_host_priv *hpriv = host->private_data; 906 907 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { 908 dev_err(&pdev->dev, 909 "BIOS update required for suspend/resume\n"); 910 return -EIO; 911 } 912 913 ahci_pci_disable_interrupts(host); 914 ata_host_suspend(host, PMSG_SUSPEND); 915 return 0; 916 } 917 918 static int ahci_pci_device_resume(struct device *dev) 919 { 920 struct pci_dev *pdev = to_pci_dev(dev); 921 struct ata_host *host = pci_get_drvdata(pdev); 922 int rc; 923 924 /* Apple BIOS helpfully mangles the registers on resume */ 925 if (is_mcp89_apple(pdev)) 926 ahci_mcp89_apple_enable(pdev); 927 928 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { 929 rc = ahci_pci_reset_controller(host); 930 if (rc) 931 return rc; 932 933 ahci_pci_init_controller(host); 934 } 935 936 ata_host_resume(host); 937 938 return 0; 939 } 940 #endif 941 942 #endif /* CONFIG_PM */ 943 944 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) 945 { 946 const int dma_bits = using_dac ? 64 : 32; 947 int rc; 948 949 /* 950 * If the device fixup already set the dma_mask to some non-standard 951 * value, don't extend it here. This happens on STA2X11, for example. 952 * 953 * XXX: manipulating the DMA mask from platform code is completely 954 * bogus, platform code should use dev->bus_dma_limit instead.. 955 */ 956 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32)) 957 return 0; 958 959 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits)); 960 if (rc) 961 dev_err(&pdev->dev, "DMA enable failed\n"); 962 return rc; 963 } 964 965 static void ahci_pci_print_info(struct ata_host *host) 966 { 967 struct pci_dev *pdev = to_pci_dev(host->dev); 968 u16 cc; 969 const char *scc_s; 970 971 pci_read_config_word(pdev, 0x0a, &cc); 972 if (cc == PCI_CLASS_STORAGE_IDE) 973 scc_s = "IDE"; 974 else if (cc == PCI_CLASS_STORAGE_SATA) 975 scc_s = "SATA"; 976 else if (cc == PCI_CLASS_STORAGE_RAID) 977 scc_s = "RAID"; 978 else 979 scc_s = "unknown"; 980 981 ahci_print_info(host, scc_s); 982 } 983 984 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is 985 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't 986 * support PMP and the 4726 either directly exports the device 987 * attached to the first downstream port or acts as a hardware storage 988 * controller and emulate a single ATA device (can be RAID 0/1 or some 989 * other configuration). 990 * 991 * When there's no device attached to the first downstream port of the 992 * 4726, "Config Disk" appears, which is a pseudo ATA device to 993 * configure the 4726. However, ATA emulation of the device is very 994 * lame. It doesn't send signature D2H Reg FIS after the initial 995 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. 996 * 997 * The following function works around the problem by always using 998 * hardreset on the port and not depending on receiving signature FIS 999 * afterward. If signature FIS isn't received soon, ATA class is 1000 * assumed without follow-up softreset. 1001 */ 1002 static void ahci_p5wdh_workaround(struct ata_host *host) 1003 { 1004 static const struct dmi_system_id sysids[] = { 1005 { 1006 .ident = "P5W DH Deluxe", 1007 .matches = { 1008 DMI_MATCH(DMI_SYS_VENDOR, 1009 "ASUSTEK COMPUTER INC"), 1010 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), 1011 }, 1012 }, 1013 { } 1014 }; 1015 struct pci_dev *pdev = to_pci_dev(host->dev); 1016 1017 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && 1018 dmi_check_system(sysids)) { 1019 struct ata_port *ap = host->ports[1]; 1020 1021 dev_info(&pdev->dev, 1022 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n"); 1023 1024 ap->ops = &ahci_p5wdh_ops; 1025 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; 1026 } 1027 } 1028 1029 /* 1030 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when 1031 * booting in BIOS compatibility mode. We restore the registers but not ID. 1032 */ 1033 static void ahci_mcp89_apple_enable(struct pci_dev *pdev) 1034 { 1035 u32 val; 1036 1037 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n"); 1038 1039 pci_read_config_dword(pdev, 0xf8, &val); 1040 val |= 1 << 0x1b; 1041 /* the following changes the device ID, but appears not to affect function */ 1042 /* val = (val & ~0xf0000000) | 0x80000000; */ 1043 pci_write_config_dword(pdev, 0xf8, val); 1044 1045 pci_read_config_dword(pdev, 0x54c, &val); 1046 val |= 1 << 0xc; 1047 pci_write_config_dword(pdev, 0x54c, val); 1048 1049 pci_read_config_dword(pdev, 0x4a4, &val); 1050 val &= 0xff; 1051 val |= 0x01060100; 1052 pci_write_config_dword(pdev, 0x4a4, val); 1053 1054 pci_read_config_dword(pdev, 0x54c, &val); 1055 val &= ~(1 << 0xc); 1056 pci_write_config_dword(pdev, 0x54c, val); 1057 1058 pci_read_config_dword(pdev, 0xf8, &val); 1059 val &= ~(1 << 0x1b); 1060 pci_write_config_dword(pdev, 0xf8, val); 1061 } 1062 1063 static bool is_mcp89_apple(struct pci_dev *pdev) 1064 { 1065 return pdev->vendor == PCI_VENDOR_ID_NVIDIA && 1066 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA && 1067 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 1068 pdev->subsystem_device == 0xcb89; 1069 } 1070 1071 /* only some SB600 ahci controllers can do 64bit DMA */ 1072 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev) 1073 { 1074 static const struct dmi_system_id sysids[] = { 1075 /* 1076 * The oldest version known to be broken is 0901 and 1077 * working is 1501 which was released on 2007-10-26. 1078 * Enable 64bit DMA on 1501 and anything newer. 1079 * 1080 * Please read bko#9412 for more info. 1081 */ 1082 { 1083 .ident = "ASUS M2A-VM", 1084 .matches = { 1085 DMI_MATCH(DMI_BOARD_VENDOR, 1086 "ASUSTeK Computer INC."), 1087 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"), 1088 }, 1089 .driver_data = "20071026", /* yyyymmdd */ 1090 }, 1091 /* 1092 * All BIOS versions for the MSI K9A2 Platinum (MS-7376) 1093 * support 64bit DMA. 1094 * 1095 * BIOS versions earlier than 1.5 had the Manufacturer DMI 1096 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD". 1097 * This spelling mistake was fixed in BIOS version 1.5, so 1098 * 1.5 and later have the Manufacturer as 1099 * "MICRO-STAR INTERNATIONAL CO.,LTD". 1100 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER". 1101 * 1102 * BIOS versions earlier than 1.9 had a Board Product Name 1103 * DMI field of "MS-7376". This was changed to be 1104 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still 1105 * match on DMI_BOARD_NAME of "MS-7376". 1106 */ 1107 { 1108 .ident = "MSI K9A2 Platinum", 1109 .matches = { 1110 DMI_MATCH(DMI_BOARD_VENDOR, 1111 "MICRO-STAR INTER"), 1112 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"), 1113 }, 1114 }, 1115 /* 1116 * All BIOS versions for the MSI K9AGM2 (MS-7327) support 1117 * 64bit DMA. 1118 * 1119 * This board also had the typo mentioned above in the 1120 * Manufacturer DMI field (fixed in BIOS version 1.5), so 1121 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again. 1122 */ 1123 { 1124 .ident = "MSI K9AGM2", 1125 .matches = { 1126 DMI_MATCH(DMI_BOARD_VENDOR, 1127 "MICRO-STAR INTER"), 1128 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"), 1129 }, 1130 }, 1131 /* 1132 * All BIOS versions for the Asus M3A support 64bit DMA. 1133 * (all release versions from 0301 to 1206 were tested) 1134 */ 1135 { 1136 .ident = "ASUS M3A", 1137 .matches = { 1138 DMI_MATCH(DMI_BOARD_VENDOR, 1139 "ASUSTeK Computer INC."), 1140 DMI_MATCH(DMI_BOARD_NAME, "M3A"), 1141 }, 1142 }, 1143 { } 1144 }; 1145 const struct dmi_system_id *match; 1146 int year, month, date; 1147 char buf[9]; 1148 1149 match = dmi_first_match(sysids); 1150 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) || 1151 !match) 1152 return false; 1153 1154 if (!match->driver_data) 1155 goto enable_64bit; 1156 1157 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1158 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1159 1160 if (strcmp(buf, match->driver_data) >= 0) 1161 goto enable_64bit; 1162 else { 1163 dev_warn(&pdev->dev, 1164 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n", 1165 match->ident); 1166 return false; 1167 } 1168 1169 enable_64bit: 1170 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident); 1171 return true; 1172 } 1173 1174 static bool ahci_broken_system_poweroff(struct pci_dev *pdev) 1175 { 1176 static const struct dmi_system_id broken_systems[] = { 1177 { 1178 .ident = "HP Compaq nx6310", 1179 .matches = { 1180 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1181 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"), 1182 }, 1183 /* PCI slot number of the controller */ 1184 .driver_data = (void *)0x1FUL, 1185 }, 1186 { 1187 .ident = "HP Compaq 6720s", 1188 .matches = { 1189 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1190 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"), 1191 }, 1192 /* PCI slot number of the controller */ 1193 .driver_data = (void *)0x1FUL, 1194 }, 1195 1196 { } /* terminate list */ 1197 }; 1198 const struct dmi_system_id *dmi = dmi_first_match(broken_systems); 1199 1200 if (dmi) { 1201 unsigned long slot = (unsigned long)dmi->driver_data; 1202 /* apply the quirk only to on-board controllers */ 1203 return slot == PCI_SLOT(pdev->devfn); 1204 } 1205 1206 return false; 1207 } 1208 1209 static bool ahci_broken_suspend(struct pci_dev *pdev) 1210 { 1211 static const struct dmi_system_id sysids[] = { 1212 /* 1213 * On HP dv[4-6] and HDX18 with earlier BIOSen, link 1214 * to the harddisk doesn't become online after 1215 * resuming from STR. Warn and fail suspend. 1216 * 1217 * http://bugzilla.kernel.org/show_bug.cgi?id=12276 1218 * 1219 * Use dates instead of versions to match as HP is 1220 * apparently recycling both product and version 1221 * strings. 1222 * 1223 * http://bugzilla.kernel.org/show_bug.cgi?id=15462 1224 */ 1225 { 1226 .ident = "dv4", 1227 .matches = { 1228 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1229 DMI_MATCH(DMI_PRODUCT_NAME, 1230 "HP Pavilion dv4 Notebook PC"), 1231 }, 1232 .driver_data = "20090105", /* F.30 */ 1233 }, 1234 { 1235 .ident = "dv5", 1236 .matches = { 1237 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1238 DMI_MATCH(DMI_PRODUCT_NAME, 1239 "HP Pavilion dv5 Notebook PC"), 1240 }, 1241 .driver_data = "20090506", /* F.16 */ 1242 }, 1243 { 1244 .ident = "dv6", 1245 .matches = { 1246 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1247 DMI_MATCH(DMI_PRODUCT_NAME, 1248 "HP Pavilion dv6 Notebook PC"), 1249 }, 1250 .driver_data = "20090423", /* F.21 */ 1251 }, 1252 { 1253 .ident = "HDX18", 1254 .matches = { 1255 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1256 DMI_MATCH(DMI_PRODUCT_NAME, 1257 "HP HDX18 Notebook PC"), 1258 }, 1259 .driver_data = "20090430", /* F.23 */ 1260 }, 1261 /* 1262 * Acer eMachines G725 has the same problem. BIOS 1263 * V1.03 is known to be broken. V3.04 is known to 1264 * work. Between, there are V1.06, V2.06 and V3.03 1265 * that we don't have much idea about. For now, 1266 * blacklist anything older than V3.04. 1267 * 1268 * http://bugzilla.kernel.org/show_bug.cgi?id=15104 1269 */ 1270 { 1271 .ident = "G725", 1272 .matches = { 1273 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"), 1274 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"), 1275 }, 1276 .driver_data = "20091216", /* V3.04 */ 1277 }, 1278 { } /* terminate list */ 1279 }; 1280 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1281 int year, month, date; 1282 char buf[9]; 1283 1284 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2)) 1285 return false; 1286 1287 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1288 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1289 1290 return strcmp(buf, dmi->driver_data) < 0; 1291 } 1292 1293 static bool ahci_broken_lpm(struct pci_dev *pdev) 1294 { 1295 static const struct dmi_system_id sysids[] = { 1296 /* Various Lenovo 50 series have LPM issues with older BIOSen */ 1297 { 1298 .matches = { 1299 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1300 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"), 1301 }, 1302 .driver_data = "20180406", /* 1.31 */ 1303 }, 1304 { 1305 .matches = { 1306 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1307 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"), 1308 }, 1309 .driver_data = "20180420", /* 1.28 */ 1310 }, 1311 { 1312 .matches = { 1313 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1314 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"), 1315 }, 1316 .driver_data = "20180315", /* 1.33 */ 1317 }, 1318 { 1319 .matches = { 1320 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1321 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"), 1322 }, 1323 /* 1324 * Note date based on release notes, 2.35 has been 1325 * reported to be good, but I've been unable to get 1326 * a hold of the reporter to get the DMI BIOS date. 1327 * TODO: fix this. 1328 */ 1329 .driver_data = "20180310", /* 2.35 */ 1330 }, 1331 { } /* terminate list */ 1332 }; 1333 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1334 int year, month, date; 1335 char buf[9]; 1336 1337 if (!dmi) 1338 return false; 1339 1340 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1341 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1342 1343 return strcmp(buf, dmi->driver_data) < 0; 1344 } 1345 1346 static bool ahci_broken_online(struct pci_dev *pdev) 1347 { 1348 #define ENCODE_BUSDEVFN(bus, slot, func) \ 1349 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func))) 1350 static const struct dmi_system_id sysids[] = { 1351 /* 1352 * There are several gigabyte boards which use 1353 * SIMG5723s configured as hardware RAID. Certain 1354 * 5723 firmware revisions shipped there keep the link 1355 * online but fail to answer properly to SRST or 1356 * IDENTIFY when no device is attached downstream 1357 * causing libata to retry quite a few times leading 1358 * to excessive detection delay. 1359 * 1360 * As these firmwares respond to the second reset try 1361 * with invalid device signature, considering unknown 1362 * sig as offline works around the problem acceptably. 1363 */ 1364 { 1365 .ident = "EP45-DQ6", 1366 .matches = { 1367 DMI_MATCH(DMI_BOARD_VENDOR, 1368 "Gigabyte Technology Co., Ltd."), 1369 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"), 1370 }, 1371 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0), 1372 }, 1373 { 1374 .ident = "EP45-DS5", 1375 .matches = { 1376 DMI_MATCH(DMI_BOARD_VENDOR, 1377 "Gigabyte Technology Co., Ltd."), 1378 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"), 1379 }, 1380 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0), 1381 }, 1382 { } /* terminate list */ 1383 }; 1384 #undef ENCODE_BUSDEVFN 1385 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1386 unsigned int val; 1387 1388 if (!dmi) 1389 return false; 1390 1391 val = (unsigned long)dmi->driver_data; 1392 1393 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff); 1394 } 1395 1396 static bool ahci_broken_devslp(struct pci_dev *pdev) 1397 { 1398 /* device with broken DEVSLP but still showing SDS capability */ 1399 static const struct pci_device_id ids[] = { 1400 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */ 1401 {} 1402 }; 1403 1404 return pci_match_id(ids, pdev); 1405 } 1406 1407 #ifdef CONFIG_ATA_ACPI 1408 static void ahci_gtf_filter_workaround(struct ata_host *host) 1409 { 1410 static const struct dmi_system_id sysids[] = { 1411 /* 1412 * Aspire 3810T issues a bunch of SATA enable commands 1413 * via _GTF including an invalid one and one which is 1414 * rejected by the device. Among the successful ones 1415 * is FPDMA non-zero offset enable which when enabled 1416 * only on the drive side leads to NCQ command 1417 * failures. Filter it out. 1418 */ 1419 { 1420 .ident = "Aspire 3810T", 1421 .matches = { 1422 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1423 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"), 1424 }, 1425 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET, 1426 }, 1427 { } 1428 }; 1429 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1430 unsigned int filter; 1431 int i; 1432 1433 if (!dmi) 1434 return; 1435 1436 filter = (unsigned long)dmi->driver_data; 1437 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n", 1438 filter, dmi->ident); 1439 1440 for (i = 0; i < host->n_ports; i++) { 1441 struct ata_port *ap = host->ports[i]; 1442 struct ata_link *link; 1443 struct ata_device *dev; 1444 1445 ata_for_each_link(link, ap, EDGE) 1446 ata_for_each_dev(dev, link, ALL) 1447 dev->gtf_filter |= filter; 1448 } 1449 } 1450 #else 1451 static inline void ahci_gtf_filter_workaround(struct ata_host *host) 1452 {} 1453 #endif 1454 1455 /* 1456 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected 1457 * as DUMMY, or detected but eventually get a "link down" and never get up 1458 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the 1459 * port_map may hold a value of 0x00. 1460 * 1461 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports 1462 * and can significantly reduce the occurrence of the problem. 1463 * 1464 * https://bugzilla.kernel.org/show_bug.cgi?id=189471 1465 */ 1466 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv, 1467 struct pci_dev *pdev) 1468 { 1469 static const struct dmi_system_id sysids[] = { 1470 { 1471 .ident = "Acer Switch Alpha 12", 1472 .matches = { 1473 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1474 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271") 1475 }, 1476 }, 1477 { } 1478 }; 1479 1480 if (dmi_check_system(sysids)) { 1481 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n"); 1482 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) { 1483 hpriv->port_map = 0x7; 1484 hpriv->cap = 0xC734FF02; 1485 } 1486 } 1487 } 1488 1489 #ifdef CONFIG_ARM64 1490 /* 1491 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently. 1492 * Workaround is to make sure all pending IRQs are served before leaving 1493 * handler. 1494 */ 1495 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance) 1496 { 1497 struct ata_host *host = dev_instance; 1498 struct ahci_host_priv *hpriv; 1499 unsigned int rc = 0; 1500 void __iomem *mmio; 1501 u32 irq_stat, irq_masked; 1502 unsigned int handled = 1; 1503 1504 hpriv = host->private_data; 1505 mmio = hpriv->mmio; 1506 irq_stat = readl(mmio + HOST_IRQ_STAT); 1507 if (!irq_stat) 1508 return IRQ_NONE; 1509 1510 do { 1511 irq_masked = irq_stat & hpriv->port_map; 1512 spin_lock(&host->lock); 1513 rc = ahci_handle_port_intr(host, irq_masked); 1514 if (!rc) 1515 handled = 0; 1516 writel(irq_stat, mmio + HOST_IRQ_STAT); 1517 irq_stat = readl(mmio + HOST_IRQ_STAT); 1518 spin_unlock(&host->lock); 1519 } while (irq_stat); 1520 1521 return IRQ_RETVAL(handled); 1522 } 1523 #endif 1524 1525 static void ahci_remap_check(struct pci_dev *pdev, int bar, 1526 struct ahci_host_priv *hpriv) 1527 { 1528 int i; 1529 u32 cap; 1530 1531 /* 1532 * Check if this device might have remapped nvme devices. 1533 */ 1534 if (pdev->vendor != PCI_VENDOR_ID_INTEL || 1535 pci_resource_len(pdev, bar) < SZ_512K || 1536 bar != AHCI_PCI_BAR_STANDARD || 1537 !(readl(hpriv->mmio + AHCI_VSCAP) & 1)) 1538 return; 1539 1540 cap = readq(hpriv->mmio + AHCI_REMAP_CAP); 1541 for (i = 0; i < AHCI_MAX_REMAP; i++) { 1542 if ((cap & (1 << i)) == 0) 1543 continue; 1544 if (readl(hpriv->mmio + ahci_remap_dcc(i)) 1545 != PCI_CLASS_STORAGE_EXPRESS) 1546 continue; 1547 1548 /* We've found a remapped device */ 1549 hpriv->remapped_nvme++; 1550 } 1551 1552 if (!hpriv->remapped_nvme) 1553 return; 1554 1555 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n", 1556 hpriv->remapped_nvme); 1557 dev_warn(&pdev->dev, 1558 "Switch your BIOS from RAID to AHCI mode to use them.\n"); 1559 1560 /* 1561 * Don't rely on the msi-x capability in the remap case, 1562 * share the legacy interrupt across ahci and remapped devices. 1563 */ 1564 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1565 } 1566 1567 static int ahci_get_irq_vector(struct ata_host *host, int port) 1568 { 1569 return pci_irq_vector(to_pci_dev(host->dev), port); 1570 } 1571 1572 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports, 1573 struct ahci_host_priv *hpriv) 1574 { 1575 int nvec; 1576 1577 if (hpriv->flags & AHCI_HFLAG_NO_MSI) 1578 return -ENODEV; 1579 1580 /* 1581 * If number of MSIs is less than number of ports then Sharing Last 1582 * Message mode could be enforced. In this case assume that advantage 1583 * of multipe MSIs is negated and use single MSI mode instead. 1584 */ 1585 if (n_ports > 1) { 1586 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX, 1587 PCI_IRQ_MSIX | PCI_IRQ_MSI); 1588 if (nvec > 0) { 1589 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) { 1590 hpriv->get_irq_vector = ahci_get_irq_vector; 1591 hpriv->flags |= AHCI_HFLAG_MULTI_MSI; 1592 return nvec; 1593 } 1594 1595 /* 1596 * Fallback to single MSI mode if the controller 1597 * enforced MRSM mode. 1598 */ 1599 printk(KERN_INFO 1600 "ahci: MRSM is on, fallback to single MSI\n"); 1601 pci_free_irq_vectors(pdev); 1602 } 1603 } 1604 1605 /* 1606 * If the host is not capable of supporting per-port vectors, fall 1607 * back to single MSI before finally attempting single MSI-X. 1608 */ 1609 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 1610 if (nvec == 1) 1611 return nvec; 1612 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX); 1613 } 1614 1615 static void ahci_update_initial_lpm_policy(struct ata_port *ap, 1616 struct ahci_host_priv *hpriv) 1617 { 1618 int policy = CONFIG_SATA_MOBILE_LPM_POLICY; 1619 1620 1621 /* Ignore processing for chipsets that don't use policy */ 1622 if (!(hpriv->flags & AHCI_HFLAG_USE_LPM_POLICY)) 1623 return; 1624 1625 /* user modified policy via module param */ 1626 if (mobile_lpm_policy != -1) { 1627 policy = mobile_lpm_policy; 1628 goto update_policy; 1629 } 1630 1631 if (policy > ATA_LPM_MED_POWER && pm_suspend_default_s2idle()) { 1632 if (hpriv->cap & HOST_CAP_PART) 1633 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL; 1634 else if (hpriv->cap & HOST_CAP_SSC) 1635 policy = ATA_LPM_MIN_POWER; 1636 } 1637 1638 update_policy: 1639 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER) 1640 ap->target_lpm_policy = policy; 1641 } 1642 1643 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv) 1644 { 1645 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev); 1646 u16 tmp16; 1647 1648 /* 1649 * Only apply the 6-port PCS quirk for known legacy platforms. 1650 */ 1651 if (!id || id->vendor != PCI_VENDOR_ID_INTEL) 1652 return; 1653 1654 /* Skip applying the quirk on Denverton and beyond */ 1655 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7) 1656 return; 1657 1658 /* 1659 * port_map is determined from PORTS_IMPL PCI register which is 1660 * implemented as write or write-once register. If the register 1661 * isn't programmed, ahci automatically generates it from number 1662 * of ports, which is good enough for PCS programming. It is 1663 * otherwise expected that platform firmware enables the ports 1664 * before the OS boots. 1665 */ 1666 pci_read_config_word(pdev, PCS_6, &tmp16); 1667 if ((tmp16 & hpriv->port_map) != hpriv->port_map) { 1668 tmp16 |= hpriv->port_map; 1669 pci_write_config_word(pdev, PCS_6, tmp16); 1670 } 1671 } 1672 1673 static ssize_t remapped_nvme_show(struct device *dev, 1674 struct device_attribute *attr, 1675 char *buf) 1676 { 1677 struct ata_host *host = dev_get_drvdata(dev); 1678 struct ahci_host_priv *hpriv = host->private_data; 1679 1680 return sysfs_emit(buf, "%u\n", hpriv->remapped_nvme); 1681 } 1682 1683 static DEVICE_ATTR_RO(remapped_nvme); 1684 1685 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1686 { 1687 unsigned int board_id = ent->driver_data; 1688 struct ata_port_info pi = ahci_port_info[board_id]; 1689 const struct ata_port_info *ppi[] = { &pi, NULL }; 1690 struct device *dev = &pdev->dev; 1691 struct ahci_host_priv *hpriv; 1692 struct ata_host *host; 1693 int n_ports, i, rc; 1694 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD; 1695 1696 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS); 1697 1698 ata_print_version_once(&pdev->dev, DRV_VERSION); 1699 1700 /* The AHCI driver can only drive the SATA ports, the PATA driver 1701 can drive them all so if both drivers are selected make sure 1702 AHCI stays out of the way */ 1703 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable) 1704 return -ENODEV; 1705 1706 /* Apple BIOS on MCP89 prevents us using AHCI */ 1707 if (is_mcp89_apple(pdev)) 1708 ahci_mcp89_apple_enable(pdev); 1709 1710 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode. 1711 * At the moment, we can only use the AHCI mode. Let the users know 1712 * that for SAS drives they're out of luck. 1713 */ 1714 if (pdev->vendor == PCI_VENDOR_ID_PROMISE) 1715 dev_info(&pdev->dev, 1716 "PDC42819 can only drive SATA devices with this driver\n"); 1717 1718 /* Some devices use non-standard BARs */ 1719 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06) 1720 ahci_pci_bar = AHCI_PCI_BAR_STA2X11; 1721 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000) 1722 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS; 1723 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) { 1724 if (pdev->device == 0xa01c) 1725 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM; 1726 if (pdev->device == 0xa084) 1727 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5; 1728 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) { 1729 if (pdev->device == 0x7a08) 1730 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON; 1731 } 1732 1733 /* acquire resources */ 1734 rc = pcim_enable_device(pdev); 1735 if (rc) 1736 return rc; 1737 1738 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 1739 (pdev->device == 0x2652 || pdev->device == 0x2653)) { 1740 u8 map; 1741 1742 /* ICH6s share the same PCI ID for both piix and ahci 1743 * modes. Enabling ahci mode while MAP indicates 1744 * combined mode is a bad idea. Yield to ata_piix. 1745 */ 1746 pci_read_config_byte(pdev, ICH_MAP, &map); 1747 if (map & 0x3) { 1748 dev_info(&pdev->dev, 1749 "controller is in combined mode, can't enable AHCI mode\n"); 1750 return -ENODEV; 1751 } 1752 } 1753 1754 /* AHCI controllers often implement SFF compatible interface. 1755 * Grab all PCI BARs just in case. 1756 */ 1757 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME); 1758 if (rc == -EBUSY) 1759 pcim_pin_device(pdev); 1760 if (rc) 1761 return rc; 1762 1763 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1764 if (!hpriv) 1765 return -ENOMEM; 1766 hpriv->flags |= (unsigned long)pi.private_data; 1767 1768 /* MCP65 revision A1 and A2 can't do MSI */ 1769 if (board_id == board_ahci_mcp65 && 1770 (pdev->revision == 0xa1 || pdev->revision == 0xa2)) 1771 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1772 1773 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */ 1774 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40) 1775 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL; 1776 1777 /* only some SB600s can do 64bit DMA */ 1778 if (ahci_sb600_enable_64bit(pdev)) 1779 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY; 1780 1781 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar]; 1782 1783 /* detect remapped nvme devices */ 1784 ahci_remap_check(pdev, ahci_pci_bar, hpriv); 1785 1786 sysfs_add_file_to_group(&pdev->dev.kobj, 1787 &dev_attr_remapped_nvme.attr, 1788 NULL); 1789 1790 /* must set flag prior to save config in order to take effect */ 1791 if (ahci_broken_devslp(pdev)) 1792 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP; 1793 1794 #ifdef CONFIG_ARM64 1795 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI && 1796 pdev->device == 0xa235 && 1797 pdev->revision < 0x30) 1798 hpriv->flags |= AHCI_HFLAG_NO_SXS; 1799 1800 if (pdev->vendor == 0x177d && pdev->device == 0xa01c) 1801 hpriv->irq_handler = ahci_thunderx_irq_handler; 1802 #endif 1803 1804 /* save initial config */ 1805 ahci_pci_save_initial_config(pdev, hpriv); 1806 1807 /* prepare host */ 1808 if (hpriv->cap & HOST_CAP_NCQ) { 1809 pi.flags |= ATA_FLAG_NCQ; 1810 /* 1811 * Auto-activate optimization is supposed to be 1812 * supported on all AHCI controllers indicating NCQ 1813 * capability, but it seems to be broken on some 1814 * chipsets including NVIDIAs. 1815 */ 1816 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA)) 1817 pi.flags |= ATA_FLAG_FPDMA_AA; 1818 1819 /* 1820 * All AHCI controllers should be forward-compatible 1821 * with the new auxiliary field. This code should be 1822 * conditionalized if any buggy AHCI controllers are 1823 * encountered. 1824 */ 1825 pi.flags |= ATA_FLAG_FPDMA_AUX; 1826 } 1827 1828 if (hpriv->cap & HOST_CAP_PMP) 1829 pi.flags |= ATA_FLAG_PMP; 1830 1831 ahci_set_em_messages(hpriv, &pi); 1832 1833 if (ahci_broken_system_poweroff(pdev)) { 1834 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN; 1835 dev_info(&pdev->dev, 1836 "quirky BIOS, skipping spindown on poweroff\n"); 1837 } 1838 1839 if (ahci_broken_lpm(pdev)) { 1840 pi.flags |= ATA_FLAG_NO_LPM; 1841 dev_warn(&pdev->dev, 1842 "BIOS update required for Link Power Management support\n"); 1843 } 1844 1845 if (ahci_broken_suspend(pdev)) { 1846 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND; 1847 dev_warn(&pdev->dev, 1848 "BIOS update required for suspend/resume\n"); 1849 } 1850 1851 if (ahci_broken_online(pdev)) { 1852 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE; 1853 dev_info(&pdev->dev, 1854 "online status unreliable, applying workaround\n"); 1855 } 1856 1857 1858 /* Acer SA5-271 workaround modifies private_data */ 1859 acer_sa5_271_workaround(hpriv, pdev); 1860 1861 /* CAP.NP sometimes indicate the index of the last enabled 1862 * port, at other times, that of the last possible port, so 1863 * determining the maximum port number requires looking at 1864 * both CAP.NP and port_map. 1865 */ 1866 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); 1867 1868 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 1869 if (!host) 1870 return -ENOMEM; 1871 host->private_data = hpriv; 1872 1873 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) { 1874 /* legacy intx interrupts */ 1875 pci_intx(pdev, 1); 1876 } 1877 hpriv->irq = pci_irq_vector(pdev, 0); 1878 1879 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) 1880 host->flags |= ATA_HOST_PARALLEL_SCAN; 1881 else 1882 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n"); 1883 1884 if (pi.flags & ATA_FLAG_EM) 1885 ahci_reset_em(host); 1886 1887 for (i = 0; i < host->n_ports; i++) { 1888 struct ata_port *ap = host->ports[i]; 1889 1890 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar"); 1891 ata_port_pbar_desc(ap, ahci_pci_bar, 1892 0x100 + ap->port_no * 0x80, "port"); 1893 1894 /* set enclosure management message type */ 1895 if (ap->flags & ATA_FLAG_EM) 1896 ap->em_message_type = hpriv->em_msg_type; 1897 1898 ahci_update_initial_lpm_policy(ap, hpriv); 1899 1900 /* disabled/not-implemented port */ 1901 if (!(hpriv->port_map & (1 << i))) 1902 ap->ops = &ata_dummy_port_ops; 1903 } 1904 1905 /* apply workaround for ASUS P5W DH Deluxe mainboard */ 1906 ahci_p5wdh_workaround(host); 1907 1908 /* apply gtf filter quirk */ 1909 ahci_gtf_filter_workaround(host); 1910 1911 /* initialize adapter */ 1912 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); 1913 if (rc) 1914 return rc; 1915 1916 rc = ahci_pci_reset_controller(host); 1917 if (rc) 1918 return rc; 1919 1920 ahci_pci_init_controller(host); 1921 ahci_pci_print_info(host); 1922 1923 pci_set_master(pdev); 1924 1925 rc = ahci_host_activate(host, &ahci_sht); 1926 if (rc) 1927 return rc; 1928 1929 pm_runtime_put_noidle(&pdev->dev); 1930 return 0; 1931 } 1932 1933 static void ahci_shutdown_one(struct pci_dev *pdev) 1934 { 1935 ata_pci_shutdown_one(pdev); 1936 } 1937 1938 static void ahci_remove_one(struct pci_dev *pdev) 1939 { 1940 sysfs_remove_file_from_group(&pdev->dev.kobj, 1941 &dev_attr_remapped_nvme.attr, 1942 NULL); 1943 pm_runtime_get_noresume(&pdev->dev); 1944 ata_pci_remove_one(pdev); 1945 } 1946 1947 module_pci_driver(ahci_pci_driver); 1948 1949 MODULE_AUTHOR("Jeff Garzik"); 1950 MODULE_DESCRIPTION("AHCI SATA low-level driver"); 1951 MODULE_LICENSE("GPL"); 1952 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); 1953 MODULE_VERSION(DRV_VERSION); 1954