1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ahci.c - AHCI SATA support 4 * 5 * Maintained by: Tejun Heo <tj@kernel.org> 6 * Please ALWAYS copy linux-ide@vger.kernel.org 7 * on emails. 8 * 9 * Copyright 2004-2005 Red Hat, Inc. 10 * 11 * libata documentation is available via 'make {ps|pdf}docs', 12 * as Documentation/driver-api/libata.rst 13 * 14 * AHCI hardware documentation: 15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/blkdev.h> 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/device.h> 27 #include <linux/dmi.h> 28 #include <linux/gfp.h> 29 #include <linux/msi.h> 30 #include <scsi/scsi_host.h> 31 #include <scsi/scsi_cmnd.h> 32 #include <linux/libata.h> 33 #include <linux/ahci-remap.h> 34 #include <linux/io-64-nonatomic-lo-hi.h> 35 #include "ahci.h" 36 37 #define DRV_NAME "ahci" 38 #define DRV_VERSION "3.0" 39 40 enum { 41 AHCI_PCI_BAR_STA2X11 = 0, 42 AHCI_PCI_BAR_CAVIUM = 0, 43 AHCI_PCI_BAR_LOONGSON = 0, 44 AHCI_PCI_BAR_ENMOTUS = 2, 45 AHCI_PCI_BAR_CAVIUM_GEN5 = 4, 46 AHCI_PCI_BAR_STANDARD = 5, 47 }; 48 49 enum board_ids { 50 /* board IDs by feature in alphabetical order */ 51 board_ahci, 52 board_ahci_ign_iferr, 53 board_ahci_mobile, 54 board_ahci_nomsi, 55 board_ahci_noncq, 56 board_ahci_nosntf, 57 board_ahci_yes_fbs, 58 59 /* board IDs for specific chipsets in alphabetical order */ 60 board_ahci_al, 61 board_ahci_avn, 62 board_ahci_mcp65, 63 board_ahci_mcp77, 64 board_ahci_mcp89, 65 board_ahci_mv, 66 board_ahci_sb600, 67 board_ahci_sb700, /* for SB700 and SB800 */ 68 board_ahci_vt8251, 69 70 /* 71 * board IDs for Intel chipsets that support more than 6 ports 72 * *and* end up needing the PCS quirk. 73 */ 74 board_ahci_pcs7, 75 76 /* aliases */ 77 board_ahci_mcp_linux = board_ahci_mcp65, 78 board_ahci_mcp67 = board_ahci_mcp65, 79 board_ahci_mcp73 = board_ahci_mcp65, 80 board_ahci_mcp79 = board_ahci_mcp77, 81 }; 82 83 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 84 static void ahci_remove_one(struct pci_dev *dev); 85 static void ahci_shutdown_one(struct pci_dev *dev); 86 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 87 unsigned long deadline); 88 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 89 unsigned long deadline); 90 static void ahci_mcp89_apple_enable(struct pci_dev *pdev); 91 static bool is_mcp89_apple(struct pci_dev *pdev); 92 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 93 unsigned long deadline); 94 #ifdef CONFIG_PM 95 static int ahci_pci_device_runtime_suspend(struct device *dev); 96 static int ahci_pci_device_runtime_resume(struct device *dev); 97 #ifdef CONFIG_PM_SLEEP 98 static int ahci_pci_device_suspend(struct device *dev); 99 static int ahci_pci_device_resume(struct device *dev); 100 #endif 101 #endif /* CONFIG_PM */ 102 103 static struct scsi_host_template ahci_sht = { 104 AHCI_SHT("ahci"), 105 }; 106 107 static struct ata_port_operations ahci_vt8251_ops = { 108 .inherits = &ahci_ops, 109 .hardreset = ahci_vt8251_hardreset, 110 }; 111 112 static struct ata_port_operations ahci_p5wdh_ops = { 113 .inherits = &ahci_ops, 114 .hardreset = ahci_p5wdh_hardreset, 115 }; 116 117 static struct ata_port_operations ahci_avn_ops = { 118 .inherits = &ahci_ops, 119 .hardreset = ahci_avn_hardreset, 120 }; 121 122 static const struct ata_port_info ahci_port_info[] = { 123 /* by features */ 124 [board_ahci] = { 125 .flags = AHCI_FLAG_COMMON, 126 .pio_mask = ATA_PIO4, 127 .udma_mask = ATA_UDMA6, 128 .port_ops = &ahci_ops, 129 }, 130 [board_ahci_ign_iferr] = { 131 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), 132 .flags = AHCI_FLAG_COMMON, 133 .pio_mask = ATA_PIO4, 134 .udma_mask = ATA_UDMA6, 135 .port_ops = &ahci_ops, 136 }, 137 [board_ahci_mobile] = { 138 AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE), 139 .flags = AHCI_FLAG_COMMON, 140 .pio_mask = ATA_PIO4, 141 .udma_mask = ATA_UDMA6, 142 .port_ops = &ahci_ops, 143 }, 144 [board_ahci_nomsi] = { 145 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI), 146 .flags = AHCI_FLAG_COMMON, 147 .pio_mask = ATA_PIO4, 148 .udma_mask = ATA_UDMA6, 149 .port_ops = &ahci_ops, 150 }, 151 [board_ahci_noncq] = { 152 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ), 153 .flags = AHCI_FLAG_COMMON, 154 .pio_mask = ATA_PIO4, 155 .udma_mask = ATA_UDMA6, 156 .port_ops = &ahci_ops, 157 }, 158 [board_ahci_nosntf] = { 159 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF), 160 .flags = AHCI_FLAG_COMMON, 161 .pio_mask = ATA_PIO4, 162 .udma_mask = ATA_UDMA6, 163 .port_ops = &ahci_ops, 164 }, 165 [board_ahci_yes_fbs] = { 166 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS), 167 .flags = AHCI_FLAG_COMMON, 168 .pio_mask = ATA_PIO4, 169 .udma_mask = ATA_UDMA6, 170 .port_ops = &ahci_ops, 171 }, 172 /* by chipsets */ 173 [board_ahci_al] = { 174 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI), 175 .flags = AHCI_FLAG_COMMON, 176 .pio_mask = ATA_PIO4, 177 .udma_mask = ATA_UDMA6, 178 .port_ops = &ahci_ops, 179 }, 180 [board_ahci_avn] = { 181 .flags = AHCI_FLAG_COMMON, 182 .pio_mask = ATA_PIO4, 183 .udma_mask = ATA_UDMA6, 184 .port_ops = &ahci_avn_ops, 185 }, 186 [board_ahci_mcp65] = { 187 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP | 188 AHCI_HFLAG_YES_NCQ), 189 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM, 190 .pio_mask = ATA_PIO4, 191 .udma_mask = ATA_UDMA6, 192 .port_ops = &ahci_ops, 193 }, 194 [board_ahci_mcp77] = { 195 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP), 196 .flags = AHCI_FLAG_COMMON, 197 .pio_mask = ATA_PIO4, 198 .udma_mask = ATA_UDMA6, 199 .port_ops = &ahci_ops, 200 }, 201 [board_ahci_mcp89] = { 202 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA), 203 .flags = AHCI_FLAG_COMMON, 204 .pio_mask = ATA_PIO4, 205 .udma_mask = ATA_UDMA6, 206 .port_ops = &ahci_ops, 207 }, 208 [board_ahci_mv] = { 209 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | 210 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP), 211 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, 212 .pio_mask = ATA_PIO4, 213 .udma_mask = ATA_UDMA6, 214 .port_ops = &ahci_ops, 215 }, 216 [board_ahci_sb600] = { 217 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | 218 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 | 219 AHCI_HFLAG_32BIT_ONLY), 220 .flags = AHCI_FLAG_COMMON, 221 .pio_mask = ATA_PIO4, 222 .udma_mask = ATA_UDMA6, 223 .port_ops = &ahci_pmp_retry_srst_ops, 224 }, 225 [board_ahci_sb700] = { /* for SB700 and SB800 */ 226 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL), 227 .flags = AHCI_FLAG_COMMON, 228 .pio_mask = ATA_PIO4, 229 .udma_mask = ATA_UDMA6, 230 .port_ops = &ahci_pmp_retry_srst_ops, 231 }, 232 [board_ahci_vt8251] = { 233 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), 234 .flags = AHCI_FLAG_COMMON, 235 .pio_mask = ATA_PIO4, 236 .udma_mask = ATA_UDMA6, 237 .port_ops = &ahci_vt8251_ops, 238 }, 239 [board_ahci_pcs7] = { 240 .flags = AHCI_FLAG_COMMON, 241 .pio_mask = ATA_PIO4, 242 .udma_mask = ATA_UDMA6, 243 .port_ops = &ahci_ops, 244 }, 245 }; 246 247 static const struct pci_device_id ahci_pci_tbl[] = { 248 /* Intel */ 249 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */ 250 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ 251 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ 252 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ 253 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ 254 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ 255 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ 256 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ 257 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ 258 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ 259 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ 260 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ 261 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8/Lewisburg RAID*/ 262 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ 263 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ 264 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ 265 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ 266 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ 267 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ 268 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ 269 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ 270 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */ 271 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */ 272 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */ 273 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */ 274 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */ 275 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ 276 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */ 277 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ 278 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ 279 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */ 280 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */ 281 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */ 282 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */ 283 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */ 284 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */ 285 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */ 286 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */ 287 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */ 288 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */ 289 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */ 290 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */ 291 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */ 292 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */ 293 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */ 294 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */ 295 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */ 296 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */ 297 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */ 298 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */ 299 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */ 300 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */ 301 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */ 302 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */ 303 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */ 304 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */ 305 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */ 306 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */ 307 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */ 308 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */ 309 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */ 310 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */ 311 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */ 312 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */ 313 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */ 314 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */ 315 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */ 316 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */ 317 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */ 318 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */ 319 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG/Lewisburg RAID*/ 320 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */ 321 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */ 322 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */ 323 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */ 324 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */ 325 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */ 326 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */ 327 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */ 328 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */ 329 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */ 330 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */ 331 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */ 332 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */ 333 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */ 334 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */ 335 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */ 336 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */ 337 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */ 338 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */ 339 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */ 340 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */ 341 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */ 342 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */ 343 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */ 344 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */ 345 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */ 346 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */ 347 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */ 348 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */ 349 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */ 350 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */ 351 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */ 352 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */ 353 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */ 354 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */ 355 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */ 356 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */ 357 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */ 358 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */ 359 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */ 360 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */ 361 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg/Lewisburg AHCI*/ 362 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg/Lewisburg RAID*/ 363 { PCI_VDEVICE(INTEL, 0x43d4), board_ahci }, /* Rocket Lake PCH-H RAID */ 364 { PCI_VDEVICE(INTEL, 0x43d5), board_ahci }, /* Rocket Lake PCH-H RAID */ 365 { PCI_VDEVICE(INTEL, 0x43d6), board_ahci }, /* Rocket Lake PCH-H RAID */ 366 { PCI_VDEVICE(INTEL, 0x43d7), board_ahci }, /* Rocket Lake PCH-H RAID */ 367 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */ 368 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */ 369 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */ 370 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */ 371 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */ 372 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */ 373 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */ 374 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */ 375 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */ 376 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */ 377 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */ 378 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */ 379 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */ 380 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */ 381 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */ 382 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */ 383 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */ 384 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */ 385 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */ 386 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */ 387 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */ 388 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */ 389 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */ 390 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */ 391 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */ 392 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */ 393 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */ 394 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */ 395 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */ 396 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */ 397 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/ 398 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/ 399 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/ 400 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/ 401 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/ 402 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/ 403 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/ 404 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/ 405 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */ 406 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */ 407 { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */ 408 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */ 409 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */ 410 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */ 411 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */ 412 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */ 413 { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_mobile }, /* Comet Lake PCH-U AHCI */ 414 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_mobile }, /* Comet Lake PCH RAID */ 415 416 /* JMicron 360/1/3/5/6, match class to avoid IDE function */ 417 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 418 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, 419 /* JMicron 362B and 362C have an AHCI function with IDE class code */ 420 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr }, 421 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr }, 422 /* May need to update quirk_jmicron_async_suspend() for additions */ 423 424 /* ATI */ 425 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ 426 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ 427 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ 428 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ 429 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ 430 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ 431 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ 432 433 /* Amazon's Annapurna Labs support */ 434 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031), 435 .class = PCI_CLASS_STORAGE_SATA_AHCI, 436 .class_mask = 0xffffff, 437 board_ahci_al }, 438 /* AMD */ 439 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */ 440 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */ 441 { PCI_VDEVICE(AMD, 0x7901), board_ahci_mobile }, /* AMD Green Sardine */ 442 /* AMD is using RAID class only for ahci controllers */ 443 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 444 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci }, 445 446 /* Dell S140/S150 */ 447 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID, 448 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci }, 449 450 /* VIA */ 451 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ 452 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ 453 454 /* NVIDIA */ 455 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */ 456 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */ 457 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */ 458 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */ 459 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */ 460 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */ 461 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */ 462 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */ 463 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */ 464 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */ 465 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */ 466 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */ 467 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */ 468 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */ 469 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */ 470 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */ 471 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */ 472 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */ 473 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */ 474 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */ 475 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */ 476 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */ 477 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */ 478 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */ 479 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */ 480 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */ 481 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */ 482 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */ 483 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */ 484 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */ 485 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */ 486 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */ 487 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */ 488 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */ 489 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */ 490 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */ 491 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */ 492 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */ 493 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */ 494 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */ 495 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */ 496 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */ 497 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */ 498 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */ 499 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */ 500 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */ 501 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */ 502 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */ 503 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */ 504 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */ 505 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */ 506 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */ 507 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */ 508 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */ 509 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */ 510 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */ 511 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */ 512 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */ 513 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */ 514 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */ 515 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */ 516 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */ 517 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */ 518 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */ 519 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */ 520 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */ 521 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */ 522 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */ 523 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */ 524 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */ 525 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */ 526 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */ 527 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */ 528 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */ 529 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */ 530 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */ 531 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */ 532 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */ 533 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */ 534 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */ 535 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */ 536 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */ 537 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */ 538 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */ 539 540 /* SiS */ 541 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ 542 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */ 543 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ 544 545 /* ST Microelectronics */ 546 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */ 547 548 /* Marvell */ 549 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ 550 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ 551 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123), 552 .class = PCI_CLASS_STORAGE_SATA_AHCI, 553 .class_mask = 0xffffff, 554 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */ 555 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125), 556 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */ 557 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178, 558 PCI_VENDOR_ID_MARVELL_EXT, 0x9170), 559 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */ 560 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a), 561 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 562 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172), 563 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */ 564 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182), 565 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 566 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192), 567 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */ 568 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0), 569 .driver_data = board_ahci_yes_fbs }, 570 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */ 571 .driver_data = board_ahci_yes_fbs }, 572 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3), 573 .driver_data = board_ahci_yes_fbs }, 574 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230), 575 .driver_data = board_ahci_yes_fbs }, 576 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */ 577 .driver_data = board_ahci_yes_fbs }, 578 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */ 579 .driver_data = board_ahci_yes_fbs }, 580 581 /* Promise */ 582 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */ 583 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */ 584 585 /* Asmedia */ 586 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */ 587 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */ 588 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */ 589 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */ 590 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */ 591 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */ 592 { PCI_VDEVICE(ASMEDIA, 0x0624), board_ahci }, /* ASM1062+JMB575 */ 593 594 /* 595 * Samsung SSDs found on some macbooks. NCQ times out if MSI is 596 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731 597 */ 598 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi }, 599 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi }, 600 601 /* Enmotus */ 602 { PCI_DEVICE(0x1c44, 0x8000), board_ahci }, 603 604 /* Loongson */ 605 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci }, 606 607 /* Generic, PCI class code for AHCI */ 608 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 609 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, 610 611 { } /* terminate list */ 612 }; 613 614 static const struct dev_pm_ops ahci_pci_pm_ops = { 615 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume) 616 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend, 617 ahci_pci_device_runtime_resume, NULL) 618 }; 619 620 static struct pci_driver ahci_pci_driver = { 621 .name = DRV_NAME, 622 .id_table = ahci_pci_tbl, 623 .probe = ahci_init_one, 624 .remove = ahci_remove_one, 625 .shutdown = ahci_shutdown_one, 626 .driver = { 627 .pm = &ahci_pci_pm_ops, 628 }, 629 }; 630 631 #if IS_ENABLED(CONFIG_PATA_MARVELL) 632 static int marvell_enable; 633 #else 634 static int marvell_enable = 1; 635 #endif 636 module_param(marvell_enable, int, 0644); 637 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)"); 638 639 static int mobile_lpm_policy = -1; 640 module_param(mobile_lpm_policy, int, 0644); 641 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets"); 642 643 static void ahci_pci_save_initial_config(struct pci_dev *pdev, 644 struct ahci_host_priv *hpriv) 645 { 646 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) { 647 dev_info(&pdev->dev, "JMB361 has only one port\n"); 648 hpriv->force_port_map = 1; 649 } 650 651 /* 652 * Temporary Marvell 6145 hack: PATA port presence 653 * is asserted through the standard AHCI port 654 * presence register, as bit 4 (counting from 0) 655 */ 656 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 657 if (pdev->device == 0x6121) 658 hpriv->mask_port_map = 0x3; 659 else 660 hpriv->mask_port_map = 0xf; 661 dev_info(&pdev->dev, 662 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n"); 663 } 664 665 ahci_save_initial_config(&pdev->dev, hpriv); 666 } 667 668 static void ahci_pci_init_controller(struct ata_host *host) 669 { 670 struct ahci_host_priv *hpriv = host->private_data; 671 struct pci_dev *pdev = to_pci_dev(host->dev); 672 void __iomem *port_mmio; 673 u32 tmp; 674 int mv; 675 676 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 677 if (pdev->device == 0x6121) 678 mv = 2; 679 else 680 mv = 4; 681 port_mmio = __ahci_port_base(host, mv); 682 683 writel(0, port_mmio + PORT_IRQ_MASK); 684 685 /* clear port IRQ */ 686 tmp = readl(port_mmio + PORT_IRQ_STAT); 687 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 688 if (tmp) 689 writel(tmp, port_mmio + PORT_IRQ_STAT); 690 } 691 692 ahci_init_controller(host); 693 } 694 695 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 696 unsigned long deadline) 697 { 698 struct ata_port *ap = link->ap; 699 struct ahci_host_priv *hpriv = ap->host->private_data; 700 bool online; 701 int rc; 702 703 DPRINTK("ENTER\n"); 704 705 hpriv->stop_engine(ap); 706 707 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 708 deadline, &online, NULL); 709 710 hpriv->start_engine(ap); 711 712 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 713 714 /* vt8251 doesn't clear BSY on signature FIS reception, 715 * request follow-up softreset. 716 */ 717 return online ? -EAGAIN : rc; 718 } 719 720 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 721 unsigned long deadline) 722 { 723 struct ata_port *ap = link->ap; 724 struct ahci_port_priv *pp = ap->private_data; 725 struct ahci_host_priv *hpriv = ap->host->private_data; 726 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 727 struct ata_taskfile tf; 728 bool online; 729 int rc; 730 731 hpriv->stop_engine(ap); 732 733 /* clear D2H reception area to properly wait for D2H FIS */ 734 ata_tf_init(link->device, &tf); 735 tf.command = ATA_BUSY; 736 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 737 738 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 739 deadline, &online, NULL); 740 741 hpriv->start_engine(ap); 742 743 /* The pseudo configuration device on SIMG4726 attached to 744 * ASUS P5W-DH Deluxe doesn't send signature FIS after 745 * hardreset if no device is attached to the first downstream 746 * port && the pseudo device locks up on SRST w/ PMP==0. To 747 * work around this, wait for !BSY only briefly. If BSY isn't 748 * cleared, perform CLO and proceed to IDENTIFY (achieved by 749 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). 750 * 751 * Wait for two seconds. Devices attached to downstream port 752 * which can't process the following IDENTIFY after this will 753 * have to be reset again. For most cases, this should 754 * suffice while making probing snappish enough. 755 */ 756 if (online) { 757 rc = ata_wait_after_reset(link, jiffies + 2 * HZ, 758 ahci_check_ready); 759 if (rc) 760 ahci_kick_engine(ap); 761 } 762 return rc; 763 } 764 765 /* 766 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports. 767 * 768 * It has been observed with some SSDs that the timing of events in the 769 * link synchronization phase can leave the port in a state that can not 770 * be recovered by a SATA-hard-reset alone. The failing signature is 771 * SStatus.DET stuck at 1 ("Device presence detected but Phy 772 * communication not established"). It was found that unloading and 773 * reloading the driver when this problem occurs allows the drive 774 * connection to be recovered (DET advanced to 0x3). The critical 775 * component of reloading the driver is that the port state machines are 776 * reset by bouncing "port enable" in the AHCI PCS configuration 777 * register. So, reproduce that effect by bouncing a port whenever we 778 * see DET==1 after a reset. 779 */ 780 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 781 unsigned long deadline) 782 { 783 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 784 struct ata_port *ap = link->ap; 785 struct ahci_port_priv *pp = ap->private_data; 786 struct ahci_host_priv *hpriv = ap->host->private_data; 787 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 788 unsigned long tmo = deadline - jiffies; 789 struct ata_taskfile tf; 790 bool online; 791 int rc, i; 792 793 DPRINTK("ENTER\n"); 794 795 hpriv->stop_engine(ap); 796 797 for (i = 0; i < 2; i++) { 798 u16 val; 799 u32 sstatus; 800 int port = ap->port_no; 801 struct ata_host *host = ap->host; 802 struct pci_dev *pdev = to_pci_dev(host->dev); 803 804 /* clear D2H reception area to properly wait for D2H FIS */ 805 ata_tf_init(link->device, &tf); 806 tf.command = ATA_BUSY; 807 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 808 809 rc = sata_link_hardreset(link, timing, deadline, &online, 810 ahci_check_ready); 811 812 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 || 813 (sstatus & 0xf) != 1) 814 break; 815 816 ata_link_info(link, "avn bounce port%d\n", port); 817 818 pci_read_config_word(pdev, 0x92, &val); 819 val &= ~(1 << port); 820 pci_write_config_word(pdev, 0x92, val); 821 ata_msleep(ap, 1000); 822 val |= 1 << port; 823 pci_write_config_word(pdev, 0x92, val); 824 deadline += tmo; 825 } 826 827 hpriv->start_engine(ap); 828 829 if (online) 830 *class = ahci_dev_classify(ap); 831 832 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 833 return rc; 834 } 835 836 837 #ifdef CONFIG_PM 838 static void ahci_pci_disable_interrupts(struct ata_host *host) 839 { 840 struct ahci_host_priv *hpriv = host->private_data; 841 void __iomem *mmio = hpriv->mmio; 842 u32 ctl; 843 844 /* AHCI spec rev1.1 section 8.3.3: 845 * Software must disable interrupts prior to requesting a 846 * transition of the HBA to D3 state. 847 */ 848 ctl = readl(mmio + HOST_CTL); 849 ctl &= ~HOST_IRQ_EN; 850 writel(ctl, mmio + HOST_CTL); 851 readl(mmio + HOST_CTL); /* flush */ 852 } 853 854 static int ahci_pci_device_runtime_suspend(struct device *dev) 855 { 856 struct pci_dev *pdev = to_pci_dev(dev); 857 struct ata_host *host = pci_get_drvdata(pdev); 858 859 ahci_pci_disable_interrupts(host); 860 return 0; 861 } 862 863 static int ahci_pci_device_runtime_resume(struct device *dev) 864 { 865 struct pci_dev *pdev = to_pci_dev(dev); 866 struct ata_host *host = pci_get_drvdata(pdev); 867 int rc; 868 869 rc = ahci_reset_controller(host); 870 if (rc) 871 return rc; 872 ahci_pci_init_controller(host); 873 return 0; 874 } 875 876 #ifdef CONFIG_PM_SLEEP 877 static int ahci_pci_device_suspend(struct device *dev) 878 { 879 struct pci_dev *pdev = to_pci_dev(dev); 880 struct ata_host *host = pci_get_drvdata(pdev); 881 struct ahci_host_priv *hpriv = host->private_data; 882 883 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { 884 dev_err(&pdev->dev, 885 "BIOS update required for suspend/resume\n"); 886 return -EIO; 887 } 888 889 ahci_pci_disable_interrupts(host); 890 return ata_host_suspend(host, PMSG_SUSPEND); 891 } 892 893 static int ahci_pci_device_resume(struct device *dev) 894 { 895 struct pci_dev *pdev = to_pci_dev(dev); 896 struct ata_host *host = pci_get_drvdata(pdev); 897 int rc; 898 899 /* Apple BIOS helpfully mangles the registers on resume */ 900 if (is_mcp89_apple(pdev)) 901 ahci_mcp89_apple_enable(pdev); 902 903 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { 904 rc = ahci_reset_controller(host); 905 if (rc) 906 return rc; 907 908 ahci_pci_init_controller(host); 909 } 910 911 ata_host_resume(host); 912 913 return 0; 914 } 915 #endif 916 917 #endif /* CONFIG_PM */ 918 919 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) 920 { 921 const int dma_bits = using_dac ? 64 : 32; 922 int rc; 923 924 /* 925 * If the device fixup already set the dma_mask to some non-standard 926 * value, don't extend it here. This happens on STA2X11, for example. 927 * 928 * XXX: manipulating the DMA mask from platform code is completely 929 * bogus, platform code should use dev->bus_dma_limit instead.. 930 */ 931 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32)) 932 return 0; 933 934 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits)); 935 if (rc) 936 dev_err(&pdev->dev, "DMA enable failed\n"); 937 return rc; 938 } 939 940 static void ahci_pci_print_info(struct ata_host *host) 941 { 942 struct pci_dev *pdev = to_pci_dev(host->dev); 943 u16 cc; 944 const char *scc_s; 945 946 pci_read_config_word(pdev, 0x0a, &cc); 947 if (cc == PCI_CLASS_STORAGE_IDE) 948 scc_s = "IDE"; 949 else if (cc == PCI_CLASS_STORAGE_SATA) 950 scc_s = "SATA"; 951 else if (cc == PCI_CLASS_STORAGE_RAID) 952 scc_s = "RAID"; 953 else 954 scc_s = "unknown"; 955 956 ahci_print_info(host, scc_s); 957 } 958 959 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is 960 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't 961 * support PMP and the 4726 either directly exports the device 962 * attached to the first downstream port or acts as a hardware storage 963 * controller and emulate a single ATA device (can be RAID 0/1 or some 964 * other configuration). 965 * 966 * When there's no device attached to the first downstream port of the 967 * 4726, "Config Disk" appears, which is a pseudo ATA device to 968 * configure the 4726. However, ATA emulation of the device is very 969 * lame. It doesn't send signature D2H Reg FIS after the initial 970 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. 971 * 972 * The following function works around the problem by always using 973 * hardreset on the port and not depending on receiving signature FIS 974 * afterward. If signature FIS isn't received soon, ATA class is 975 * assumed without follow-up softreset. 976 */ 977 static void ahci_p5wdh_workaround(struct ata_host *host) 978 { 979 static const struct dmi_system_id sysids[] = { 980 { 981 .ident = "P5W DH Deluxe", 982 .matches = { 983 DMI_MATCH(DMI_SYS_VENDOR, 984 "ASUSTEK COMPUTER INC"), 985 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), 986 }, 987 }, 988 { } 989 }; 990 struct pci_dev *pdev = to_pci_dev(host->dev); 991 992 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && 993 dmi_check_system(sysids)) { 994 struct ata_port *ap = host->ports[1]; 995 996 dev_info(&pdev->dev, 997 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n"); 998 999 ap->ops = &ahci_p5wdh_ops; 1000 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; 1001 } 1002 } 1003 1004 /* 1005 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when 1006 * booting in BIOS compatibility mode. We restore the registers but not ID. 1007 */ 1008 static void ahci_mcp89_apple_enable(struct pci_dev *pdev) 1009 { 1010 u32 val; 1011 1012 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n"); 1013 1014 pci_read_config_dword(pdev, 0xf8, &val); 1015 val |= 1 << 0x1b; 1016 /* the following changes the device ID, but appears not to affect function */ 1017 /* val = (val & ~0xf0000000) | 0x80000000; */ 1018 pci_write_config_dword(pdev, 0xf8, val); 1019 1020 pci_read_config_dword(pdev, 0x54c, &val); 1021 val |= 1 << 0xc; 1022 pci_write_config_dword(pdev, 0x54c, val); 1023 1024 pci_read_config_dword(pdev, 0x4a4, &val); 1025 val &= 0xff; 1026 val |= 0x01060100; 1027 pci_write_config_dword(pdev, 0x4a4, val); 1028 1029 pci_read_config_dword(pdev, 0x54c, &val); 1030 val &= ~(1 << 0xc); 1031 pci_write_config_dword(pdev, 0x54c, val); 1032 1033 pci_read_config_dword(pdev, 0xf8, &val); 1034 val &= ~(1 << 0x1b); 1035 pci_write_config_dword(pdev, 0xf8, val); 1036 } 1037 1038 static bool is_mcp89_apple(struct pci_dev *pdev) 1039 { 1040 return pdev->vendor == PCI_VENDOR_ID_NVIDIA && 1041 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA && 1042 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 1043 pdev->subsystem_device == 0xcb89; 1044 } 1045 1046 /* only some SB600 ahci controllers can do 64bit DMA */ 1047 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev) 1048 { 1049 static const struct dmi_system_id sysids[] = { 1050 /* 1051 * The oldest version known to be broken is 0901 and 1052 * working is 1501 which was released on 2007-10-26. 1053 * Enable 64bit DMA on 1501 and anything newer. 1054 * 1055 * Please read bko#9412 for more info. 1056 */ 1057 { 1058 .ident = "ASUS M2A-VM", 1059 .matches = { 1060 DMI_MATCH(DMI_BOARD_VENDOR, 1061 "ASUSTeK Computer INC."), 1062 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"), 1063 }, 1064 .driver_data = "20071026", /* yyyymmdd */ 1065 }, 1066 /* 1067 * All BIOS versions for the MSI K9A2 Platinum (MS-7376) 1068 * support 64bit DMA. 1069 * 1070 * BIOS versions earlier than 1.5 had the Manufacturer DMI 1071 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD". 1072 * This spelling mistake was fixed in BIOS version 1.5, so 1073 * 1.5 and later have the Manufacturer as 1074 * "MICRO-STAR INTERNATIONAL CO.,LTD". 1075 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER". 1076 * 1077 * BIOS versions earlier than 1.9 had a Board Product Name 1078 * DMI field of "MS-7376". This was changed to be 1079 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still 1080 * match on DMI_BOARD_NAME of "MS-7376". 1081 */ 1082 { 1083 .ident = "MSI K9A2 Platinum", 1084 .matches = { 1085 DMI_MATCH(DMI_BOARD_VENDOR, 1086 "MICRO-STAR INTER"), 1087 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"), 1088 }, 1089 }, 1090 /* 1091 * All BIOS versions for the MSI K9AGM2 (MS-7327) support 1092 * 64bit DMA. 1093 * 1094 * This board also had the typo mentioned above in the 1095 * Manufacturer DMI field (fixed in BIOS version 1.5), so 1096 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again. 1097 */ 1098 { 1099 .ident = "MSI K9AGM2", 1100 .matches = { 1101 DMI_MATCH(DMI_BOARD_VENDOR, 1102 "MICRO-STAR INTER"), 1103 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"), 1104 }, 1105 }, 1106 /* 1107 * All BIOS versions for the Asus M3A support 64bit DMA. 1108 * (all release versions from 0301 to 1206 were tested) 1109 */ 1110 { 1111 .ident = "ASUS M3A", 1112 .matches = { 1113 DMI_MATCH(DMI_BOARD_VENDOR, 1114 "ASUSTeK Computer INC."), 1115 DMI_MATCH(DMI_BOARD_NAME, "M3A"), 1116 }, 1117 }, 1118 { } 1119 }; 1120 const struct dmi_system_id *match; 1121 int year, month, date; 1122 char buf[9]; 1123 1124 match = dmi_first_match(sysids); 1125 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) || 1126 !match) 1127 return false; 1128 1129 if (!match->driver_data) 1130 goto enable_64bit; 1131 1132 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1133 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1134 1135 if (strcmp(buf, match->driver_data) >= 0) 1136 goto enable_64bit; 1137 else { 1138 dev_warn(&pdev->dev, 1139 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n", 1140 match->ident); 1141 return false; 1142 } 1143 1144 enable_64bit: 1145 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident); 1146 return true; 1147 } 1148 1149 static bool ahci_broken_system_poweroff(struct pci_dev *pdev) 1150 { 1151 static const struct dmi_system_id broken_systems[] = { 1152 { 1153 .ident = "HP Compaq nx6310", 1154 .matches = { 1155 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1156 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"), 1157 }, 1158 /* PCI slot number of the controller */ 1159 .driver_data = (void *)0x1FUL, 1160 }, 1161 { 1162 .ident = "HP Compaq 6720s", 1163 .matches = { 1164 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1165 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"), 1166 }, 1167 /* PCI slot number of the controller */ 1168 .driver_data = (void *)0x1FUL, 1169 }, 1170 1171 { } /* terminate list */ 1172 }; 1173 const struct dmi_system_id *dmi = dmi_first_match(broken_systems); 1174 1175 if (dmi) { 1176 unsigned long slot = (unsigned long)dmi->driver_data; 1177 /* apply the quirk only to on-board controllers */ 1178 return slot == PCI_SLOT(pdev->devfn); 1179 } 1180 1181 return false; 1182 } 1183 1184 static bool ahci_broken_suspend(struct pci_dev *pdev) 1185 { 1186 static const struct dmi_system_id sysids[] = { 1187 /* 1188 * On HP dv[4-6] and HDX18 with earlier BIOSen, link 1189 * to the harddisk doesn't become online after 1190 * resuming from STR. Warn and fail suspend. 1191 * 1192 * http://bugzilla.kernel.org/show_bug.cgi?id=12276 1193 * 1194 * Use dates instead of versions to match as HP is 1195 * apparently recycling both product and version 1196 * strings. 1197 * 1198 * http://bugzilla.kernel.org/show_bug.cgi?id=15462 1199 */ 1200 { 1201 .ident = "dv4", 1202 .matches = { 1203 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1204 DMI_MATCH(DMI_PRODUCT_NAME, 1205 "HP Pavilion dv4 Notebook PC"), 1206 }, 1207 .driver_data = "20090105", /* F.30 */ 1208 }, 1209 { 1210 .ident = "dv5", 1211 .matches = { 1212 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1213 DMI_MATCH(DMI_PRODUCT_NAME, 1214 "HP Pavilion dv5 Notebook PC"), 1215 }, 1216 .driver_data = "20090506", /* F.16 */ 1217 }, 1218 { 1219 .ident = "dv6", 1220 .matches = { 1221 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1222 DMI_MATCH(DMI_PRODUCT_NAME, 1223 "HP Pavilion dv6 Notebook PC"), 1224 }, 1225 .driver_data = "20090423", /* F.21 */ 1226 }, 1227 { 1228 .ident = "HDX18", 1229 .matches = { 1230 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1231 DMI_MATCH(DMI_PRODUCT_NAME, 1232 "HP HDX18 Notebook PC"), 1233 }, 1234 .driver_data = "20090430", /* F.23 */ 1235 }, 1236 /* 1237 * Acer eMachines G725 has the same problem. BIOS 1238 * V1.03 is known to be broken. V3.04 is known to 1239 * work. Between, there are V1.06, V2.06 and V3.03 1240 * that we don't have much idea about. For now, 1241 * blacklist anything older than V3.04. 1242 * 1243 * http://bugzilla.kernel.org/show_bug.cgi?id=15104 1244 */ 1245 { 1246 .ident = "G725", 1247 .matches = { 1248 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"), 1249 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"), 1250 }, 1251 .driver_data = "20091216", /* V3.04 */ 1252 }, 1253 { } /* terminate list */ 1254 }; 1255 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1256 int year, month, date; 1257 char buf[9]; 1258 1259 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2)) 1260 return false; 1261 1262 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1263 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1264 1265 return strcmp(buf, dmi->driver_data) < 0; 1266 } 1267 1268 static bool ahci_broken_lpm(struct pci_dev *pdev) 1269 { 1270 static const struct dmi_system_id sysids[] = { 1271 /* Various Lenovo 50 series have LPM issues with older BIOSen */ 1272 { 1273 .matches = { 1274 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1275 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"), 1276 }, 1277 .driver_data = "20180406", /* 1.31 */ 1278 }, 1279 { 1280 .matches = { 1281 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1282 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"), 1283 }, 1284 .driver_data = "20180420", /* 1.28 */ 1285 }, 1286 { 1287 .matches = { 1288 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1289 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"), 1290 }, 1291 .driver_data = "20180315", /* 1.33 */ 1292 }, 1293 { 1294 .matches = { 1295 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1296 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"), 1297 }, 1298 /* 1299 * Note date based on release notes, 2.35 has been 1300 * reported to be good, but I've been unable to get 1301 * a hold of the reporter to get the DMI BIOS date. 1302 * TODO: fix this. 1303 */ 1304 .driver_data = "20180310", /* 2.35 */ 1305 }, 1306 { } /* terminate list */ 1307 }; 1308 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1309 int year, month, date; 1310 char buf[9]; 1311 1312 if (!dmi) 1313 return false; 1314 1315 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1316 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1317 1318 return strcmp(buf, dmi->driver_data) < 0; 1319 } 1320 1321 static bool ahci_broken_online(struct pci_dev *pdev) 1322 { 1323 #define ENCODE_BUSDEVFN(bus, slot, func) \ 1324 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func))) 1325 static const struct dmi_system_id sysids[] = { 1326 /* 1327 * There are several gigabyte boards which use 1328 * SIMG5723s configured as hardware RAID. Certain 1329 * 5723 firmware revisions shipped there keep the link 1330 * online but fail to answer properly to SRST or 1331 * IDENTIFY when no device is attached downstream 1332 * causing libata to retry quite a few times leading 1333 * to excessive detection delay. 1334 * 1335 * As these firmwares respond to the second reset try 1336 * with invalid device signature, considering unknown 1337 * sig as offline works around the problem acceptably. 1338 */ 1339 { 1340 .ident = "EP45-DQ6", 1341 .matches = { 1342 DMI_MATCH(DMI_BOARD_VENDOR, 1343 "Gigabyte Technology Co., Ltd."), 1344 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"), 1345 }, 1346 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0), 1347 }, 1348 { 1349 .ident = "EP45-DS5", 1350 .matches = { 1351 DMI_MATCH(DMI_BOARD_VENDOR, 1352 "Gigabyte Technology Co., Ltd."), 1353 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"), 1354 }, 1355 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0), 1356 }, 1357 { } /* terminate list */ 1358 }; 1359 #undef ENCODE_BUSDEVFN 1360 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1361 unsigned int val; 1362 1363 if (!dmi) 1364 return false; 1365 1366 val = (unsigned long)dmi->driver_data; 1367 1368 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff); 1369 } 1370 1371 static bool ahci_broken_devslp(struct pci_dev *pdev) 1372 { 1373 /* device with broken DEVSLP but still showing SDS capability */ 1374 static const struct pci_device_id ids[] = { 1375 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */ 1376 {} 1377 }; 1378 1379 return pci_match_id(ids, pdev); 1380 } 1381 1382 #ifdef CONFIG_ATA_ACPI 1383 static void ahci_gtf_filter_workaround(struct ata_host *host) 1384 { 1385 static const struct dmi_system_id sysids[] = { 1386 /* 1387 * Aspire 3810T issues a bunch of SATA enable commands 1388 * via _GTF including an invalid one and one which is 1389 * rejected by the device. Among the successful ones 1390 * is FPDMA non-zero offset enable which when enabled 1391 * only on the drive side leads to NCQ command 1392 * failures. Filter it out. 1393 */ 1394 { 1395 .ident = "Aspire 3810T", 1396 .matches = { 1397 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1398 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"), 1399 }, 1400 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET, 1401 }, 1402 { } 1403 }; 1404 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1405 unsigned int filter; 1406 int i; 1407 1408 if (!dmi) 1409 return; 1410 1411 filter = (unsigned long)dmi->driver_data; 1412 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n", 1413 filter, dmi->ident); 1414 1415 for (i = 0; i < host->n_ports; i++) { 1416 struct ata_port *ap = host->ports[i]; 1417 struct ata_link *link; 1418 struct ata_device *dev; 1419 1420 ata_for_each_link(link, ap, EDGE) 1421 ata_for_each_dev(dev, link, ALL) 1422 dev->gtf_filter |= filter; 1423 } 1424 } 1425 #else 1426 static inline void ahci_gtf_filter_workaround(struct ata_host *host) 1427 {} 1428 #endif 1429 1430 /* 1431 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected 1432 * as DUMMY, or detected but eventually get a "link down" and never get up 1433 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the 1434 * port_map may hold a value of 0x00. 1435 * 1436 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports 1437 * and can significantly reduce the occurrence of the problem. 1438 * 1439 * https://bugzilla.kernel.org/show_bug.cgi?id=189471 1440 */ 1441 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv, 1442 struct pci_dev *pdev) 1443 { 1444 static const struct dmi_system_id sysids[] = { 1445 { 1446 .ident = "Acer Switch Alpha 12", 1447 .matches = { 1448 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1449 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271") 1450 }, 1451 }, 1452 { } 1453 }; 1454 1455 if (dmi_check_system(sysids)) { 1456 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n"); 1457 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) { 1458 hpriv->port_map = 0x7; 1459 hpriv->cap = 0xC734FF02; 1460 } 1461 } 1462 } 1463 1464 #ifdef CONFIG_ARM64 1465 /* 1466 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently. 1467 * Workaround is to make sure all pending IRQs are served before leaving 1468 * handler. 1469 */ 1470 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance) 1471 { 1472 struct ata_host *host = dev_instance; 1473 struct ahci_host_priv *hpriv; 1474 unsigned int rc = 0; 1475 void __iomem *mmio; 1476 u32 irq_stat, irq_masked; 1477 unsigned int handled = 1; 1478 1479 VPRINTK("ENTER\n"); 1480 hpriv = host->private_data; 1481 mmio = hpriv->mmio; 1482 irq_stat = readl(mmio + HOST_IRQ_STAT); 1483 if (!irq_stat) 1484 return IRQ_NONE; 1485 1486 do { 1487 irq_masked = irq_stat & hpriv->port_map; 1488 spin_lock(&host->lock); 1489 rc = ahci_handle_port_intr(host, irq_masked); 1490 if (!rc) 1491 handled = 0; 1492 writel(irq_stat, mmio + HOST_IRQ_STAT); 1493 irq_stat = readl(mmio + HOST_IRQ_STAT); 1494 spin_unlock(&host->lock); 1495 } while (irq_stat); 1496 VPRINTK("EXIT\n"); 1497 1498 return IRQ_RETVAL(handled); 1499 } 1500 #endif 1501 1502 static void ahci_remap_check(struct pci_dev *pdev, int bar, 1503 struct ahci_host_priv *hpriv) 1504 { 1505 int i; 1506 u32 cap; 1507 1508 /* 1509 * Check if this device might have remapped nvme devices. 1510 */ 1511 if (pdev->vendor != PCI_VENDOR_ID_INTEL || 1512 pci_resource_len(pdev, bar) < SZ_512K || 1513 bar != AHCI_PCI_BAR_STANDARD || 1514 !(readl(hpriv->mmio + AHCI_VSCAP) & 1)) 1515 return; 1516 1517 cap = readq(hpriv->mmio + AHCI_REMAP_CAP); 1518 for (i = 0; i < AHCI_MAX_REMAP; i++) { 1519 if ((cap & (1 << i)) == 0) 1520 continue; 1521 if (readl(hpriv->mmio + ahci_remap_dcc(i)) 1522 != PCI_CLASS_STORAGE_EXPRESS) 1523 continue; 1524 1525 /* We've found a remapped device */ 1526 hpriv->remapped_nvme++; 1527 } 1528 1529 if (!hpriv->remapped_nvme) 1530 return; 1531 1532 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n", 1533 hpriv->remapped_nvme); 1534 dev_warn(&pdev->dev, 1535 "Switch your BIOS from RAID to AHCI mode to use them.\n"); 1536 1537 /* 1538 * Don't rely on the msi-x capability in the remap case, 1539 * share the legacy interrupt across ahci and remapped devices. 1540 */ 1541 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1542 } 1543 1544 static int ahci_get_irq_vector(struct ata_host *host, int port) 1545 { 1546 return pci_irq_vector(to_pci_dev(host->dev), port); 1547 } 1548 1549 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports, 1550 struct ahci_host_priv *hpriv) 1551 { 1552 int nvec; 1553 1554 if (hpriv->flags & AHCI_HFLAG_NO_MSI) 1555 return -ENODEV; 1556 1557 /* 1558 * If number of MSIs is less than number of ports then Sharing Last 1559 * Message mode could be enforced. In this case assume that advantage 1560 * of multipe MSIs is negated and use single MSI mode instead. 1561 */ 1562 if (n_ports > 1) { 1563 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX, 1564 PCI_IRQ_MSIX | PCI_IRQ_MSI); 1565 if (nvec > 0) { 1566 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) { 1567 hpriv->get_irq_vector = ahci_get_irq_vector; 1568 hpriv->flags |= AHCI_HFLAG_MULTI_MSI; 1569 return nvec; 1570 } 1571 1572 /* 1573 * Fallback to single MSI mode if the controller 1574 * enforced MRSM mode. 1575 */ 1576 printk(KERN_INFO 1577 "ahci: MRSM is on, fallback to single MSI\n"); 1578 pci_free_irq_vectors(pdev); 1579 } 1580 } 1581 1582 /* 1583 * If the host is not capable of supporting per-port vectors, fall 1584 * back to single MSI before finally attempting single MSI-X. 1585 */ 1586 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 1587 if (nvec == 1) 1588 return nvec; 1589 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX); 1590 } 1591 1592 static void ahci_update_initial_lpm_policy(struct ata_port *ap, 1593 struct ahci_host_priv *hpriv) 1594 { 1595 int policy = CONFIG_SATA_MOBILE_LPM_POLICY; 1596 1597 1598 /* Ignore processing for non mobile platforms */ 1599 if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE)) 1600 return; 1601 1602 /* user modified policy via module param */ 1603 if (mobile_lpm_policy != -1) { 1604 policy = mobile_lpm_policy; 1605 goto update_policy; 1606 } 1607 1608 #ifdef CONFIG_ACPI 1609 if (policy > ATA_LPM_MED_POWER && 1610 (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) { 1611 if (hpriv->cap & HOST_CAP_PART) 1612 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL; 1613 else if (hpriv->cap & HOST_CAP_SSC) 1614 policy = ATA_LPM_MIN_POWER; 1615 } 1616 #endif 1617 1618 update_policy: 1619 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER) 1620 ap->target_lpm_policy = policy; 1621 } 1622 1623 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv) 1624 { 1625 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev); 1626 u16 tmp16; 1627 1628 /* 1629 * Only apply the 6-port PCS quirk for known legacy platforms. 1630 */ 1631 if (!id || id->vendor != PCI_VENDOR_ID_INTEL) 1632 return; 1633 1634 /* Skip applying the quirk on Denverton and beyond */ 1635 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7) 1636 return; 1637 1638 /* 1639 * port_map is determined from PORTS_IMPL PCI register which is 1640 * implemented as write or write-once register. If the register 1641 * isn't programmed, ahci automatically generates it from number 1642 * of ports, which is good enough for PCS programming. It is 1643 * otherwise expected that platform firmware enables the ports 1644 * before the OS boots. 1645 */ 1646 pci_read_config_word(pdev, PCS_6, &tmp16); 1647 if ((tmp16 & hpriv->port_map) != hpriv->port_map) { 1648 tmp16 |= hpriv->port_map; 1649 pci_write_config_word(pdev, PCS_6, tmp16); 1650 } 1651 } 1652 1653 static ssize_t remapped_nvme_show(struct device *dev, 1654 struct device_attribute *attr, 1655 char *buf) 1656 { 1657 struct ata_host *host = dev_get_drvdata(dev); 1658 struct ahci_host_priv *hpriv = host->private_data; 1659 1660 return sprintf(buf, "%u\n", hpriv->remapped_nvme); 1661 } 1662 1663 static DEVICE_ATTR_RO(remapped_nvme); 1664 1665 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1666 { 1667 unsigned int board_id = ent->driver_data; 1668 struct ata_port_info pi = ahci_port_info[board_id]; 1669 const struct ata_port_info *ppi[] = { &pi, NULL }; 1670 struct device *dev = &pdev->dev; 1671 struct ahci_host_priv *hpriv; 1672 struct ata_host *host; 1673 int n_ports, i, rc; 1674 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD; 1675 1676 VPRINTK("ENTER\n"); 1677 1678 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS); 1679 1680 ata_print_version_once(&pdev->dev, DRV_VERSION); 1681 1682 /* The AHCI driver can only drive the SATA ports, the PATA driver 1683 can drive them all so if both drivers are selected make sure 1684 AHCI stays out of the way */ 1685 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable) 1686 return -ENODEV; 1687 1688 /* Apple BIOS on MCP89 prevents us using AHCI */ 1689 if (is_mcp89_apple(pdev)) 1690 ahci_mcp89_apple_enable(pdev); 1691 1692 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode. 1693 * At the moment, we can only use the AHCI mode. Let the users know 1694 * that for SAS drives they're out of luck. 1695 */ 1696 if (pdev->vendor == PCI_VENDOR_ID_PROMISE) 1697 dev_info(&pdev->dev, 1698 "PDC42819 can only drive SATA devices with this driver\n"); 1699 1700 /* Some devices use non-standard BARs */ 1701 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06) 1702 ahci_pci_bar = AHCI_PCI_BAR_STA2X11; 1703 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000) 1704 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS; 1705 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) { 1706 if (pdev->device == 0xa01c) 1707 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM; 1708 if (pdev->device == 0xa084) 1709 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5; 1710 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) { 1711 if (pdev->device == 0x7a08) 1712 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON; 1713 } 1714 1715 /* acquire resources */ 1716 rc = pcim_enable_device(pdev); 1717 if (rc) 1718 return rc; 1719 1720 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 1721 (pdev->device == 0x2652 || pdev->device == 0x2653)) { 1722 u8 map; 1723 1724 /* ICH6s share the same PCI ID for both piix and ahci 1725 * modes. Enabling ahci mode while MAP indicates 1726 * combined mode is a bad idea. Yield to ata_piix. 1727 */ 1728 pci_read_config_byte(pdev, ICH_MAP, &map); 1729 if (map & 0x3) { 1730 dev_info(&pdev->dev, 1731 "controller is in combined mode, can't enable AHCI mode\n"); 1732 return -ENODEV; 1733 } 1734 } 1735 1736 /* AHCI controllers often implement SFF compatible interface. 1737 * Grab all PCI BARs just in case. 1738 */ 1739 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME); 1740 if (rc == -EBUSY) 1741 pcim_pin_device(pdev); 1742 if (rc) 1743 return rc; 1744 1745 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1746 if (!hpriv) 1747 return -ENOMEM; 1748 hpriv->flags |= (unsigned long)pi.private_data; 1749 1750 /* MCP65 revision A1 and A2 can't do MSI */ 1751 if (board_id == board_ahci_mcp65 && 1752 (pdev->revision == 0xa1 || pdev->revision == 0xa2)) 1753 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1754 1755 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */ 1756 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40) 1757 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL; 1758 1759 /* only some SB600s can do 64bit DMA */ 1760 if (ahci_sb600_enable_64bit(pdev)) 1761 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY; 1762 1763 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar]; 1764 1765 /* detect remapped nvme devices */ 1766 ahci_remap_check(pdev, ahci_pci_bar, hpriv); 1767 1768 sysfs_add_file_to_group(&pdev->dev.kobj, 1769 &dev_attr_remapped_nvme.attr, 1770 NULL); 1771 1772 /* must set flag prior to save config in order to take effect */ 1773 if (ahci_broken_devslp(pdev)) 1774 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP; 1775 1776 #ifdef CONFIG_ARM64 1777 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI && 1778 pdev->device == 0xa235 && 1779 pdev->revision < 0x30) 1780 hpriv->flags |= AHCI_HFLAG_NO_SXS; 1781 1782 if (pdev->vendor == 0x177d && pdev->device == 0xa01c) 1783 hpriv->irq_handler = ahci_thunderx_irq_handler; 1784 #endif 1785 1786 /* save initial config */ 1787 ahci_pci_save_initial_config(pdev, hpriv); 1788 1789 /* 1790 * If platform firmware failed to enable ports, try to enable 1791 * them here. 1792 */ 1793 ahci_intel_pcs_quirk(pdev, hpriv); 1794 1795 /* prepare host */ 1796 if (hpriv->cap & HOST_CAP_NCQ) { 1797 pi.flags |= ATA_FLAG_NCQ; 1798 /* 1799 * Auto-activate optimization is supposed to be 1800 * supported on all AHCI controllers indicating NCQ 1801 * capability, but it seems to be broken on some 1802 * chipsets including NVIDIAs. 1803 */ 1804 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA)) 1805 pi.flags |= ATA_FLAG_FPDMA_AA; 1806 1807 /* 1808 * All AHCI controllers should be forward-compatible 1809 * with the new auxiliary field. This code should be 1810 * conditionalized if any buggy AHCI controllers are 1811 * encountered. 1812 */ 1813 pi.flags |= ATA_FLAG_FPDMA_AUX; 1814 } 1815 1816 if (hpriv->cap & HOST_CAP_PMP) 1817 pi.flags |= ATA_FLAG_PMP; 1818 1819 ahci_set_em_messages(hpriv, &pi); 1820 1821 if (ahci_broken_system_poweroff(pdev)) { 1822 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN; 1823 dev_info(&pdev->dev, 1824 "quirky BIOS, skipping spindown on poweroff\n"); 1825 } 1826 1827 if (ahci_broken_lpm(pdev)) { 1828 pi.flags |= ATA_FLAG_NO_LPM; 1829 dev_warn(&pdev->dev, 1830 "BIOS update required for Link Power Management support\n"); 1831 } 1832 1833 if (ahci_broken_suspend(pdev)) { 1834 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND; 1835 dev_warn(&pdev->dev, 1836 "BIOS update required for suspend/resume\n"); 1837 } 1838 1839 if (ahci_broken_online(pdev)) { 1840 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE; 1841 dev_info(&pdev->dev, 1842 "online status unreliable, applying workaround\n"); 1843 } 1844 1845 1846 /* Acer SA5-271 workaround modifies private_data */ 1847 acer_sa5_271_workaround(hpriv, pdev); 1848 1849 /* CAP.NP sometimes indicate the index of the last enabled 1850 * port, at other times, that of the last possible port, so 1851 * determining the maximum port number requires looking at 1852 * both CAP.NP and port_map. 1853 */ 1854 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); 1855 1856 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 1857 if (!host) 1858 return -ENOMEM; 1859 host->private_data = hpriv; 1860 1861 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) { 1862 /* legacy intx interrupts */ 1863 pci_intx(pdev, 1); 1864 } 1865 hpriv->irq = pci_irq_vector(pdev, 0); 1866 1867 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) 1868 host->flags |= ATA_HOST_PARALLEL_SCAN; 1869 else 1870 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n"); 1871 1872 if (pi.flags & ATA_FLAG_EM) 1873 ahci_reset_em(host); 1874 1875 for (i = 0; i < host->n_ports; i++) { 1876 struct ata_port *ap = host->ports[i]; 1877 1878 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar"); 1879 ata_port_pbar_desc(ap, ahci_pci_bar, 1880 0x100 + ap->port_no * 0x80, "port"); 1881 1882 /* set enclosure management message type */ 1883 if (ap->flags & ATA_FLAG_EM) 1884 ap->em_message_type = hpriv->em_msg_type; 1885 1886 ahci_update_initial_lpm_policy(ap, hpriv); 1887 1888 /* disabled/not-implemented port */ 1889 if (!(hpriv->port_map & (1 << i))) 1890 ap->ops = &ata_dummy_port_ops; 1891 } 1892 1893 /* apply workaround for ASUS P5W DH Deluxe mainboard */ 1894 ahci_p5wdh_workaround(host); 1895 1896 /* apply gtf filter quirk */ 1897 ahci_gtf_filter_workaround(host); 1898 1899 /* initialize adapter */ 1900 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); 1901 if (rc) 1902 return rc; 1903 1904 rc = ahci_reset_controller(host); 1905 if (rc) 1906 return rc; 1907 1908 ahci_pci_init_controller(host); 1909 ahci_pci_print_info(host); 1910 1911 pci_set_master(pdev); 1912 1913 rc = ahci_host_activate(host, &ahci_sht); 1914 if (rc) 1915 return rc; 1916 1917 pm_runtime_put_noidle(&pdev->dev); 1918 return 0; 1919 } 1920 1921 static void ahci_shutdown_one(struct pci_dev *pdev) 1922 { 1923 ata_pci_shutdown_one(pdev); 1924 } 1925 1926 static void ahci_remove_one(struct pci_dev *pdev) 1927 { 1928 sysfs_remove_file_from_group(&pdev->dev.kobj, 1929 &dev_attr_remapped_nvme.attr, 1930 NULL); 1931 pm_runtime_get_noresume(&pdev->dev); 1932 ata_pci_remove_one(pdev); 1933 } 1934 1935 module_pci_driver(ahci_pci_driver); 1936 1937 MODULE_AUTHOR("Jeff Garzik"); 1938 MODULE_DESCRIPTION("AHCI SATA low-level driver"); 1939 MODULE_LICENSE("GPL"); 1940 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); 1941 MODULE_VERSION(DRV_VERSION); 1942