1 /* 2 * ahci.c - AHCI SATA support 3 * 4 * Maintained by: Tejun Heo <tj@kernel.org> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2004-2005 Red Hat, Inc. 9 * 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; see the file COPYING. If not, write to 23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * 26 * libata documentation is available via 'make {ps|pdf}docs', 27 * as Documentation/DocBook/libata.* 28 * 29 * AHCI hardware documentation: 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 32 * 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/module.h> 37 #include <linux/pci.h> 38 #include <linux/blkdev.h> 39 #include <linux/delay.h> 40 #include <linux/interrupt.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/device.h> 43 #include <linux/dmi.h> 44 #include <linux/gfp.h> 45 #include <scsi/scsi_host.h> 46 #include <scsi/scsi_cmnd.h> 47 #include <linux/libata.h> 48 #include "ahci.h" 49 50 #define DRV_NAME "ahci" 51 #define DRV_VERSION "3.0" 52 53 enum { 54 AHCI_PCI_BAR_STA2X11 = 0, 55 AHCI_PCI_BAR_ENMOTUS = 2, 56 AHCI_PCI_BAR_STANDARD = 5, 57 }; 58 59 enum board_ids { 60 /* board IDs by feature in alphabetical order */ 61 board_ahci, 62 board_ahci_ign_iferr, 63 board_ahci_nomsi, 64 board_ahci_noncq, 65 board_ahci_nosntf, 66 board_ahci_yes_fbs, 67 68 /* board IDs for specific chipsets in alphabetical order */ 69 board_ahci_avn, 70 board_ahci_mcp65, 71 board_ahci_mcp77, 72 board_ahci_mcp89, 73 board_ahci_mv, 74 board_ahci_sb600, 75 board_ahci_sb700, /* for SB700 and SB800 */ 76 board_ahci_vt8251, 77 78 /* aliases */ 79 board_ahci_mcp_linux = board_ahci_mcp65, 80 board_ahci_mcp67 = board_ahci_mcp65, 81 board_ahci_mcp73 = board_ahci_mcp65, 82 board_ahci_mcp79 = board_ahci_mcp77, 83 }; 84 85 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 86 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 87 unsigned long deadline); 88 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 89 unsigned long deadline); 90 static void ahci_mcp89_apple_enable(struct pci_dev *pdev); 91 static bool is_mcp89_apple(struct pci_dev *pdev); 92 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 93 unsigned long deadline); 94 #ifdef CONFIG_PM 95 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); 96 static int ahci_pci_device_resume(struct pci_dev *pdev); 97 #endif 98 99 static struct scsi_host_template ahci_sht = { 100 AHCI_SHT("ahci"), 101 }; 102 103 static struct ata_port_operations ahci_vt8251_ops = { 104 .inherits = &ahci_ops, 105 .hardreset = ahci_vt8251_hardreset, 106 }; 107 108 static struct ata_port_operations ahci_p5wdh_ops = { 109 .inherits = &ahci_ops, 110 .hardreset = ahci_p5wdh_hardreset, 111 }; 112 113 static struct ata_port_operations ahci_avn_ops = { 114 .inherits = &ahci_ops, 115 .hardreset = ahci_avn_hardreset, 116 }; 117 118 static const struct ata_port_info ahci_port_info[] = { 119 /* by features */ 120 [board_ahci] = { 121 .flags = AHCI_FLAG_COMMON, 122 .pio_mask = ATA_PIO4, 123 .udma_mask = ATA_UDMA6, 124 .port_ops = &ahci_ops, 125 }, 126 [board_ahci_ign_iferr] = { 127 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), 128 .flags = AHCI_FLAG_COMMON, 129 .pio_mask = ATA_PIO4, 130 .udma_mask = ATA_UDMA6, 131 .port_ops = &ahci_ops, 132 }, 133 [board_ahci_nomsi] = { 134 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI), 135 .flags = AHCI_FLAG_COMMON, 136 .pio_mask = ATA_PIO4, 137 .udma_mask = ATA_UDMA6, 138 .port_ops = &ahci_ops, 139 }, 140 [board_ahci_noncq] = { 141 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ), 142 .flags = AHCI_FLAG_COMMON, 143 .pio_mask = ATA_PIO4, 144 .udma_mask = ATA_UDMA6, 145 .port_ops = &ahci_ops, 146 }, 147 [board_ahci_nosntf] = { 148 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF), 149 .flags = AHCI_FLAG_COMMON, 150 .pio_mask = ATA_PIO4, 151 .udma_mask = ATA_UDMA6, 152 .port_ops = &ahci_ops, 153 }, 154 [board_ahci_yes_fbs] = { 155 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS), 156 .flags = AHCI_FLAG_COMMON, 157 .pio_mask = ATA_PIO4, 158 .udma_mask = ATA_UDMA6, 159 .port_ops = &ahci_ops, 160 }, 161 /* by chipsets */ 162 [board_ahci_avn] = { 163 .flags = AHCI_FLAG_COMMON, 164 .pio_mask = ATA_PIO4, 165 .udma_mask = ATA_UDMA6, 166 .port_ops = &ahci_avn_ops, 167 }, 168 [board_ahci_mcp65] = { 169 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP | 170 AHCI_HFLAG_YES_NCQ), 171 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM, 172 .pio_mask = ATA_PIO4, 173 .udma_mask = ATA_UDMA6, 174 .port_ops = &ahci_ops, 175 }, 176 [board_ahci_mcp77] = { 177 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP), 178 .flags = AHCI_FLAG_COMMON, 179 .pio_mask = ATA_PIO4, 180 .udma_mask = ATA_UDMA6, 181 .port_ops = &ahci_ops, 182 }, 183 [board_ahci_mcp89] = { 184 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA), 185 .flags = AHCI_FLAG_COMMON, 186 .pio_mask = ATA_PIO4, 187 .udma_mask = ATA_UDMA6, 188 .port_ops = &ahci_ops, 189 }, 190 [board_ahci_mv] = { 191 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | 192 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP), 193 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, 194 .pio_mask = ATA_PIO4, 195 .udma_mask = ATA_UDMA6, 196 .port_ops = &ahci_ops, 197 }, 198 [board_ahci_sb600] = { 199 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | 200 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 | 201 AHCI_HFLAG_32BIT_ONLY), 202 .flags = AHCI_FLAG_COMMON, 203 .pio_mask = ATA_PIO4, 204 .udma_mask = ATA_UDMA6, 205 .port_ops = &ahci_pmp_retry_srst_ops, 206 }, 207 [board_ahci_sb700] = { /* for SB700 and SB800 */ 208 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL), 209 .flags = AHCI_FLAG_COMMON, 210 .pio_mask = ATA_PIO4, 211 .udma_mask = ATA_UDMA6, 212 .port_ops = &ahci_pmp_retry_srst_ops, 213 }, 214 [board_ahci_vt8251] = { 215 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), 216 .flags = AHCI_FLAG_COMMON, 217 .pio_mask = ATA_PIO4, 218 .udma_mask = ATA_UDMA6, 219 .port_ops = &ahci_vt8251_ops, 220 }, 221 }; 222 223 static const struct pci_device_id ahci_pci_tbl[] = { 224 /* Intel */ 225 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ 226 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ 227 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ 228 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ 229 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ 230 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ 231 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ 232 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ 233 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ 234 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ 235 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ 236 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */ 237 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ 238 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ 239 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ 240 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ 241 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ 242 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ 243 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ 244 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ 245 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */ 246 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */ 247 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */ 248 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */ 249 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */ 250 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ 251 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */ 252 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ 253 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ 254 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */ 255 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */ 256 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */ 257 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */ 258 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */ 259 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */ 260 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */ 261 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */ 262 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */ 263 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */ 264 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */ 265 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */ 266 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */ 267 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */ 268 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */ 269 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */ 270 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */ 271 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */ 272 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */ 273 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */ 274 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */ 275 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */ 276 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */ 277 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */ 278 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */ 279 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */ 280 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */ 281 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */ 282 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */ 283 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */ 284 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */ 285 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */ 286 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */ 287 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */ 288 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */ 289 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */ 290 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */ 291 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */ 292 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */ 293 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */ 294 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */ 295 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */ 296 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */ 297 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */ 298 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */ 299 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */ 300 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */ 301 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */ 302 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */ 303 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */ 304 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */ 305 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */ 306 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */ 307 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */ 308 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */ 309 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */ 310 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */ 311 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */ 312 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */ 313 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */ 314 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */ 315 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */ 316 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */ 317 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */ 318 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */ 319 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */ 320 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */ 321 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */ 322 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */ 323 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */ 324 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */ 325 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */ 326 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */ 327 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */ 328 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */ 329 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */ 330 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */ 331 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */ 332 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */ 333 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */ 334 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */ 335 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */ 336 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */ 337 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */ 338 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */ 339 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */ 340 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */ 341 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */ 342 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */ 343 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */ 344 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */ 345 346 /* JMicron 360/1/3/5/6, match class to avoid IDE function */ 347 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 348 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, 349 /* JMicron 362B and 362C have an AHCI function with IDE class code */ 350 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr }, 351 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr }, 352 353 /* ATI */ 354 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ 355 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ 356 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ 357 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ 358 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ 359 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ 360 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ 361 362 /* AMD */ 363 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */ 364 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */ 365 /* AMD is using RAID class only for ahci controllers */ 366 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 367 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci }, 368 369 /* VIA */ 370 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ 371 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ 372 373 /* NVIDIA */ 374 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */ 375 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */ 376 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */ 377 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */ 378 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */ 379 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */ 380 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */ 381 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */ 382 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */ 383 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */ 384 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */ 385 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */ 386 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */ 387 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */ 388 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */ 389 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */ 390 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */ 391 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */ 392 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */ 393 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */ 394 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */ 395 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */ 396 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */ 397 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */ 398 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */ 399 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */ 400 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */ 401 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */ 402 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */ 403 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */ 404 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */ 405 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */ 406 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */ 407 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */ 408 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */ 409 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */ 410 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */ 411 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */ 412 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */ 413 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */ 414 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */ 415 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */ 416 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */ 417 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */ 418 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */ 419 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */ 420 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */ 421 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */ 422 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */ 423 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */ 424 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */ 425 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */ 426 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */ 427 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */ 428 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */ 429 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */ 430 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */ 431 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */ 432 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */ 433 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */ 434 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */ 435 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */ 436 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */ 437 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */ 438 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */ 439 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */ 440 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */ 441 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */ 442 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */ 443 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */ 444 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */ 445 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */ 446 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */ 447 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */ 448 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */ 449 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */ 450 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */ 451 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */ 452 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */ 453 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */ 454 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */ 455 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */ 456 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */ 457 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */ 458 459 /* SiS */ 460 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ 461 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */ 462 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ 463 464 /* ST Microelectronics */ 465 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */ 466 467 /* Marvell */ 468 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ 469 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ 470 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123), 471 .class = PCI_CLASS_STORAGE_SATA_AHCI, 472 .class_mask = 0xffffff, 473 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */ 474 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125), 475 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */ 476 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178, 477 PCI_VENDOR_ID_MARVELL_EXT, 0x9170), 478 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */ 479 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a), 480 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 481 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172), 482 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */ 483 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182), 484 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 485 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192), 486 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */ 487 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0), 488 .driver_data = board_ahci_yes_fbs }, 489 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3), 490 .driver_data = board_ahci_yes_fbs }, 491 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230), 492 .driver_data = board_ahci_yes_fbs }, 493 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), 494 .driver_data = board_ahci_yes_fbs }, 495 496 /* Promise */ 497 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */ 498 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */ 499 500 /* Asmedia */ 501 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */ 502 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */ 503 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */ 504 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */ 505 506 /* 507 * Samsung SSDs found on some macbooks. NCQ times out if MSI is 508 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731 509 */ 510 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi }, 511 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi }, 512 513 /* Enmotus */ 514 { PCI_DEVICE(0x1c44, 0x8000), board_ahci }, 515 516 /* Generic, PCI class code for AHCI */ 517 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 518 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, 519 520 { } /* terminate list */ 521 }; 522 523 524 static struct pci_driver ahci_pci_driver = { 525 .name = DRV_NAME, 526 .id_table = ahci_pci_tbl, 527 .probe = ahci_init_one, 528 .remove = ata_pci_remove_one, 529 #ifdef CONFIG_PM 530 .suspend = ahci_pci_device_suspend, 531 .resume = ahci_pci_device_resume, 532 #endif 533 }; 534 535 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE) 536 static int marvell_enable; 537 #else 538 static int marvell_enable = 1; 539 #endif 540 module_param(marvell_enable, int, 0644); 541 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)"); 542 543 544 static void ahci_pci_save_initial_config(struct pci_dev *pdev, 545 struct ahci_host_priv *hpriv) 546 { 547 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) { 548 dev_info(&pdev->dev, "JMB361 has only one port\n"); 549 hpriv->force_port_map = 1; 550 } 551 552 /* 553 * Temporary Marvell 6145 hack: PATA port presence 554 * is asserted through the standard AHCI port 555 * presence register, as bit 4 (counting from 0) 556 */ 557 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 558 if (pdev->device == 0x6121) 559 hpriv->mask_port_map = 0x3; 560 else 561 hpriv->mask_port_map = 0xf; 562 dev_info(&pdev->dev, 563 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n"); 564 } 565 566 ahci_save_initial_config(&pdev->dev, hpriv); 567 } 568 569 static int ahci_pci_reset_controller(struct ata_host *host) 570 { 571 struct pci_dev *pdev = to_pci_dev(host->dev); 572 573 ahci_reset_controller(host); 574 575 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 576 struct ahci_host_priv *hpriv = host->private_data; 577 u16 tmp16; 578 579 /* configure PCS */ 580 pci_read_config_word(pdev, 0x92, &tmp16); 581 if ((tmp16 & hpriv->port_map) != hpriv->port_map) { 582 tmp16 |= hpriv->port_map; 583 pci_write_config_word(pdev, 0x92, tmp16); 584 } 585 } 586 587 return 0; 588 } 589 590 static void ahci_pci_init_controller(struct ata_host *host) 591 { 592 struct ahci_host_priv *hpriv = host->private_data; 593 struct pci_dev *pdev = to_pci_dev(host->dev); 594 void __iomem *port_mmio; 595 u32 tmp; 596 int mv; 597 598 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 599 if (pdev->device == 0x6121) 600 mv = 2; 601 else 602 mv = 4; 603 port_mmio = __ahci_port_base(host, mv); 604 605 writel(0, port_mmio + PORT_IRQ_MASK); 606 607 /* clear port IRQ */ 608 tmp = readl(port_mmio + PORT_IRQ_STAT); 609 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 610 if (tmp) 611 writel(tmp, port_mmio + PORT_IRQ_STAT); 612 } 613 614 ahci_init_controller(host); 615 } 616 617 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 618 unsigned long deadline) 619 { 620 struct ata_port *ap = link->ap; 621 struct ahci_host_priv *hpriv = ap->host->private_data; 622 bool online; 623 int rc; 624 625 DPRINTK("ENTER\n"); 626 627 ahci_stop_engine(ap); 628 629 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 630 deadline, &online, NULL); 631 632 hpriv->start_engine(ap); 633 634 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 635 636 /* vt8251 doesn't clear BSY on signature FIS reception, 637 * request follow-up softreset. 638 */ 639 return online ? -EAGAIN : rc; 640 } 641 642 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 643 unsigned long deadline) 644 { 645 struct ata_port *ap = link->ap; 646 struct ahci_port_priv *pp = ap->private_data; 647 struct ahci_host_priv *hpriv = ap->host->private_data; 648 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 649 struct ata_taskfile tf; 650 bool online; 651 int rc; 652 653 ahci_stop_engine(ap); 654 655 /* clear D2H reception area to properly wait for D2H FIS */ 656 ata_tf_init(link->device, &tf); 657 tf.command = ATA_BUSY; 658 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 659 660 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 661 deadline, &online, NULL); 662 663 hpriv->start_engine(ap); 664 665 /* The pseudo configuration device on SIMG4726 attached to 666 * ASUS P5W-DH Deluxe doesn't send signature FIS after 667 * hardreset if no device is attached to the first downstream 668 * port && the pseudo device locks up on SRST w/ PMP==0. To 669 * work around this, wait for !BSY only briefly. If BSY isn't 670 * cleared, perform CLO and proceed to IDENTIFY (achieved by 671 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). 672 * 673 * Wait for two seconds. Devices attached to downstream port 674 * which can't process the following IDENTIFY after this will 675 * have to be reset again. For most cases, this should 676 * suffice while making probing snappish enough. 677 */ 678 if (online) { 679 rc = ata_wait_after_reset(link, jiffies + 2 * HZ, 680 ahci_check_ready); 681 if (rc) 682 ahci_kick_engine(ap); 683 } 684 return rc; 685 } 686 687 /* 688 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports. 689 * 690 * It has been observed with some SSDs that the timing of events in the 691 * link synchronization phase can leave the port in a state that can not 692 * be recovered by a SATA-hard-reset alone. The failing signature is 693 * SStatus.DET stuck at 1 ("Device presence detected but Phy 694 * communication not established"). It was found that unloading and 695 * reloading the driver when this problem occurs allows the drive 696 * connection to be recovered (DET advanced to 0x3). The critical 697 * component of reloading the driver is that the port state machines are 698 * reset by bouncing "port enable" in the AHCI PCS configuration 699 * register. So, reproduce that effect by bouncing a port whenever we 700 * see DET==1 after a reset. 701 */ 702 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 703 unsigned long deadline) 704 { 705 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 706 struct ata_port *ap = link->ap; 707 struct ahci_port_priv *pp = ap->private_data; 708 struct ahci_host_priv *hpriv = ap->host->private_data; 709 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 710 unsigned long tmo = deadline - jiffies; 711 struct ata_taskfile tf; 712 bool online; 713 int rc, i; 714 715 DPRINTK("ENTER\n"); 716 717 ahci_stop_engine(ap); 718 719 for (i = 0; i < 2; i++) { 720 u16 val; 721 u32 sstatus; 722 int port = ap->port_no; 723 struct ata_host *host = ap->host; 724 struct pci_dev *pdev = to_pci_dev(host->dev); 725 726 /* clear D2H reception area to properly wait for D2H FIS */ 727 ata_tf_init(link->device, &tf); 728 tf.command = ATA_BUSY; 729 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 730 731 rc = sata_link_hardreset(link, timing, deadline, &online, 732 ahci_check_ready); 733 734 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 || 735 (sstatus & 0xf) != 1) 736 break; 737 738 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n", 739 port); 740 741 pci_read_config_word(pdev, 0x92, &val); 742 val &= ~(1 << port); 743 pci_write_config_word(pdev, 0x92, val); 744 ata_msleep(ap, 1000); 745 val |= 1 << port; 746 pci_write_config_word(pdev, 0x92, val); 747 deadline += tmo; 748 } 749 750 hpriv->start_engine(ap); 751 752 if (online) 753 *class = ahci_dev_classify(ap); 754 755 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 756 return rc; 757 } 758 759 760 #ifdef CONFIG_PM 761 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) 762 { 763 struct ata_host *host = pci_get_drvdata(pdev); 764 struct ahci_host_priv *hpriv = host->private_data; 765 void __iomem *mmio = hpriv->mmio; 766 u32 ctl; 767 768 if (mesg.event & PM_EVENT_SUSPEND && 769 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { 770 dev_err(&pdev->dev, 771 "BIOS update required for suspend/resume\n"); 772 return -EIO; 773 } 774 775 if (mesg.event & PM_EVENT_SLEEP) { 776 /* AHCI spec rev1.1 section 8.3.3: 777 * Software must disable interrupts prior to requesting a 778 * transition of the HBA to D3 state. 779 */ 780 ctl = readl(mmio + HOST_CTL); 781 ctl &= ~HOST_IRQ_EN; 782 writel(ctl, mmio + HOST_CTL); 783 readl(mmio + HOST_CTL); /* flush */ 784 } 785 786 return ata_pci_device_suspend(pdev, mesg); 787 } 788 789 static int ahci_pci_device_resume(struct pci_dev *pdev) 790 { 791 struct ata_host *host = pci_get_drvdata(pdev); 792 int rc; 793 794 rc = ata_pci_device_do_resume(pdev); 795 if (rc) 796 return rc; 797 798 /* Apple BIOS helpfully mangles the registers on resume */ 799 if (is_mcp89_apple(pdev)) 800 ahci_mcp89_apple_enable(pdev); 801 802 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { 803 rc = ahci_pci_reset_controller(host); 804 if (rc) 805 return rc; 806 807 ahci_pci_init_controller(host); 808 } 809 810 ata_host_resume(host); 811 812 return 0; 813 } 814 #endif 815 816 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) 817 { 818 int rc; 819 820 /* 821 * If the device fixup already set the dma_mask to some non-standard 822 * value, don't extend it here. This happens on STA2X11, for example. 823 */ 824 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32)) 825 return 0; 826 827 if (using_dac && 828 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) { 829 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); 830 if (rc) { 831 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 832 if (rc) { 833 dev_err(&pdev->dev, 834 "64-bit DMA enable failed\n"); 835 return rc; 836 } 837 } 838 } else { 839 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 840 if (rc) { 841 dev_err(&pdev->dev, "32-bit DMA enable failed\n"); 842 return rc; 843 } 844 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 845 if (rc) { 846 dev_err(&pdev->dev, 847 "32-bit consistent DMA enable failed\n"); 848 return rc; 849 } 850 } 851 return 0; 852 } 853 854 static void ahci_pci_print_info(struct ata_host *host) 855 { 856 struct pci_dev *pdev = to_pci_dev(host->dev); 857 u16 cc; 858 const char *scc_s; 859 860 pci_read_config_word(pdev, 0x0a, &cc); 861 if (cc == PCI_CLASS_STORAGE_IDE) 862 scc_s = "IDE"; 863 else if (cc == PCI_CLASS_STORAGE_SATA) 864 scc_s = "SATA"; 865 else if (cc == PCI_CLASS_STORAGE_RAID) 866 scc_s = "RAID"; 867 else 868 scc_s = "unknown"; 869 870 ahci_print_info(host, scc_s); 871 } 872 873 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is 874 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't 875 * support PMP and the 4726 either directly exports the device 876 * attached to the first downstream port or acts as a hardware storage 877 * controller and emulate a single ATA device (can be RAID 0/1 or some 878 * other configuration). 879 * 880 * When there's no device attached to the first downstream port of the 881 * 4726, "Config Disk" appears, which is a pseudo ATA device to 882 * configure the 4726. However, ATA emulation of the device is very 883 * lame. It doesn't send signature D2H Reg FIS after the initial 884 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. 885 * 886 * The following function works around the problem by always using 887 * hardreset on the port and not depending on receiving signature FIS 888 * afterward. If signature FIS isn't received soon, ATA class is 889 * assumed without follow-up softreset. 890 */ 891 static void ahci_p5wdh_workaround(struct ata_host *host) 892 { 893 static const struct dmi_system_id sysids[] = { 894 { 895 .ident = "P5W DH Deluxe", 896 .matches = { 897 DMI_MATCH(DMI_SYS_VENDOR, 898 "ASUSTEK COMPUTER INC"), 899 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), 900 }, 901 }, 902 { } 903 }; 904 struct pci_dev *pdev = to_pci_dev(host->dev); 905 906 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && 907 dmi_check_system(sysids)) { 908 struct ata_port *ap = host->ports[1]; 909 910 dev_info(&pdev->dev, 911 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n"); 912 913 ap->ops = &ahci_p5wdh_ops; 914 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; 915 } 916 } 917 918 /* 919 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when 920 * booting in BIOS compatibility mode. We restore the registers but not ID. 921 */ 922 static void ahci_mcp89_apple_enable(struct pci_dev *pdev) 923 { 924 u32 val; 925 926 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n"); 927 928 pci_read_config_dword(pdev, 0xf8, &val); 929 val |= 1 << 0x1b; 930 /* the following changes the device ID, but appears not to affect function */ 931 /* val = (val & ~0xf0000000) | 0x80000000; */ 932 pci_write_config_dword(pdev, 0xf8, val); 933 934 pci_read_config_dword(pdev, 0x54c, &val); 935 val |= 1 << 0xc; 936 pci_write_config_dword(pdev, 0x54c, val); 937 938 pci_read_config_dword(pdev, 0x4a4, &val); 939 val &= 0xff; 940 val |= 0x01060100; 941 pci_write_config_dword(pdev, 0x4a4, val); 942 943 pci_read_config_dword(pdev, 0x54c, &val); 944 val &= ~(1 << 0xc); 945 pci_write_config_dword(pdev, 0x54c, val); 946 947 pci_read_config_dword(pdev, 0xf8, &val); 948 val &= ~(1 << 0x1b); 949 pci_write_config_dword(pdev, 0xf8, val); 950 } 951 952 static bool is_mcp89_apple(struct pci_dev *pdev) 953 { 954 return pdev->vendor == PCI_VENDOR_ID_NVIDIA && 955 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA && 956 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 957 pdev->subsystem_device == 0xcb89; 958 } 959 960 /* only some SB600 ahci controllers can do 64bit DMA */ 961 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev) 962 { 963 static const struct dmi_system_id sysids[] = { 964 /* 965 * The oldest version known to be broken is 0901 and 966 * working is 1501 which was released on 2007-10-26. 967 * Enable 64bit DMA on 1501 and anything newer. 968 * 969 * Please read bko#9412 for more info. 970 */ 971 { 972 .ident = "ASUS M2A-VM", 973 .matches = { 974 DMI_MATCH(DMI_BOARD_VENDOR, 975 "ASUSTeK Computer INC."), 976 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"), 977 }, 978 .driver_data = "20071026", /* yyyymmdd */ 979 }, 980 /* 981 * All BIOS versions for the MSI K9A2 Platinum (MS-7376) 982 * support 64bit DMA. 983 * 984 * BIOS versions earlier than 1.5 had the Manufacturer DMI 985 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD". 986 * This spelling mistake was fixed in BIOS version 1.5, so 987 * 1.5 and later have the Manufacturer as 988 * "MICRO-STAR INTERNATIONAL CO.,LTD". 989 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER". 990 * 991 * BIOS versions earlier than 1.9 had a Board Product Name 992 * DMI field of "MS-7376". This was changed to be 993 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still 994 * match on DMI_BOARD_NAME of "MS-7376". 995 */ 996 { 997 .ident = "MSI K9A2 Platinum", 998 .matches = { 999 DMI_MATCH(DMI_BOARD_VENDOR, 1000 "MICRO-STAR INTER"), 1001 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"), 1002 }, 1003 }, 1004 /* 1005 * All BIOS versions for the MSI K9AGM2 (MS-7327) support 1006 * 64bit DMA. 1007 * 1008 * This board also had the typo mentioned above in the 1009 * Manufacturer DMI field (fixed in BIOS version 1.5), so 1010 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again. 1011 */ 1012 { 1013 .ident = "MSI K9AGM2", 1014 .matches = { 1015 DMI_MATCH(DMI_BOARD_VENDOR, 1016 "MICRO-STAR INTER"), 1017 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"), 1018 }, 1019 }, 1020 /* 1021 * All BIOS versions for the Asus M3A support 64bit DMA. 1022 * (all release versions from 0301 to 1206 were tested) 1023 */ 1024 { 1025 .ident = "ASUS M3A", 1026 .matches = { 1027 DMI_MATCH(DMI_BOARD_VENDOR, 1028 "ASUSTeK Computer INC."), 1029 DMI_MATCH(DMI_BOARD_NAME, "M3A"), 1030 }, 1031 }, 1032 { } 1033 }; 1034 const struct dmi_system_id *match; 1035 int year, month, date; 1036 char buf[9]; 1037 1038 match = dmi_first_match(sysids); 1039 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) || 1040 !match) 1041 return false; 1042 1043 if (!match->driver_data) 1044 goto enable_64bit; 1045 1046 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1047 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1048 1049 if (strcmp(buf, match->driver_data) >= 0) 1050 goto enable_64bit; 1051 else { 1052 dev_warn(&pdev->dev, 1053 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n", 1054 match->ident); 1055 return false; 1056 } 1057 1058 enable_64bit: 1059 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident); 1060 return true; 1061 } 1062 1063 static bool ahci_broken_system_poweroff(struct pci_dev *pdev) 1064 { 1065 static const struct dmi_system_id broken_systems[] = { 1066 { 1067 .ident = "HP Compaq nx6310", 1068 .matches = { 1069 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1070 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"), 1071 }, 1072 /* PCI slot number of the controller */ 1073 .driver_data = (void *)0x1FUL, 1074 }, 1075 { 1076 .ident = "HP Compaq 6720s", 1077 .matches = { 1078 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1079 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"), 1080 }, 1081 /* PCI slot number of the controller */ 1082 .driver_data = (void *)0x1FUL, 1083 }, 1084 1085 { } /* terminate list */ 1086 }; 1087 const struct dmi_system_id *dmi = dmi_first_match(broken_systems); 1088 1089 if (dmi) { 1090 unsigned long slot = (unsigned long)dmi->driver_data; 1091 /* apply the quirk only to on-board controllers */ 1092 return slot == PCI_SLOT(pdev->devfn); 1093 } 1094 1095 return false; 1096 } 1097 1098 static bool ahci_broken_suspend(struct pci_dev *pdev) 1099 { 1100 static const struct dmi_system_id sysids[] = { 1101 /* 1102 * On HP dv[4-6] and HDX18 with earlier BIOSen, link 1103 * to the harddisk doesn't become online after 1104 * resuming from STR. Warn and fail suspend. 1105 * 1106 * http://bugzilla.kernel.org/show_bug.cgi?id=12276 1107 * 1108 * Use dates instead of versions to match as HP is 1109 * apparently recycling both product and version 1110 * strings. 1111 * 1112 * http://bugzilla.kernel.org/show_bug.cgi?id=15462 1113 */ 1114 { 1115 .ident = "dv4", 1116 .matches = { 1117 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1118 DMI_MATCH(DMI_PRODUCT_NAME, 1119 "HP Pavilion dv4 Notebook PC"), 1120 }, 1121 .driver_data = "20090105", /* F.30 */ 1122 }, 1123 { 1124 .ident = "dv5", 1125 .matches = { 1126 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1127 DMI_MATCH(DMI_PRODUCT_NAME, 1128 "HP Pavilion dv5 Notebook PC"), 1129 }, 1130 .driver_data = "20090506", /* F.16 */ 1131 }, 1132 { 1133 .ident = "dv6", 1134 .matches = { 1135 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1136 DMI_MATCH(DMI_PRODUCT_NAME, 1137 "HP Pavilion dv6 Notebook PC"), 1138 }, 1139 .driver_data = "20090423", /* F.21 */ 1140 }, 1141 { 1142 .ident = "HDX18", 1143 .matches = { 1144 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1145 DMI_MATCH(DMI_PRODUCT_NAME, 1146 "HP HDX18 Notebook PC"), 1147 }, 1148 .driver_data = "20090430", /* F.23 */ 1149 }, 1150 /* 1151 * Acer eMachines G725 has the same problem. BIOS 1152 * V1.03 is known to be broken. V3.04 is known to 1153 * work. Between, there are V1.06, V2.06 and V3.03 1154 * that we don't have much idea about. For now, 1155 * blacklist anything older than V3.04. 1156 * 1157 * http://bugzilla.kernel.org/show_bug.cgi?id=15104 1158 */ 1159 { 1160 .ident = "G725", 1161 .matches = { 1162 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"), 1163 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"), 1164 }, 1165 .driver_data = "20091216", /* V3.04 */ 1166 }, 1167 { } /* terminate list */ 1168 }; 1169 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1170 int year, month, date; 1171 char buf[9]; 1172 1173 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2)) 1174 return false; 1175 1176 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1177 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1178 1179 return strcmp(buf, dmi->driver_data) < 0; 1180 } 1181 1182 static bool ahci_broken_online(struct pci_dev *pdev) 1183 { 1184 #define ENCODE_BUSDEVFN(bus, slot, func) \ 1185 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func))) 1186 static const struct dmi_system_id sysids[] = { 1187 /* 1188 * There are several gigabyte boards which use 1189 * SIMG5723s configured as hardware RAID. Certain 1190 * 5723 firmware revisions shipped there keep the link 1191 * online but fail to answer properly to SRST or 1192 * IDENTIFY when no device is attached downstream 1193 * causing libata to retry quite a few times leading 1194 * to excessive detection delay. 1195 * 1196 * As these firmwares respond to the second reset try 1197 * with invalid device signature, considering unknown 1198 * sig as offline works around the problem acceptably. 1199 */ 1200 { 1201 .ident = "EP45-DQ6", 1202 .matches = { 1203 DMI_MATCH(DMI_BOARD_VENDOR, 1204 "Gigabyte Technology Co., Ltd."), 1205 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"), 1206 }, 1207 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0), 1208 }, 1209 { 1210 .ident = "EP45-DS5", 1211 .matches = { 1212 DMI_MATCH(DMI_BOARD_VENDOR, 1213 "Gigabyte Technology Co., Ltd."), 1214 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"), 1215 }, 1216 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0), 1217 }, 1218 { } /* terminate list */ 1219 }; 1220 #undef ENCODE_BUSDEVFN 1221 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1222 unsigned int val; 1223 1224 if (!dmi) 1225 return false; 1226 1227 val = (unsigned long)dmi->driver_data; 1228 1229 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff); 1230 } 1231 1232 static bool ahci_broken_devslp(struct pci_dev *pdev) 1233 { 1234 /* device with broken DEVSLP but still showing SDS capability */ 1235 static const struct pci_device_id ids[] = { 1236 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */ 1237 {} 1238 }; 1239 1240 return pci_match_id(ids, pdev); 1241 } 1242 1243 #ifdef CONFIG_ATA_ACPI 1244 static void ahci_gtf_filter_workaround(struct ata_host *host) 1245 { 1246 static const struct dmi_system_id sysids[] = { 1247 /* 1248 * Aspire 3810T issues a bunch of SATA enable commands 1249 * via _GTF including an invalid one and one which is 1250 * rejected by the device. Among the successful ones 1251 * is FPDMA non-zero offset enable which when enabled 1252 * only on the drive side leads to NCQ command 1253 * failures. Filter it out. 1254 */ 1255 { 1256 .ident = "Aspire 3810T", 1257 .matches = { 1258 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1259 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"), 1260 }, 1261 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET, 1262 }, 1263 { } 1264 }; 1265 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1266 unsigned int filter; 1267 int i; 1268 1269 if (!dmi) 1270 return; 1271 1272 filter = (unsigned long)dmi->driver_data; 1273 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n", 1274 filter, dmi->ident); 1275 1276 for (i = 0; i < host->n_ports; i++) { 1277 struct ata_port *ap = host->ports[i]; 1278 struct ata_link *link; 1279 struct ata_device *dev; 1280 1281 ata_for_each_link(link, ap, EDGE) 1282 ata_for_each_dev(dev, link, ALL) 1283 dev->gtf_filter |= filter; 1284 } 1285 } 1286 #else 1287 static inline void ahci_gtf_filter_workaround(struct ata_host *host) 1288 {} 1289 #endif 1290 1291 static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports, 1292 struct ahci_host_priv *hpriv) 1293 { 1294 int rc, nvec; 1295 1296 if (hpriv->flags & AHCI_HFLAG_NO_MSI) 1297 goto intx; 1298 1299 nvec = pci_msi_vec_count(pdev); 1300 if (nvec < 0) 1301 goto intx; 1302 1303 /* 1304 * If number of MSIs is less than number of ports then Sharing Last 1305 * Message mode could be enforced. In this case assume that advantage 1306 * of multipe MSIs is negated and use single MSI mode instead. 1307 */ 1308 if (nvec < n_ports) 1309 goto single_msi; 1310 1311 rc = pci_enable_msi_exact(pdev, nvec); 1312 if (rc == -ENOSPC) 1313 goto single_msi; 1314 else if (rc < 0) 1315 goto intx; 1316 1317 /* fallback to single MSI mode if the controller enforced MRSM mode */ 1318 if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) { 1319 pci_disable_msi(pdev); 1320 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n"); 1321 goto single_msi; 1322 } 1323 1324 if (nvec > 1) 1325 hpriv->flags |= AHCI_HFLAG_MULTI_MSI; 1326 1327 return nvec; 1328 1329 single_msi: 1330 if (pci_enable_msi(pdev)) 1331 goto intx; 1332 return 1; 1333 1334 intx: 1335 pci_intx(pdev, 1); 1336 return 0; 1337 } 1338 1339 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1340 { 1341 unsigned int board_id = ent->driver_data; 1342 struct ata_port_info pi = ahci_port_info[board_id]; 1343 const struct ata_port_info *ppi[] = { &pi, NULL }; 1344 struct device *dev = &pdev->dev; 1345 struct ahci_host_priv *hpriv; 1346 struct ata_host *host; 1347 int n_ports, i, rc; 1348 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD; 1349 1350 VPRINTK("ENTER\n"); 1351 1352 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS); 1353 1354 ata_print_version_once(&pdev->dev, DRV_VERSION); 1355 1356 /* The AHCI driver can only drive the SATA ports, the PATA driver 1357 can drive them all so if both drivers are selected make sure 1358 AHCI stays out of the way */ 1359 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable) 1360 return -ENODEV; 1361 1362 /* Apple BIOS on MCP89 prevents us using AHCI */ 1363 if (is_mcp89_apple(pdev)) 1364 ahci_mcp89_apple_enable(pdev); 1365 1366 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode. 1367 * At the moment, we can only use the AHCI mode. Let the users know 1368 * that for SAS drives they're out of luck. 1369 */ 1370 if (pdev->vendor == PCI_VENDOR_ID_PROMISE) 1371 dev_info(&pdev->dev, 1372 "PDC42819 can only drive SATA devices with this driver\n"); 1373 1374 /* Both Connext and Enmotus devices use non-standard BARs */ 1375 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06) 1376 ahci_pci_bar = AHCI_PCI_BAR_STA2X11; 1377 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000) 1378 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS; 1379 1380 /* 1381 * The JMicron chip 361/363 contains one SATA controller and one 1382 * PATA controller,for powering on these both controllers, we must 1383 * follow the sequence one by one, otherwise one of them can not be 1384 * powered on successfully, so here we disable the async suspend 1385 * method for these chips. 1386 */ 1387 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && 1388 (pdev->device == PCI_DEVICE_ID_JMICRON_JMB363 || 1389 pdev->device == PCI_DEVICE_ID_JMICRON_JMB361)) 1390 device_disable_async_suspend(&pdev->dev); 1391 1392 /* acquire resources */ 1393 rc = pcim_enable_device(pdev); 1394 if (rc) 1395 return rc; 1396 1397 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 1398 (pdev->device == 0x2652 || pdev->device == 0x2653)) { 1399 u8 map; 1400 1401 /* ICH6s share the same PCI ID for both piix and ahci 1402 * modes. Enabling ahci mode while MAP indicates 1403 * combined mode is a bad idea. Yield to ata_piix. 1404 */ 1405 pci_read_config_byte(pdev, ICH_MAP, &map); 1406 if (map & 0x3) { 1407 dev_info(&pdev->dev, 1408 "controller is in combined mode, can't enable AHCI mode\n"); 1409 return -ENODEV; 1410 } 1411 } 1412 1413 /* AHCI controllers often implement SFF compatible interface. 1414 * Grab all PCI BARs just in case. 1415 */ 1416 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME); 1417 if (rc == -EBUSY) 1418 pcim_pin_device(pdev); 1419 if (rc) 1420 return rc; 1421 1422 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1423 if (!hpriv) 1424 return -ENOMEM; 1425 hpriv->flags |= (unsigned long)pi.private_data; 1426 1427 /* MCP65 revision A1 and A2 can't do MSI */ 1428 if (board_id == board_ahci_mcp65 && 1429 (pdev->revision == 0xa1 || pdev->revision == 0xa2)) 1430 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1431 1432 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */ 1433 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40) 1434 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL; 1435 1436 /* only some SB600s can do 64bit DMA */ 1437 if (ahci_sb600_enable_64bit(pdev)) 1438 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY; 1439 1440 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar]; 1441 1442 /* must set flag prior to save config in order to take effect */ 1443 if (ahci_broken_devslp(pdev)) 1444 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP; 1445 1446 /* save initial config */ 1447 ahci_pci_save_initial_config(pdev, hpriv); 1448 1449 /* prepare host */ 1450 if (hpriv->cap & HOST_CAP_NCQ) { 1451 pi.flags |= ATA_FLAG_NCQ; 1452 /* 1453 * Auto-activate optimization is supposed to be 1454 * supported on all AHCI controllers indicating NCQ 1455 * capability, but it seems to be broken on some 1456 * chipsets including NVIDIAs. 1457 */ 1458 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA)) 1459 pi.flags |= ATA_FLAG_FPDMA_AA; 1460 1461 /* 1462 * All AHCI controllers should be forward-compatible 1463 * with the new auxiliary field. This code should be 1464 * conditionalized if any buggy AHCI controllers are 1465 * encountered. 1466 */ 1467 pi.flags |= ATA_FLAG_FPDMA_AUX; 1468 } 1469 1470 if (hpriv->cap & HOST_CAP_PMP) 1471 pi.flags |= ATA_FLAG_PMP; 1472 1473 ahci_set_em_messages(hpriv, &pi); 1474 1475 if (ahci_broken_system_poweroff(pdev)) { 1476 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN; 1477 dev_info(&pdev->dev, 1478 "quirky BIOS, skipping spindown on poweroff\n"); 1479 } 1480 1481 if (ahci_broken_suspend(pdev)) { 1482 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND; 1483 dev_warn(&pdev->dev, 1484 "BIOS update required for suspend/resume\n"); 1485 } 1486 1487 if (ahci_broken_online(pdev)) { 1488 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE; 1489 dev_info(&pdev->dev, 1490 "online status unreliable, applying workaround\n"); 1491 } 1492 1493 /* CAP.NP sometimes indicate the index of the last enabled 1494 * port, at other times, that of the last possible port, so 1495 * determining the maximum port number requires looking at 1496 * both CAP.NP and port_map. 1497 */ 1498 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); 1499 1500 ahci_init_interrupts(pdev, n_ports, hpriv); 1501 1502 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 1503 if (!host) 1504 return -ENOMEM; 1505 host->private_data = hpriv; 1506 1507 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) 1508 host->flags |= ATA_HOST_PARALLEL_SCAN; 1509 else 1510 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n"); 1511 1512 if (pi.flags & ATA_FLAG_EM) 1513 ahci_reset_em(host); 1514 1515 for (i = 0; i < host->n_ports; i++) { 1516 struct ata_port *ap = host->ports[i]; 1517 1518 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar"); 1519 ata_port_pbar_desc(ap, ahci_pci_bar, 1520 0x100 + ap->port_no * 0x80, "port"); 1521 1522 /* set enclosure management message type */ 1523 if (ap->flags & ATA_FLAG_EM) 1524 ap->em_message_type = hpriv->em_msg_type; 1525 1526 1527 /* disabled/not-implemented port */ 1528 if (!(hpriv->port_map & (1 << i))) 1529 ap->ops = &ata_dummy_port_ops; 1530 } 1531 1532 /* apply workaround for ASUS P5W DH Deluxe mainboard */ 1533 ahci_p5wdh_workaround(host); 1534 1535 /* apply gtf filter quirk */ 1536 ahci_gtf_filter_workaround(host); 1537 1538 /* initialize adapter */ 1539 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); 1540 if (rc) 1541 return rc; 1542 1543 rc = ahci_pci_reset_controller(host); 1544 if (rc) 1545 return rc; 1546 1547 ahci_pci_init_controller(host); 1548 ahci_pci_print_info(host); 1549 1550 pci_set_master(pdev); 1551 1552 return ahci_host_activate(host, pdev->irq, &ahci_sht); 1553 } 1554 1555 module_pci_driver(ahci_pci_driver); 1556 1557 MODULE_AUTHOR("Jeff Garzik"); 1558 MODULE_DESCRIPTION("AHCI SATA low-level driver"); 1559 MODULE_LICENSE("GPL"); 1560 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); 1561 MODULE_VERSION(DRV_VERSION); 1562