1 /* 2 * ahci.c - AHCI SATA support 3 * 4 * Maintained by: Tejun Heo <tj@kernel.org> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2004-2005 Red Hat, Inc. 9 * 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; see the file COPYING. If not, write to 23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * 26 * libata documentation is available via 'make {ps|pdf}docs', 27 * as Documentation/DocBook/libata.* 28 * 29 * AHCI hardware documentation: 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 32 * 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/module.h> 37 #include <linux/pci.h> 38 #include <linux/init.h> 39 #include <linux/blkdev.h> 40 #include <linux/delay.h> 41 #include <linux/interrupt.h> 42 #include <linux/dma-mapping.h> 43 #include <linux/device.h> 44 #include <linux/dmi.h> 45 #include <linux/gfp.h> 46 #include <scsi/scsi_host.h> 47 #include <scsi/scsi_cmnd.h> 48 #include <linux/libata.h> 49 #include "ahci.h" 50 51 #define DRV_NAME "ahci" 52 #define DRV_VERSION "3.0" 53 54 enum { 55 AHCI_PCI_BAR_STA2X11 = 0, 56 AHCI_PCI_BAR_ENMOTUS = 2, 57 AHCI_PCI_BAR_STANDARD = 5, 58 }; 59 60 enum board_ids { 61 /* board IDs by feature in alphabetical order */ 62 board_ahci, 63 board_ahci_ign_iferr, 64 board_ahci_noncq, 65 board_ahci_nosntf, 66 board_ahci_yes_fbs, 67 68 /* board IDs for specific chipsets in alphabetical order */ 69 board_ahci_mcp65, 70 board_ahci_mcp77, 71 board_ahci_mcp89, 72 board_ahci_mv, 73 board_ahci_sb600, 74 board_ahci_sb700, /* for SB700 and SB800 */ 75 board_ahci_vt8251, 76 77 /* aliases */ 78 board_ahci_mcp_linux = board_ahci_mcp65, 79 board_ahci_mcp67 = board_ahci_mcp65, 80 board_ahci_mcp73 = board_ahci_mcp65, 81 board_ahci_mcp79 = board_ahci_mcp77, 82 }; 83 84 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 85 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 86 unsigned long deadline); 87 static void ahci_mcp89_apple_enable(struct pci_dev *pdev); 88 static bool is_mcp89_apple(struct pci_dev *pdev); 89 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 90 unsigned long deadline); 91 #ifdef CONFIG_PM 92 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); 93 static int ahci_pci_device_resume(struct pci_dev *pdev); 94 #endif 95 96 static struct scsi_host_template ahci_sht = { 97 AHCI_SHT("ahci"), 98 }; 99 100 static struct ata_port_operations ahci_vt8251_ops = { 101 .inherits = &ahci_ops, 102 .hardreset = ahci_vt8251_hardreset, 103 }; 104 105 static struct ata_port_operations ahci_p5wdh_ops = { 106 .inherits = &ahci_ops, 107 .hardreset = ahci_p5wdh_hardreset, 108 }; 109 110 static const struct ata_port_info ahci_port_info[] = { 111 /* by features */ 112 [board_ahci] = { 113 .flags = AHCI_FLAG_COMMON, 114 .pio_mask = ATA_PIO4, 115 .udma_mask = ATA_UDMA6, 116 .port_ops = &ahci_ops, 117 }, 118 [board_ahci_ign_iferr] = { 119 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), 120 .flags = AHCI_FLAG_COMMON, 121 .pio_mask = ATA_PIO4, 122 .udma_mask = ATA_UDMA6, 123 .port_ops = &ahci_ops, 124 }, 125 [board_ahci_noncq] = { 126 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ), 127 .flags = AHCI_FLAG_COMMON, 128 .pio_mask = ATA_PIO4, 129 .udma_mask = ATA_UDMA6, 130 .port_ops = &ahci_ops, 131 }, 132 [board_ahci_nosntf] = { 133 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF), 134 .flags = AHCI_FLAG_COMMON, 135 .pio_mask = ATA_PIO4, 136 .udma_mask = ATA_UDMA6, 137 .port_ops = &ahci_ops, 138 }, 139 [board_ahci_yes_fbs] = { 140 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS), 141 .flags = AHCI_FLAG_COMMON, 142 .pio_mask = ATA_PIO4, 143 .udma_mask = ATA_UDMA6, 144 .port_ops = &ahci_ops, 145 }, 146 /* by chipsets */ 147 [board_ahci_mcp65] = { 148 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP | 149 AHCI_HFLAG_YES_NCQ), 150 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM, 151 .pio_mask = ATA_PIO4, 152 .udma_mask = ATA_UDMA6, 153 .port_ops = &ahci_ops, 154 }, 155 [board_ahci_mcp77] = { 156 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP), 157 .flags = AHCI_FLAG_COMMON, 158 .pio_mask = ATA_PIO4, 159 .udma_mask = ATA_UDMA6, 160 .port_ops = &ahci_ops, 161 }, 162 [board_ahci_mcp89] = { 163 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA), 164 .flags = AHCI_FLAG_COMMON, 165 .pio_mask = ATA_PIO4, 166 .udma_mask = ATA_UDMA6, 167 .port_ops = &ahci_ops, 168 }, 169 [board_ahci_mv] = { 170 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | 171 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP), 172 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, 173 .pio_mask = ATA_PIO4, 174 .udma_mask = ATA_UDMA6, 175 .port_ops = &ahci_ops, 176 }, 177 [board_ahci_sb600] = { 178 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | 179 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 | 180 AHCI_HFLAG_32BIT_ONLY), 181 .flags = AHCI_FLAG_COMMON, 182 .pio_mask = ATA_PIO4, 183 .udma_mask = ATA_UDMA6, 184 .port_ops = &ahci_pmp_retry_srst_ops, 185 }, 186 [board_ahci_sb700] = { /* for SB700 and SB800 */ 187 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL), 188 .flags = AHCI_FLAG_COMMON, 189 .pio_mask = ATA_PIO4, 190 .udma_mask = ATA_UDMA6, 191 .port_ops = &ahci_pmp_retry_srst_ops, 192 }, 193 [board_ahci_vt8251] = { 194 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), 195 .flags = AHCI_FLAG_COMMON, 196 .pio_mask = ATA_PIO4, 197 .udma_mask = ATA_UDMA6, 198 .port_ops = &ahci_vt8251_ops, 199 }, 200 }; 201 202 static const struct pci_device_id ahci_pci_tbl[] = { 203 /* Intel */ 204 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ 205 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ 206 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ 207 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ 208 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ 209 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ 210 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ 211 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ 212 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ 213 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ 214 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ 215 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */ 216 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ 217 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ 218 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ 219 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ 220 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ 221 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ 222 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ 223 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ 224 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */ 225 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */ 226 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */ 227 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */ 228 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */ 229 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ 230 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */ 231 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ 232 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ 233 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */ 234 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */ 235 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */ 236 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */ 237 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */ 238 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */ 239 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */ 240 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */ 241 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */ 242 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */ 243 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */ 244 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */ 245 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */ 246 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */ 247 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */ 248 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */ 249 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */ 250 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */ 251 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */ 252 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */ 253 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */ 254 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */ 255 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */ 256 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */ 257 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */ 258 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */ 259 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */ 260 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */ 261 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */ 262 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */ 263 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */ 264 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */ 265 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */ 266 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */ 267 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */ 268 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */ 269 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */ 270 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */ 271 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */ 272 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */ 273 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */ 274 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */ 275 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */ 276 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */ 277 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */ 278 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */ 279 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */ 280 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */ 281 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */ 282 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */ 283 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */ 284 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */ 285 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */ 286 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */ 287 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */ 288 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */ 289 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */ 290 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */ 291 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */ 292 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */ 293 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */ 294 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */ 295 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */ 296 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */ 297 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */ 298 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */ 299 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */ 300 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */ 301 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */ 302 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */ 303 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */ 304 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */ 305 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */ 306 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */ 307 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */ 308 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */ 309 310 /* JMicron 360/1/3/5/6, match class to avoid IDE function */ 311 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 312 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, 313 /* JMicron 362B and 362C have an AHCI function with IDE class code */ 314 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr }, 315 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr }, 316 317 /* ATI */ 318 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ 319 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ 320 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ 321 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ 322 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ 323 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ 324 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ 325 326 /* AMD */ 327 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */ 328 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */ 329 /* AMD is using RAID class only for ahci controllers */ 330 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 331 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci }, 332 333 /* VIA */ 334 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ 335 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ 336 337 /* NVIDIA */ 338 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */ 339 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */ 340 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */ 341 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */ 342 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */ 343 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */ 344 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */ 345 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */ 346 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */ 347 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */ 348 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */ 349 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */ 350 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */ 351 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */ 352 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */ 353 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */ 354 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */ 355 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */ 356 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */ 357 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */ 358 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */ 359 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */ 360 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */ 361 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */ 362 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */ 363 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */ 364 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */ 365 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */ 366 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */ 367 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */ 368 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */ 369 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */ 370 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */ 371 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */ 372 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */ 373 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */ 374 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */ 375 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */ 376 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */ 377 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */ 378 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */ 379 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */ 380 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */ 381 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */ 382 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */ 383 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */ 384 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */ 385 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */ 386 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */ 387 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */ 388 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */ 389 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */ 390 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */ 391 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */ 392 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */ 393 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */ 394 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */ 395 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */ 396 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */ 397 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */ 398 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */ 399 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */ 400 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */ 401 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */ 402 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */ 403 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */ 404 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */ 405 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */ 406 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */ 407 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */ 408 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */ 409 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */ 410 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */ 411 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */ 412 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */ 413 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */ 414 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */ 415 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */ 416 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */ 417 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */ 418 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */ 419 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */ 420 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */ 421 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */ 422 423 /* SiS */ 424 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ 425 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */ 426 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ 427 428 /* ST Microelectronics */ 429 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */ 430 431 /* Marvell */ 432 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ 433 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ 434 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123), 435 .class = PCI_CLASS_STORAGE_SATA_AHCI, 436 .class_mask = 0xffffff, 437 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */ 438 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125), 439 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */ 440 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178, 441 PCI_VENDOR_ID_MARVELL_EXT, 0x9170), 442 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */ 443 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a), 444 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 445 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172), 446 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 447 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192), 448 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */ 449 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3), 450 .driver_data = board_ahci_yes_fbs }, 451 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230), 452 .driver_data = board_ahci_yes_fbs }, 453 454 /* Promise */ 455 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */ 456 457 /* Asmedia */ 458 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */ 459 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */ 460 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */ 461 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */ 462 463 /* 464 * Samsung SSDs found on some macbooks. NCQ times out. 465 * https://bugzilla.kernel.org/show_bug.cgi?id=60731 466 */ 467 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_noncq }, 468 469 /* Enmotus */ 470 { PCI_DEVICE(0x1c44, 0x8000), board_ahci }, 471 472 /* Generic, PCI class code for AHCI */ 473 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 474 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, 475 476 { } /* terminate list */ 477 }; 478 479 480 static struct pci_driver ahci_pci_driver = { 481 .name = DRV_NAME, 482 .id_table = ahci_pci_tbl, 483 .probe = ahci_init_one, 484 .remove = ata_pci_remove_one, 485 #ifdef CONFIG_PM 486 .suspend = ahci_pci_device_suspend, 487 .resume = ahci_pci_device_resume, 488 #endif 489 }; 490 491 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE) 492 static int marvell_enable; 493 #else 494 static int marvell_enable = 1; 495 #endif 496 module_param(marvell_enable, int, 0644); 497 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)"); 498 499 500 static void ahci_pci_save_initial_config(struct pci_dev *pdev, 501 struct ahci_host_priv *hpriv) 502 { 503 unsigned int force_port_map = 0; 504 unsigned int mask_port_map = 0; 505 506 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) { 507 dev_info(&pdev->dev, "JMB361 has only one port\n"); 508 force_port_map = 1; 509 } 510 511 /* 512 * Temporary Marvell 6145 hack: PATA port presence 513 * is asserted through the standard AHCI port 514 * presence register, as bit 4 (counting from 0) 515 */ 516 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 517 if (pdev->device == 0x6121) 518 mask_port_map = 0x3; 519 else 520 mask_port_map = 0xf; 521 dev_info(&pdev->dev, 522 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n"); 523 } 524 525 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map, 526 mask_port_map); 527 } 528 529 static int ahci_pci_reset_controller(struct ata_host *host) 530 { 531 struct pci_dev *pdev = to_pci_dev(host->dev); 532 533 ahci_reset_controller(host); 534 535 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 536 struct ahci_host_priv *hpriv = host->private_data; 537 u16 tmp16; 538 539 /* configure PCS */ 540 pci_read_config_word(pdev, 0x92, &tmp16); 541 if ((tmp16 & hpriv->port_map) != hpriv->port_map) { 542 tmp16 |= hpriv->port_map; 543 pci_write_config_word(pdev, 0x92, tmp16); 544 } 545 } 546 547 return 0; 548 } 549 550 static void ahci_pci_init_controller(struct ata_host *host) 551 { 552 struct ahci_host_priv *hpriv = host->private_data; 553 struct pci_dev *pdev = to_pci_dev(host->dev); 554 void __iomem *port_mmio; 555 u32 tmp; 556 int mv; 557 558 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 559 if (pdev->device == 0x6121) 560 mv = 2; 561 else 562 mv = 4; 563 port_mmio = __ahci_port_base(host, mv); 564 565 writel(0, port_mmio + PORT_IRQ_MASK); 566 567 /* clear port IRQ */ 568 tmp = readl(port_mmio + PORT_IRQ_STAT); 569 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 570 if (tmp) 571 writel(tmp, port_mmio + PORT_IRQ_STAT); 572 } 573 574 ahci_init_controller(host); 575 } 576 577 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 578 unsigned long deadline) 579 { 580 struct ata_port *ap = link->ap; 581 bool online; 582 int rc; 583 584 DPRINTK("ENTER\n"); 585 586 ahci_stop_engine(ap); 587 588 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 589 deadline, &online, NULL); 590 591 ahci_start_engine(ap); 592 593 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 594 595 /* vt8251 doesn't clear BSY on signature FIS reception, 596 * request follow-up softreset. 597 */ 598 return online ? -EAGAIN : rc; 599 } 600 601 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 602 unsigned long deadline) 603 { 604 struct ata_port *ap = link->ap; 605 struct ahci_port_priv *pp = ap->private_data; 606 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 607 struct ata_taskfile tf; 608 bool online; 609 int rc; 610 611 ahci_stop_engine(ap); 612 613 /* clear D2H reception area to properly wait for D2H FIS */ 614 ata_tf_init(link->device, &tf); 615 tf.command = ATA_BUSY; 616 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 617 618 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 619 deadline, &online, NULL); 620 621 ahci_start_engine(ap); 622 623 /* The pseudo configuration device on SIMG4726 attached to 624 * ASUS P5W-DH Deluxe doesn't send signature FIS after 625 * hardreset if no device is attached to the first downstream 626 * port && the pseudo device locks up on SRST w/ PMP==0. To 627 * work around this, wait for !BSY only briefly. If BSY isn't 628 * cleared, perform CLO and proceed to IDENTIFY (achieved by 629 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). 630 * 631 * Wait for two seconds. Devices attached to downstream port 632 * which can't process the following IDENTIFY after this will 633 * have to be reset again. For most cases, this should 634 * suffice while making probing snappish enough. 635 */ 636 if (online) { 637 rc = ata_wait_after_reset(link, jiffies + 2 * HZ, 638 ahci_check_ready); 639 if (rc) 640 ahci_kick_engine(ap); 641 } 642 return rc; 643 } 644 645 #ifdef CONFIG_PM 646 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) 647 { 648 struct ata_host *host = pci_get_drvdata(pdev); 649 struct ahci_host_priv *hpriv = host->private_data; 650 void __iomem *mmio = hpriv->mmio; 651 u32 ctl; 652 653 if (mesg.event & PM_EVENT_SUSPEND && 654 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { 655 dev_err(&pdev->dev, 656 "BIOS update required for suspend/resume\n"); 657 return -EIO; 658 } 659 660 if (mesg.event & PM_EVENT_SLEEP) { 661 /* AHCI spec rev1.1 section 8.3.3: 662 * Software must disable interrupts prior to requesting a 663 * transition of the HBA to D3 state. 664 */ 665 ctl = readl(mmio + HOST_CTL); 666 ctl &= ~HOST_IRQ_EN; 667 writel(ctl, mmio + HOST_CTL); 668 readl(mmio + HOST_CTL); /* flush */ 669 } 670 671 return ata_pci_device_suspend(pdev, mesg); 672 } 673 674 static int ahci_pci_device_resume(struct pci_dev *pdev) 675 { 676 struct ata_host *host = pci_get_drvdata(pdev); 677 int rc; 678 679 rc = ata_pci_device_do_resume(pdev); 680 if (rc) 681 return rc; 682 683 /* Apple BIOS helpfully mangles the registers on resume */ 684 if (is_mcp89_apple(pdev)) 685 ahci_mcp89_apple_enable(pdev); 686 687 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { 688 rc = ahci_pci_reset_controller(host); 689 if (rc) 690 return rc; 691 692 ahci_pci_init_controller(host); 693 } 694 695 ata_host_resume(host); 696 697 return 0; 698 } 699 #endif 700 701 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) 702 { 703 int rc; 704 705 /* 706 * If the device fixup already set the dma_mask to some non-standard 707 * value, don't extend it here. This happens on STA2X11, for example. 708 */ 709 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32)) 710 return 0; 711 712 if (using_dac && 713 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 714 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 715 if (rc) { 716 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 717 if (rc) { 718 dev_err(&pdev->dev, 719 "64-bit DMA enable failed\n"); 720 return rc; 721 } 722 } 723 } else { 724 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 725 if (rc) { 726 dev_err(&pdev->dev, "32-bit DMA enable failed\n"); 727 return rc; 728 } 729 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 730 if (rc) { 731 dev_err(&pdev->dev, 732 "32-bit consistent DMA enable failed\n"); 733 return rc; 734 } 735 } 736 return 0; 737 } 738 739 static void ahci_pci_print_info(struct ata_host *host) 740 { 741 struct pci_dev *pdev = to_pci_dev(host->dev); 742 u16 cc; 743 const char *scc_s; 744 745 pci_read_config_word(pdev, 0x0a, &cc); 746 if (cc == PCI_CLASS_STORAGE_IDE) 747 scc_s = "IDE"; 748 else if (cc == PCI_CLASS_STORAGE_SATA) 749 scc_s = "SATA"; 750 else if (cc == PCI_CLASS_STORAGE_RAID) 751 scc_s = "RAID"; 752 else 753 scc_s = "unknown"; 754 755 ahci_print_info(host, scc_s); 756 } 757 758 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is 759 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't 760 * support PMP and the 4726 either directly exports the device 761 * attached to the first downstream port or acts as a hardware storage 762 * controller and emulate a single ATA device (can be RAID 0/1 or some 763 * other configuration). 764 * 765 * When there's no device attached to the first downstream port of the 766 * 4726, "Config Disk" appears, which is a pseudo ATA device to 767 * configure the 4726. However, ATA emulation of the device is very 768 * lame. It doesn't send signature D2H Reg FIS after the initial 769 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. 770 * 771 * The following function works around the problem by always using 772 * hardreset on the port and not depending on receiving signature FIS 773 * afterward. If signature FIS isn't received soon, ATA class is 774 * assumed without follow-up softreset. 775 */ 776 static void ahci_p5wdh_workaround(struct ata_host *host) 777 { 778 static struct dmi_system_id sysids[] = { 779 { 780 .ident = "P5W DH Deluxe", 781 .matches = { 782 DMI_MATCH(DMI_SYS_VENDOR, 783 "ASUSTEK COMPUTER INC"), 784 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), 785 }, 786 }, 787 { } 788 }; 789 struct pci_dev *pdev = to_pci_dev(host->dev); 790 791 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && 792 dmi_check_system(sysids)) { 793 struct ata_port *ap = host->ports[1]; 794 795 dev_info(&pdev->dev, 796 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n"); 797 798 ap->ops = &ahci_p5wdh_ops; 799 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; 800 } 801 } 802 803 /* 804 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when 805 * booting in BIOS compatibility mode. We restore the registers but not ID. 806 */ 807 static void ahci_mcp89_apple_enable(struct pci_dev *pdev) 808 { 809 u32 val; 810 811 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n"); 812 813 pci_read_config_dword(pdev, 0xf8, &val); 814 val |= 1 << 0x1b; 815 /* the following changes the device ID, but appears not to affect function */ 816 /* val = (val & ~0xf0000000) | 0x80000000; */ 817 pci_write_config_dword(pdev, 0xf8, val); 818 819 pci_read_config_dword(pdev, 0x54c, &val); 820 val |= 1 << 0xc; 821 pci_write_config_dword(pdev, 0x54c, val); 822 823 pci_read_config_dword(pdev, 0x4a4, &val); 824 val &= 0xff; 825 val |= 0x01060100; 826 pci_write_config_dword(pdev, 0x4a4, val); 827 828 pci_read_config_dword(pdev, 0x54c, &val); 829 val &= ~(1 << 0xc); 830 pci_write_config_dword(pdev, 0x54c, val); 831 832 pci_read_config_dword(pdev, 0xf8, &val); 833 val &= ~(1 << 0x1b); 834 pci_write_config_dword(pdev, 0xf8, val); 835 } 836 837 static bool is_mcp89_apple(struct pci_dev *pdev) 838 { 839 return pdev->vendor == PCI_VENDOR_ID_NVIDIA && 840 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA && 841 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 842 pdev->subsystem_device == 0xcb89; 843 } 844 845 /* only some SB600 ahci controllers can do 64bit DMA */ 846 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev) 847 { 848 static const struct dmi_system_id sysids[] = { 849 /* 850 * The oldest version known to be broken is 0901 and 851 * working is 1501 which was released on 2007-10-26. 852 * Enable 64bit DMA on 1501 and anything newer. 853 * 854 * Please read bko#9412 for more info. 855 */ 856 { 857 .ident = "ASUS M2A-VM", 858 .matches = { 859 DMI_MATCH(DMI_BOARD_VENDOR, 860 "ASUSTeK Computer INC."), 861 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"), 862 }, 863 .driver_data = "20071026", /* yyyymmdd */ 864 }, 865 /* 866 * All BIOS versions for the MSI K9A2 Platinum (MS-7376) 867 * support 64bit DMA. 868 * 869 * BIOS versions earlier than 1.5 had the Manufacturer DMI 870 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD". 871 * This spelling mistake was fixed in BIOS version 1.5, so 872 * 1.5 and later have the Manufacturer as 873 * "MICRO-STAR INTERNATIONAL CO.,LTD". 874 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER". 875 * 876 * BIOS versions earlier than 1.9 had a Board Product Name 877 * DMI field of "MS-7376". This was changed to be 878 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still 879 * match on DMI_BOARD_NAME of "MS-7376". 880 */ 881 { 882 .ident = "MSI K9A2 Platinum", 883 .matches = { 884 DMI_MATCH(DMI_BOARD_VENDOR, 885 "MICRO-STAR INTER"), 886 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"), 887 }, 888 }, 889 /* 890 * All BIOS versions for the MSI K9AGM2 (MS-7327) support 891 * 64bit DMA. 892 * 893 * This board also had the typo mentioned above in the 894 * Manufacturer DMI field (fixed in BIOS version 1.5), so 895 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again. 896 */ 897 { 898 .ident = "MSI K9AGM2", 899 .matches = { 900 DMI_MATCH(DMI_BOARD_VENDOR, 901 "MICRO-STAR INTER"), 902 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"), 903 }, 904 }, 905 /* 906 * All BIOS versions for the Asus M3A support 64bit DMA. 907 * (all release versions from 0301 to 1206 were tested) 908 */ 909 { 910 .ident = "ASUS M3A", 911 .matches = { 912 DMI_MATCH(DMI_BOARD_VENDOR, 913 "ASUSTeK Computer INC."), 914 DMI_MATCH(DMI_BOARD_NAME, "M3A"), 915 }, 916 }, 917 { } 918 }; 919 const struct dmi_system_id *match; 920 int year, month, date; 921 char buf[9]; 922 923 match = dmi_first_match(sysids); 924 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) || 925 !match) 926 return false; 927 928 if (!match->driver_data) 929 goto enable_64bit; 930 931 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 932 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 933 934 if (strcmp(buf, match->driver_data) >= 0) 935 goto enable_64bit; 936 else { 937 dev_warn(&pdev->dev, 938 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n", 939 match->ident); 940 return false; 941 } 942 943 enable_64bit: 944 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident); 945 return true; 946 } 947 948 static bool ahci_broken_system_poweroff(struct pci_dev *pdev) 949 { 950 static const struct dmi_system_id broken_systems[] = { 951 { 952 .ident = "HP Compaq nx6310", 953 .matches = { 954 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 955 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"), 956 }, 957 /* PCI slot number of the controller */ 958 .driver_data = (void *)0x1FUL, 959 }, 960 { 961 .ident = "HP Compaq 6720s", 962 .matches = { 963 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 964 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"), 965 }, 966 /* PCI slot number of the controller */ 967 .driver_data = (void *)0x1FUL, 968 }, 969 970 { } /* terminate list */ 971 }; 972 const struct dmi_system_id *dmi = dmi_first_match(broken_systems); 973 974 if (dmi) { 975 unsigned long slot = (unsigned long)dmi->driver_data; 976 /* apply the quirk only to on-board controllers */ 977 return slot == PCI_SLOT(pdev->devfn); 978 } 979 980 return false; 981 } 982 983 static bool ahci_broken_suspend(struct pci_dev *pdev) 984 { 985 static const struct dmi_system_id sysids[] = { 986 /* 987 * On HP dv[4-6] and HDX18 with earlier BIOSen, link 988 * to the harddisk doesn't become online after 989 * resuming from STR. Warn and fail suspend. 990 * 991 * http://bugzilla.kernel.org/show_bug.cgi?id=12276 992 * 993 * Use dates instead of versions to match as HP is 994 * apparently recycling both product and version 995 * strings. 996 * 997 * http://bugzilla.kernel.org/show_bug.cgi?id=15462 998 */ 999 { 1000 .ident = "dv4", 1001 .matches = { 1002 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1003 DMI_MATCH(DMI_PRODUCT_NAME, 1004 "HP Pavilion dv4 Notebook PC"), 1005 }, 1006 .driver_data = "20090105", /* F.30 */ 1007 }, 1008 { 1009 .ident = "dv5", 1010 .matches = { 1011 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1012 DMI_MATCH(DMI_PRODUCT_NAME, 1013 "HP Pavilion dv5 Notebook PC"), 1014 }, 1015 .driver_data = "20090506", /* F.16 */ 1016 }, 1017 { 1018 .ident = "dv6", 1019 .matches = { 1020 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1021 DMI_MATCH(DMI_PRODUCT_NAME, 1022 "HP Pavilion dv6 Notebook PC"), 1023 }, 1024 .driver_data = "20090423", /* F.21 */ 1025 }, 1026 { 1027 .ident = "HDX18", 1028 .matches = { 1029 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1030 DMI_MATCH(DMI_PRODUCT_NAME, 1031 "HP HDX18 Notebook PC"), 1032 }, 1033 .driver_data = "20090430", /* F.23 */ 1034 }, 1035 /* 1036 * Acer eMachines G725 has the same problem. BIOS 1037 * V1.03 is known to be broken. V3.04 is known to 1038 * work. Between, there are V1.06, V2.06 and V3.03 1039 * that we don't have much idea about. For now, 1040 * blacklist anything older than V3.04. 1041 * 1042 * http://bugzilla.kernel.org/show_bug.cgi?id=15104 1043 */ 1044 { 1045 .ident = "G725", 1046 .matches = { 1047 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"), 1048 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"), 1049 }, 1050 .driver_data = "20091216", /* V3.04 */ 1051 }, 1052 { } /* terminate list */ 1053 }; 1054 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1055 int year, month, date; 1056 char buf[9]; 1057 1058 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2)) 1059 return false; 1060 1061 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1062 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1063 1064 return strcmp(buf, dmi->driver_data) < 0; 1065 } 1066 1067 static bool ahci_broken_online(struct pci_dev *pdev) 1068 { 1069 #define ENCODE_BUSDEVFN(bus, slot, func) \ 1070 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func))) 1071 static const struct dmi_system_id sysids[] = { 1072 /* 1073 * There are several gigabyte boards which use 1074 * SIMG5723s configured as hardware RAID. Certain 1075 * 5723 firmware revisions shipped there keep the link 1076 * online but fail to answer properly to SRST or 1077 * IDENTIFY when no device is attached downstream 1078 * causing libata to retry quite a few times leading 1079 * to excessive detection delay. 1080 * 1081 * As these firmwares respond to the second reset try 1082 * with invalid device signature, considering unknown 1083 * sig as offline works around the problem acceptably. 1084 */ 1085 { 1086 .ident = "EP45-DQ6", 1087 .matches = { 1088 DMI_MATCH(DMI_BOARD_VENDOR, 1089 "Gigabyte Technology Co., Ltd."), 1090 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"), 1091 }, 1092 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0), 1093 }, 1094 { 1095 .ident = "EP45-DS5", 1096 .matches = { 1097 DMI_MATCH(DMI_BOARD_VENDOR, 1098 "Gigabyte Technology Co., Ltd."), 1099 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"), 1100 }, 1101 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0), 1102 }, 1103 { } /* terminate list */ 1104 }; 1105 #undef ENCODE_BUSDEVFN 1106 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1107 unsigned int val; 1108 1109 if (!dmi) 1110 return false; 1111 1112 val = (unsigned long)dmi->driver_data; 1113 1114 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff); 1115 } 1116 1117 #ifdef CONFIG_ATA_ACPI 1118 static void ahci_gtf_filter_workaround(struct ata_host *host) 1119 { 1120 static const struct dmi_system_id sysids[] = { 1121 /* 1122 * Aspire 3810T issues a bunch of SATA enable commands 1123 * via _GTF including an invalid one and one which is 1124 * rejected by the device. Among the successful ones 1125 * is FPDMA non-zero offset enable which when enabled 1126 * only on the drive side leads to NCQ command 1127 * failures. Filter it out. 1128 */ 1129 { 1130 .ident = "Aspire 3810T", 1131 .matches = { 1132 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1133 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"), 1134 }, 1135 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET, 1136 }, 1137 { } 1138 }; 1139 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1140 unsigned int filter; 1141 int i; 1142 1143 if (!dmi) 1144 return; 1145 1146 filter = (unsigned long)dmi->driver_data; 1147 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n", 1148 filter, dmi->ident); 1149 1150 for (i = 0; i < host->n_ports; i++) { 1151 struct ata_port *ap = host->ports[i]; 1152 struct ata_link *link; 1153 struct ata_device *dev; 1154 1155 ata_for_each_link(link, ap, EDGE) 1156 ata_for_each_dev(dev, link, ALL) 1157 dev->gtf_filter |= filter; 1158 } 1159 } 1160 #else 1161 static inline void ahci_gtf_filter_workaround(struct ata_host *host) 1162 {} 1163 #endif 1164 1165 static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports, 1166 struct ahci_host_priv *hpriv) 1167 { 1168 int rc, nvec; 1169 1170 if (hpriv->flags & AHCI_HFLAG_NO_MSI) 1171 goto intx; 1172 1173 rc = pci_msi_vec_count(pdev); 1174 if (rc < 0) 1175 goto intx; 1176 1177 /* 1178 * If number of MSIs is less than number of ports then Sharing Last 1179 * Message mode could be enforced. In this case assume that advantage 1180 * of multipe MSIs is negated and use single MSI mode instead. 1181 */ 1182 if (rc < n_ports) 1183 goto single_msi; 1184 1185 nvec = rc; 1186 rc = pci_enable_msi_block(pdev, nvec); 1187 if (rc < 0) 1188 goto intx; 1189 else if (rc > 0) 1190 goto single_msi; 1191 1192 return nvec; 1193 1194 single_msi: 1195 rc = pci_enable_msi(pdev); 1196 if (rc) 1197 goto intx; 1198 return 1; 1199 1200 intx: 1201 pci_intx(pdev, 1); 1202 return 0; 1203 } 1204 1205 /** 1206 * ahci_host_activate - start AHCI host, request IRQs and register it 1207 * @host: target ATA host 1208 * @irq: base IRQ number to request 1209 * @n_msis: number of MSIs allocated for this host 1210 * @irq_handler: irq_handler used when requesting IRQs 1211 * @irq_flags: irq_flags used when requesting IRQs 1212 * 1213 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1 1214 * when multiple MSIs were allocated. That is one MSI per port, starting 1215 * from @irq. 1216 * 1217 * LOCKING: 1218 * Inherited from calling layer (may sleep). 1219 * 1220 * RETURNS: 1221 * 0 on success, -errno otherwise. 1222 */ 1223 int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis) 1224 { 1225 int i, rc; 1226 1227 /* Sharing Last Message among several ports is not supported */ 1228 if (n_msis < host->n_ports) 1229 return -EINVAL; 1230 1231 rc = ata_host_start(host); 1232 if (rc) 1233 return rc; 1234 1235 for (i = 0; i < host->n_ports; i++) { 1236 const char* desc; 1237 struct ahci_port_priv *pp = host->ports[i]->private_data; 1238 1239 /* pp is NULL for dummy ports */ 1240 if (pp) 1241 desc = pp->irq_desc; 1242 else 1243 desc = dev_driver_string(host->dev); 1244 1245 rc = devm_request_threaded_irq(host->dev, 1246 irq + i, ahci_hw_interrupt, ahci_thread_fn, IRQF_SHARED, 1247 desc, host->ports[i]); 1248 if (rc) 1249 goto out_free_irqs; 1250 } 1251 1252 for (i = 0; i < host->n_ports; i++) 1253 ata_port_desc(host->ports[i], "irq %d", irq + i); 1254 1255 rc = ata_host_register(host, &ahci_sht); 1256 if (rc) 1257 goto out_free_all_irqs; 1258 1259 return 0; 1260 1261 out_free_all_irqs: 1262 i = host->n_ports; 1263 out_free_irqs: 1264 for (i--; i >= 0; i--) 1265 devm_free_irq(host->dev, irq + i, host->ports[i]); 1266 1267 return rc; 1268 } 1269 1270 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1271 { 1272 unsigned int board_id = ent->driver_data; 1273 struct ata_port_info pi = ahci_port_info[board_id]; 1274 const struct ata_port_info *ppi[] = { &pi, NULL }; 1275 struct device *dev = &pdev->dev; 1276 struct ahci_host_priv *hpriv; 1277 struct ata_host *host; 1278 int n_ports, n_msis, i, rc; 1279 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD; 1280 1281 VPRINTK("ENTER\n"); 1282 1283 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS); 1284 1285 ata_print_version_once(&pdev->dev, DRV_VERSION); 1286 1287 /* The AHCI driver can only drive the SATA ports, the PATA driver 1288 can drive them all so if both drivers are selected make sure 1289 AHCI stays out of the way */ 1290 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable) 1291 return -ENODEV; 1292 1293 /* Apple BIOS on MCP89 prevents us using AHCI */ 1294 if (is_mcp89_apple(pdev)) 1295 ahci_mcp89_apple_enable(pdev); 1296 1297 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode. 1298 * At the moment, we can only use the AHCI mode. Let the users know 1299 * that for SAS drives they're out of luck. 1300 */ 1301 if (pdev->vendor == PCI_VENDOR_ID_PROMISE) 1302 dev_info(&pdev->dev, 1303 "PDC42819 can only drive SATA devices with this driver\n"); 1304 1305 /* Both Connext and Enmotus devices use non-standard BARs */ 1306 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06) 1307 ahci_pci_bar = AHCI_PCI_BAR_STA2X11; 1308 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000) 1309 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS; 1310 1311 /* acquire resources */ 1312 rc = pcim_enable_device(pdev); 1313 if (rc) 1314 return rc; 1315 1316 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 1317 (pdev->device == 0x2652 || pdev->device == 0x2653)) { 1318 u8 map; 1319 1320 /* ICH6s share the same PCI ID for both piix and ahci 1321 * modes. Enabling ahci mode while MAP indicates 1322 * combined mode is a bad idea. Yield to ata_piix. 1323 */ 1324 pci_read_config_byte(pdev, ICH_MAP, &map); 1325 if (map & 0x3) { 1326 dev_info(&pdev->dev, 1327 "controller is in combined mode, can't enable AHCI mode\n"); 1328 return -ENODEV; 1329 } 1330 } 1331 1332 /* AHCI controllers often implement SFF compatible interface. 1333 * Grab all PCI BARs just in case. 1334 */ 1335 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME); 1336 if (rc == -EBUSY) 1337 pcim_pin_device(pdev); 1338 if (rc) 1339 return rc; 1340 1341 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1342 if (!hpriv) 1343 return -ENOMEM; 1344 hpriv->flags |= (unsigned long)pi.private_data; 1345 1346 /* MCP65 revision A1 and A2 can't do MSI */ 1347 if (board_id == board_ahci_mcp65 && 1348 (pdev->revision == 0xa1 || pdev->revision == 0xa2)) 1349 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1350 1351 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */ 1352 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40) 1353 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL; 1354 1355 /* only some SB600s can do 64bit DMA */ 1356 if (ahci_sb600_enable_64bit(pdev)) 1357 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY; 1358 1359 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar]; 1360 1361 /* save initial config */ 1362 ahci_pci_save_initial_config(pdev, hpriv); 1363 1364 /* prepare host */ 1365 if (hpriv->cap & HOST_CAP_NCQ) { 1366 pi.flags |= ATA_FLAG_NCQ; 1367 /* 1368 * Auto-activate optimization is supposed to be 1369 * supported on all AHCI controllers indicating NCQ 1370 * capability, but it seems to be broken on some 1371 * chipsets including NVIDIAs. 1372 */ 1373 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA)) 1374 pi.flags |= ATA_FLAG_FPDMA_AA; 1375 1376 /* 1377 * All AHCI controllers should be forward-compatible 1378 * with the new auxiliary field. This code should be 1379 * conditionalized if any buggy AHCI controllers are 1380 * encountered. 1381 */ 1382 pi.flags |= ATA_FLAG_FPDMA_AUX; 1383 } 1384 1385 if (hpriv->cap & HOST_CAP_PMP) 1386 pi.flags |= ATA_FLAG_PMP; 1387 1388 ahci_set_em_messages(hpriv, &pi); 1389 1390 if (ahci_broken_system_poweroff(pdev)) { 1391 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN; 1392 dev_info(&pdev->dev, 1393 "quirky BIOS, skipping spindown on poweroff\n"); 1394 } 1395 1396 if (ahci_broken_suspend(pdev)) { 1397 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND; 1398 dev_warn(&pdev->dev, 1399 "BIOS update required for suspend/resume\n"); 1400 } 1401 1402 if (ahci_broken_online(pdev)) { 1403 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE; 1404 dev_info(&pdev->dev, 1405 "online status unreliable, applying workaround\n"); 1406 } 1407 1408 /* CAP.NP sometimes indicate the index of the last enabled 1409 * port, at other times, that of the last possible port, so 1410 * determining the maximum port number requires looking at 1411 * both CAP.NP and port_map. 1412 */ 1413 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); 1414 1415 n_msis = ahci_init_interrupts(pdev, n_ports, hpriv); 1416 if (n_msis > 1) 1417 hpriv->flags |= AHCI_HFLAG_MULTI_MSI; 1418 1419 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 1420 if (!host) 1421 return -ENOMEM; 1422 host->private_data = hpriv; 1423 1424 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) 1425 host->flags |= ATA_HOST_PARALLEL_SCAN; 1426 else 1427 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n"); 1428 1429 if (pi.flags & ATA_FLAG_EM) 1430 ahci_reset_em(host); 1431 1432 for (i = 0; i < host->n_ports; i++) { 1433 struct ata_port *ap = host->ports[i]; 1434 1435 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar"); 1436 ata_port_pbar_desc(ap, ahci_pci_bar, 1437 0x100 + ap->port_no * 0x80, "port"); 1438 1439 /* set enclosure management message type */ 1440 if (ap->flags & ATA_FLAG_EM) 1441 ap->em_message_type = hpriv->em_msg_type; 1442 1443 1444 /* disabled/not-implemented port */ 1445 if (!(hpriv->port_map & (1 << i))) 1446 ap->ops = &ata_dummy_port_ops; 1447 } 1448 1449 /* apply workaround for ASUS P5W DH Deluxe mainboard */ 1450 ahci_p5wdh_workaround(host); 1451 1452 /* apply gtf filter quirk */ 1453 ahci_gtf_filter_workaround(host); 1454 1455 /* initialize adapter */ 1456 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); 1457 if (rc) 1458 return rc; 1459 1460 rc = ahci_pci_reset_controller(host); 1461 if (rc) 1462 return rc; 1463 1464 ahci_pci_init_controller(host); 1465 ahci_pci_print_info(host); 1466 1467 pci_set_master(pdev); 1468 1469 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) 1470 return ahci_host_activate(host, pdev->irq, n_msis); 1471 1472 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED, 1473 &ahci_sht); 1474 } 1475 1476 module_pci_driver(ahci_pci_driver); 1477 1478 MODULE_AUTHOR("Jeff Garzik"); 1479 MODULE_DESCRIPTION("AHCI SATA low-level driver"); 1480 MODULE_LICENSE("GPL"); 1481 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); 1482 MODULE_VERSION(DRV_VERSION); 1483