1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ahci.c - AHCI SATA support 4 * 5 * Maintained by: Tejun Heo <tj@kernel.org> 6 * Please ALWAYS copy linux-ide@vger.kernel.org 7 * on emails. 8 * 9 * Copyright 2004-2005 Red Hat, Inc. 10 * 11 * libata documentation is available via 'make {ps|pdf}docs', 12 * as Documentation/driver-api/libata.rst 13 * 14 * AHCI hardware documentation: 15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/blkdev.h> 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/device.h> 27 #include <linux/dmi.h> 28 #include <linux/gfp.h> 29 #include <linux/msi.h> 30 #include <scsi/scsi_host.h> 31 #include <scsi/scsi_cmnd.h> 32 #include <linux/libata.h> 33 #include <linux/ahci-remap.h> 34 #include <linux/io-64-nonatomic-lo-hi.h> 35 #include "ahci.h" 36 37 #define DRV_NAME "ahci" 38 #define DRV_VERSION "3.0" 39 40 enum { 41 AHCI_PCI_BAR_STA2X11 = 0, 42 AHCI_PCI_BAR_CAVIUM = 0, 43 AHCI_PCI_BAR_ENMOTUS = 2, 44 AHCI_PCI_BAR_CAVIUM_GEN5 = 4, 45 AHCI_PCI_BAR_STANDARD = 5, 46 }; 47 48 enum board_ids { 49 /* board IDs by feature in alphabetical order */ 50 board_ahci, 51 board_ahci_ign_iferr, 52 board_ahci_mobile, 53 board_ahci_nomsi, 54 board_ahci_noncq, 55 board_ahci_nosntf, 56 board_ahci_yes_fbs, 57 58 /* board IDs for specific chipsets in alphabetical order */ 59 board_ahci_avn, 60 board_ahci_mcp65, 61 board_ahci_mcp77, 62 board_ahci_mcp89, 63 board_ahci_mv, 64 board_ahci_sb600, 65 board_ahci_sb700, /* for SB700 and SB800 */ 66 board_ahci_vt8251, 67 68 /* 69 * board IDs for Intel chipsets that support more than 6 ports 70 * *and* end up needing the PCS quirk. 71 */ 72 board_ahci_pcs7, 73 74 /* aliases */ 75 board_ahci_mcp_linux = board_ahci_mcp65, 76 board_ahci_mcp67 = board_ahci_mcp65, 77 board_ahci_mcp73 = board_ahci_mcp65, 78 board_ahci_mcp79 = board_ahci_mcp77, 79 }; 80 81 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 82 static void ahci_remove_one(struct pci_dev *dev); 83 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 84 unsigned long deadline); 85 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 86 unsigned long deadline); 87 static void ahci_mcp89_apple_enable(struct pci_dev *pdev); 88 static bool is_mcp89_apple(struct pci_dev *pdev); 89 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 90 unsigned long deadline); 91 #ifdef CONFIG_PM 92 static int ahci_pci_device_runtime_suspend(struct device *dev); 93 static int ahci_pci_device_runtime_resume(struct device *dev); 94 #ifdef CONFIG_PM_SLEEP 95 static int ahci_pci_device_suspend(struct device *dev); 96 static int ahci_pci_device_resume(struct device *dev); 97 #endif 98 #endif /* CONFIG_PM */ 99 100 static struct scsi_host_template ahci_sht = { 101 AHCI_SHT("ahci"), 102 }; 103 104 static struct ata_port_operations ahci_vt8251_ops = { 105 .inherits = &ahci_ops, 106 .hardreset = ahci_vt8251_hardreset, 107 }; 108 109 static struct ata_port_operations ahci_p5wdh_ops = { 110 .inherits = &ahci_ops, 111 .hardreset = ahci_p5wdh_hardreset, 112 }; 113 114 static struct ata_port_operations ahci_avn_ops = { 115 .inherits = &ahci_ops, 116 .hardreset = ahci_avn_hardreset, 117 }; 118 119 static const struct ata_port_info ahci_port_info[] = { 120 /* by features */ 121 [board_ahci] = { 122 .flags = AHCI_FLAG_COMMON, 123 .pio_mask = ATA_PIO4, 124 .udma_mask = ATA_UDMA6, 125 .port_ops = &ahci_ops, 126 }, 127 [board_ahci_ign_iferr] = { 128 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), 129 .flags = AHCI_FLAG_COMMON, 130 .pio_mask = ATA_PIO4, 131 .udma_mask = ATA_UDMA6, 132 .port_ops = &ahci_ops, 133 }, 134 [board_ahci_mobile] = { 135 AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE), 136 .flags = AHCI_FLAG_COMMON, 137 .pio_mask = ATA_PIO4, 138 .udma_mask = ATA_UDMA6, 139 .port_ops = &ahci_ops, 140 }, 141 [board_ahci_nomsi] = { 142 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI), 143 .flags = AHCI_FLAG_COMMON, 144 .pio_mask = ATA_PIO4, 145 .udma_mask = ATA_UDMA6, 146 .port_ops = &ahci_ops, 147 }, 148 [board_ahci_noncq] = { 149 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ), 150 .flags = AHCI_FLAG_COMMON, 151 .pio_mask = ATA_PIO4, 152 .udma_mask = ATA_UDMA6, 153 .port_ops = &ahci_ops, 154 }, 155 [board_ahci_nosntf] = { 156 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF), 157 .flags = AHCI_FLAG_COMMON, 158 .pio_mask = ATA_PIO4, 159 .udma_mask = ATA_UDMA6, 160 .port_ops = &ahci_ops, 161 }, 162 [board_ahci_yes_fbs] = { 163 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS), 164 .flags = AHCI_FLAG_COMMON, 165 .pio_mask = ATA_PIO4, 166 .udma_mask = ATA_UDMA6, 167 .port_ops = &ahci_ops, 168 }, 169 /* by chipsets */ 170 [board_ahci_avn] = { 171 .flags = AHCI_FLAG_COMMON, 172 .pio_mask = ATA_PIO4, 173 .udma_mask = ATA_UDMA6, 174 .port_ops = &ahci_avn_ops, 175 }, 176 [board_ahci_mcp65] = { 177 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP | 178 AHCI_HFLAG_YES_NCQ), 179 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM, 180 .pio_mask = ATA_PIO4, 181 .udma_mask = ATA_UDMA6, 182 .port_ops = &ahci_ops, 183 }, 184 [board_ahci_mcp77] = { 185 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP), 186 .flags = AHCI_FLAG_COMMON, 187 .pio_mask = ATA_PIO4, 188 .udma_mask = ATA_UDMA6, 189 .port_ops = &ahci_ops, 190 }, 191 [board_ahci_mcp89] = { 192 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA), 193 .flags = AHCI_FLAG_COMMON, 194 .pio_mask = ATA_PIO4, 195 .udma_mask = ATA_UDMA6, 196 .port_ops = &ahci_ops, 197 }, 198 [board_ahci_mv] = { 199 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | 200 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP), 201 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, 202 .pio_mask = ATA_PIO4, 203 .udma_mask = ATA_UDMA6, 204 .port_ops = &ahci_ops, 205 }, 206 [board_ahci_sb600] = { 207 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | 208 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 | 209 AHCI_HFLAG_32BIT_ONLY), 210 .flags = AHCI_FLAG_COMMON, 211 .pio_mask = ATA_PIO4, 212 .udma_mask = ATA_UDMA6, 213 .port_ops = &ahci_pmp_retry_srst_ops, 214 }, 215 [board_ahci_sb700] = { /* for SB700 and SB800 */ 216 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL), 217 .flags = AHCI_FLAG_COMMON, 218 .pio_mask = ATA_PIO4, 219 .udma_mask = ATA_UDMA6, 220 .port_ops = &ahci_pmp_retry_srst_ops, 221 }, 222 [board_ahci_vt8251] = { 223 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), 224 .flags = AHCI_FLAG_COMMON, 225 .pio_mask = ATA_PIO4, 226 .udma_mask = ATA_UDMA6, 227 .port_ops = &ahci_vt8251_ops, 228 }, 229 [board_ahci_pcs7] = { 230 .flags = AHCI_FLAG_COMMON, 231 .pio_mask = ATA_PIO4, 232 .udma_mask = ATA_UDMA6, 233 .port_ops = &ahci_ops, 234 }, 235 }; 236 237 static const struct pci_device_id ahci_pci_tbl[] = { 238 /* Intel */ 239 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ 240 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ 241 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ 242 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ 243 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ 244 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ 245 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ 246 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ 247 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ 248 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ 249 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ 250 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */ 251 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ 252 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ 253 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ 254 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ 255 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ 256 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ 257 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ 258 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ 259 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */ 260 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */ 261 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */ 262 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */ 263 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */ 264 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ 265 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */ 266 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ 267 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ 268 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */ 269 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */ 270 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */ 271 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */ 272 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */ 273 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */ 274 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */ 275 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */ 276 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */ 277 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */ 278 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */ 279 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */ 280 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */ 281 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */ 282 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */ 283 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */ 284 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */ 285 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */ 286 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */ 287 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */ 288 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */ 289 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */ 290 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */ 291 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */ 292 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */ 293 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */ 294 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */ 295 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */ 296 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */ 297 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */ 298 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */ 299 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */ 300 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */ 301 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */ 302 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */ 303 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */ 304 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */ 305 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */ 306 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */ 307 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */ 308 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */ 309 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */ 310 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */ 311 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */ 312 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */ 313 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */ 314 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */ 315 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */ 316 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */ 317 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */ 318 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */ 319 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */ 320 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */ 321 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */ 322 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */ 323 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */ 324 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */ 325 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */ 326 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */ 327 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */ 328 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */ 329 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */ 330 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */ 331 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */ 332 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */ 333 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */ 334 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */ 335 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */ 336 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */ 337 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */ 338 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */ 339 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */ 340 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */ 341 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */ 342 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */ 343 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */ 344 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */ 345 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */ 346 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */ 347 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */ 348 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */ 349 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */ 350 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */ 351 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */ 352 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */ 353 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */ 354 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */ 355 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */ 356 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */ 357 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */ 358 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */ 359 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */ 360 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */ 361 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */ 362 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */ 363 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */ 364 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */ 365 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */ 366 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */ 367 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */ 368 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */ 369 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */ 370 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */ 371 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */ 372 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */ 373 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */ 374 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */ 375 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */ 376 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */ 377 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */ 378 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */ 379 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */ 380 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */ 381 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */ 382 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/ 383 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/ 384 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/ 385 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/ 386 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/ 387 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/ 388 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/ 389 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/ 390 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/ 391 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/ 392 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/ 393 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/ 394 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */ 395 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */ 396 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */ 397 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */ 398 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */ 399 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */ 400 401 /* JMicron 360/1/3/5/6, match class to avoid IDE function */ 402 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 403 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, 404 /* JMicron 362B and 362C have an AHCI function with IDE class code */ 405 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr }, 406 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr }, 407 /* May need to update quirk_jmicron_async_suspend() for additions */ 408 409 /* ATI */ 410 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ 411 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ 412 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ 413 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ 414 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ 415 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ 416 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ 417 418 /* AMD */ 419 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */ 420 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */ 421 /* AMD is using RAID class only for ahci controllers */ 422 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 423 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci }, 424 425 /* VIA */ 426 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ 427 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ 428 429 /* NVIDIA */ 430 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */ 431 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */ 432 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */ 433 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */ 434 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */ 435 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */ 436 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */ 437 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */ 438 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */ 439 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */ 440 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */ 441 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */ 442 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */ 443 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */ 444 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */ 445 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */ 446 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */ 447 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */ 448 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */ 449 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */ 450 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */ 451 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */ 452 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */ 453 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */ 454 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */ 455 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */ 456 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */ 457 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */ 458 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */ 459 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */ 460 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */ 461 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */ 462 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */ 463 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */ 464 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */ 465 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */ 466 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */ 467 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */ 468 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */ 469 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */ 470 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */ 471 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */ 472 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */ 473 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */ 474 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */ 475 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */ 476 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */ 477 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */ 478 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */ 479 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */ 480 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */ 481 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */ 482 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */ 483 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */ 484 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */ 485 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */ 486 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */ 487 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */ 488 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */ 489 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */ 490 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */ 491 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */ 492 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */ 493 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */ 494 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */ 495 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */ 496 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */ 497 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */ 498 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */ 499 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */ 500 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */ 501 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */ 502 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */ 503 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */ 504 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */ 505 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */ 506 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */ 507 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */ 508 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */ 509 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */ 510 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */ 511 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */ 512 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */ 513 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */ 514 515 /* SiS */ 516 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ 517 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */ 518 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ 519 520 /* ST Microelectronics */ 521 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */ 522 523 /* Marvell */ 524 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ 525 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ 526 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123), 527 .class = PCI_CLASS_STORAGE_SATA_AHCI, 528 .class_mask = 0xffffff, 529 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */ 530 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125), 531 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */ 532 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178, 533 PCI_VENDOR_ID_MARVELL_EXT, 0x9170), 534 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */ 535 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a), 536 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 537 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172), 538 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */ 539 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182), 540 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 541 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192), 542 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */ 543 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0), 544 .driver_data = board_ahci_yes_fbs }, 545 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */ 546 .driver_data = board_ahci_yes_fbs }, 547 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3), 548 .driver_data = board_ahci_yes_fbs }, 549 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230), 550 .driver_data = board_ahci_yes_fbs }, 551 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */ 552 .driver_data = board_ahci_yes_fbs }, 553 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */ 554 .driver_data = board_ahci_yes_fbs }, 555 556 /* Promise */ 557 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */ 558 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */ 559 560 /* Asmedia */ 561 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */ 562 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */ 563 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */ 564 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */ 565 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */ 566 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */ 567 568 /* 569 * Samsung SSDs found on some macbooks. NCQ times out if MSI is 570 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731 571 */ 572 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi }, 573 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi }, 574 575 /* Enmotus */ 576 { PCI_DEVICE(0x1c44, 0x8000), board_ahci }, 577 578 /* Generic, PCI class code for AHCI */ 579 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 580 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, 581 582 { } /* terminate list */ 583 }; 584 585 static const struct dev_pm_ops ahci_pci_pm_ops = { 586 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume) 587 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend, 588 ahci_pci_device_runtime_resume, NULL) 589 }; 590 591 static struct pci_driver ahci_pci_driver = { 592 .name = DRV_NAME, 593 .id_table = ahci_pci_tbl, 594 .probe = ahci_init_one, 595 .remove = ahci_remove_one, 596 .driver = { 597 .pm = &ahci_pci_pm_ops, 598 }, 599 }; 600 601 #if IS_ENABLED(CONFIG_PATA_MARVELL) 602 static int marvell_enable; 603 #else 604 static int marvell_enable = 1; 605 #endif 606 module_param(marvell_enable, int, 0644); 607 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)"); 608 609 static int mobile_lpm_policy = -1; 610 module_param(mobile_lpm_policy, int, 0644); 611 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets"); 612 613 static void ahci_pci_save_initial_config(struct pci_dev *pdev, 614 struct ahci_host_priv *hpriv) 615 { 616 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) { 617 dev_info(&pdev->dev, "JMB361 has only one port\n"); 618 hpriv->force_port_map = 1; 619 } 620 621 /* 622 * Temporary Marvell 6145 hack: PATA port presence 623 * is asserted through the standard AHCI port 624 * presence register, as bit 4 (counting from 0) 625 */ 626 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 627 if (pdev->device == 0x6121) 628 hpriv->mask_port_map = 0x3; 629 else 630 hpriv->mask_port_map = 0xf; 631 dev_info(&pdev->dev, 632 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n"); 633 } 634 635 ahci_save_initial_config(&pdev->dev, hpriv); 636 } 637 638 static void ahci_pci_init_controller(struct ata_host *host) 639 { 640 struct ahci_host_priv *hpriv = host->private_data; 641 struct pci_dev *pdev = to_pci_dev(host->dev); 642 void __iomem *port_mmio; 643 u32 tmp; 644 int mv; 645 646 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 647 if (pdev->device == 0x6121) 648 mv = 2; 649 else 650 mv = 4; 651 port_mmio = __ahci_port_base(host, mv); 652 653 writel(0, port_mmio + PORT_IRQ_MASK); 654 655 /* clear port IRQ */ 656 tmp = readl(port_mmio + PORT_IRQ_STAT); 657 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 658 if (tmp) 659 writel(tmp, port_mmio + PORT_IRQ_STAT); 660 } 661 662 ahci_init_controller(host); 663 } 664 665 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 666 unsigned long deadline) 667 { 668 struct ata_port *ap = link->ap; 669 struct ahci_host_priv *hpriv = ap->host->private_data; 670 bool online; 671 int rc; 672 673 DPRINTK("ENTER\n"); 674 675 hpriv->stop_engine(ap); 676 677 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 678 deadline, &online, NULL); 679 680 hpriv->start_engine(ap); 681 682 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 683 684 /* vt8251 doesn't clear BSY on signature FIS reception, 685 * request follow-up softreset. 686 */ 687 return online ? -EAGAIN : rc; 688 } 689 690 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 691 unsigned long deadline) 692 { 693 struct ata_port *ap = link->ap; 694 struct ahci_port_priv *pp = ap->private_data; 695 struct ahci_host_priv *hpriv = ap->host->private_data; 696 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 697 struct ata_taskfile tf; 698 bool online; 699 int rc; 700 701 hpriv->stop_engine(ap); 702 703 /* clear D2H reception area to properly wait for D2H FIS */ 704 ata_tf_init(link->device, &tf); 705 tf.command = ATA_BUSY; 706 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 707 708 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 709 deadline, &online, NULL); 710 711 hpriv->start_engine(ap); 712 713 /* The pseudo configuration device on SIMG4726 attached to 714 * ASUS P5W-DH Deluxe doesn't send signature FIS after 715 * hardreset if no device is attached to the first downstream 716 * port && the pseudo device locks up on SRST w/ PMP==0. To 717 * work around this, wait for !BSY only briefly. If BSY isn't 718 * cleared, perform CLO and proceed to IDENTIFY (achieved by 719 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). 720 * 721 * Wait for two seconds. Devices attached to downstream port 722 * which can't process the following IDENTIFY after this will 723 * have to be reset again. For most cases, this should 724 * suffice while making probing snappish enough. 725 */ 726 if (online) { 727 rc = ata_wait_after_reset(link, jiffies + 2 * HZ, 728 ahci_check_ready); 729 if (rc) 730 ahci_kick_engine(ap); 731 } 732 return rc; 733 } 734 735 /* 736 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports. 737 * 738 * It has been observed with some SSDs that the timing of events in the 739 * link synchronization phase can leave the port in a state that can not 740 * be recovered by a SATA-hard-reset alone. The failing signature is 741 * SStatus.DET stuck at 1 ("Device presence detected but Phy 742 * communication not established"). It was found that unloading and 743 * reloading the driver when this problem occurs allows the drive 744 * connection to be recovered (DET advanced to 0x3). The critical 745 * component of reloading the driver is that the port state machines are 746 * reset by bouncing "port enable" in the AHCI PCS configuration 747 * register. So, reproduce that effect by bouncing a port whenever we 748 * see DET==1 after a reset. 749 */ 750 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 751 unsigned long deadline) 752 { 753 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 754 struct ata_port *ap = link->ap; 755 struct ahci_port_priv *pp = ap->private_data; 756 struct ahci_host_priv *hpriv = ap->host->private_data; 757 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 758 unsigned long tmo = deadline - jiffies; 759 struct ata_taskfile tf; 760 bool online; 761 int rc, i; 762 763 DPRINTK("ENTER\n"); 764 765 hpriv->stop_engine(ap); 766 767 for (i = 0; i < 2; i++) { 768 u16 val; 769 u32 sstatus; 770 int port = ap->port_no; 771 struct ata_host *host = ap->host; 772 struct pci_dev *pdev = to_pci_dev(host->dev); 773 774 /* clear D2H reception area to properly wait for D2H FIS */ 775 ata_tf_init(link->device, &tf); 776 tf.command = ATA_BUSY; 777 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 778 779 rc = sata_link_hardreset(link, timing, deadline, &online, 780 ahci_check_ready); 781 782 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 || 783 (sstatus & 0xf) != 1) 784 break; 785 786 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n", 787 port); 788 789 pci_read_config_word(pdev, 0x92, &val); 790 val &= ~(1 << port); 791 pci_write_config_word(pdev, 0x92, val); 792 ata_msleep(ap, 1000); 793 val |= 1 << port; 794 pci_write_config_word(pdev, 0x92, val); 795 deadline += tmo; 796 } 797 798 hpriv->start_engine(ap); 799 800 if (online) 801 *class = ahci_dev_classify(ap); 802 803 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 804 return rc; 805 } 806 807 808 #ifdef CONFIG_PM 809 static void ahci_pci_disable_interrupts(struct ata_host *host) 810 { 811 struct ahci_host_priv *hpriv = host->private_data; 812 void __iomem *mmio = hpriv->mmio; 813 u32 ctl; 814 815 /* AHCI spec rev1.1 section 8.3.3: 816 * Software must disable interrupts prior to requesting a 817 * transition of the HBA to D3 state. 818 */ 819 ctl = readl(mmio + HOST_CTL); 820 ctl &= ~HOST_IRQ_EN; 821 writel(ctl, mmio + HOST_CTL); 822 readl(mmio + HOST_CTL); /* flush */ 823 } 824 825 static int ahci_pci_device_runtime_suspend(struct device *dev) 826 { 827 struct pci_dev *pdev = to_pci_dev(dev); 828 struct ata_host *host = pci_get_drvdata(pdev); 829 830 ahci_pci_disable_interrupts(host); 831 return 0; 832 } 833 834 static int ahci_pci_device_runtime_resume(struct device *dev) 835 { 836 struct pci_dev *pdev = to_pci_dev(dev); 837 struct ata_host *host = pci_get_drvdata(pdev); 838 int rc; 839 840 rc = ahci_reset_controller(host); 841 if (rc) 842 return rc; 843 ahci_pci_init_controller(host); 844 return 0; 845 } 846 847 #ifdef CONFIG_PM_SLEEP 848 static int ahci_pci_device_suspend(struct device *dev) 849 { 850 struct pci_dev *pdev = to_pci_dev(dev); 851 struct ata_host *host = pci_get_drvdata(pdev); 852 struct ahci_host_priv *hpriv = host->private_data; 853 854 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { 855 dev_err(&pdev->dev, 856 "BIOS update required for suspend/resume\n"); 857 return -EIO; 858 } 859 860 ahci_pci_disable_interrupts(host); 861 return ata_host_suspend(host, PMSG_SUSPEND); 862 } 863 864 static int ahci_pci_device_resume(struct device *dev) 865 { 866 struct pci_dev *pdev = to_pci_dev(dev); 867 struct ata_host *host = pci_get_drvdata(pdev); 868 int rc; 869 870 /* Apple BIOS helpfully mangles the registers on resume */ 871 if (is_mcp89_apple(pdev)) 872 ahci_mcp89_apple_enable(pdev); 873 874 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { 875 rc = ahci_reset_controller(host); 876 if (rc) 877 return rc; 878 879 ahci_pci_init_controller(host); 880 } 881 882 ata_host_resume(host); 883 884 return 0; 885 } 886 #endif 887 888 #endif /* CONFIG_PM */ 889 890 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) 891 { 892 const int dma_bits = using_dac ? 64 : 32; 893 int rc; 894 895 /* 896 * If the device fixup already set the dma_mask to some non-standard 897 * value, don't extend it here. This happens on STA2X11, for example. 898 * 899 * XXX: manipulating the DMA mask from platform code is completely 900 * bogus, platform code should use dev->bus_dma_mask instead.. 901 */ 902 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32)) 903 return 0; 904 905 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits)); 906 if (rc) 907 dev_err(&pdev->dev, "DMA enable failed\n"); 908 return rc; 909 } 910 911 static void ahci_pci_print_info(struct ata_host *host) 912 { 913 struct pci_dev *pdev = to_pci_dev(host->dev); 914 u16 cc; 915 const char *scc_s; 916 917 pci_read_config_word(pdev, 0x0a, &cc); 918 if (cc == PCI_CLASS_STORAGE_IDE) 919 scc_s = "IDE"; 920 else if (cc == PCI_CLASS_STORAGE_SATA) 921 scc_s = "SATA"; 922 else if (cc == PCI_CLASS_STORAGE_RAID) 923 scc_s = "RAID"; 924 else 925 scc_s = "unknown"; 926 927 ahci_print_info(host, scc_s); 928 } 929 930 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is 931 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't 932 * support PMP and the 4726 either directly exports the device 933 * attached to the first downstream port or acts as a hardware storage 934 * controller and emulate a single ATA device (can be RAID 0/1 or some 935 * other configuration). 936 * 937 * When there's no device attached to the first downstream port of the 938 * 4726, "Config Disk" appears, which is a pseudo ATA device to 939 * configure the 4726. However, ATA emulation of the device is very 940 * lame. It doesn't send signature D2H Reg FIS after the initial 941 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. 942 * 943 * The following function works around the problem by always using 944 * hardreset on the port and not depending on receiving signature FIS 945 * afterward. If signature FIS isn't received soon, ATA class is 946 * assumed without follow-up softreset. 947 */ 948 static void ahci_p5wdh_workaround(struct ata_host *host) 949 { 950 static const struct dmi_system_id sysids[] = { 951 { 952 .ident = "P5W DH Deluxe", 953 .matches = { 954 DMI_MATCH(DMI_SYS_VENDOR, 955 "ASUSTEK COMPUTER INC"), 956 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), 957 }, 958 }, 959 { } 960 }; 961 struct pci_dev *pdev = to_pci_dev(host->dev); 962 963 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && 964 dmi_check_system(sysids)) { 965 struct ata_port *ap = host->ports[1]; 966 967 dev_info(&pdev->dev, 968 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n"); 969 970 ap->ops = &ahci_p5wdh_ops; 971 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; 972 } 973 } 974 975 /* 976 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when 977 * booting in BIOS compatibility mode. We restore the registers but not ID. 978 */ 979 static void ahci_mcp89_apple_enable(struct pci_dev *pdev) 980 { 981 u32 val; 982 983 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n"); 984 985 pci_read_config_dword(pdev, 0xf8, &val); 986 val |= 1 << 0x1b; 987 /* the following changes the device ID, but appears not to affect function */ 988 /* val = (val & ~0xf0000000) | 0x80000000; */ 989 pci_write_config_dword(pdev, 0xf8, val); 990 991 pci_read_config_dword(pdev, 0x54c, &val); 992 val |= 1 << 0xc; 993 pci_write_config_dword(pdev, 0x54c, val); 994 995 pci_read_config_dword(pdev, 0x4a4, &val); 996 val &= 0xff; 997 val |= 0x01060100; 998 pci_write_config_dword(pdev, 0x4a4, val); 999 1000 pci_read_config_dword(pdev, 0x54c, &val); 1001 val &= ~(1 << 0xc); 1002 pci_write_config_dword(pdev, 0x54c, val); 1003 1004 pci_read_config_dword(pdev, 0xf8, &val); 1005 val &= ~(1 << 0x1b); 1006 pci_write_config_dword(pdev, 0xf8, val); 1007 } 1008 1009 static bool is_mcp89_apple(struct pci_dev *pdev) 1010 { 1011 return pdev->vendor == PCI_VENDOR_ID_NVIDIA && 1012 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA && 1013 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 1014 pdev->subsystem_device == 0xcb89; 1015 } 1016 1017 /* only some SB600 ahci controllers can do 64bit DMA */ 1018 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev) 1019 { 1020 static const struct dmi_system_id sysids[] = { 1021 /* 1022 * The oldest version known to be broken is 0901 and 1023 * working is 1501 which was released on 2007-10-26. 1024 * Enable 64bit DMA on 1501 and anything newer. 1025 * 1026 * Please read bko#9412 for more info. 1027 */ 1028 { 1029 .ident = "ASUS M2A-VM", 1030 .matches = { 1031 DMI_MATCH(DMI_BOARD_VENDOR, 1032 "ASUSTeK Computer INC."), 1033 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"), 1034 }, 1035 .driver_data = "20071026", /* yyyymmdd */ 1036 }, 1037 /* 1038 * All BIOS versions for the MSI K9A2 Platinum (MS-7376) 1039 * support 64bit DMA. 1040 * 1041 * BIOS versions earlier than 1.5 had the Manufacturer DMI 1042 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD". 1043 * This spelling mistake was fixed in BIOS version 1.5, so 1044 * 1.5 and later have the Manufacturer as 1045 * "MICRO-STAR INTERNATIONAL CO.,LTD". 1046 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER". 1047 * 1048 * BIOS versions earlier than 1.9 had a Board Product Name 1049 * DMI field of "MS-7376". This was changed to be 1050 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still 1051 * match on DMI_BOARD_NAME of "MS-7376". 1052 */ 1053 { 1054 .ident = "MSI K9A2 Platinum", 1055 .matches = { 1056 DMI_MATCH(DMI_BOARD_VENDOR, 1057 "MICRO-STAR INTER"), 1058 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"), 1059 }, 1060 }, 1061 /* 1062 * All BIOS versions for the MSI K9AGM2 (MS-7327) support 1063 * 64bit DMA. 1064 * 1065 * This board also had the typo mentioned above in the 1066 * Manufacturer DMI field (fixed in BIOS version 1.5), so 1067 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again. 1068 */ 1069 { 1070 .ident = "MSI K9AGM2", 1071 .matches = { 1072 DMI_MATCH(DMI_BOARD_VENDOR, 1073 "MICRO-STAR INTER"), 1074 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"), 1075 }, 1076 }, 1077 /* 1078 * All BIOS versions for the Asus M3A support 64bit DMA. 1079 * (all release versions from 0301 to 1206 were tested) 1080 */ 1081 { 1082 .ident = "ASUS M3A", 1083 .matches = { 1084 DMI_MATCH(DMI_BOARD_VENDOR, 1085 "ASUSTeK Computer INC."), 1086 DMI_MATCH(DMI_BOARD_NAME, "M3A"), 1087 }, 1088 }, 1089 { } 1090 }; 1091 const struct dmi_system_id *match; 1092 int year, month, date; 1093 char buf[9]; 1094 1095 match = dmi_first_match(sysids); 1096 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) || 1097 !match) 1098 return false; 1099 1100 if (!match->driver_data) 1101 goto enable_64bit; 1102 1103 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1104 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1105 1106 if (strcmp(buf, match->driver_data) >= 0) 1107 goto enable_64bit; 1108 else { 1109 dev_warn(&pdev->dev, 1110 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n", 1111 match->ident); 1112 return false; 1113 } 1114 1115 enable_64bit: 1116 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident); 1117 return true; 1118 } 1119 1120 static bool ahci_broken_system_poweroff(struct pci_dev *pdev) 1121 { 1122 static const struct dmi_system_id broken_systems[] = { 1123 { 1124 .ident = "HP Compaq nx6310", 1125 .matches = { 1126 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1127 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"), 1128 }, 1129 /* PCI slot number of the controller */ 1130 .driver_data = (void *)0x1FUL, 1131 }, 1132 { 1133 .ident = "HP Compaq 6720s", 1134 .matches = { 1135 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1136 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"), 1137 }, 1138 /* PCI slot number of the controller */ 1139 .driver_data = (void *)0x1FUL, 1140 }, 1141 1142 { } /* terminate list */ 1143 }; 1144 const struct dmi_system_id *dmi = dmi_first_match(broken_systems); 1145 1146 if (dmi) { 1147 unsigned long slot = (unsigned long)dmi->driver_data; 1148 /* apply the quirk only to on-board controllers */ 1149 return slot == PCI_SLOT(pdev->devfn); 1150 } 1151 1152 return false; 1153 } 1154 1155 static bool ahci_broken_suspend(struct pci_dev *pdev) 1156 { 1157 static const struct dmi_system_id sysids[] = { 1158 /* 1159 * On HP dv[4-6] and HDX18 with earlier BIOSen, link 1160 * to the harddisk doesn't become online after 1161 * resuming from STR. Warn and fail suspend. 1162 * 1163 * http://bugzilla.kernel.org/show_bug.cgi?id=12276 1164 * 1165 * Use dates instead of versions to match as HP is 1166 * apparently recycling both product and version 1167 * strings. 1168 * 1169 * http://bugzilla.kernel.org/show_bug.cgi?id=15462 1170 */ 1171 { 1172 .ident = "dv4", 1173 .matches = { 1174 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1175 DMI_MATCH(DMI_PRODUCT_NAME, 1176 "HP Pavilion dv4 Notebook PC"), 1177 }, 1178 .driver_data = "20090105", /* F.30 */ 1179 }, 1180 { 1181 .ident = "dv5", 1182 .matches = { 1183 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1184 DMI_MATCH(DMI_PRODUCT_NAME, 1185 "HP Pavilion dv5 Notebook PC"), 1186 }, 1187 .driver_data = "20090506", /* F.16 */ 1188 }, 1189 { 1190 .ident = "dv6", 1191 .matches = { 1192 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1193 DMI_MATCH(DMI_PRODUCT_NAME, 1194 "HP Pavilion dv6 Notebook PC"), 1195 }, 1196 .driver_data = "20090423", /* F.21 */ 1197 }, 1198 { 1199 .ident = "HDX18", 1200 .matches = { 1201 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1202 DMI_MATCH(DMI_PRODUCT_NAME, 1203 "HP HDX18 Notebook PC"), 1204 }, 1205 .driver_data = "20090430", /* F.23 */ 1206 }, 1207 /* 1208 * Acer eMachines G725 has the same problem. BIOS 1209 * V1.03 is known to be broken. V3.04 is known to 1210 * work. Between, there are V1.06, V2.06 and V3.03 1211 * that we don't have much idea about. For now, 1212 * blacklist anything older than V3.04. 1213 * 1214 * http://bugzilla.kernel.org/show_bug.cgi?id=15104 1215 */ 1216 { 1217 .ident = "G725", 1218 .matches = { 1219 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"), 1220 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"), 1221 }, 1222 .driver_data = "20091216", /* V3.04 */ 1223 }, 1224 { } /* terminate list */ 1225 }; 1226 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1227 int year, month, date; 1228 char buf[9]; 1229 1230 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2)) 1231 return false; 1232 1233 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1234 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1235 1236 return strcmp(buf, dmi->driver_data) < 0; 1237 } 1238 1239 static bool ahci_broken_lpm(struct pci_dev *pdev) 1240 { 1241 static const struct dmi_system_id sysids[] = { 1242 /* Various Lenovo 50 series have LPM issues with older BIOSen */ 1243 { 1244 .matches = { 1245 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1246 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"), 1247 }, 1248 .driver_data = "20180406", /* 1.31 */ 1249 }, 1250 { 1251 .matches = { 1252 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1253 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"), 1254 }, 1255 .driver_data = "20180420", /* 1.28 */ 1256 }, 1257 { 1258 .matches = { 1259 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1260 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"), 1261 }, 1262 .driver_data = "20180315", /* 1.33 */ 1263 }, 1264 { 1265 .matches = { 1266 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1267 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"), 1268 }, 1269 /* 1270 * Note date based on release notes, 2.35 has been 1271 * reported to be good, but I've been unable to get 1272 * a hold of the reporter to get the DMI BIOS date. 1273 * TODO: fix this. 1274 */ 1275 .driver_data = "20180310", /* 2.35 */ 1276 }, 1277 { } /* terminate list */ 1278 }; 1279 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1280 int year, month, date; 1281 char buf[9]; 1282 1283 if (!dmi) 1284 return false; 1285 1286 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1287 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1288 1289 return strcmp(buf, dmi->driver_data) < 0; 1290 } 1291 1292 static bool ahci_broken_online(struct pci_dev *pdev) 1293 { 1294 #define ENCODE_BUSDEVFN(bus, slot, func) \ 1295 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func))) 1296 static const struct dmi_system_id sysids[] = { 1297 /* 1298 * There are several gigabyte boards which use 1299 * SIMG5723s configured as hardware RAID. Certain 1300 * 5723 firmware revisions shipped there keep the link 1301 * online but fail to answer properly to SRST or 1302 * IDENTIFY when no device is attached downstream 1303 * causing libata to retry quite a few times leading 1304 * to excessive detection delay. 1305 * 1306 * As these firmwares respond to the second reset try 1307 * with invalid device signature, considering unknown 1308 * sig as offline works around the problem acceptably. 1309 */ 1310 { 1311 .ident = "EP45-DQ6", 1312 .matches = { 1313 DMI_MATCH(DMI_BOARD_VENDOR, 1314 "Gigabyte Technology Co., Ltd."), 1315 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"), 1316 }, 1317 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0), 1318 }, 1319 { 1320 .ident = "EP45-DS5", 1321 .matches = { 1322 DMI_MATCH(DMI_BOARD_VENDOR, 1323 "Gigabyte Technology Co., Ltd."), 1324 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"), 1325 }, 1326 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0), 1327 }, 1328 { } /* terminate list */ 1329 }; 1330 #undef ENCODE_BUSDEVFN 1331 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1332 unsigned int val; 1333 1334 if (!dmi) 1335 return false; 1336 1337 val = (unsigned long)dmi->driver_data; 1338 1339 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff); 1340 } 1341 1342 static bool ahci_broken_devslp(struct pci_dev *pdev) 1343 { 1344 /* device with broken DEVSLP but still showing SDS capability */ 1345 static const struct pci_device_id ids[] = { 1346 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */ 1347 {} 1348 }; 1349 1350 return pci_match_id(ids, pdev); 1351 } 1352 1353 #ifdef CONFIG_ATA_ACPI 1354 static void ahci_gtf_filter_workaround(struct ata_host *host) 1355 { 1356 static const struct dmi_system_id sysids[] = { 1357 /* 1358 * Aspire 3810T issues a bunch of SATA enable commands 1359 * via _GTF including an invalid one and one which is 1360 * rejected by the device. Among the successful ones 1361 * is FPDMA non-zero offset enable which when enabled 1362 * only on the drive side leads to NCQ command 1363 * failures. Filter it out. 1364 */ 1365 { 1366 .ident = "Aspire 3810T", 1367 .matches = { 1368 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1369 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"), 1370 }, 1371 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET, 1372 }, 1373 { } 1374 }; 1375 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1376 unsigned int filter; 1377 int i; 1378 1379 if (!dmi) 1380 return; 1381 1382 filter = (unsigned long)dmi->driver_data; 1383 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n", 1384 filter, dmi->ident); 1385 1386 for (i = 0; i < host->n_ports; i++) { 1387 struct ata_port *ap = host->ports[i]; 1388 struct ata_link *link; 1389 struct ata_device *dev; 1390 1391 ata_for_each_link(link, ap, EDGE) 1392 ata_for_each_dev(dev, link, ALL) 1393 dev->gtf_filter |= filter; 1394 } 1395 } 1396 #else 1397 static inline void ahci_gtf_filter_workaround(struct ata_host *host) 1398 {} 1399 #endif 1400 1401 /* 1402 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected 1403 * as DUMMY, or detected but eventually get a "link down" and never get up 1404 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the 1405 * port_map may hold a value of 0x00. 1406 * 1407 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports 1408 * and can significantly reduce the occurrence of the problem. 1409 * 1410 * https://bugzilla.kernel.org/show_bug.cgi?id=189471 1411 */ 1412 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv, 1413 struct pci_dev *pdev) 1414 { 1415 static const struct dmi_system_id sysids[] = { 1416 { 1417 .ident = "Acer Switch Alpha 12", 1418 .matches = { 1419 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1420 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271") 1421 }, 1422 }, 1423 { } 1424 }; 1425 1426 if (dmi_check_system(sysids)) { 1427 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n"); 1428 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) { 1429 hpriv->port_map = 0x7; 1430 hpriv->cap = 0xC734FF02; 1431 } 1432 } 1433 } 1434 1435 #ifdef CONFIG_ARM64 1436 /* 1437 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently. 1438 * Workaround is to make sure all pending IRQs are served before leaving 1439 * handler. 1440 */ 1441 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance) 1442 { 1443 struct ata_host *host = dev_instance; 1444 struct ahci_host_priv *hpriv; 1445 unsigned int rc = 0; 1446 void __iomem *mmio; 1447 u32 irq_stat, irq_masked; 1448 unsigned int handled = 1; 1449 1450 VPRINTK("ENTER\n"); 1451 hpriv = host->private_data; 1452 mmio = hpriv->mmio; 1453 irq_stat = readl(mmio + HOST_IRQ_STAT); 1454 if (!irq_stat) 1455 return IRQ_NONE; 1456 1457 do { 1458 irq_masked = irq_stat & hpriv->port_map; 1459 spin_lock(&host->lock); 1460 rc = ahci_handle_port_intr(host, irq_masked); 1461 if (!rc) 1462 handled = 0; 1463 writel(irq_stat, mmio + HOST_IRQ_STAT); 1464 irq_stat = readl(mmio + HOST_IRQ_STAT); 1465 spin_unlock(&host->lock); 1466 } while (irq_stat); 1467 VPRINTK("EXIT\n"); 1468 1469 return IRQ_RETVAL(handled); 1470 } 1471 #endif 1472 1473 static void ahci_remap_check(struct pci_dev *pdev, int bar, 1474 struct ahci_host_priv *hpriv) 1475 { 1476 int i, count = 0; 1477 u32 cap; 1478 1479 /* 1480 * Check if this device might have remapped nvme devices. 1481 */ 1482 if (pdev->vendor != PCI_VENDOR_ID_INTEL || 1483 pci_resource_len(pdev, bar) < SZ_512K || 1484 bar != AHCI_PCI_BAR_STANDARD || 1485 !(readl(hpriv->mmio + AHCI_VSCAP) & 1)) 1486 return; 1487 1488 cap = readq(hpriv->mmio + AHCI_REMAP_CAP); 1489 for (i = 0; i < AHCI_MAX_REMAP; i++) { 1490 if ((cap & (1 << i)) == 0) 1491 continue; 1492 if (readl(hpriv->mmio + ahci_remap_dcc(i)) 1493 != PCI_CLASS_STORAGE_EXPRESS) 1494 continue; 1495 1496 /* We've found a remapped device */ 1497 count++; 1498 } 1499 1500 if (!count) 1501 return; 1502 1503 dev_warn(&pdev->dev, "Found %d remapped NVMe devices.\n", count); 1504 dev_warn(&pdev->dev, 1505 "Switch your BIOS from RAID to AHCI mode to use them.\n"); 1506 1507 /* 1508 * Don't rely on the msi-x capability in the remap case, 1509 * share the legacy interrupt across ahci and remapped devices. 1510 */ 1511 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1512 } 1513 1514 static int ahci_get_irq_vector(struct ata_host *host, int port) 1515 { 1516 return pci_irq_vector(to_pci_dev(host->dev), port); 1517 } 1518 1519 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports, 1520 struct ahci_host_priv *hpriv) 1521 { 1522 int nvec; 1523 1524 if (hpriv->flags & AHCI_HFLAG_NO_MSI) 1525 return -ENODEV; 1526 1527 /* 1528 * If number of MSIs is less than number of ports then Sharing Last 1529 * Message mode could be enforced. In this case assume that advantage 1530 * of multipe MSIs is negated and use single MSI mode instead. 1531 */ 1532 if (n_ports > 1) { 1533 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX, 1534 PCI_IRQ_MSIX | PCI_IRQ_MSI); 1535 if (nvec > 0) { 1536 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) { 1537 hpriv->get_irq_vector = ahci_get_irq_vector; 1538 hpriv->flags |= AHCI_HFLAG_MULTI_MSI; 1539 return nvec; 1540 } 1541 1542 /* 1543 * Fallback to single MSI mode if the controller 1544 * enforced MRSM mode. 1545 */ 1546 printk(KERN_INFO 1547 "ahci: MRSM is on, fallback to single MSI\n"); 1548 pci_free_irq_vectors(pdev); 1549 } 1550 } 1551 1552 /* 1553 * If the host is not capable of supporting per-port vectors, fall 1554 * back to single MSI before finally attempting single MSI-X. 1555 */ 1556 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 1557 if (nvec == 1) 1558 return nvec; 1559 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX); 1560 } 1561 1562 static void ahci_update_initial_lpm_policy(struct ata_port *ap, 1563 struct ahci_host_priv *hpriv) 1564 { 1565 int policy = CONFIG_SATA_MOBILE_LPM_POLICY; 1566 1567 1568 /* Ignore processing for non mobile platforms */ 1569 if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE)) 1570 return; 1571 1572 /* user modified policy via module param */ 1573 if (mobile_lpm_policy != -1) { 1574 policy = mobile_lpm_policy; 1575 goto update_policy; 1576 } 1577 1578 #ifdef CONFIG_ACPI 1579 if (policy > ATA_LPM_MED_POWER && 1580 (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) { 1581 if (hpriv->cap & HOST_CAP_PART) 1582 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL; 1583 else if (hpriv->cap & HOST_CAP_SSC) 1584 policy = ATA_LPM_MIN_POWER; 1585 } 1586 #endif 1587 1588 update_policy: 1589 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER) 1590 ap->target_lpm_policy = policy; 1591 } 1592 1593 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv) 1594 { 1595 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev); 1596 u16 tmp16; 1597 1598 /* 1599 * Only apply the 6-port PCS quirk for known legacy platforms. 1600 */ 1601 if (!id || id->vendor != PCI_VENDOR_ID_INTEL) 1602 return; 1603 1604 /* Skip applying the quirk on Denverton and beyond */ 1605 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7) 1606 return; 1607 1608 /* 1609 * port_map is determined from PORTS_IMPL PCI register which is 1610 * implemented as write or write-once register. If the register 1611 * isn't programmed, ahci automatically generates it from number 1612 * of ports, which is good enough for PCS programming. It is 1613 * otherwise expected that platform firmware enables the ports 1614 * before the OS boots. 1615 */ 1616 pci_read_config_word(pdev, PCS_6, &tmp16); 1617 if ((tmp16 & hpriv->port_map) != hpriv->port_map) { 1618 tmp16 |= hpriv->port_map; 1619 pci_write_config_word(pdev, PCS_6, tmp16); 1620 } 1621 } 1622 1623 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1624 { 1625 unsigned int board_id = ent->driver_data; 1626 struct ata_port_info pi = ahci_port_info[board_id]; 1627 const struct ata_port_info *ppi[] = { &pi, NULL }; 1628 struct device *dev = &pdev->dev; 1629 struct ahci_host_priv *hpriv; 1630 struct ata_host *host; 1631 int n_ports, i, rc; 1632 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD; 1633 1634 VPRINTK("ENTER\n"); 1635 1636 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS); 1637 1638 ata_print_version_once(&pdev->dev, DRV_VERSION); 1639 1640 /* The AHCI driver can only drive the SATA ports, the PATA driver 1641 can drive them all so if both drivers are selected make sure 1642 AHCI stays out of the way */ 1643 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable) 1644 return -ENODEV; 1645 1646 /* Apple BIOS on MCP89 prevents us using AHCI */ 1647 if (is_mcp89_apple(pdev)) 1648 ahci_mcp89_apple_enable(pdev); 1649 1650 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode. 1651 * At the moment, we can only use the AHCI mode. Let the users know 1652 * that for SAS drives they're out of luck. 1653 */ 1654 if (pdev->vendor == PCI_VENDOR_ID_PROMISE) 1655 dev_info(&pdev->dev, 1656 "PDC42819 can only drive SATA devices with this driver\n"); 1657 1658 /* Some devices use non-standard BARs */ 1659 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06) 1660 ahci_pci_bar = AHCI_PCI_BAR_STA2X11; 1661 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000) 1662 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS; 1663 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) { 1664 if (pdev->device == 0xa01c) 1665 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM; 1666 if (pdev->device == 0xa084) 1667 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5; 1668 } 1669 1670 /* acquire resources */ 1671 rc = pcim_enable_device(pdev); 1672 if (rc) 1673 return rc; 1674 1675 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 1676 (pdev->device == 0x2652 || pdev->device == 0x2653)) { 1677 u8 map; 1678 1679 /* ICH6s share the same PCI ID for both piix and ahci 1680 * modes. Enabling ahci mode while MAP indicates 1681 * combined mode is a bad idea. Yield to ata_piix. 1682 */ 1683 pci_read_config_byte(pdev, ICH_MAP, &map); 1684 if (map & 0x3) { 1685 dev_info(&pdev->dev, 1686 "controller is in combined mode, can't enable AHCI mode\n"); 1687 return -ENODEV; 1688 } 1689 } 1690 1691 /* AHCI controllers often implement SFF compatible interface. 1692 * Grab all PCI BARs just in case. 1693 */ 1694 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME); 1695 if (rc == -EBUSY) 1696 pcim_pin_device(pdev); 1697 if (rc) 1698 return rc; 1699 1700 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1701 if (!hpriv) 1702 return -ENOMEM; 1703 hpriv->flags |= (unsigned long)pi.private_data; 1704 1705 /* MCP65 revision A1 and A2 can't do MSI */ 1706 if (board_id == board_ahci_mcp65 && 1707 (pdev->revision == 0xa1 || pdev->revision == 0xa2)) 1708 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1709 1710 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */ 1711 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40) 1712 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL; 1713 1714 /* only some SB600s can do 64bit DMA */ 1715 if (ahci_sb600_enable_64bit(pdev)) 1716 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY; 1717 1718 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar]; 1719 1720 /* detect remapped nvme devices */ 1721 ahci_remap_check(pdev, ahci_pci_bar, hpriv); 1722 1723 /* must set flag prior to save config in order to take effect */ 1724 if (ahci_broken_devslp(pdev)) 1725 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP; 1726 1727 #ifdef CONFIG_ARM64 1728 if (pdev->vendor == 0x177d && pdev->device == 0xa01c) 1729 hpriv->irq_handler = ahci_thunderx_irq_handler; 1730 #endif 1731 1732 /* save initial config */ 1733 ahci_pci_save_initial_config(pdev, hpriv); 1734 1735 /* 1736 * If platform firmware failed to enable ports, try to enable 1737 * them here. 1738 */ 1739 ahci_intel_pcs_quirk(pdev, hpriv); 1740 1741 /* prepare host */ 1742 if (hpriv->cap & HOST_CAP_NCQ) { 1743 pi.flags |= ATA_FLAG_NCQ; 1744 /* 1745 * Auto-activate optimization is supposed to be 1746 * supported on all AHCI controllers indicating NCQ 1747 * capability, but it seems to be broken on some 1748 * chipsets including NVIDIAs. 1749 */ 1750 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA)) 1751 pi.flags |= ATA_FLAG_FPDMA_AA; 1752 1753 /* 1754 * All AHCI controllers should be forward-compatible 1755 * with the new auxiliary field. This code should be 1756 * conditionalized if any buggy AHCI controllers are 1757 * encountered. 1758 */ 1759 pi.flags |= ATA_FLAG_FPDMA_AUX; 1760 } 1761 1762 if (hpriv->cap & HOST_CAP_PMP) 1763 pi.flags |= ATA_FLAG_PMP; 1764 1765 ahci_set_em_messages(hpriv, &pi); 1766 1767 if (ahci_broken_system_poweroff(pdev)) { 1768 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN; 1769 dev_info(&pdev->dev, 1770 "quirky BIOS, skipping spindown on poweroff\n"); 1771 } 1772 1773 if (ahci_broken_lpm(pdev)) { 1774 pi.flags |= ATA_FLAG_NO_LPM; 1775 dev_warn(&pdev->dev, 1776 "BIOS update required for Link Power Management support\n"); 1777 } 1778 1779 if (ahci_broken_suspend(pdev)) { 1780 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND; 1781 dev_warn(&pdev->dev, 1782 "BIOS update required for suspend/resume\n"); 1783 } 1784 1785 if (ahci_broken_online(pdev)) { 1786 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE; 1787 dev_info(&pdev->dev, 1788 "online status unreliable, applying workaround\n"); 1789 } 1790 1791 1792 /* Acer SA5-271 workaround modifies private_data */ 1793 acer_sa5_271_workaround(hpriv, pdev); 1794 1795 /* CAP.NP sometimes indicate the index of the last enabled 1796 * port, at other times, that of the last possible port, so 1797 * determining the maximum port number requires looking at 1798 * both CAP.NP and port_map. 1799 */ 1800 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); 1801 1802 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 1803 if (!host) 1804 return -ENOMEM; 1805 host->private_data = hpriv; 1806 1807 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) { 1808 /* legacy intx interrupts */ 1809 pci_intx(pdev, 1); 1810 } 1811 hpriv->irq = pci_irq_vector(pdev, 0); 1812 1813 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) 1814 host->flags |= ATA_HOST_PARALLEL_SCAN; 1815 else 1816 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n"); 1817 1818 if (pi.flags & ATA_FLAG_EM) 1819 ahci_reset_em(host); 1820 1821 for (i = 0; i < host->n_ports; i++) { 1822 struct ata_port *ap = host->ports[i]; 1823 1824 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar"); 1825 ata_port_pbar_desc(ap, ahci_pci_bar, 1826 0x100 + ap->port_no * 0x80, "port"); 1827 1828 /* set enclosure management message type */ 1829 if (ap->flags & ATA_FLAG_EM) 1830 ap->em_message_type = hpriv->em_msg_type; 1831 1832 ahci_update_initial_lpm_policy(ap, hpriv); 1833 1834 /* disabled/not-implemented port */ 1835 if (!(hpriv->port_map & (1 << i))) 1836 ap->ops = &ata_dummy_port_ops; 1837 } 1838 1839 /* apply workaround for ASUS P5W DH Deluxe mainboard */ 1840 ahci_p5wdh_workaround(host); 1841 1842 /* apply gtf filter quirk */ 1843 ahci_gtf_filter_workaround(host); 1844 1845 /* initialize adapter */ 1846 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); 1847 if (rc) 1848 return rc; 1849 1850 rc = ahci_reset_controller(host); 1851 if (rc) 1852 return rc; 1853 1854 ahci_pci_init_controller(host); 1855 ahci_pci_print_info(host); 1856 1857 pci_set_master(pdev); 1858 1859 rc = ahci_host_activate(host, &ahci_sht); 1860 if (rc) 1861 return rc; 1862 1863 pm_runtime_put_noidle(&pdev->dev); 1864 return 0; 1865 } 1866 1867 static void ahci_remove_one(struct pci_dev *pdev) 1868 { 1869 pm_runtime_get_noresume(&pdev->dev); 1870 ata_pci_remove_one(pdev); 1871 } 1872 1873 module_pci_driver(ahci_pci_driver); 1874 1875 MODULE_AUTHOR("Jeff Garzik"); 1876 MODULE_DESCRIPTION("AHCI SATA low-level driver"); 1877 MODULE_LICENSE("GPL"); 1878 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); 1879 MODULE_VERSION(DRV_VERSION); 1880