1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ahci.c - AHCI SATA support 4 * 5 * Maintained by: Tejun Heo <tj@kernel.org> 6 * Please ALWAYS copy linux-ide@vger.kernel.org 7 * on emails. 8 * 9 * Copyright 2004-2005 Red Hat, Inc. 10 * 11 * libata documentation is available via 'make {ps|pdf}docs', 12 * as Documentation/driver-api/libata.rst 13 * 14 * AHCI hardware documentation: 15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/blkdev.h> 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/device.h> 27 #include <linux/dmi.h> 28 #include <linux/gfp.h> 29 #include <linux/msi.h> 30 #include <scsi/scsi_host.h> 31 #include <scsi/scsi_cmnd.h> 32 #include <linux/libata.h> 33 #include <linux/ahci-remap.h> 34 #include <linux/io-64-nonatomic-lo-hi.h> 35 #include "ahci.h" 36 37 #define DRV_NAME "ahci" 38 #define DRV_VERSION "3.0" 39 40 enum { 41 AHCI_PCI_BAR_STA2X11 = 0, 42 AHCI_PCI_BAR_CAVIUM = 0, 43 AHCI_PCI_BAR_LOONGSON = 0, 44 AHCI_PCI_BAR_ENMOTUS = 2, 45 AHCI_PCI_BAR_CAVIUM_GEN5 = 4, 46 AHCI_PCI_BAR_STANDARD = 5, 47 }; 48 49 enum board_ids { 50 /* board IDs by feature in alphabetical order */ 51 board_ahci, 52 board_ahci_ign_iferr, 53 board_ahci_mobile, 54 board_ahci_nomsi, 55 board_ahci_noncq, 56 board_ahci_nosntf, 57 board_ahci_yes_fbs, 58 59 /* board IDs for specific chipsets in alphabetical order */ 60 board_ahci_al, 61 board_ahci_avn, 62 board_ahci_mcp65, 63 board_ahci_mcp77, 64 board_ahci_mcp89, 65 board_ahci_mv, 66 board_ahci_sb600, 67 board_ahci_sb700, /* for SB700 and SB800 */ 68 board_ahci_vt8251, 69 70 /* 71 * board IDs for Intel chipsets that support more than 6 ports 72 * *and* end up needing the PCS quirk. 73 */ 74 board_ahci_pcs7, 75 76 /* aliases */ 77 board_ahci_mcp_linux = board_ahci_mcp65, 78 board_ahci_mcp67 = board_ahci_mcp65, 79 board_ahci_mcp73 = board_ahci_mcp65, 80 board_ahci_mcp79 = board_ahci_mcp77, 81 }; 82 83 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 84 static void ahci_remove_one(struct pci_dev *dev); 85 static void ahci_shutdown_one(struct pci_dev *dev); 86 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 87 unsigned long deadline); 88 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 89 unsigned long deadline); 90 static void ahci_mcp89_apple_enable(struct pci_dev *pdev); 91 static bool is_mcp89_apple(struct pci_dev *pdev); 92 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 93 unsigned long deadline); 94 #ifdef CONFIG_PM 95 static int ahci_pci_device_runtime_suspend(struct device *dev); 96 static int ahci_pci_device_runtime_resume(struct device *dev); 97 #ifdef CONFIG_PM_SLEEP 98 static int ahci_pci_device_suspend(struct device *dev); 99 static int ahci_pci_device_resume(struct device *dev); 100 #endif 101 #endif /* CONFIG_PM */ 102 103 static struct scsi_host_template ahci_sht = { 104 AHCI_SHT("ahci"), 105 }; 106 107 static struct ata_port_operations ahci_vt8251_ops = { 108 .inherits = &ahci_ops, 109 .hardreset = ahci_vt8251_hardreset, 110 }; 111 112 static struct ata_port_operations ahci_p5wdh_ops = { 113 .inherits = &ahci_ops, 114 .hardreset = ahci_p5wdh_hardreset, 115 }; 116 117 static struct ata_port_operations ahci_avn_ops = { 118 .inherits = &ahci_ops, 119 .hardreset = ahci_avn_hardreset, 120 }; 121 122 static const struct ata_port_info ahci_port_info[] = { 123 /* by features */ 124 [board_ahci] = { 125 .flags = AHCI_FLAG_COMMON, 126 .pio_mask = ATA_PIO4, 127 .udma_mask = ATA_UDMA6, 128 .port_ops = &ahci_ops, 129 }, 130 [board_ahci_ign_iferr] = { 131 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), 132 .flags = AHCI_FLAG_COMMON, 133 .pio_mask = ATA_PIO4, 134 .udma_mask = ATA_UDMA6, 135 .port_ops = &ahci_ops, 136 }, 137 [board_ahci_mobile] = { 138 AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE), 139 .flags = AHCI_FLAG_COMMON, 140 .pio_mask = ATA_PIO4, 141 .udma_mask = ATA_UDMA6, 142 .port_ops = &ahci_ops, 143 }, 144 [board_ahci_nomsi] = { 145 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI), 146 .flags = AHCI_FLAG_COMMON, 147 .pio_mask = ATA_PIO4, 148 .udma_mask = ATA_UDMA6, 149 .port_ops = &ahci_ops, 150 }, 151 [board_ahci_noncq] = { 152 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ), 153 .flags = AHCI_FLAG_COMMON, 154 .pio_mask = ATA_PIO4, 155 .udma_mask = ATA_UDMA6, 156 .port_ops = &ahci_ops, 157 }, 158 [board_ahci_nosntf] = { 159 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF), 160 .flags = AHCI_FLAG_COMMON, 161 .pio_mask = ATA_PIO4, 162 .udma_mask = ATA_UDMA6, 163 .port_ops = &ahci_ops, 164 }, 165 [board_ahci_yes_fbs] = { 166 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS), 167 .flags = AHCI_FLAG_COMMON, 168 .pio_mask = ATA_PIO4, 169 .udma_mask = ATA_UDMA6, 170 .port_ops = &ahci_ops, 171 }, 172 /* by chipsets */ 173 [board_ahci_al] = { 174 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI), 175 .flags = AHCI_FLAG_COMMON, 176 .pio_mask = ATA_PIO4, 177 .udma_mask = ATA_UDMA6, 178 .port_ops = &ahci_ops, 179 }, 180 [board_ahci_avn] = { 181 .flags = AHCI_FLAG_COMMON, 182 .pio_mask = ATA_PIO4, 183 .udma_mask = ATA_UDMA6, 184 .port_ops = &ahci_avn_ops, 185 }, 186 [board_ahci_mcp65] = { 187 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP | 188 AHCI_HFLAG_YES_NCQ), 189 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM, 190 .pio_mask = ATA_PIO4, 191 .udma_mask = ATA_UDMA6, 192 .port_ops = &ahci_ops, 193 }, 194 [board_ahci_mcp77] = { 195 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP), 196 .flags = AHCI_FLAG_COMMON, 197 .pio_mask = ATA_PIO4, 198 .udma_mask = ATA_UDMA6, 199 .port_ops = &ahci_ops, 200 }, 201 [board_ahci_mcp89] = { 202 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA), 203 .flags = AHCI_FLAG_COMMON, 204 .pio_mask = ATA_PIO4, 205 .udma_mask = ATA_UDMA6, 206 .port_ops = &ahci_ops, 207 }, 208 [board_ahci_mv] = { 209 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | 210 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP), 211 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, 212 .pio_mask = ATA_PIO4, 213 .udma_mask = ATA_UDMA6, 214 .port_ops = &ahci_ops, 215 }, 216 [board_ahci_sb600] = { 217 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | 218 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 | 219 AHCI_HFLAG_32BIT_ONLY), 220 .flags = AHCI_FLAG_COMMON, 221 .pio_mask = ATA_PIO4, 222 .udma_mask = ATA_UDMA6, 223 .port_ops = &ahci_pmp_retry_srst_ops, 224 }, 225 [board_ahci_sb700] = { /* for SB700 and SB800 */ 226 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL), 227 .flags = AHCI_FLAG_COMMON, 228 .pio_mask = ATA_PIO4, 229 .udma_mask = ATA_UDMA6, 230 .port_ops = &ahci_pmp_retry_srst_ops, 231 }, 232 [board_ahci_vt8251] = { 233 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), 234 .flags = AHCI_FLAG_COMMON, 235 .pio_mask = ATA_PIO4, 236 .udma_mask = ATA_UDMA6, 237 .port_ops = &ahci_vt8251_ops, 238 }, 239 [board_ahci_pcs7] = { 240 .flags = AHCI_FLAG_COMMON, 241 .pio_mask = ATA_PIO4, 242 .udma_mask = ATA_UDMA6, 243 .port_ops = &ahci_ops, 244 }, 245 }; 246 247 static const struct pci_device_id ahci_pci_tbl[] = { 248 /* Intel */ 249 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */ 250 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ 251 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ 252 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ 253 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ 254 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ 255 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ 256 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ 257 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ 258 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ 259 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ 260 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ 261 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */ 262 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ 263 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ 264 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ 265 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ 266 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ 267 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ 268 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ 269 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ 270 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */ 271 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */ 272 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */ 273 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */ 274 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */ 275 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ 276 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */ 277 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ 278 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ 279 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */ 280 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */ 281 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */ 282 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */ 283 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */ 284 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */ 285 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */ 286 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */ 287 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */ 288 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */ 289 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */ 290 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */ 291 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */ 292 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */ 293 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */ 294 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */ 295 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */ 296 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */ 297 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */ 298 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */ 299 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */ 300 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */ 301 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */ 302 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */ 303 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */ 304 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */ 305 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */ 306 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */ 307 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */ 308 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */ 309 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */ 310 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */ 311 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */ 312 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */ 313 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */ 314 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */ 315 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */ 316 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */ 317 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */ 318 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */ 319 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */ 320 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */ 321 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */ 322 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */ 323 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */ 324 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */ 325 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */ 326 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */ 327 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */ 328 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */ 329 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */ 330 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */ 331 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */ 332 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */ 333 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */ 334 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */ 335 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */ 336 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */ 337 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */ 338 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */ 339 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */ 340 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */ 341 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */ 342 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */ 343 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */ 344 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */ 345 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */ 346 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */ 347 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */ 348 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */ 349 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */ 350 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */ 351 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */ 352 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */ 353 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */ 354 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */ 355 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */ 356 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */ 357 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */ 358 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */ 359 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */ 360 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */ 361 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */ 362 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */ 363 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */ 364 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */ 365 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */ 366 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */ 367 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */ 368 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */ 369 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */ 370 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */ 371 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */ 372 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */ 373 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */ 374 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */ 375 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */ 376 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */ 377 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */ 378 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */ 379 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */ 380 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */ 381 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */ 382 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */ 383 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */ 384 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */ 385 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */ 386 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */ 387 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */ 388 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */ 389 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */ 390 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */ 391 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */ 392 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */ 393 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/ 394 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/ 395 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/ 396 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/ 397 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/ 398 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/ 399 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/ 400 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/ 401 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/ 402 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/ 403 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/ 404 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/ 405 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */ 406 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */ 407 { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */ 408 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */ 409 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */ 410 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */ 411 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */ 412 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */ 413 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_mobile }, /* Comet Lake PCH RAID */ 414 415 /* JMicron 360/1/3/5/6, match class to avoid IDE function */ 416 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 417 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, 418 /* JMicron 362B and 362C have an AHCI function with IDE class code */ 419 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr }, 420 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr }, 421 /* May need to update quirk_jmicron_async_suspend() for additions */ 422 423 /* ATI */ 424 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ 425 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ 426 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ 427 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ 428 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ 429 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ 430 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ 431 432 /* Amazon's Annapurna Labs support */ 433 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031), 434 .class = PCI_CLASS_STORAGE_SATA_AHCI, 435 .class_mask = 0xffffff, 436 board_ahci_al }, 437 /* AMD */ 438 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */ 439 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */ 440 /* AMD is using RAID class only for ahci controllers */ 441 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 442 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci }, 443 444 /* VIA */ 445 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ 446 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ 447 448 /* NVIDIA */ 449 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */ 450 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */ 451 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */ 452 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */ 453 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */ 454 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */ 455 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */ 456 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */ 457 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */ 458 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */ 459 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */ 460 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */ 461 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */ 462 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */ 463 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */ 464 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */ 465 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */ 466 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */ 467 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */ 468 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */ 469 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */ 470 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */ 471 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */ 472 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */ 473 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */ 474 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */ 475 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */ 476 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */ 477 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */ 478 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */ 479 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */ 480 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */ 481 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */ 482 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */ 483 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */ 484 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */ 485 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */ 486 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */ 487 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */ 488 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */ 489 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */ 490 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */ 491 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */ 492 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */ 493 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */ 494 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */ 495 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */ 496 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */ 497 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */ 498 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */ 499 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */ 500 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */ 501 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */ 502 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */ 503 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */ 504 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */ 505 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */ 506 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */ 507 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */ 508 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */ 509 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */ 510 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */ 511 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */ 512 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */ 513 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */ 514 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */ 515 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */ 516 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */ 517 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */ 518 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */ 519 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */ 520 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */ 521 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */ 522 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */ 523 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */ 524 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */ 525 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */ 526 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */ 527 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */ 528 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */ 529 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */ 530 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */ 531 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */ 532 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */ 533 534 /* SiS */ 535 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ 536 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */ 537 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ 538 539 /* ST Microelectronics */ 540 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */ 541 542 /* Marvell */ 543 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ 544 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ 545 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123), 546 .class = PCI_CLASS_STORAGE_SATA_AHCI, 547 .class_mask = 0xffffff, 548 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */ 549 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125), 550 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */ 551 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178, 552 PCI_VENDOR_ID_MARVELL_EXT, 0x9170), 553 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */ 554 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a), 555 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 556 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172), 557 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */ 558 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182), 559 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 560 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192), 561 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */ 562 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0), 563 .driver_data = board_ahci_yes_fbs }, 564 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */ 565 .driver_data = board_ahci_yes_fbs }, 566 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3), 567 .driver_data = board_ahci_yes_fbs }, 568 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230), 569 .driver_data = board_ahci_yes_fbs }, 570 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */ 571 .driver_data = board_ahci_yes_fbs }, 572 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */ 573 .driver_data = board_ahci_yes_fbs }, 574 575 /* Promise */ 576 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */ 577 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */ 578 579 /* Asmedia */ 580 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */ 581 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */ 582 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */ 583 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */ 584 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */ 585 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */ 586 587 /* 588 * Samsung SSDs found on some macbooks. NCQ times out if MSI is 589 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731 590 */ 591 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi }, 592 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi }, 593 594 /* Enmotus */ 595 { PCI_DEVICE(0x1c44, 0x8000), board_ahci }, 596 597 /* Loongson */ 598 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci }, 599 600 /* Generic, PCI class code for AHCI */ 601 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 602 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, 603 604 { } /* terminate list */ 605 }; 606 607 static const struct dev_pm_ops ahci_pci_pm_ops = { 608 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume) 609 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend, 610 ahci_pci_device_runtime_resume, NULL) 611 }; 612 613 static struct pci_driver ahci_pci_driver = { 614 .name = DRV_NAME, 615 .id_table = ahci_pci_tbl, 616 .probe = ahci_init_one, 617 .remove = ahci_remove_one, 618 .shutdown = ahci_shutdown_one, 619 .driver = { 620 .pm = &ahci_pci_pm_ops, 621 }, 622 }; 623 624 #if IS_ENABLED(CONFIG_PATA_MARVELL) 625 static int marvell_enable; 626 #else 627 static int marvell_enable = 1; 628 #endif 629 module_param(marvell_enable, int, 0644); 630 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)"); 631 632 static int mobile_lpm_policy = -1; 633 module_param(mobile_lpm_policy, int, 0644); 634 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets"); 635 636 static void ahci_pci_save_initial_config(struct pci_dev *pdev, 637 struct ahci_host_priv *hpriv) 638 { 639 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) { 640 dev_info(&pdev->dev, "JMB361 has only one port\n"); 641 hpriv->force_port_map = 1; 642 } 643 644 /* 645 * Temporary Marvell 6145 hack: PATA port presence 646 * is asserted through the standard AHCI port 647 * presence register, as bit 4 (counting from 0) 648 */ 649 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 650 if (pdev->device == 0x6121) 651 hpriv->mask_port_map = 0x3; 652 else 653 hpriv->mask_port_map = 0xf; 654 dev_info(&pdev->dev, 655 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n"); 656 } 657 658 ahci_save_initial_config(&pdev->dev, hpriv); 659 } 660 661 static void ahci_pci_init_controller(struct ata_host *host) 662 { 663 struct ahci_host_priv *hpriv = host->private_data; 664 struct pci_dev *pdev = to_pci_dev(host->dev); 665 void __iomem *port_mmio; 666 u32 tmp; 667 int mv; 668 669 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 670 if (pdev->device == 0x6121) 671 mv = 2; 672 else 673 mv = 4; 674 port_mmio = __ahci_port_base(host, mv); 675 676 writel(0, port_mmio + PORT_IRQ_MASK); 677 678 /* clear port IRQ */ 679 tmp = readl(port_mmio + PORT_IRQ_STAT); 680 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 681 if (tmp) 682 writel(tmp, port_mmio + PORT_IRQ_STAT); 683 } 684 685 ahci_init_controller(host); 686 } 687 688 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 689 unsigned long deadline) 690 { 691 struct ata_port *ap = link->ap; 692 struct ahci_host_priv *hpriv = ap->host->private_data; 693 bool online; 694 int rc; 695 696 DPRINTK("ENTER\n"); 697 698 hpriv->stop_engine(ap); 699 700 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 701 deadline, &online, NULL); 702 703 hpriv->start_engine(ap); 704 705 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 706 707 /* vt8251 doesn't clear BSY on signature FIS reception, 708 * request follow-up softreset. 709 */ 710 return online ? -EAGAIN : rc; 711 } 712 713 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 714 unsigned long deadline) 715 { 716 struct ata_port *ap = link->ap; 717 struct ahci_port_priv *pp = ap->private_data; 718 struct ahci_host_priv *hpriv = ap->host->private_data; 719 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 720 struct ata_taskfile tf; 721 bool online; 722 int rc; 723 724 hpriv->stop_engine(ap); 725 726 /* clear D2H reception area to properly wait for D2H FIS */ 727 ata_tf_init(link->device, &tf); 728 tf.command = ATA_BUSY; 729 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 730 731 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 732 deadline, &online, NULL); 733 734 hpriv->start_engine(ap); 735 736 /* The pseudo configuration device on SIMG4726 attached to 737 * ASUS P5W-DH Deluxe doesn't send signature FIS after 738 * hardreset if no device is attached to the first downstream 739 * port && the pseudo device locks up on SRST w/ PMP==0. To 740 * work around this, wait for !BSY only briefly. If BSY isn't 741 * cleared, perform CLO and proceed to IDENTIFY (achieved by 742 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). 743 * 744 * Wait for two seconds. Devices attached to downstream port 745 * which can't process the following IDENTIFY after this will 746 * have to be reset again. For most cases, this should 747 * suffice while making probing snappish enough. 748 */ 749 if (online) { 750 rc = ata_wait_after_reset(link, jiffies + 2 * HZ, 751 ahci_check_ready); 752 if (rc) 753 ahci_kick_engine(ap); 754 } 755 return rc; 756 } 757 758 /* 759 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports. 760 * 761 * It has been observed with some SSDs that the timing of events in the 762 * link synchronization phase can leave the port in a state that can not 763 * be recovered by a SATA-hard-reset alone. The failing signature is 764 * SStatus.DET stuck at 1 ("Device presence detected but Phy 765 * communication not established"). It was found that unloading and 766 * reloading the driver when this problem occurs allows the drive 767 * connection to be recovered (DET advanced to 0x3). The critical 768 * component of reloading the driver is that the port state machines are 769 * reset by bouncing "port enable" in the AHCI PCS configuration 770 * register. So, reproduce that effect by bouncing a port whenever we 771 * see DET==1 after a reset. 772 */ 773 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 774 unsigned long deadline) 775 { 776 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 777 struct ata_port *ap = link->ap; 778 struct ahci_port_priv *pp = ap->private_data; 779 struct ahci_host_priv *hpriv = ap->host->private_data; 780 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 781 unsigned long tmo = deadline - jiffies; 782 struct ata_taskfile tf; 783 bool online; 784 int rc, i; 785 786 DPRINTK("ENTER\n"); 787 788 hpriv->stop_engine(ap); 789 790 for (i = 0; i < 2; i++) { 791 u16 val; 792 u32 sstatus; 793 int port = ap->port_no; 794 struct ata_host *host = ap->host; 795 struct pci_dev *pdev = to_pci_dev(host->dev); 796 797 /* clear D2H reception area to properly wait for D2H FIS */ 798 ata_tf_init(link->device, &tf); 799 tf.command = ATA_BUSY; 800 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 801 802 rc = sata_link_hardreset(link, timing, deadline, &online, 803 ahci_check_ready); 804 805 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 || 806 (sstatus & 0xf) != 1) 807 break; 808 809 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n", 810 port); 811 812 pci_read_config_word(pdev, 0x92, &val); 813 val &= ~(1 << port); 814 pci_write_config_word(pdev, 0x92, val); 815 ata_msleep(ap, 1000); 816 val |= 1 << port; 817 pci_write_config_word(pdev, 0x92, val); 818 deadline += tmo; 819 } 820 821 hpriv->start_engine(ap); 822 823 if (online) 824 *class = ahci_dev_classify(ap); 825 826 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 827 return rc; 828 } 829 830 831 #ifdef CONFIG_PM 832 static void ahci_pci_disable_interrupts(struct ata_host *host) 833 { 834 struct ahci_host_priv *hpriv = host->private_data; 835 void __iomem *mmio = hpriv->mmio; 836 u32 ctl; 837 838 /* AHCI spec rev1.1 section 8.3.3: 839 * Software must disable interrupts prior to requesting a 840 * transition of the HBA to D3 state. 841 */ 842 ctl = readl(mmio + HOST_CTL); 843 ctl &= ~HOST_IRQ_EN; 844 writel(ctl, mmio + HOST_CTL); 845 readl(mmio + HOST_CTL); /* flush */ 846 } 847 848 static int ahci_pci_device_runtime_suspend(struct device *dev) 849 { 850 struct pci_dev *pdev = to_pci_dev(dev); 851 struct ata_host *host = pci_get_drvdata(pdev); 852 853 ahci_pci_disable_interrupts(host); 854 return 0; 855 } 856 857 static int ahci_pci_device_runtime_resume(struct device *dev) 858 { 859 struct pci_dev *pdev = to_pci_dev(dev); 860 struct ata_host *host = pci_get_drvdata(pdev); 861 int rc; 862 863 rc = ahci_reset_controller(host); 864 if (rc) 865 return rc; 866 ahci_pci_init_controller(host); 867 return 0; 868 } 869 870 #ifdef CONFIG_PM_SLEEP 871 static int ahci_pci_device_suspend(struct device *dev) 872 { 873 struct pci_dev *pdev = to_pci_dev(dev); 874 struct ata_host *host = pci_get_drvdata(pdev); 875 struct ahci_host_priv *hpriv = host->private_data; 876 877 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { 878 dev_err(&pdev->dev, 879 "BIOS update required for suspend/resume\n"); 880 return -EIO; 881 } 882 883 ahci_pci_disable_interrupts(host); 884 return ata_host_suspend(host, PMSG_SUSPEND); 885 } 886 887 static int ahci_pci_device_resume(struct device *dev) 888 { 889 struct pci_dev *pdev = to_pci_dev(dev); 890 struct ata_host *host = pci_get_drvdata(pdev); 891 int rc; 892 893 /* Apple BIOS helpfully mangles the registers on resume */ 894 if (is_mcp89_apple(pdev)) 895 ahci_mcp89_apple_enable(pdev); 896 897 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { 898 rc = ahci_reset_controller(host); 899 if (rc) 900 return rc; 901 902 ahci_pci_init_controller(host); 903 } 904 905 ata_host_resume(host); 906 907 return 0; 908 } 909 #endif 910 911 #endif /* CONFIG_PM */ 912 913 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) 914 { 915 const int dma_bits = using_dac ? 64 : 32; 916 int rc; 917 918 /* 919 * If the device fixup already set the dma_mask to some non-standard 920 * value, don't extend it here. This happens on STA2X11, for example. 921 * 922 * XXX: manipulating the DMA mask from platform code is completely 923 * bogus, platform code should use dev->bus_dma_limit instead.. 924 */ 925 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32)) 926 return 0; 927 928 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits)); 929 if (rc) 930 dev_err(&pdev->dev, "DMA enable failed\n"); 931 return rc; 932 } 933 934 static void ahci_pci_print_info(struct ata_host *host) 935 { 936 struct pci_dev *pdev = to_pci_dev(host->dev); 937 u16 cc; 938 const char *scc_s; 939 940 pci_read_config_word(pdev, 0x0a, &cc); 941 if (cc == PCI_CLASS_STORAGE_IDE) 942 scc_s = "IDE"; 943 else if (cc == PCI_CLASS_STORAGE_SATA) 944 scc_s = "SATA"; 945 else if (cc == PCI_CLASS_STORAGE_RAID) 946 scc_s = "RAID"; 947 else 948 scc_s = "unknown"; 949 950 ahci_print_info(host, scc_s); 951 } 952 953 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is 954 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't 955 * support PMP and the 4726 either directly exports the device 956 * attached to the first downstream port or acts as a hardware storage 957 * controller and emulate a single ATA device (can be RAID 0/1 or some 958 * other configuration). 959 * 960 * When there's no device attached to the first downstream port of the 961 * 4726, "Config Disk" appears, which is a pseudo ATA device to 962 * configure the 4726. However, ATA emulation of the device is very 963 * lame. It doesn't send signature D2H Reg FIS after the initial 964 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. 965 * 966 * The following function works around the problem by always using 967 * hardreset on the port and not depending on receiving signature FIS 968 * afterward. If signature FIS isn't received soon, ATA class is 969 * assumed without follow-up softreset. 970 */ 971 static void ahci_p5wdh_workaround(struct ata_host *host) 972 { 973 static const struct dmi_system_id sysids[] = { 974 { 975 .ident = "P5W DH Deluxe", 976 .matches = { 977 DMI_MATCH(DMI_SYS_VENDOR, 978 "ASUSTEK COMPUTER INC"), 979 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), 980 }, 981 }, 982 { } 983 }; 984 struct pci_dev *pdev = to_pci_dev(host->dev); 985 986 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && 987 dmi_check_system(sysids)) { 988 struct ata_port *ap = host->ports[1]; 989 990 dev_info(&pdev->dev, 991 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n"); 992 993 ap->ops = &ahci_p5wdh_ops; 994 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; 995 } 996 } 997 998 /* 999 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when 1000 * booting in BIOS compatibility mode. We restore the registers but not ID. 1001 */ 1002 static void ahci_mcp89_apple_enable(struct pci_dev *pdev) 1003 { 1004 u32 val; 1005 1006 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n"); 1007 1008 pci_read_config_dword(pdev, 0xf8, &val); 1009 val |= 1 << 0x1b; 1010 /* the following changes the device ID, but appears not to affect function */ 1011 /* val = (val & ~0xf0000000) | 0x80000000; */ 1012 pci_write_config_dword(pdev, 0xf8, val); 1013 1014 pci_read_config_dword(pdev, 0x54c, &val); 1015 val |= 1 << 0xc; 1016 pci_write_config_dword(pdev, 0x54c, val); 1017 1018 pci_read_config_dword(pdev, 0x4a4, &val); 1019 val &= 0xff; 1020 val |= 0x01060100; 1021 pci_write_config_dword(pdev, 0x4a4, val); 1022 1023 pci_read_config_dword(pdev, 0x54c, &val); 1024 val &= ~(1 << 0xc); 1025 pci_write_config_dword(pdev, 0x54c, val); 1026 1027 pci_read_config_dword(pdev, 0xf8, &val); 1028 val &= ~(1 << 0x1b); 1029 pci_write_config_dword(pdev, 0xf8, val); 1030 } 1031 1032 static bool is_mcp89_apple(struct pci_dev *pdev) 1033 { 1034 return pdev->vendor == PCI_VENDOR_ID_NVIDIA && 1035 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA && 1036 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 1037 pdev->subsystem_device == 0xcb89; 1038 } 1039 1040 /* only some SB600 ahci controllers can do 64bit DMA */ 1041 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev) 1042 { 1043 static const struct dmi_system_id sysids[] = { 1044 /* 1045 * The oldest version known to be broken is 0901 and 1046 * working is 1501 which was released on 2007-10-26. 1047 * Enable 64bit DMA on 1501 and anything newer. 1048 * 1049 * Please read bko#9412 for more info. 1050 */ 1051 { 1052 .ident = "ASUS M2A-VM", 1053 .matches = { 1054 DMI_MATCH(DMI_BOARD_VENDOR, 1055 "ASUSTeK Computer INC."), 1056 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"), 1057 }, 1058 .driver_data = "20071026", /* yyyymmdd */ 1059 }, 1060 /* 1061 * All BIOS versions for the MSI K9A2 Platinum (MS-7376) 1062 * support 64bit DMA. 1063 * 1064 * BIOS versions earlier than 1.5 had the Manufacturer DMI 1065 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD". 1066 * This spelling mistake was fixed in BIOS version 1.5, so 1067 * 1.5 and later have the Manufacturer as 1068 * "MICRO-STAR INTERNATIONAL CO.,LTD". 1069 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER". 1070 * 1071 * BIOS versions earlier than 1.9 had a Board Product Name 1072 * DMI field of "MS-7376". This was changed to be 1073 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still 1074 * match on DMI_BOARD_NAME of "MS-7376". 1075 */ 1076 { 1077 .ident = "MSI K9A2 Platinum", 1078 .matches = { 1079 DMI_MATCH(DMI_BOARD_VENDOR, 1080 "MICRO-STAR INTER"), 1081 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"), 1082 }, 1083 }, 1084 /* 1085 * All BIOS versions for the MSI K9AGM2 (MS-7327) support 1086 * 64bit DMA. 1087 * 1088 * This board also had the typo mentioned above in the 1089 * Manufacturer DMI field (fixed in BIOS version 1.5), so 1090 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again. 1091 */ 1092 { 1093 .ident = "MSI K9AGM2", 1094 .matches = { 1095 DMI_MATCH(DMI_BOARD_VENDOR, 1096 "MICRO-STAR INTER"), 1097 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"), 1098 }, 1099 }, 1100 /* 1101 * All BIOS versions for the Asus M3A support 64bit DMA. 1102 * (all release versions from 0301 to 1206 were tested) 1103 */ 1104 { 1105 .ident = "ASUS M3A", 1106 .matches = { 1107 DMI_MATCH(DMI_BOARD_VENDOR, 1108 "ASUSTeK Computer INC."), 1109 DMI_MATCH(DMI_BOARD_NAME, "M3A"), 1110 }, 1111 }, 1112 { } 1113 }; 1114 const struct dmi_system_id *match; 1115 int year, month, date; 1116 char buf[9]; 1117 1118 match = dmi_first_match(sysids); 1119 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) || 1120 !match) 1121 return false; 1122 1123 if (!match->driver_data) 1124 goto enable_64bit; 1125 1126 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1127 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1128 1129 if (strcmp(buf, match->driver_data) >= 0) 1130 goto enable_64bit; 1131 else { 1132 dev_warn(&pdev->dev, 1133 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n", 1134 match->ident); 1135 return false; 1136 } 1137 1138 enable_64bit: 1139 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident); 1140 return true; 1141 } 1142 1143 static bool ahci_broken_system_poweroff(struct pci_dev *pdev) 1144 { 1145 static const struct dmi_system_id broken_systems[] = { 1146 { 1147 .ident = "HP Compaq nx6310", 1148 .matches = { 1149 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1150 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"), 1151 }, 1152 /* PCI slot number of the controller */ 1153 .driver_data = (void *)0x1FUL, 1154 }, 1155 { 1156 .ident = "HP Compaq 6720s", 1157 .matches = { 1158 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1159 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"), 1160 }, 1161 /* PCI slot number of the controller */ 1162 .driver_data = (void *)0x1FUL, 1163 }, 1164 1165 { } /* terminate list */ 1166 }; 1167 const struct dmi_system_id *dmi = dmi_first_match(broken_systems); 1168 1169 if (dmi) { 1170 unsigned long slot = (unsigned long)dmi->driver_data; 1171 /* apply the quirk only to on-board controllers */ 1172 return slot == PCI_SLOT(pdev->devfn); 1173 } 1174 1175 return false; 1176 } 1177 1178 static bool ahci_broken_suspend(struct pci_dev *pdev) 1179 { 1180 static const struct dmi_system_id sysids[] = { 1181 /* 1182 * On HP dv[4-6] and HDX18 with earlier BIOSen, link 1183 * to the harddisk doesn't become online after 1184 * resuming from STR. Warn and fail suspend. 1185 * 1186 * http://bugzilla.kernel.org/show_bug.cgi?id=12276 1187 * 1188 * Use dates instead of versions to match as HP is 1189 * apparently recycling both product and version 1190 * strings. 1191 * 1192 * http://bugzilla.kernel.org/show_bug.cgi?id=15462 1193 */ 1194 { 1195 .ident = "dv4", 1196 .matches = { 1197 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1198 DMI_MATCH(DMI_PRODUCT_NAME, 1199 "HP Pavilion dv4 Notebook PC"), 1200 }, 1201 .driver_data = "20090105", /* F.30 */ 1202 }, 1203 { 1204 .ident = "dv5", 1205 .matches = { 1206 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1207 DMI_MATCH(DMI_PRODUCT_NAME, 1208 "HP Pavilion dv5 Notebook PC"), 1209 }, 1210 .driver_data = "20090506", /* F.16 */ 1211 }, 1212 { 1213 .ident = "dv6", 1214 .matches = { 1215 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1216 DMI_MATCH(DMI_PRODUCT_NAME, 1217 "HP Pavilion dv6 Notebook PC"), 1218 }, 1219 .driver_data = "20090423", /* F.21 */ 1220 }, 1221 { 1222 .ident = "HDX18", 1223 .matches = { 1224 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1225 DMI_MATCH(DMI_PRODUCT_NAME, 1226 "HP HDX18 Notebook PC"), 1227 }, 1228 .driver_data = "20090430", /* F.23 */ 1229 }, 1230 /* 1231 * Acer eMachines G725 has the same problem. BIOS 1232 * V1.03 is known to be broken. V3.04 is known to 1233 * work. Between, there are V1.06, V2.06 and V3.03 1234 * that we don't have much idea about. For now, 1235 * blacklist anything older than V3.04. 1236 * 1237 * http://bugzilla.kernel.org/show_bug.cgi?id=15104 1238 */ 1239 { 1240 .ident = "G725", 1241 .matches = { 1242 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"), 1243 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"), 1244 }, 1245 .driver_data = "20091216", /* V3.04 */ 1246 }, 1247 { } /* terminate list */ 1248 }; 1249 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1250 int year, month, date; 1251 char buf[9]; 1252 1253 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2)) 1254 return false; 1255 1256 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1257 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1258 1259 return strcmp(buf, dmi->driver_data) < 0; 1260 } 1261 1262 static bool ahci_broken_lpm(struct pci_dev *pdev) 1263 { 1264 static const struct dmi_system_id sysids[] = { 1265 /* Various Lenovo 50 series have LPM issues with older BIOSen */ 1266 { 1267 .matches = { 1268 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1269 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"), 1270 }, 1271 .driver_data = "20180406", /* 1.31 */ 1272 }, 1273 { 1274 .matches = { 1275 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1276 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"), 1277 }, 1278 .driver_data = "20180420", /* 1.28 */ 1279 }, 1280 { 1281 .matches = { 1282 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1283 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"), 1284 }, 1285 .driver_data = "20180315", /* 1.33 */ 1286 }, 1287 { 1288 .matches = { 1289 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1290 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"), 1291 }, 1292 /* 1293 * Note date based on release notes, 2.35 has been 1294 * reported to be good, but I've been unable to get 1295 * a hold of the reporter to get the DMI BIOS date. 1296 * TODO: fix this. 1297 */ 1298 .driver_data = "20180310", /* 2.35 */ 1299 }, 1300 { } /* terminate list */ 1301 }; 1302 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1303 int year, month, date; 1304 char buf[9]; 1305 1306 if (!dmi) 1307 return false; 1308 1309 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1310 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1311 1312 return strcmp(buf, dmi->driver_data) < 0; 1313 } 1314 1315 static bool ahci_broken_online(struct pci_dev *pdev) 1316 { 1317 #define ENCODE_BUSDEVFN(bus, slot, func) \ 1318 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func))) 1319 static const struct dmi_system_id sysids[] = { 1320 /* 1321 * There are several gigabyte boards which use 1322 * SIMG5723s configured as hardware RAID. Certain 1323 * 5723 firmware revisions shipped there keep the link 1324 * online but fail to answer properly to SRST or 1325 * IDENTIFY when no device is attached downstream 1326 * causing libata to retry quite a few times leading 1327 * to excessive detection delay. 1328 * 1329 * As these firmwares respond to the second reset try 1330 * with invalid device signature, considering unknown 1331 * sig as offline works around the problem acceptably. 1332 */ 1333 { 1334 .ident = "EP45-DQ6", 1335 .matches = { 1336 DMI_MATCH(DMI_BOARD_VENDOR, 1337 "Gigabyte Technology Co., Ltd."), 1338 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"), 1339 }, 1340 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0), 1341 }, 1342 { 1343 .ident = "EP45-DS5", 1344 .matches = { 1345 DMI_MATCH(DMI_BOARD_VENDOR, 1346 "Gigabyte Technology Co., Ltd."), 1347 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"), 1348 }, 1349 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0), 1350 }, 1351 { } /* terminate list */ 1352 }; 1353 #undef ENCODE_BUSDEVFN 1354 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1355 unsigned int val; 1356 1357 if (!dmi) 1358 return false; 1359 1360 val = (unsigned long)dmi->driver_data; 1361 1362 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff); 1363 } 1364 1365 static bool ahci_broken_devslp(struct pci_dev *pdev) 1366 { 1367 /* device with broken DEVSLP but still showing SDS capability */ 1368 static const struct pci_device_id ids[] = { 1369 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */ 1370 {} 1371 }; 1372 1373 return pci_match_id(ids, pdev); 1374 } 1375 1376 #ifdef CONFIG_ATA_ACPI 1377 static void ahci_gtf_filter_workaround(struct ata_host *host) 1378 { 1379 static const struct dmi_system_id sysids[] = { 1380 /* 1381 * Aspire 3810T issues a bunch of SATA enable commands 1382 * via _GTF including an invalid one and one which is 1383 * rejected by the device. Among the successful ones 1384 * is FPDMA non-zero offset enable which when enabled 1385 * only on the drive side leads to NCQ command 1386 * failures. Filter it out. 1387 */ 1388 { 1389 .ident = "Aspire 3810T", 1390 .matches = { 1391 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1392 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"), 1393 }, 1394 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET, 1395 }, 1396 { } 1397 }; 1398 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1399 unsigned int filter; 1400 int i; 1401 1402 if (!dmi) 1403 return; 1404 1405 filter = (unsigned long)dmi->driver_data; 1406 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n", 1407 filter, dmi->ident); 1408 1409 for (i = 0; i < host->n_ports; i++) { 1410 struct ata_port *ap = host->ports[i]; 1411 struct ata_link *link; 1412 struct ata_device *dev; 1413 1414 ata_for_each_link(link, ap, EDGE) 1415 ata_for_each_dev(dev, link, ALL) 1416 dev->gtf_filter |= filter; 1417 } 1418 } 1419 #else 1420 static inline void ahci_gtf_filter_workaround(struct ata_host *host) 1421 {} 1422 #endif 1423 1424 /* 1425 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected 1426 * as DUMMY, or detected but eventually get a "link down" and never get up 1427 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the 1428 * port_map may hold a value of 0x00. 1429 * 1430 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports 1431 * and can significantly reduce the occurrence of the problem. 1432 * 1433 * https://bugzilla.kernel.org/show_bug.cgi?id=189471 1434 */ 1435 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv, 1436 struct pci_dev *pdev) 1437 { 1438 static const struct dmi_system_id sysids[] = { 1439 { 1440 .ident = "Acer Switch Alpha 12", 1441 .matches = { 1442 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1443 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271") 1444 }, 1445 }, 1446 { } 1447 }; 1448 1449 if (dmi_check_system(sysids)) { 1450 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n"); 1451 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) { 1452 hpriv->port_map = 0x7; 1453 hpriv->cap = 0xC734FF02; 1454 } 1455 } 1456 } 1457 1458 #ifdef CONFIG_ARM64 1459 /* 1460 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently. 1461 * Workaround is to make sure all pending IRQs are served before leaving 1462 * handler. 1463 */ 1464 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance) 1465 { 1466 struct ata_host *host = dev_instance; 1467 struct ahci_host_priv *hpriv; 1468 unsigned int rc = 0; 1469 void __iomem *mmio; 1470 u32 irq_stat, irq_masked; 1471 unsigned int handled = 1; 1472 1473 VPRINTK("ENTER\n"); 1474 hpriv = host->private_data; 1475 mmio = hpriv->mmio; 1476 irq_stat = readl(mmio + HOST_IRQ_STAT); 1477 if (!irq_stat) 1478 return IRQ_NONE; 1479 1480 do { 1481 irq_masked = irq_stat & hpriv->port_map; 1482 spin_lock(&host->lock); 1483 rc = ahci_handle_port_intr(host, irq_masked); 1484 if (!rc) 1485 handled = 0; 1486 writel(irq_stat, mmio + HOST_IRQ_STAT); 1487 irq_stat = readl(mmio + HOST_IRQ_STAT); 1488 spin_unlock(&host->lock); 1489 } while (irq_stat); 1490 VPRINTK("EXIT\n"); 1491 1492 return IRQ_RETVAL(handled); 1493 } 1494 #endif 1495 1496 static void ahci_remap_check(struct pci_dev *pdev, int bar, 1497 struct ahci_host_priv *hpriv) 1498 { 1499 int i; 1500 u32 cap; 1501 1502 /* 1503 * Check if this device might have remapped nvme devices. 1504 */ 1505 if (pdev->vendor != PCI_VENDOR_ID_INTEL || 1506 pci_resource_len(pdev, bar) < SZ_512K || 1507 bar != AHCI_PCI_BAR_STANDARD || 1508 !(readl(hpriv->mmio + AHCI_VSCAP) & 1)) 1509 return; 1510 1511 cap = readq(hpriv->mmio + AHCI_REMAP_CAP); 1512 for (i = 0; i < AHCI_MAX_REMAP; i++) { 1513 if ((cap & (1 << i)) == 0) 1514 continue; 1515 if (readl(hpriv->mmio + ahci_remap_dcc(i)) 1516 != PCI_CLASS_STORAGE_EXPRESS) 1517 continue; 1518 1519 /* We've found a remapped device */ 1520 hpriv->remapped_nvme++; 1521 } 1522 1523 if (!hpriv->remapped_nvme) 1524 return; 1525 1526 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n", 1527 hpriv->remapped_nvme); 1528 dev_warn(&pdev->dev, 1529 "Switch your BIOS from RAID to AHCI mode to use them.\n"); 1530 1531 /* 1532 * Don't rely on the msi-x capability in the remap case, 1533 * share the legacy interrupt across ahci and remapped devices. 1534 */ 1535 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1536 } 1537 1538 static int ahci_get_irq_vector(struct ata_host *host, int port) 1539 { 1540 return pci_irq_vector(to_pci_dev(host->dev), port); 1541 } 1542 1543 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports, 1544 struct ahci_host_priv *hpriv) 1545 { 1546 int nvec; 1547 1548 if (hpriv->flags & AHCI_HFLAG_NO_MSI) 1549 return -ENODEV; 1550 1551 /* 1552 * If number of MSIs is less than number of ports then Sharing Last 1553 * Message mode could be enforced. In this case assume that advantage 1554 * of multipe MSIs is negated and use single MSI mode instead. 1555 */ 1556 if (n_ports > 1) { 1557 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX, 1558 PCI_IRQ_MSIX | PCI_IRQ_MSI); 1559 if (nvec > 0) { 1560 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) { 1561 hpriv->get_irq_vector = ahci_get_irq_vector; 1562 hpriv->flags |= AHCI_HFLAG_MULTI_MSI; 1563 return nvec; 1564 } 1565 1566 /* 1567 * Fallback to single MSI mode if the controller 1568 * enforced MRSM mode. 1569 */ 1570 printk(KERN_INFO 1571 "ahci: MRSM is on, fallback to single MSI\n"); 1572 pci_free_irq_vectors(pdev); 1573 } 1574 } 1575 1576 /* 1577 * If the host is not capable of supporting per-port vectors, fall 1578 * back to single MSI before finally attempting single MSI-X. 1579 */ 1580 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 1581 if (nvec == 1) 1582 return nvec; 1583 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX); 1584 } 1585 1586 static void ahci_update_initial_lpm_policy(struct ata_port *ap, 1587 struct ahci_host_priv *hpriv) 1588 { 1589 int policy = CONFIG_SATA_MOBILE_LPM_POLICY; 1590 1591 1592 /* Ignore processing for non mobile platforms */ 1593 if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE)) 1594 return; 1595 1596 /* user modified policy via module param */ 1597 if (mobile_lpm_policy != -1) { 1598 policy = mobile_lpm_policy; 1599 goto update_policy; 1600 } 1601 1602 #ifdef CONFIG_ACPI 1603 if (policy > ATA_LPM_MED_POWER && 1604 (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) { 1605 if (hpriv->cap & HOST_CAP_PART) 1606 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL; 1607 else if (hpriv->cap & HOST_CAP_SSC) 1608 policy = ATA_LPM_MIN_POWER; 1609 } 1610 #endif 1611 1612 update_policy: 1613 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER) 1614 ap->target_lpm_policy = policy; 1615 } 1616 1617 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv) 1618 { 1619 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev); 1620 u16 tmp16; 1621 1622 /* 1623 * Only apply the 6-port PCS quirk for known legacy platforms. 1624 */ 1625 if (!id || id->vendor != PCI_VENDOR_ID_INTEL) 1626 return; 1627 1628 /* Skip applying the quirk on Denverton and beyond */ 1629 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7) 1630 return; 1631 1632 /* 1633 * port_map is determined from PORTS_IMPL PCI register which is 1634 * implemented as write or write-once register. If the register 1635 * isn't programmed, ahci automatically generates it from number 1636 * of ports, which is good enough for PCS programming. It is 1637 * otherwise expected that platform firmware enables the ports 1638 * before the OS boots. 1639 */ 1640 pci_read_config_word(pdev, PCS_6, &tmp16); 1641 if ((tmp16 & hpriv->port_map) != hpriv->port_map) { 1642 tmp16 |= hpriv->port_map; 1643 pci_write_config_word(pdev, PCS_6, tmp16); 1644 } 1645 } 1646 1647 static ssize_t remapped_nvme_show(struct device *dev, 1648 struct device_attribute *attr, 1649 char *buf) 1650 { 1651 struct ata_host *host = dev_get_drvdata(dev); 1652 struct ahci_host_priv *hpriv = host->private_data; 1653 1654 return sprintf(buf, "%u\n", hpriv->remapped_nvme); 1655 } 1656 1657 static DEVICE_ATTR_RO(remapped_nvme); 1658 1659 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1660 { 1661 unsigned int board_id = ent->driver_data; 1662 struct ata_port_info pi = ahci_port_info[board_id]; 1663 const struct ata_port_info *ppi[] = { &pi, NULL }; 1664 struct device *dev = &pdev->dev; 1665 struct ahci_host_priv *hpriv; 1666 struct ata_host *host; 1667 int n_ports, i, rc; 1668 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD; 1669 1670 VPRINTK("ENTER\n"); 1671 1672 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS); 1673 1674 ata_print_version_once(&pdev->dev, DRV_VERSION); 1675 1676 /* The AHCI driver can only drive the SATA ports, the PATA driver 1677 can drive them all so if both drivers are selected make sure 1678 AHCI stays out of the way */ 1679 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable) 1680 return -ENODEV; 1681 1682 /* Apple BIOS on MCP89 prevents us using AHCI */ 1683 if (is_mcp89_apple(pdev)) 1684 ahci_mcp89_apple_enable(pdev); 1685 1686 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode. 1687 * At the moment, we can only use the AHCI mode. Let the users know 1688 * that for SAS drives they're out of luck. 1689 */ 1690 if (pdev->vendor == PCI_VENDOR_ID_PROMISE) 1691 dev_info(&pdev->dev, 1692 "PDC42819 can only drive SATA devices with this driver\n"); 1693 1694 /* Some devices use non-standard BARs */ 1695 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06) 1696 ahci_pci_bar = AHCI_PCI_BAR_STA2X11; 1697 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000) 1698 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS; 1699 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) { 1700 if (pdev->device == 0xa01c) 1701 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM; 1702 if (pdev->device == 0xa084) 1703 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5; 1704 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) { 1705 if (pdev->device == 0x7a08) 1706 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON; 1707 } 1708 1709 /* acquire resources */ 1710 rc = pcim_enable_device(pdev); 1711 if (rc) 1712 return rc; 1713 1714 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 1715 (pdev->device == 0x2652 || pdev->device == 0x2653)) { 1716 u8 map; 1717 1718 /* ICH6s share the same PCI ID for both piix and ahci 1719 * modes. Enabling ahci mode while MAP indicates 1720 * combined mode is a bad idea. Yield to ata_piix. 1721 */ 1722 pci_read_config_byte(pdev, ICH_MAP, &map); 1723 if (map & 0x3) { 1724 dev_info(&pdev->dev, 1725 "controller is in combined mode, can't enable AHCI mode\n"); 1726 return -ENODEV; 1727 } 1728 } 1729 1730 /* AHCI controllers often implement SFF compatible interface. 1731 * Grab all PCI BARs just in case. 1732 */ 1733 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME); 1734 if (rc == -EBUSY) 1735 pcim_pin_device(pdev); 1736 if (rc) 1737 return rc; 1738 1739 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1740 if (!hpriv) 1741 return -ENOMEM; 1742 hpriv->flags |= (unsigned long)pi.private_data; 1743 1744 /* MCP65 revision A1 and A2 can't do MSI */ 1745 if (board_id == board_ahci_mcp65 && 1746 (pdev->revision == 0xa1 || pdev->revision == 0xa2)) 1747 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1748 1749 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */ 1750 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40) 1751 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL; 1752 1753 /* only some SB600s can do 64bit DMA */ 1754 if (ahci_sb600_enable_64bit(pdev)) 1755 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY; 1756 1757 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar]; 1758 1759 /* detect remapped nvme devices */ 1760 ahci_remap_check(pdev, ahci_pci_bar, hpriv); 1761 1762 sysfs_add_file_to_group(&pdev->dev.kobj, 1763 &dev_attr_remapped_nvme.attr, 1764 NULL); 1765 1766 /* must set flag prior to save config in order to take effect */ 1767 if (ahci_broken_devslp(pdev)) 1768 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP; 1769 1770 #ifdef CONFIG_ARM64 1771 if (pdev->vendor == 0x177d && pdev->device == 0xa01c) 1772 hpriv->irq_handler = ahci_thunderx_irq_handler; 1773 #endif 1774 1775 /* save initial config */ 1776 ahci_pci_save_initial_config(pdev, hpriv); 1777 1778 /* 1779 * If platform firmware failed to enable ports, try to enable 1780 * them here. 1781 */ 1782 ahci_intel_pcs_quirk(pdev, hpriv); 1783 1784 /* prepare host */ 1785 if (hpriv->cap & HOST_CAP_NCQ) { 1786 pi.flags |= ATA_FLAG_NCQ; 1787 /* 1788 * Auto-activate optimization is supposed to be 1789 * supported on all AHCI controllers indicating NCQ 1790 * capability, but it seems to be broken on some 1791 * chipsets including NVIDIAs. 1792 */ 1793 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA)) 1794 pi.flags |= ATA_FLAG_FPDMA_AA; 1795 1796 /* 1797 * All AHCI controllers should be forward-compatible 1798 * with the new auxiliary field. This code should be 1799 * conditionalized if any buggy AHCI controllers are 1800 * encountered. 1801 */ 1802 pi.flags |= ATA_FLAG_FPDMA_AUX; 1803 } 1804 1805 if (hpriv->cap & HOST_CAP_PMP) 1806 pi.flags |= ATA_FLAG_PMP; 1807 1808 ahci_set_em_messages(hpriv, &pi); 1809 1810 if (ahci_broken_system_poweroff(pdev)) { 1811 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN; 1812 dev_info(&pdev->dev, 1813 "quirky BIOS, skipping spindown on poweroff\n"); 1814 } 1815 1816 if (ahci_broken_lpm(pdev)) { 1817 pi.flags |= ATA_FLAG_NO_LPM; 1818 dev_warn(&pdev->dev, 1819 "BIOS update required for Link Power Management support\n"); 1820 } 1821 1822 if (ahci_broken_suspend(pdev)) { 1823 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND; 1824 dev_warn(&pdev->dev, 1825 "BIOS update required for suspend/resume\n"); 1826 } 1827 1828 if (ahci_broken_online(pdev)) { 1829 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE; 1830 dev_info(&pdev->dev, 1831 "online status unreliable, applying workaround\n"); 1832 } 1833 1834 1835 /* Acer SA5-271 workaround modifies private_data */ 1836 acer_sa5_271_workaround(hpriv, pdev); 1837 1838 /* CAP.NP sometimes indicate the index of the last enabled 1839 * port, at other times, that of the last possible port, so 1840 * determining the maximum port number requires looking at 1841 * both CAP.NP and port_map. 1842 */ 1843 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); 1844 1845 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 1846 if (!host) 1847 return -ENOMEM; 1848 host->private_data = hpriv; 1849 1850 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) { 1851 /* legacy intx interrupts */ 1852 pci_intx(pdev, 1); 1853 } 1854 hpriv->irq = pci_irq_vector(pdev, 0); 1855 1856 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) 1857 host->flags |= ATA_HOST_PARALLEL_SCAN; 1858 else 1859 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n"); 1860 1861 if (pi.flags & ATA_FLAG_EM) 1862 ahci_reset_em(host); 1863 1864 for (i = 0; i < host->n_ports; i++) { 1865 struct ata_port *ap = host->ports[i]; 1866 1867 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar"); 1868 ata_port_pbar_desc(ap, ahci_pci_bar, 1869 0x100 + ap->port_no * 0x80, "port"); 1870 1871 /* set enclosure management message type */ 1872 if (ap->flags & ATA_FLAG_EM) 1873 ap->em_message_type = hpriv->em_msg_type; 1874 1875 ahci_update_initial_lpm_policy(ap, hpriv); 1876 1877 /* disabled/not-implemented port */ 1878 if (!(hpriv->port_map & (1 << i))) 1879 ap->ops = &ata_dummy_port_ops; 1880 } 1881 1882 /* apply workaround for ASUS P5W DH Deluxe mainboard */ 1883 ahci_p5wdh_workaround(host); 1884 1885 /* apply gtf filter quirk */ 1886 ahci_gtf_filter_workaround(host); 1887 1888 /* initialize adapter */ 1889 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); 1890 if (rc) 1891 return rc; 1892 1893 rc = ahci_reset_controller(host); 1894 if (rc) 1895 return rc; 1896 1897 ahci_pci_init_controller(host); 1898 ahci_pci_print_info(host); 1899 1900 pci_set_master(pdev); 1901 1902 rc = ahci_host_activate(host, &ahci_sht); 1903 if (rc) 1904 return rc; 1905 1906 pm_runtime_put_noidle(&pdev->dev); 1907 return 0; 1908 } 1909 1910 static void ahci_shutdown_one(struct pci_dev *pdev) 1911 { 1912 ata_pci_shutdown_one(pdev); 1913 } 1914 1915 static void ahci_remove_one(struct pci_dev *pdev) 1916 { 1917 sysfs_remove_file_from_group(&pdev->dev.kobj, 1918 &dev_attr_remapped_nvme.attr, 1919 NULL); 1920 pm_runtime_get_noresume(&pdev->dev); 1921 ata_pci_remove_one(pdev); 1922 } 1923 1924 module_pci_driver(ahci_pci_driver); 1925 1926 MODULE_AUTHOR("Jeff Garzik"); 1927 MODULE_DESCRIPTION("AHCI SATA low-level driver"); 1928 MODULE_LICENSE("GPL"); 1929 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); 1930 MODULE_VERSION(DRV_VERSION); 1931