1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (C) 2011 Google, Inc. 5 * 6 * Author: 7 * Jay Cheng <jacheng@nvidia.com> 8 * James Wylder <james.wylder@motorola.com> 9 * Benoit Goby <benoit@android.com> 10 * Colin Cross <ccross@android.com> 11 * Hiroshi DOYU <hdoyu@nvidia.com> 12 */ 13 14 #include <linux/err.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/platform_device.h> 18 #include <linux/io.h> 19 #include <linux/of.h> 20 21 #include <soc/tegra/ahb.h> 22 23 #define DRV_NAME "tegra-ahb" 24 25 #define AHB_ARBITRATION_DISABLE 0x04 26 #define AHB_ARBITRATION_PRIORITY_CTRL 0x08 27 #define AHB_PRIORITY_WEIGHT(x) (((x) & 0x7) << 29) 28 #define PRIORITY_SELECT_USB BIT(6) 29 #define PRIORITY_SELECT_USB2 BIT(18) 30 #define PRIORITY_SELECT_USB3 BIT(17) 31 32 #define AHB_GIZMO_AHB_MEM 0x10 33 #define ENB_FAST_REARBITRATE BIT(2) 34 #define DONT_SPLIT_AHB_WR BIT(7) 35 36 #define AHB_GIZMO_APB_DMA 0x14 37 #define AHB_GIZMO_IDE 0x1c 38 #define AHB_GIZMO_USB 0x20 39 #define AHB_GIZMO_AHB_XBAR_BRIDGE 0x24 40 #define AHB_GIZMO_CPU_AHB_BRIDGE 0x28 41 #define AHB_GIZMO_COP_AHB_BRIDGE 0x2c 42 #define AHB_GIZMO_XBAR_APB_CTLR 0x30 43 #define AHB_GIZMO_VCP_AHB_BRIDGE 0x34 44 #define AHB_GIZMO_NAND 0x40 45 #define AHB_GIZMO_SDMMC4 0x48 46 #define AHB_GIZMO_XIO 0x4c 47 #define AHB_GIZMO_BSEV 0x64 48 #define AHB_GIZMO_BSEA 0x74 49 #define AHB_GIZMO_NOR 0x78 50 #define AHB_GIZMO_USB2 0x7c 51 #define AHB_GIZMO_USB3 0x80 52 #define IMMEDIATE BIT(18) 53 54 #define AHB_GIZMO_SDMMC1 0x84 55 #define AHB_GIZMO_SDMMC2 0x88 56 #define AHB_GIZMO_SDMMC3 0x8c 57 #define AHB_MEM_PREFETCH_CFG_X 0xdc 58 #define AHB_ARBITRATION_XBAR_CTRL 0xe0 59 #define AHB_MEM_PREFETCH_CFG3 0xe4 60 #define AHB_MEM_PREFETCH_CFG4 0xe8 61 #define AHB_MEM_PREFETCH_CFG1 0xf0 62 #define AHB_MEM_PREFETCH_CFG2 0xf4 63 #define PREFETCH_ENB BIT(31) 64 #define MST_ID(x) (((x) & 0x1f) << 26) 65 #define AHBDMA_MST_ID MST_ID(5) 66 #define USB_MST_ID MST_ID(6) 67 #define USB2_MST_ID MST_ID(18) 68 #define USB3_MST_ID MST_ID(17) 69 #define ADDR_BNDRY(x) (((x) & 0xf) << 21) 70 #define INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0) 71 72 #define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID 0xfc 73 74 #define AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE BIT(17) 75 76 /* 77 * INCORRECT_BASE_ADDR_LOW_BYTE: Legacy kernel DT files for Tegra SoCs 78 * prior to Tegra124 generally use a physical base address ending in 79 * 0x4 for the AHB IP block. According to the TRM, the low byte 80 * should be 0x0. During device probing, this macro is used to detect 81 * whether the passed-in physical address is incorrect, and if so, to 82 * correct it. 83 */ 84 #define INCORRECT_BASE_ADDR_LOW_BYTE 0x4 85 86 static struct platform_driver tegra_ahb_driver; 87 88 static const u32 tegra_ahb_gizmo[] = { 89 AHB_ARBITRATION_DISABLE, 90 AHB_ARBITRATION_PRIORITY_CTRL, 91 AHB_GIZMO_AHB_MEM, 92 AHB_GIZMO_APB_DMA, 93 AHB_GIZMO_IDE, 94 AHB_GIZMO_USB, 95 AHB_GIZMO_AHB_XBAR_BRIDGE, 96 AHB_GIZMO_CPU_AHB_BRIDGE, 97 AHB_GIZMO_COP_AHB_BRIDGE, 98 AHB_GIZMO_XBAR_APB_CTLR, 99 AHB_GIZMO_VCP_AHB_BRIDGE, 100 AHB_GIZMO_NAND, 101 AHB_GIZMO_SDMMC4, 102 AHB_GIZMO_XIO, 103 AHB_GIZMO_BSEV, 104 AHB_GIZMO_BSEA, 105 AHB_GIZMO_NOR, 106 AHB_GIZMO_USB2, 107 AHB_GIZMO_USB3, 108 AHB_GIZMO_SDMMC1, 109 AHB_GIZMO_SDMMC2, 110 AHB_GIZMO_SDMMC3, 111 AHB_MEM_PREFETCH_CFG_X, 112 AHB_ARBITRATION_XBAR_CTRL, 113 AHB_MEM_PREFETCH_CFG3, 114 AHB_MEM_PREFETCH_CFG4, 115 AHB_MEM_PREFETCH_CFG1, 116 AHB_MEM_PREFETCH_CFG2, 117 AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID, 118 }; 119 120 struct tegra_ahb { 121 void __iomem *regs; 122 struct device *dev; 123 u32 ctx[]; 124 }; 125 126 static inline u32 gizmo_readl(struct tegra_ahb *ahb, u32 offset) 127 { 128 return readl(ahb->regs + offset); 129 } 130 131 static inline void gizmo_writel(struct tegra_ahb *ahb, u32 value, u32 offset) 132 { 133 writel(value, ahb->regs + offset); 134 } 135 136 #ifdef CONFIG_TEGRA_IOMMU_SMMU 137 int tegra_ahb_enable_smmu(struct device_node *dn) 138 { 139 struct device *dev; 140 u32 val; 141 struct tegra_ahb *ahb; 142 143 dev = driver_find_device_by_of_node(&tegra_ahb_driver.driver, dn); 144 if (!dev) 145 return -EPROBE_DEFER; 146 ahb = dev_get_drvdata(dev); 147 val = gizmo_readl(ahb, AHB_ARBITRATION_XBAR_CTRL); 148 val |= AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE; 149 gizmo_writel(ahb, val, AHB_ARBITRATION_XBAR_CTRL); 150 return 0; 151 } 152 EXPORT_SYMBOL(tegra_ahb_enable_smmu); 153 #endif 154 155 static int __maybe_unused tegra_ahb_suspend(struct device *dev) 156 { 157 int i; 158 struct tegra_ahb *ahb = dev_get_drvdata(dev); 159 160 for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++) 161 ahb->ctx[i] = gizmo_readl(ahb, tegra_ahb_gizmo[i]); 162 return 0; 163 } 164 165 static int __maybe_unused tegra_ahb_resume(struct device *dev) 166 { 167 int i; 168 struct tegra_ahb *ahb = dev_get_drvdata(dev); 169 170 for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++) 171 gizmo_writel(ahb, ahb->ctx[i], tegra_ahb_gizmo[i]); 172 return 0; 173 } 174 175 static UNIVERSAL_DEV_PM_OPS(tegra_ahb_pm, 176 tegra_ahb_suspend, 177 tegra_ahb_resume, NULL); 178 179 static void tegra_ahb_gizmo_init(struct tegra_ahb *ahb) 180 { 181 u32 val; 182 183 val = gizmo_readl(ahb, AHB_GIZMO_AHB_MEM); 184 val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR; 185 gizmo_writel(ahb, val, AHB_GIZMO_AHB_MEM); 186 187 val = gizmo_readl(ahb, AHB_GIZMO_USB); 188 val |= IMMEDIATE; 189 gizmo_writel(ahb, val, AHB_GIZMO_USB); 190 191 val = gizmo_readl(ahb, AHB_GIZMO_USB2); 192 val |= IMMEDIATE; 193 gizmo_writel(ahb, val, AHB_GIZMO_USB2); 194 195 val = gizmo_readl(ahb, AHB_GIZMO_USB3); 196 val |= IMMEDIATE; 197 gizmo_writel(ahb, val, AHB_GIZMO_USB3); 198 199 val = gizmo_readl(ahb, AHB_ARBITRATION_PRIORITY_CTRL); 200 val |= PRIORITY_SELECT_USB | 201 PRIORITY_SELECT_USB2 | 202 PRIORITY_SELECT_USB3 | 203 AHB_PRIORITY_WEIGHT(7); 204 gizmo_writel(ahb, val, AHB_ARBITRATION_PRIORITY_CTRL); 205 206 val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG1); 207 val &= ~MST_ID(~0); 208 val |= PREFETCH_ENB | 209 AHBDMA_MST_ID | 210 ADDR_BNDRY(0xc) | 211 INACTIVITY_TIMEOUT(0x1000); 212 gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG1); 213 214 val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG2); 215 val &= ~MST_ID(~0); 216 val |= PREFETCH_ENB | 217 USB_MST_ID | 218 ADDR_BNDRY(0xc) | 219 INACTIVITY_TIMEOUT(0x1000); 220 gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG2); 221 222 val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG3); 223 val &= ~MST_ID(~0); 224 val |= PREFETCH_ENB | 225 USB3_MST_ID | 226 ADDR_BNDRY(0xc) | 227 INACTIVITY_TIMEOUT(0x1000); 228 gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG3); 229 230 val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG4); 231 val &= ~MST_ID(~0); 232 val |= PREFETCH_ENB | 233 USB2_MST_ID | 234 ADDR_BNDRY(0xc) | 235 INACTIVITY_TIMEOUT(0x1000); 236 gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG4); 237 } 238 239 static int tegra_ahb_probe(struct platform_device *pdev) 240 { 241 struct resource *res; 242 struct tegra_ahb *ahb; 243 size_t bytes; 244 245 bytes = sizeof(*ahb) + sizeof(u32) * ARRAY_SIZE(tegra_ahb_gizmo); 246 ahb = devm_kzalloc(&pdev->dev, bytes, GFP_KERNEL); 247 if (!ahb) 248 return -ENOMEM; 249 250 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 251 252 /* Correct the IP block base address if necessary */ 253 if (res && 254 (res->start & INCORRECT_BASE_ADDR_LOW_BYTE) == 255 INCORRECT_BASE_ADDR_LOW_BYTE) { 256 dev_warn(&pdev->dev, "incorrect AHB base address in DT data - enabling workaround\n"); 257 res->start -= INCORRECT_BASE_ADDR_LOW_BYTE; 258 } 259 260 ahb->regs = devm_ioremap_resource(&pdev->dev, res); 261 if (IS_ERR(ahb->regs)) 262 return PTR_ERR(ahb->regs); 263 264 ahb->dev = &pdev->dev; 265 platform_set_drvdata(pdev, ahb); 266 tegra_ahb_gizmo_init(ahb); 267 return 0; 268 } 269 270 static const struct of_device_id tegra_ahb_of_match[] = { 271 { .compatible = "nvidia,tegra30-ahb", }, 272 { .compatible = "nvidia,tegra20-ahb", }, 273 {}, 274 }; 275 276 static struct platform_driver tegra_ahb_driver = { 277 .probe = tegra_ahb_probe, 278 .driver = { 279 .name = DRV_NAME, 280 .of_match_table = tegra_ahb_of_match, 281 .pm = &tegra_ahb_pm, 282 }, 283 }; 284 module_platform_driver(tegra_ahb_driver); 285 286 MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>"); 287 MODULE_DESCRIPTION("Tegra AHB driver"); 288 MODULE_LICENSE("GPL v2"); 289 MODULE_ALIAS("platform:" DRV_NAME); 290