1 /* 2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 3 * Copyright (C) 2011 Google, Inc. 4 * 5 * Author: 6 * Jay Cheng <jacheng@nvidia.com> 7 * James Wylder <james.wylder@motorola.com> 8 * Benoit Goby <benoit@android.com> 9 * Colin Cross <ccross@android.com> 10 * Hiroshi DOYU <hdoyu@nvidia.com> 11 * 12 * This software is licensed under the terms of the GNU General Public 13 * License version 2, as published by the Free Software Foundation, and 14 * may be copied, distributed, and modified under those terms. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 */ 22 23 #include <linux/err.h> 24 #include <linux/kernel.h> 25 #include <linux/module.h> 26 #include <linux/platform_device.h> 27 #include <linux/io.h> 28 29 #include <soc/tegra/ahb.h> 30 31 #define DRV_NAME "tegra-ahb" 32 33 #define AHB_ARBITRATION_DISABLE 0x00 34 #define AHB_ARBITRATION_PRIORITY_CTRL 0x04 35 #define AHB_PRIORITY_WEIGHT(x) (((x) & 0x7) << 29) 36 #define PRIORITY_SELECT_USB BIT(6) 37 #define PRIORITY_SELECT_USB2 BIT(18) 38 #define PRIORITY_SELECT_USB3 BIT(17) 39 40 #define AHB_GIZMO_AHB_MEM 0x0c 41 #define ENB_FAST_REARBITRATE BIT(2) 42 #define DONT_SPLIT_AHB_WR BIT(7) 43 44 #define AHB_GIZMO_APB_DMA 0x10 45 #define AHB_GIZMO_IDE 0x18 46 #define AHB_GIZMO_USB 0x1c 47 #define AHB_GIZMO_AHB_XBAR_BRIDGE 0x20 48 #define AHB_GIZMO_CPU_AHB_BRIDGE 0x24 49 #define AHB_GIZMO_COP_AHB_BRIDGE 0x28 50 #define AHB_GIZMO_XBAR_APB_CTLR 0x2c 51 #define AHB_GIZMO_VCP_AHB_BRIDGE 0x30 52 #define AHB_GIZMO_NAND 0x3c 53 #define AHB_GIZMO_SDMMC4 0x44 54 #define AHB_GIZMO_XIO 0x48 55 #define AHB_GIZMO_BSEV 0x60 56 #define AHB_GIZMO_BSEA 0x70 57 #define AHB_GIZMO_NOR 0x74 58 #define AHB_GIZMO_USB2 0x78 59 #define AHB_GIZMO_USB3 0x7c 60 #define IMMEDIATE BIT(18) 61 62 #define AHB_GIZMO_SDMMC1 0x80 63 #define AHB_GIZMO_SDMMC2 0x84 64 #define AHB_GIZMO_SDMMC3 0x88 65 #define AHB_MEM_PREFETCH_CFG_X 0xd8 66 #define AHB_ARBITRATION_XBAR_CTRL 0xdc 67 #define AHB_MEM_PREFETCH_CFG3 0xe0 68 #define AHB_MEM_PREFETCH_CFG4 0xe4 69 #define AHB_MEM_PREFETCH_CFG1 0xec 70 #define AHB_MEM_PREFETCH_CFG2 0xf0 71 #define PREFETCH_ENB BIT(31) 72 #define MST_ID(x) (((x) & 0x1f) << 26) 73 #define AHBDMA_MST_ID MST_ID(5) 74 #define USB_MST_ID MST_ID(6) 75 #define USB2_MST_ID MST_ID(18) 76 #define USB3_MST_ID MST_ID(17) 77 #define ADDR_BNDRY(x) (((x) & 0xf) << 21) 78 #define INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0) 79 80 #define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID 0xf8 81 82 #define AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE BIT(17) 83 84 static struct platform_driver tegra_ahb_driver; 85 86 static const u32 tegra_ahb_gizmo[] = { 87 AHB_ARBITRATION_DISABLE, 88 AHB_ARBITRATION_PRIORITY_CTRL, 89 AHB_GIZMO_AHB_MEM, 90 AHB_GIZMO_APB_DMA, 91 AHB_GIZMO_IDE, 92 AHB_GIZMO_USB, 93 AHB_GIZMO_AHB_XBAR_BRIDGE, 94 AHB_GIZMO_CPU_AHB_BRIDGE, 95 AHB_GIZMO_COP_AHB_BRIDGE, 96 AHB_GIZMO_XBAR_APB_CTLR, 97 AHB_GIZMO_VCP_AHB_BRIDGE, 98 AHB_GIZMO_NAND, 99 AHB_GIZMO_SDMMC4, 100 AHB_GIZMO_XIO, 101 AHB_GIZMO_BSEV, 102 AHB_GIZMO_BSEA, 103 AHB_GIZMO_NOR, 104 AHB_GIZMO_USB2, 105 AHB_GIZMO_USB3, 106 AHB_GIZMO_SDMMC1, 107 AHB_GIZMO_SDMMC2, 108 AHB_GIZMO_SDMMC3, 109 AHB_MEM_PREFETCH_CFG_X, 110 AHB_ARBITRATION_XBAR_CTRL, 111 AHB_MEM_PREFETCH_CFG3, 112 AHB_MEM_PREFETCH_CFG4, 113 AHB_MEM_PREFETCH_CFG1, 114 AHB_MEM_PREFETCH_CFG2, 115 AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID, 116 }; 117 118 struct tegra_ahb { 119 void __iomem *regs; 120 struct device *dev; 121 u32 ctx[0]; 122 }; 123 124 static inline u32 gizmo_readl(struct tegra_ahb *ahb, u32 offset) 125 { 126 return readl(ahb->regs + offset); 127 } 128 129 static inline void gizmo_writel(struct tegra_ahb *ahb, u32 value, u32 offset) 130 { 131 writel(value, ahb->regs + offset); 132 } 133 134 #ifdef CONFIG_TEGRA_IOMMU_SMMU 135 static int tegra_ahb_match_by_smmu(struct device *dev, void *data) 136 { 137 struct tegra_ahb *ahb = dev_get_drvdata(dev); 138 struct device_node *dn = data; 139 140 return (ahb->dev->of_node == dn) ? 1 : 0; 141 } 142 143 int tegra_ahb_enable_smmu(struct device_node *dn) 144 { 145 struct device *dev; 146 u32 val; 147 struct tegra_ahb *ahb; 148 149 dev = driver_find_device(&tegra_ahb_driver.driver, NULL, dn, 150 tegra_ahb_match_by_smmu); 151 if (!dev) 152 return -EPROBE_DEFER; 153 ahb = dev_get_drvdata(dev); 154 val = gizmo_readl(ahb, AHB_ARBITRATION_XBAR_CTRL); 155 val |= AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE; 156 gizmo_writel(ahb, val, AHB_ARBITRATION_XBAR_CTRL); 157 return 0; 158 } 159 EXPORT_SYMBOL(tegra_ahb_enable_smmu); 160 #endif 161 162 #ifdef CONFIG_PM 163 static int tegra_ahb_suspend(struct device *dev) 164 { 165 int i; 166 struct tegra_ahb *ahb = dev_get_drvdata(dev); 167 168 for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++) 169 ahb->ctx[i] = gizmo_readl(ahb, tegra_ahb_gizmo[i]); 170 return 0; 171 } 172 173 static int tegra_ahb_resume(struct device *dev) 174 { 175 int i; 176 struct tegra_ahb *ahb = dev_get_drvdata(dev); 177 178 for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++) 179 gizmo_writel(ahb, ahb->ctx[i], tegra_ahb_gizmo[i]); 180 return 0; 181 } 182 #endif 183 184 static UNIVERSAL_DEV_PM_OPS(tegra_ahb_pm, 185 tegra_ahb_suspend, 186 tegra_ahb_resume, NULL); 187 188 static void tegra_ahb_gizmo_init(struct tegra_ahb *ahb) 189 { 190 u32 val; 191 192 val = gizmo_readl(ahb, AHB_GIZMO_AHB_MEM); 193 val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR; 194 gizmo_writel(ahb, val, AHB_GIZMO_AHB_MEM); 195 196 val = gizmo_readl(ahb, AHB_GIZMO_USB); 197 val |= IMMEDIATE; 198 gizmo_writel(ahb, val, AHB_GIZMO_USB); 199 200 val = gizmo_readl(ahb, AHB_GIZMO_USB2); 201 val |= IMMEDIATE; 202 gizmo_writel(ahb, val, AHB_GIZMO_USB2); 203 204 val = gizmo_readl(ahb, AHB_GIZMO_USB3); 205 val |= IMMEDIATE; 206 gizmo_writel(ahb, val, AHB_GIZMO_USB3); 207 208 val = gizmo_readl(ahb, AHB_ARBITRATION_PRIORITY_CTRL); 209 val |= PRIORITY_SELECT_USB | 210 PRIORITY_SELECT_USB2 | 211 PRIORITY_SELECT_USB3 | 212 AHB_PRIORITY_WEIGHT(7); 213 gizmo_writel(ahb, val, AHB_ARBITRATION_PRIORITY_CTRL); 214 215 val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG1); 216 val &= ~MST_ID(~0); 217 val |= PREFETCH_ENB | 218 AHBDMA_MST_ID | 219 ADDR_BNDRY(0xc) | 220 INACTIVITY_TIMEOUT(0x1000); 221 gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG1); 222 223 val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG2); 224 val &= ~MST_ID(~0); 225 val |= PREFETCH_ENB | 226 USB_MST_ID | 227 ADDR_BNDRY(0xc) | 228 INACTIVITY_TIMEOUT(0x1000); 229 gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG2); 230 231 val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG3); 232 val &= ~MST_ID(~0); 233 val |= PREFETCH_ENB | 234 USB3_MST_ID | 235 ADDR_BNDRY(0xc) | 236 INACTIVITY_TIMEOUT(0x1000); 237 gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG3); 238 239 val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG4); 240 val &= ~MST_ID(~0); 241 val |= PREFETCH_ENB | 242 USB2_MST_ID | 243 ADDR_BNDRY(0xc) | 244 INACTIVITY_TIMEOUT(0x1000); 245 gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG4); 246 } 247 248 static int tegra_ahb_probe(struct platform_device *pdev) 249 { 250 struct resource *res; 251 struct tegra_ahb *ahb; 252 size_t bytes; 253 254 bytes = sizeof(*ahb) + sizeof(u32) * ARRAY_SIZE(tegra_ahb_gizmo); 255 ahb = devm_kzalloc(&pdev->dev, bytes, GFP_KERNEL); 256 if (!ahb) 257 return -ENOMEM; 258 259 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 260 ahb->regs = devm_ioremap_resource(&pdev->dev, res); 261 if (IS_ERR(ahb->regs)) 262 return PTR_ERR(ahb->regs); 263 264 ahb->dev = &pdev->dev; 265 platform_set_drvdata(pdev, ahb); 266 tegra_ahb_gizmo_init(ahb); 267 return 0; 268 } 269 270 static const struct of_device_id tegra_ahb_of_match[] = { 271 { .compatible = "nvidia,tegra30-ahb", }, 272 { .compatible = "nvidia,tegra20-ahb", }, 273 {}, 274 }; 275 276 static struct platform_driver tegra_ahb_driver = { 277 .probe = tegra_ahb_probe, 278 .driver = { 279 .name = DRV_NAME, 280 .owner = THIS_MODULE, 281 .of_match_table = tegra_ahb_of_match, 282 .pm = &tegra_ahb_pm, 283 }, 284 }; 285 module_platform_driver(tegra_ahb_driver); 286 287 MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>"); 288 MODULE_DESCRIPTION("Tegra AHB driver"); 289 MODULE_LICENSE("GPL v2"); 290 MODULE_ALIAS("platform:" DRV_NAME); 291