1 /* 2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 3 * Copyright (C) 2011 Google, Inc. 4 * 5 * Author: 6 * Jay Cheng <jacheng@nvidia.com> 7 * James Wylder <james.wylder@motorola.com> 8 * Benoit Goby <benoit@android.com> 9 * Colin Cross <ccross@android.com> 10 * Hiroshi DOYU <hdoyu@nvidia.com> 11 * 12 * This software is licensed under the terms of the GNU General Public 13 * License version 2, as published by the Free Software Foundation, and 14 * may be copied, distributed, and modified under those terms. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 */ 22 23 #include <linux/err.h> 24 #include <linux/kernel.h> 25 #include <linux/module.h> 26 #include <linux/platform_device.h> 27 #include <linux/io.h> 28 #include <linux/of.h> 29 30 #include <soc/tegra/ahb.h> 31 32 #define DRV_NAME "tegra-ahb" 33 34 #define AHB_ARBITRATION_DISABLE 0x04 35 #define AHB_ARBITRATION_PRIORITY_CTRL 0x08 36 #define AHB_PRIORITY_WEIGHT(x) (((x) & 0x7) << 29) 37 #define PRIORITY_SELECT_USB BIT(6) 38 #define PRIORITY_SELECT_USB2 BIT(18) 39 #define PRIORITY_SELECT_USB3 BIT(17) 40 41 #define AHB_GIZMO_AHB_MEM 0x10 42 #define ENB_FAST_REARBITRATE BIT(2) 43 #define DONT_SPLIT_AHB_WR BIT(7) 44 45 #define AHB_GIZMO_APB_DMA 0x14 46 #define AHB_GIZMO_IDE 0x1c 47 #define AHB_GIZMO_USB 0x20 48 #define AHB_GIZMO_AHB_XBAR_BRIDGE 0x24 49 #define AHB_GIZMO_CPU_AHB_BRIDGE 0x28 50 #define AHB_GIZMO_COP_AHB_BRIDGE 0x2c 51 #define AHB_GIZMO_XBAR_APB_CTLR 0x30 52 #define AHB_GIZMO_VCP_AHB_BRIDGE 0x34 53 #define AHB_GIZMO_NAND 0x40 54 #define AHB_GIZMO_SDMMC4 0x48 55 #define AHB_GIZMO_XIO 0x4c 56 #define AHB_GIZMO_BSEV 0x64 57 #define AHB_GIZMO_BSEA 0x74 58 #define AHB_GIZMO_NOR 0x78 59 #define AHB_GIZMO_USB2 0x7c 60 #define AHB_GIZMO_USB3 0x80 61 #define IMMEDIATE BIT(18) 62 63 #define AHB_GIZMO_SDMMC1 0x84 64 #define AHB_GIZMO_SDMMC2 0x88 65 #define AHB_GIZMO_SDMMC3 0x8c 66 #define AHB_MEM_PREFETCH_CFG_X 0xdc 67 #define AHB_ARBITRATION_XBAR_CTRL 0xe0 68 #define AHB_MEM_PREFETCH_CFG3 0xe4 69 #define AHB_MEM_PREFETCH_CFG4 0xe8 70 #define AHB_MEM_PREFETCH_CFG1 0xf0 71 #define AHB_MEM_PREFETCH_CFG2 0xf4 72 #define PREFETCH_ENB BIT(31) 73 #define MST_ID(x) (((x) & 0x1f) << 26) 74 #define AHBDMA_MST_ID MST_ID(5) 75 #define USB_MST_ID MST_ID(6) 76 #define USB2_MST_ID MST_ID(18) 77 #define USB3_MST_ID MST_ID(17) 78 #define ADDR_BNDRY(x) (((x) & 0xf) << 21) 79 #define INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0) 80 81 #define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID 0xfc 82 83 #define AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE BIT(17) 84 85 /* 86 * INCORRECT_BASE_ADDR_LOW_BYTE: Legacy kernel DT files for Tegra SoCs 87 * prior to Tegra124 generally use a physical base address ending in 88 * 0x4 for the AHB IP block. According to the TRM, the low byte 89 * should be 0x0. During device probing, this macro is used to detect 90 * whether the passed-in physical address is incorrect, and if so, to 91 * correct it. 92 */ 93 #define INCORRECT_BASE_ADDR_LOW_BYTE 0x4 94 95 static struct platform_driver tegra_ahb_driver; 96 97 static const u32 tegra_ahb_gizmo[] = { 98 AHB_ARBITRATION_DISABLE, 99 AHB_ARBITRATION_PRIORITY_CTRL, 100 AHB_GIZMO_AHB_MEM, 101 AHB_GIZMO_APB_DMA, 102 AHB_GIZMO_IDE, 103 AHB_GIZMO_USB, 104 AHB_GIZMO_AHB_XBAR_BRIDGE, 105 AHB_GIZMO_CPU_AHB_BRIDGE, 106 AHB_GIZMO_COP_AHB_BRIDGE, 107 AHB_GIZMO_XBAR_APB_CTLR, 108 AHB_GIZMO_VCP_AHB_BRIDGE, 109 AHB_GIZMO_NAND, 110 AHB_GIZMO_SDMMC4, 111 AHB_GIZMO_XIO, 112 AHB_GIZMO_BSEV, 113 AHB_GIZMO_BSEA, 114 AHB_GIZMO_NOR, 115 AHB_GIZMO_USB2, 116 AHB_GIZMO_USB3, 117 AHB_GIZMO_SDMMC1, 118 AHB_GIZMO_SDMMC2, 119 AHB_GIZMO_SDMMC3, 120 AHB_MEM_PREFETCH_CFG_X, 121 AHB_ARBITRATION_XBAR_CTRL, 122 AHB_MEM_PREFETCH_CFG3, 123 AHB_MEM_PREFETCH_CFG4, 124 AHB_MEM_PREFETCH_CFG1, 125 AHB_MEM_PREFETCH_CFG2, 126 AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID, 127 }; 128 129 struct tegra_ahb { 130 void __iomem *regs; 131 struct device *dev; 132 u32 ctx[0]; 133 }; 134 135 static inline u32 gizmo_readl(struct tegra_ahb *ahb, u32 offset) 136 { 137 return readl(ahb->regs + offset); 138 } 139 140 static inline void gizmo_writel(struct tegra_ahb *ahb, u32 value, u32 offset) 141 { 142 writel(value, ahb->regs + offset); 143 } 144 145 #ifdef CONFIG_TEGRA_IOMMU_SMMU 146 static int tegra_ahb_match_by_smmu(struct device *dev, void *data) 147 { 148 struct tegra_ahb *ahb = dev_get_drvdata(dev); 149 struct device_node *dn = data; 150 151 return (ahb->dev->of_node == dn) ? 1 : 0; 152 } 153 154 int tegra_ahb_enable_smmu(struct device_node *dn) 155 { 156 struct device *dev; 157 u32 val; 158 struct tegra_ahb *ahb; 159 160 dev = driver_find_device(&tegra_ahb_driver.driver, NULL, dn, 161 tegra_ahb_match_by_smmu); 162 if (!dev) 163 return -EPROBE_DEFER; 164 ahb = dev_get_drvdata(dev); 165 val = gizmo_readl(ahb, AHB_ARBITRATION_XBAR_CTRL); 166 val |= AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE; 167 gizmo_writel(ahb, val, AHB_ARBITRATION_XBAR_CTRL); 168 return 0; 169 } 170 EXPORT_SYMBOL(tegra_ahb_enable_smmu); 171 #endif 172 173 static int __maybe_unused tegra_ahb_suspend(struct device *dev) 174 { 175 int i; 176 struct tegra_ahb *ahb = dev_get_drvdata(dev); 177 178 for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++) 179 ahb->ctx[i] = gizmo_readl(ahb, tegra_ahb_gizmo[i]); 180 return 0; 181 } 182 183 static int __maybe_unused tegra_ahb_resume(struct device *dev) 184 { 185 int i; 186 struct tegra_ahb *ahb = dev_get_drvdata(dev); 187 188 for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++) 189 gizmo_writel(ahb, ahb->ctx[i], tegra_ahb_gizmo[i]); 190 return 0; 191 } 192 193 static UNIVERSAL_DEV_PM_OPS(tegra_ahb_pm, 194 tegra_ahb_suspend, 195 tegra_ahb_resume, NULL); 196 197 static void tegra_ahb_gizmo_init(struct tegra_ahb *ahb) 198 { 199 u32 val; 200 201 val = gizmo_readl(ahb, AHB_GIZMO_AHB_MEM); 202 val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR; 203 gizmo_writel(ahb, val, AHB_GIZMO_AHB_MEM); 204 205 val = gizmo_readl(ahb, AHB_GIZMO_USB); 206 val |= IMMEDIATE; 207 gizmo_writel(ahb, val, AHB_GIZMO_USB); 208 209 val = gizmo_readl(ahb, AHB_GIZMO_USB2); 210 val |= IMMEDIATE; 211 gizmo_writel(ahb, val, AHB_GIZMO_USB2); 212 213 val = gizmo_readl(ahb, AHB_GIZMO_USB3); 214 val |= IMMEDIATE; 215 gizmo_writel(ahb, val, AHB_GIZMO_USB3); 216 217 val = gizmo_readl(ahb, AHB_ARBITRATION_PRIORITY_CTRL); 218 val |= PRIORITY_SELECT_USB | 219 PRIORITY_SELECT_USB2 | 220 PRIORITY_SELECT_USB3 | 221 AHB_PRIORITY_WEIGHT(7); 222 gizmo_writel(ahb, val, AHB_ARBITRATION_PRIORITY_CTRL); 223 224 val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG1); 225 val &= ~MST_ID(~0); 226 val |= PREFETCH_ENB | 227 AHBDMA_MST_ID | 228 ADDR_BNDRY(0xc) | 229 INACTIVITY_TIMEOUT(0x1000); 230 gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG1); 231 232 val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG2); 233 val &= ~MST_ID(~0); 234 val |= PREFETCH_ENB | 235 USB_MST_ID | 236 ADDR_BNDRY(0xc) | 237 INACTIVITY_TIMEOUT(0x1000); 238 gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG2); 239 240 val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG3); 241 val &= ~MST_ID(~0); 242 val |= PREFETCH_ENB | 243 USB3_MST_ID | 244 ADDR_BNDRY(0xc) | 245 INACTIVITY_TIMEOUT(0x1000); 246 gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG3); 247 248 val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG4); 249 val &= ~MST_ID(~0); 250 val |= PREFETCH_ENB | 251 USB2_MST_ID | 252 ADDR_BNDRY(0xc) | 253 INACTIVITY_TIMEOUT(0x1000); 254 gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG4); 255 } 256 257 static int tegra_ahb_probe(struct platform_device *pdev) 258 { 259 struct resource *res; 260 struct tegra_ahb *ahb; 261 size_t bytes; 262 263 bytes = sizeof(*ahb) + sizeof(u32) * ARRAY_SIZE(tegra_ahb_gizmo); 264 ahb = devm_kzalloc(&pdev->dev, bytes, GFP_KERNEL); 265 if (!ahb) 266 return -ENOMEM; 267 268 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 269 270 /* Correct the IP block base address if necessary */ 271 if (res && 272 (res->start & INCORRECT_BASE_ADDR_LOW_BYTE) == 273 INCORRECT_BASE_ADDR_LOW_BYTE) { 274 dev_warn(&pdev->dev, "incorrect AHB base address in DT data - enabling workaround\n"); 275 res->start -= INCORRECT_BASE_ADDR_LOW_BYTE; 276 } 277 278 ahb->regs = devm_ioremap_resource(&pdev->dev, res); 279 if (IS_ERR(ahb->regs)) 280 return PTR_ERR(ahb->regs); 281 282 ahb->dev = &pdev->dev; 283 platform_set_drvdata(pdev, ahb); 284 tegra_ahb_gizmo_init(ahb); 285 return 0; 286 } 287 288 static const struct of_device_id tegra_ahb_of_match[] = { 289 { .compatible = "nvidia,tegra30-ahb", }, 290 { .compatible = "nvidia,tegra20-ahb", }, 291 {}, 292 }; 293 294 static struct platform_driver tegra_ahb_driver = { 295 .probe = tegra_ahb_probe, 296 .driver = { 297 .name = DRV_NAME, 298 .of_match_table = tegra_ahb_of_match, 299 .pm = &tegra_ahb_pm, 300 }, 301 }; 302 module_platform_driver(tegra_ahb_driver); 303 304 MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>"); 305 MODULE_DESCRIPTION("Tegra AHB driver"); 306 MODULE_LICENSE("GPL v2"); 307 MODULE_ALIAS("platform:" DRV_NAME); 308