1 /* 2 * processor_idle - idle state submodule to the ACPI processor driver 3 * 4 * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> 5 * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> 6 * Copyright (C) 2004, 2005 Dominik Brodowski <linux@brodo.de> 7 * Copyright (C) 2004 Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> 8 * - Added processor hotplug support 9 * Copyright (C) 2005 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> 10 * - Added support for C3 on SMP 11 * 12 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or (at 17 * your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, but 20 * WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 22 * General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License along 25 * with this program; if not, write to the Free Software Foundation, Inc., 26 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. 27 * 28 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 29 */ 30 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/init.h> 34 #include <linux/cpufreq.h> 35 #include <linux/proc_fs.h> 36 #include <linux/seq_file.h> 37 #include <linux/acpi.h> 38 #include <linux/dmi.h> 39 #include <linux/moduleparam.h> 40 #include <linux/sched.h> /* need_resched() */ 41 #include <linux/pm_qos_params.h> 42 #include <linux/clockchips.h> 43 #include <linux/cpuidle.h> 44 #include <linux/irqflags.h> 45 46 /* 47 * Include the apic definitions for x86 to have the APIC timer related defines 48 * available also for UP (on SMP it gets magically included via linux/smp.h). 49 * asm/acpi.h is not an option, as it would require more include magic. Also 50 * creating an empty asm-ia64/apic.h would just trade pest vs. cholera. 51 */ 52 #ifdef CONFIG_X86 53 #include <asm/apic.h> 54 #endif 55 56 #include <asm/io.h> 57 #include <asm/uaccess.h> 58 59 #include <acpi/acpi_bus.h> 60 #include <acpi/processor.h> 61 #include <asm/processor.h> 62 63 #define ACPI_PROCESSOR_CLASS "processor" 64 #define _COMPONENT ACPI_PROCESSOR_COMPONENT 65 ACPI_MODULE_NAME("processor_idle"); 66 #define ACPI_PROCESSOR_FILE_POWER "power" 67 #define PM_TIMER_TICK_NS (1000000000ULL/PM_TIMER_FREQUENCY) 68 #define C2_OVERHEAD 1 /* 1us */ 69 #define C3_OVERHEAD 1 /* 1us */ 70 #define PM_TIMER_TICKS_TO_US(p) (((p) * 1000)/(PM_TIMER_FREQUENCY/1000)) 71 72 static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER; 73 module_param(max_cstate, uint, 0000); 74 static unsigned int nocst __read_mostly; 75 module_param(nocst, uint, 0000); 76 77 static unsigned int latency_factor __read_mostly = 2; 78 module_param(latency_factor, uint, 0644); 79 80 static s64 us_to_pm_timer_ticks(s64 t) 81 { 82 return div64_u64(t * PM_TIMER_FREQUENCY, 1000000); 83 } 84 /* 85 * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3. 86 * For now disable this. Probably a bug somewhere else. 87 * 88 * To skip this limit, boot/load with a large max_cstate limit. 89 */ 90 static int set_max_cstate(const struct dmi_system_id *id) 91 { 92 if (max_cstate > ACPI_PROCESSOR_MAX_POWER) 93 return 0; 94 95 printk(KERN_NOTICE PREFIX "%s detected - limiting to C%ld max_cstate." 96 " Override with \"processor.max_cstate=%d\"\n", id->ident, 97 (long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1); 98 99 max_cstate = (long)id->driver_data; 100 101 return 0; 102 } 103 104 /* Actually this shouldn't be __cpuinitdata, would be better to fix the 105 callers to only run once -AK */ 106 static struct dmi_system_id __cpuinitdata processor_power_dmi_table[] = { 107 { set_max_cstate, "Clevo 5600D", { 108 DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), 109 DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")}, 110 (void *)2}, 111 {}, 112 }; 113 114 115 /* 116 * Callers should disable interrupts before the call and enable 117 * interrupts after return. 118 */ 119 static void acpi_safe_halt(void) 120 { 121 current_thread_info()->status &= ~TS_POLLING; 122 /* 123 * TS_POLLING-cleared state must be visible before we 124 * test NEED_RESCHED: 125 */ 126 smp_mb(); 127 if (!need_resched()) { 128 safe_halt(); 129 local_irq_disable(); 130 } 131 current_thread_info()->status |= TS_POLLING; 132 } 133 134 #ifdef ARCH_APICTIMER_STOPS_ON_C3 135 136 /* 137 * Some BIOS implementations switch to C3 in the published C2 state. 138 * This seems to be a common problem on AMD boxen, but other vendors 139 * are affected too. We pick the most conservative approach: we assume 140 * that the local APIC stops in both C2 and C3. 141 */ 142 static void lapic_timer_check_state(int state, struct acpi_processor *pr, 143 struct acpi_processor_cx *cx) 144 { 145 struct acpi_processor_power *pwr = &pr->power; 146 u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2; 147 148 if (cpu_has(&cpu_data(pr->id), X86_FEATURE_ARAT)) 149 return; 150 151 if (boot_cpu_has(X86_FEATURE_AMDC1E)) 152 type = ACPI_STATE_C1; 153 154 /* 155 * Check, if one of the previous states already marked the lapic 156 * unstable 157 */ 158 if (pwr->timer_broadcast_on_state < state) 159 return; 160 161 if (cx->type >= type) 162 pr->power.timer_broadcast_on_state = state; 163 } 164 165 static void lapic_timer_propagate_broadcast(void *arg) 166 { 167 struct acpi_processor *pr = (struct acpi_processor *) arg; 168 unsigned long reason; 169 170 reason = pr->power.timer_broadcast_on_state < INT_MAX ? 171 CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF; 172 173 clockevents_notify(reason, &pr->id); 174 } 175 176 /* Power(C) State timer broadcast control */ 177 static void lapic_timer_state_broadcast(struct acpi_processor *pr, 178 struct acpi_processor_cx *cx, 179 int broadcast) 180 { 181 int state = cx - pr->power.states; 182 183 if (state >= pr->power.timer_broadcast_on_state) { 184 unsigned long reason; 185 186 reason = broadcast ? CLOCK_EVT_NOTIFY_BROADCAST_ENTER : 187 CLOCK_EVT_NOTIFY_BROADCAST_EXIT; 188 clockevents_notify(reason, &pr->id); 189 } 190 } 191 192 #else 193 194 static void lapic_timer_check_state(int state, struct acpi_processor *pr, 195 struct acpi_processor_cx *cstate) { } 196 static void lapic_timer_propagate_broadcast(struct acpi_processor *pr) { } 197 static void lapic_timer_state_broadcast(struct acpi_processor *pr, 198 struct acpi_processor_cx *cx, 199 int broadcast) 200 { 201 } 202 203 #endif 204 205 /* 206 * Suspend / resume control 207 */ 208 static int acpi_idle_suspend; 209 static u32 saved_bm_rld; 210 211 static void acpi_idle_bm_rld_save(void) 212 { 213 acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_RLD, &saved_bm_rld); 214 } 215 static void acpi_idle_bm_rld_restore(void) 216 { 217 u32 resumed_bm_rld; 218 219 acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_RLD, &resumed_bm_rld); 220 221 if (resumed_bm_rld != saved_bm_rld) 222 acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, saved_bm_rld); 223 } 224 225 int acpi_processor_suspend(struct acpi_device * device, pm_message_t state) 226 { 227 if (acpi_idle_suspend == 1) 228 return 0; 229 230 acpi_idle_bm_rld_save(); 231 acpi_idle_suspend = 1; 232 return 0; 233 } 234 235 int acpi_processor_resume(struct acpi_device * device) 236 { 237 if (acpi_idle_suspend == 0) 238 return 0; 239 240 acpi_idle_bm_rld_restore(); 241 acpi_idle_suspend = 0; 242 return 0; 243 } 244 245 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86) 246 static void tsc_check_state(int state) 247 { 248 switch (boot_cpu_data.x86_vendor) { 249 case X86_VENDOR_AMD: 250 case X86_VENDOR_INTEL: 251 /* 252 * AMD Fam10h TSC will tick in all 253 * C/P/S0/S1 states when this bit is set. 254 */ 255 if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) 256 return; 257 258 /*FALL THROUGH*/ 259 default: 260 /* TSC could halt in idle, so notify users */ 261 if (state > ACPI_STATE_C1) 262 mark_tsc_unstable("TSC halts in idle"); 263 } 264 } 265 #else 266 static void tsc_check_state(int state) { return; } 267 #endif 268 269 static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr) 270 { 271 272 if (!pr) 273 return -EINVAL; 274 275 if (!pr->pblk) 276 return -ENODEV; 277 278 /* if info is obtained from pblk/fadt, type equals state */ 279 pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2; 280 pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3; 281 282 #ifndef CONFIG_HOTPLUG_CPU 283 /* 284 * Check for P_LVL2_UP flag before entering C2 and above on 285 * an SMP system. 286 */ 287 if ((num_online_cpus() > 1) && 288 !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) 289 return -ENODEV; 290 #endif 291 292 /* determine C2 and C3 address from pblk */ 293 pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4; 294 pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5; 295 296 /* determine latencies from FADT */ 297 pr->power.states[ACPI_STATE_C2].latency = acpi_gbl_FADT.C2latency; 298 pr->power.states[ACPI_STATE_C3].latency = acpi_gbl_FADT.C3latency; 299 300 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 301 "lvl2[0x%08x] lvl3[0x%08x]\n", 302 pr->power.states[ACPI_STATE_C2].address, 303 pr->power.states[ACPI_STATE_C3].address)); 304 305 return 0; 306 } 307 308 static int acpi_processor_get_power_info_default(struct acpi_processor *pr) 309 { 310 if (!pr->power.states[ACPI_STATE_C1].valid) { 311 /* set the first C-State to C1 */ 312 /* all processors need to support C1 */ 313 pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1; 314 pr->power.states[ACPI_STATE_C1].valid = 1; 315 pr->power.states[ACPI_STATE_C1].entry_method = ACPI_CSTATE_HALT; 316 } 317 /* the C0 state only exists as a filler in our array */ 318 pr->power.states[ACPI_STATE_C0].valid = 1; 319 return 0; 320 } 321 322 static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) 323 { 324 acpi_status status = 0; 325 acpi_integer count; 326 int current_count; 327 int i; 328 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 329 union acpi_object *cst; 330 331 332 if (nocst) 333 return -ENODEV; 334 335 current_count = 0; 336 337 status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer); 338 if (ACPI_FAILURE(status)) { 339 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _CST, giving up\n")); 340 return -ENODEV; 341 } 342 343 cst = buffer.pointer; 344 345 /* There must be at least 2 elements */ 346 if (!cst || (cst->type != ACPI_TYPE_PACKAGE) || cst->package.count < 2) { 347 printk(KERN_ERR PREFIX "not enough elements in _CST\n"); 348 status = -EFAULT; 349 goto end; 350 } 351 352 count = cst->package.elements[0].integer.value; 353 354 /* Validate number of power states. */ 355 if (count < 1 || count != cst->package.count - 1) { 356 printk(KERN_ERR PREFIX "count given by _CST is not valid\n"); 357 status = -EFAULT; 358 goto end; 359 } 360 361 /* Tell driver that at least _CST is supported. */ 362 pr->flags.has_cst = 1; 363 364 for (i = 1; i <= count; i++) { 365 union acpi_object *element; 366 union acpi_object *obj; 367 struct acpi_power_register *reg; 368 struct acpi_processor_cx cx; 369 370 memset(&cx, 0, sizeof(cx)); 371 372 element = &(cst->package.elements[i]); 373 if (element->type != ACPI_TYPE_PACKAGE) 374 continue; 375 376 if (element->package.count != 4) 377 continue; 378 379 obj = &(element->package.elements[0]); 380 381 if (obj->type != ACPI_TYPE_BUFFER) 382 continue; 383 384 reg = (struct acpi_power_register *)obj->buffer.pointer; 385 386 if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO && 387 (reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) 388 continue; 389 390 /* There should be an easy way to extract an integer... */ 391 obj = &(element->package.elements[1]); 392 if (obj->type != ACPI_TYPE_INTEGER) 393 continue; 394 395 cx.type = obj->integer.value; 396 /* 397 * Some buggy BIOSes won't list C1 in _CST - 398 * Let acpi_processor_get_power_info_default() handle them later 399 */ 400 if (i == 1 && cx.type != ACPI_STATE_C1) 401 current_count++; 402 403 cx.address = reg->address; 404 cx.index = current_count + 1; 405 406 cx.entry_method = ACPI_CSTATE_SYSTEMIO; 407 if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) { 408 if (acpi_processor_ffh_cstate_probe 409 (pr->id, &cx, reg) == 0) { 410 cx.entry_method = ACPI_CSTATE_FFH; 411 } else if (cx.type == ACPI_STATE_C1) { 412 /* 413 * C1 is a special case where FIXED_HARDWARE 414 * can be handled in non-MWAIT way as well. 415 * In that case, save this _CST entry info. 416 * Otherwise, ignore this info and continue. 417 */ 418 cx.entry_method = ACPI_CSTATE_HALT; 419 snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); 420 } else { 421 continue; 422 } 423 if (cx.type == ACPI_STATE_C1 && 424 (idle_halt || idle_nomwait)) { 425 /* 426 * In most cases the C1 space_id obtained from 427 * _CST object is FIXED_HARDWARE access mode. 428 * But when the option of idle=halt is added, 429 * the entry_method type should be changed from 430 * CSTATE_FFH to CSTATE_HALT. 431 * When the option of idle=nomwait is added, 432 * the C1 entry_method type should be 433 * CSTATE_HALT. 434 */ 435 cx.entry_method = ACPI_CSTATE_HALT; 436 snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); 437 } 438 } else { 439 snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI IOPORT 0x%x", 440 cx.address); 441 } 442 443 if (cx.type == ACPI_STATE_C1) { 444 cx.valid = 1; 445 } 446 447 obj = &(element->package.elements[2]); 448 if (obj->type != ACPI_TYPE_INTEGER) 449 continue; 450 451 cx.latency = obj->integer.value; 452 453 obj = &(element->package.elements[3]); 454 if (obj->type != ACPI_TYPE_INTEGER) 455 continue; 456 457 cx.power = obj->integer.value; 458 459 current_count++; 460 memcpy(&(pr->power.states[current_count]), &cx, sizeof(cx)); 461 462 /* 463 * We support total ACPI_PROCESSOR_MAX_POWER - 1 464 * (From 1 through ACPI_PROCESSOR_MAX_POWER - 1) 465 */ 466 if (current_count >= (ACPI_PROCESSOR_MAX_POWER - 1)) { 467 printk(KERN_WARNING 468 "Limiting number of power states to max (%d)\n", 469 ACPI_PROCESSOR_MAX_POWER); 470 printk(KERN_WARNING 471 "Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n"); 472 break; 473 } 474 } 475 476 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d power states\n", 477 current_count)); 478 479 /* Validate number of power states discovered */ 480 if (current_count < 2) 481 status = -EFAULT; 482 483 end: 484 kfree(buffer.pointer); 485 486 return status; 487 } 488 489 static void acpi_processor_power_verify_c2(struct acpi_processor_cx *cx) 490 { 491 492 if (!cx->address) 493 return; 494 495 /* 496 * C2 latency must be less than or equal to 100 497 * microseconds. 498 */ 499 else if (cx->latency > ACPI_PROCESSOR_MAX_C2_LATENCY) { 500 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 501 "latency too large [%d]\n", cx->latency)); 502 return; 503 } 504 505 /* 506 * Otherwise we've met all of our C2 requirements. 507 * Normalize the C2 latency to expidite policy 508 */ 509 cx->valid = 1; 510 511 cx->latency_ticks = cx->latency; 512 513 return; 514 } 515 516 static void acpi_processor_power_verify_c3(struct acpi_processor *pr, 517 struct acpi_processor_cx *cx) 518 { 519 static int bm_check_flag = -1; 520 static int bm_control_flag = -1; 521 522 523 if (!cx->address) 524 return; 525 526 /* 527 * C3 latency must be less than or equal to 1000 528 * microseconds. 529 */ 530 else if (cx->latency > ACPI_PROCESSOR_MAX_C3_LATENCY) { 531 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 532 "latency too large [%d]\n", cx->latency)); 533 return; 534 } 535 536 /* 537 * PIIX4 Erratum #18: We don't support C3 when Type-F (fast) 538 * DMA transfers are used by any ISA device to avoid livelock. 539 * Note that we could disable Type-F DMA (as recommended by 540 * the erratum), but this is known to disrupt certain ISA 541 * devices thus we take the conservative approach. 542 */ 543 else if (errata.piix4.fdma) { 544 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 545 "C3 not supported on PIIX4 with Type-F DMA\n")); 546 return; 547 } 548 549 /* All the logic here assumes flags.bm_check is same across all CPUs */ 550 if (bm_check_flag == -1) { 551 /* Determine whether bm_check is needed based on CPU */ 552 acpi_processor_power_init_bm_check(&(pr->flags), pr->id); 553 bm_check_flag = pr->flags.bm_check; 554 bm_control_flag = pr->flags.bm_control; 555 } else { 556 pr->flags.bm_check = bm_check_flag; 557 pr->flags.bm_control = bm_control_flag; 558 } 559 560 if (pr->flags.bm_check) { 561 if (!pr->flags.bm_control) { 562 if (pr->flags.has_cst != 1) { 563 /* bus mastering control is necessary */ 564 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 565 "C3 support requires BM control\n")); 566 return; 567 } else { 568 /* Here we enter C3 without bus mastering */ 569 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 570 "C3 support without BM control\n")); 571 } 572 } 573 } else { 574 /* 575 * WBINVD should be set in fadt, for C3 state to be 576 * supported on when bm_check is not required. 577 */ 578 if (!(acpi_gbl_FADT.flags & ACPI_FADT_WBINVD)) { 579 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 580 "Cache invalidation should work properly" 581 " for C3 to be enabled on SMP systems\n")); 582 return; 583 } 584 } 585 586 /* 587 * Otherwise we've met all of our C3 requirements. 588 * Normalize the C3 latency to expidite policy. Enable 589 * checking of bus mastering status (bm_check) so we can 590 * use this in our C3 policy 591 */ 592 cx->valid = 1; 593 594 cx->latency_ticks = cx->latency; 595 /* 596 * On older chipsets, BM_RLD needs to be set 597 * in order for Bus Master activity to wake the 598 * system from C3. Newer chipsets handle DMA 599 * during C3 automatically and BM_RLD is a NOP. 600 * In either case, the proper way to 601 * handle BM_RLD is to set it and leave it set. 602 */ 603 acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, 1); 604 605 return; 606 } 607 608 static int acpi_processor_power_verify(struct acpi_processor *pr) 609 { 610 unsigned int i; 611 unsigned int working = 0; 612 613 pr->power.timer_broadcast_on_state = INT_MAX; 614 615 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { 616 struct acpi_processor_cx *cx = &pr->power.states[i]; 617 618 switch (cx->type) { 619 case ACPI_STATE_C1: 620 cx->valid = 1; 621 break; 622 623 case ACPI_STATE_C2: 624 acpi_processor_power_verify_c2(cx); 625 break; 626 627 case ACPI_STATE_C3: 628 acpi_processor_power_verify_c3(pr, cx); 629 break; 630 } 631 if (!cx->valid) 632 continue; 633 634 lapic_timer_check_state(i, pr, cx); 635 tsc_check_state(cx->type); 636 working++; 637 } 638 639 smp_call_function_single(pr->id, lapic_timer_propagate_broadcast, 640 pr, 1); 641 642 return (working); 643 } 644 645 static int acpi_processor_get_power_info(struct acpi_processor *pr) 646 { 647 unsigned int i; 648 int result; 649 650 651 /* NOTE: the idle thread may not be running while calling 652 * this function */ 653 654 /* Zero initialize all the C-states info. */ 655 memset(pr->power.states, 0, sizeof(pr->power.states)); 656 657 result = acpi_processor_get_power_info_cst(pr); 658 if (result == -ENODEV) 659 result = acpi_processor_get_power_info_fadt(pr); 660 661 if (result) 662 return result; 663 664 acpi_processor_get_power_info_default(pr); 665 666 pr->power.count = acpi_processor_power_verify(pr); 667 668 /* 669 * if one state of type C2 or C3 is available, mark this 670 * CPU as being "idle manageable" 671 */ 672 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { 673 if (pr->power.states[i].valid) { 674 pr->power.count = i; 675 if (pr->power.states[i].type >= ACPI_STATE_C2) 676 pr->flags.power = 1; 677 } 678 } 679 680 return 0; 681 } 682 683 static int acpi_processor_power_seq_show(struct seq_file *seq, void *offset) 684 { 685 struct acpi_processor *pr = seq->private; 686 unsigned int i; 687 688 689 if (!pr) 690 goto end; 691 692 seq_printf(seq, "active state: C%zd\n" 693 "max_cstate: C%d\n" 694 "maximum allowed latency: %d usec\n", 695 pr->power.state ? pr->power.state - pr->power.states : 0, 696 max_cstate, pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY)); 697 698 seq_puts(seq, "states:\n"); 699 700 for (i = 1; i <= pr->power.count; i++) { 701 seq_printf(seq, " %cC%d: ", 702 (&pr->power.states[i] == 703 pr->power.state ? '*' : ' '), i); 704 705 if (!pr->power.states[i].valid) { 706 seq_puts(seq, "<not supported>\n"); 707 continue; 708 } 709 710 switch (pr->power.states[i].type) { 711 case ACPI_STATE_C1: 712 seq_printf(seq, "type[C1] "); 713 break; 714 case ACPI_STATE_C2: 715 seq_printf(seq, "type[C2] "); 716 break; 717 case ACPI_STATE_C3: 718 seq_printf(seq, "type[C3] "); 719 break; 720 default: 721 seq_printf(seq, "type[--] "); 722 break; 723 } 724 725 if (pr->power.states[i].promotion.state) 726 seq_printf(seq, "promotion[C%zd] ", 727 (pr->power.states[i].promotion.state - 728 pr->power.states)); 729 else 730 seq_puts(seq, "promotion[--] "); 731 732 if (pr->power.states[i].demotion.state) 733 seq_printf(seq, "demotion[C%zd] ", 734 (pr->power.states[i].demotion.state - 735 pr->power.states)); 736 else 737 seq_puts(seq, "demotion[--] "); 738 739 seq_printf(seq, "latency[%03d] usage[%08d] duration[%020llu]\n", 740 pr->power.states[i].latency, 741 pr->power.states[i].usage, 742 (unsigned long long)pr->power.states[i].time); 743 } 744 745 end: 746 return 0; 747 } 748 749 static int acpi_processor_power_open_fs(struct inode *inode, struct file *file) 750 { 751 return single_open(file, acpi_processor_power_seq_show, 752 PDE(inode)->data); 753 } 754 755 static const struct file_operations acpi_processor_power_fops = { 756 .owner = THIS_MODULE, 757 .open = acpi_processor_power_open_fs, 758 .read = seq_read, 759 .llseek = seq_lseek, 760 .release = single_release, 761 }; 762 763 764 /** 765 * acpi_idle_bm_check - checks if bus master activity was detected 766 */ 767 static int acpi_idle_bm_check(void) 768 { 769 u32 bm_status = 0; 770 771 acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status); 772 if (bm_status) 773 acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, 1); 774 /* 775 * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect 776 * the true state of bus mastering activity; forcing us to 777 * manually check the BMIDEA bit of each IDE channel. 778 */ 779 else if (errata.piix4.bmisx) { 780 if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01) 781 || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01)) 782 bm_status = 1; 783 } 784 return bm_status; 785 } 786 787 /** 788 * acpi_idle_do_entry - a helper function that does C2 and C3 type entry 789 * @cx: cstate data 790 * 791 * Caller disables interrupt before call and enables interrupt after return. 792 */ 793 static inline void acpi_idle_do_entry(struct acpi_processor_cx *cx) 794 { 795 /* Don't trace irqs off for idle */ 796 stop_critical_timings(); 797 if (cx->entry_method == ACPI_CSTATE_FFH) { 798 /* Call into architectural FFH based C-state */ 799 acpi_processor_ffh_cstate_enter(cx); 800 } else if (cx->entry_method == ACPI_CSTATE_HALT) { 801 acpi_safe_halt(); 802 } else { 803 int unused; 804 /* IO port based C-state */ 805 inb(cx->address); 806 /* Dummy wait op - must do something useless after P_LVL2 read 807 because chipsets cannot guarantee that STPCLK# signal 808 gets asserted in time to freeze execution properly. */ 809 unused = inl(acpi_gbl_FADT.xpm_timer_block.address); 810 } 811 start_critical_timings(); 812 } 813 814 /** 815 * acpi_idle_enter_c1 - enters an ACPI C1 state-type 816 * @dev: the target CPU 817 * @state: the state data 818 * 819 * This is equivalent to the HALT instruction. 820 */ 821 static int acpi_idle_enter_c1(struct cpuidle_device *dev, 822 struct cpuidle_state *state) 823 { 824 ktime_t kt1, kt2; 825 s64 idle_time; 826 struct acpi_processor *pr; 827 struct acpi_processor_cx *cx = cpuidle_get_statedata(state); 828 829 pr = __get_cpu_var(processors); 830 831 if (unlikely(!pr)) 832 return 0; 833 834 local_irq_disable(); 835 836 /* Do not access any ACPI IO ports in suspend path */ 837 if (acpi_idle_suspend) { 838 local_irq_enable(); 839 cpu_relax(); 840 return 0; 841 } 842 843 lapic_timer_state_broadcast(pr, cx, 1); 844 kt1 = ktime_get_real(); 845 acpi_idle_do_entry(cx); 846 kt2 = ktime_get_real(); 847 idle_time = ktime_to_us(ktime_sub(kt2, kt1)); 848 849 local_irq_enable(); 850 cx->usage++; 851 lapic_timer_state_broadcast(pr, cx, 0); 852 853 return idle_time; 854 } 855 856 /** 857 * acpi_idle_enter_simple - enters an ACPI state without BM handling 858 * @dev: the target CPU 859 * @state: the state data 860 */ 861 static int acpi_idle_enter_simple(struct cpuidle_device *dev, 862 struct cpuidle_state *state) 863 { 864 struct acpi_processor *pr; 865 struct acpi_processor_cx *cx = cpuidle_get_statedata(state); 866 ktime_t kt1, kt2; 867 s64 idle_time; 868 s64 sleep_ticks = 0; 869 870 pr = __get_cpu_var(processors); 871 872 if (unlikely(!pr)) 873 return 0; 874 875 if (acpi_idle_suspend) 876 return(acpi_idle_enter_c1(dev, state)); 877 878 local_irq_disable(); 879 current_thread_info()->status &= ~TS_POLLING; 880 /* 881 * TS_POLLING-cleared state must be visible before we test 882 * NEED_RESCHED: 883 */ 884 smp_mb(); 885 886 if (unlikely(need_resched())) { 887 current_thread_info()->status |= TS_POLLING; 888 local_irq_enable(); 889 return 0; 890 } 891 892 /* 893 * Must be done before busmaster disable as we might need to 894 * access HPET ! 895 */ 896 lapic_timer_state_broadcast(pr, cx, 1); 897 898 if (cx->type == ACPI_STATE_C3) 899 ACPI_FLUSH_CPU_CACHE(); 900 901 kt1 = ktime_get_real(); 902 /* Tell the scheduler that we are going deep-idle: */ 903 sched_clock_idle_sleep_event(); 904 acpi_idle_do_entry(cx); 905 kt2 = ktime_get_real(); 906 idle_time = ktime_to_us(ktime_sub(kt2, kt1)); 907 908 sleep_ticks = us_to_pm_timer_ticks(idle_time); 909 910 /* Tell the scheduler how much we idled: */ 911 sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); 912 913 local_irq_enable(); 914 current_thread_info()->status |= TS_POLLING; 915 916 cx->usage++; 917 918 lapic_timer_state_broadcast(pr, cx, 0); 919 cx->time += sleep_ticks; 920 return idle_time; 921 } 922 923 static int c3_cpu_count; 924 static DEFINE_SPINLOCK(c3_lock); 925 926 /** 927 * acpi_idle_enter_bm - enters C3 with proper BM handling 928 * @dev: the target CPU 929 * @state: the state data 930 * 931 * If BM is detected, the deepest non-C3 idle state is entered instead. 932 */ 933 static int acpi_idle_enter_bm(struct cpuidle_device *dev, 934 struct cpuidle_state *state) 935 { 936 struct acpi_processor *pr; 937 struct acpi_processor_cx *cx = cpuidle_get_statedata(state); 938 ktime_t kt1, kt2; 939 s64 idle_time; 940 s64 sleep_ticks = 0; 941 942 943 pr = __get_cpu_var(processors); 944 945 if (unlikely(!pr)) 946 return 0; 947 948 if (acpi_idle_suspend) 949 return(acpi_idle_enter_c1(dev, state)); 950 951 if (acpi_idle_bm_check()) { 952 if (dev->safe_state) { 953 dev->last_state = dev->safe_state; 954 return dev->safe_state->enter(dev, dev->safe_state); 955 } else { 956 local_irq_disable(); 957 acpi_safe_halt(); 958 local_irq_enable(); 959 return 0; 960 } 961 } 962 963 local_irq_disable(); 964 current_thread_info()->status &= ~TS_POLLING; 965 /* 966 * TS_POLLING-cleared state must be visible before we test 967 * NEED_RESCHED: 968 */ 969 smp_mb(); 970 971 if (unlikely(need_resched())) { 972 current_thread_info()->status |= TS_POLLING; 973 local_irq_enable(); 974 return 0; 975 } 976 977 acpi_unlazy_tlb(smp_processor_id()); 978 979 /* Tell the scheduler that we are going deep-idle: */ 980 sched_clock_idle_sleep_event(); 981 /* 982 * Must be done before busmaster disable as we might need to 983 * access HPET ! 984 */ 985 lapic_timer_state_broadcast(pr, cx, 1); 986 987 kt1 = ktime_get_real(); 988 /* 989 * disable bus master 990 * bm_check implies we need ARB_DIS 991 * !bm_check implies we need cache flush 992 * bm_control implies whether we can do ARB_DIS 993 * 994 * That leaves a case where bm_check is set and bm_control is 995 * not set. In that case we cannot do much, we enter C3 996 * without doing anything. 997 */ 998 if (pr->flags.bm_check && pr->flags.bm_control) { 999 spin_lock(&c3_lock); 1000 c3_cpu_count++; 1001 /* Disable bus master arbitration when all CPUs are in C3 */ 1002 if (c3_cpu_count == num_online_cpus()) 1003 acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 1); 1004 spin_unlock(&c3_lock); 1005 } else if (!pr->flags.bm_check) { 1006 ACPI_FLUSH_CPU_CACHE(); 1007 } 1008 1009 acpi_idle_do_entry(cx); 1010 1011 /* Re-enable bus master arbitration */ 1012 if (pr->flags.bm_check && pr->flags.bm_control) { 1013 spin_lock(&c3_lock); 1014 acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 0); 1015 c3_cpu_count--; 1016 spin_unlock(&c3_lock); 1017 } 1018 kt2 = ktime_get_real(); 1019 idle_time = ktime_to_us(ktime_sub(kt2, kt1)); 1020 1021 sleep_ticks = us_to_pm_timer_ticks(idle_time); 1022 /* Tell the scheduler how much we idled: */ 1023 sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); 1024 1025 local_irq_enable(); 1026 current_thread_info()->status |= TS_POLLING; 1027 1028 cx->usage++; 1029 1030 lapic_timer_state_broadcast(pr, cx, 0); 1031 cx->time += sleep_ticks; 1032 return idle_time; 1033 } 1034 1035 struct cpuidle_driver acpi_idle_driver = { 1036 .name = "acpi_idle", 1037 .owner = THIS_MODULE, 1038 }; 1039 1040 /** 1041 * acpi_processor_setup_cpuidle - prepares and configures CPUIDLE 1042 * @pr: the ACPI processor 1043 */ 1044 static int acpi_processor_setup_cpuidle(struct acpi_processor *pr) 1045 { 1046 int i, count = CPUIDLE_DRIVER_STATE_START; 1047 struct acpi_processor_cx *cx; 1048 struct cpuidle_state *state; 1049 struct cpuidle_device *dev = &pr->power.dev; 1050 1051 if (!pr->flags.power_setup_done) 1052 return -EINVAL; 1053 1054 if (pr->flags.power == 0) { 1055 return -EINVAL; 1056 } 1057 1058 dev->cpu = pr->id; 1059 for (i = 0; i < CPUIDLE_STATE_MAX; i++) { 1060 dev->states[i].name[0] = '\0'; 1061 dev->states[i].desc[0] = '\0'; 1062 } 1063 1064 if (max_cstate == 0) 1065 max_cstate = 1; 1066 1067 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { 1068 cx = &pr->power.states[i]; 1069 state = &dev->states[count]; 1070 1071 if (!cx->valid) 1072 continue; 1073 1074 #ifdef CONFIG_HOTPLUG_CPU 1075 if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) && 1076 !pr->flags.has_cst && 1077 !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) 1078 continue; 1079 #endif 1080 cpuidle_set_statedata(state, cx); 1081 1082 snprintf(state->name, CPUIDLE_NAME_LEN, "C%d", i); 1083 strncpy(state->desc, cx->desc, CPUIDLE_DESC_LEN); 1084 state->exit_latency = cx->latency; 1085 state->target_residency = cx->latency * latency_factor; 1086 state->power_usage = cx->power; 1087 1088 state->flags = 0; 1089 switch (cx->type) { 1090 case ACPI_STATE_C1: 1091 state->flags |= CPUIDLE_FLAG_SHALLOW; 1092 if (cx->entry_method == ACPI_CSTATE_FFH) 1093 state->flags |= CPUIDLE_FLAG_TIME_VALID; 1094 1095 state->enter = acpi_idle_enter_c1; 1096 dev->safe_state = state; 1097 break; 1098 1099 case ACPI_STATE_C2: 1100 state->flags |= CPUIDLE_FLAG_BALANCED; 1101 state->flags |= CPUIDLE_FLAG_TIME_VALID; 1102 state->enter = acpi_idle_enter_simple; 1103 dev->safe_state = state; 1104 break; 1105 1106 case ACPI_STATE_C3: 1107 state->flags |= CPUIDLE_FLAG_DEEP; 1108 state->flags |= CPUIDLE_FLAG_TIME_VALID; 1109 state->flags |= CPUIDLE_FLAG_CHECK_BM; 1110 state->enter = pr->flags.bm_check ? 1111 acpi_idle_enter_bm : 1112 acpi_idle_enter_simple; 1113 break; 1114 } 1115 1116 count++; 1117 if (count == CPUIDLE_STATE_MAX) 1118 break; 1119 } 1120 1121 dev->state_count = count; 1122 1123 if (!count) 1124 return -EINVAL; 1125 1126 return 0; 1127 } 1128 1129 int acpi_processor_cst_has_changed(struct acpi_processor *pr) 1130 { 1131 int ret = 0; 1132 1133 if (boot_option_idle_override) 1134 return 0; 1135 1136 if (!pr) 1137 return -EINVAL; 1138 1139 if (nocst) { 1140 return -ENODEV; 1141 } 1142 1143 if (!pr->flags.power_setup_done) 1144 return -ENODEV; 1145 1146 cpuidle_pause_and_lock(); 1147 cpuidle_disable_device(&pr->power.dev); 1148 acpi_processor_get_power_info(pr); 1149 if (pr->flags.power) { 1150 acpi_processor_setup_cpuidle(pr); 1151 ret = cpuidle_enable_device(&pr->power.dev); 1152 } 1153 cpuidle_resume_and_unlock(); 1154 1155 return ret; 1156 } 1157 1158 int __cpuinit acpi_processor_power_init(struct acpi_processor *pr, 1159 struct acpi_device *device) 1160 { 1161 acpi_status status = 0; 1162 static int first_run; 1163 struct proc_dir_entry *entry = NULL; 1164 unsigned int i; 1165 1166 if (boot_option_idle_override) 1167 return 0; 1168 1169 if (!first_run) { 1170 if (idle_halt) { 1171 /* 1172 * When the boot option of "idle=halt" is added, halt 1173 * is used for CPU IDLE. 1174 * In such case C2/C3 is meaningless. So the max_cstate 1175 * is set to one. 1176 */ 1177 max_cstate = 1; 1178 } 1179 dmi_check_system(processor_power_dmi_table); 1180 max_cstate = acpi_processor_cstate_check(max_cstate); 1181 if (max_cstate < ACPI_C_STATES_MAX) 1182 printk(KERN_NOTICE 1183 "ACPI: processor limited to max C-state %d\n", 1184 max_cstate); 1185 first_run++; 1186 } 1187 1188 if (!pr) 1189 return -EINVAL; 1190 1191 if (acpi_gbl_FADT.cst_control && !nocst) { 1192 status = 1193 acpi_os_write_port(acpi_gbl_FADT.smi_command, acpi_gbl_FADT.cst_control, 8); 1194 if (ACPI_FAILURE(status)) { 1195 ACPI_EXCEPTION((AE_INFO, status, 1196 "Notifying BIOS of _CST ability failed")); 1197 } 1198 } 1199 1200 acpi_processor_get_power_info(pr); 1201 pr->flags.power_setup_done = 1; 1202 1203 /* 1204 * Install the idle handler if processor power management is supported. 1205 * Note that we use previously set idle handler will be used on 1206 * platforms that only support C1. 1207 */ 1208 if (pr->flags.power) { 1209 acpi_processor_setup_cpuidle(pr); 1210 if (cpuidle_register_device(&pr->power.dev)) 1211 return -EIO; 1212 1213 printk(KERN_INFO PREFIX "CPU%d (power states:", pr->id); 1214 for (i = 1; i <= pr->power.count; i++) 1215 if (pr->power.states[i].valid) 1216 printk(" C%d[C%d]", i, 1217 pr->power.states[i].type); 1218 printk(")\n"); 1219 } 1220 1221 /* 'power' [R] */ 1222 entry = proc_create_data(ACPI_PROCESSOR_FILE_POWER, 1223 S_IRUGO, acpi_device_dir(device), 1224 &acpi_processor_power_fops, 1225 acpi_driver_data(device)); 1226 if (!entry) 1227 return -EIO; 1228 return 0; 1229 } 1230 1231 int acpi_processor_power_exit(struct acpi_processor *pr, 1232 struct acpi_device *device) 1233 { 1234 if (boot_option_idle_override) 1235 return 0; 1236 1237 cpuidle_unregister_device(&pr->power.dev); 1238 pr->flags.power_setup_done = 0; 1239 1240 if (acpi_device_dir(device)) 1241 remove_proc_entry(ACPI_PROCESSOR_FILE_POWER, 1242 acpi_device_dir(device)); 1243 1244 return 0; 1245 } 1246