1 /* 2 * processor_idle - idle state submodule to the ACPI processor driver 3 * 4 * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> 5 * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> 6 * Copyright (C) 2004, 2005 Dominik Brodowski <linux@brodo.de> 7 * Copyright (C) 2004 Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> 8 * - Added processor hotplug support 9 * Copyright (C) 2005 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> 10 * - Added support for C3 on SMP 11 * 12 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or (at 17 * your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, but 20 * WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 22 * General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License along 25 * with this program; if not, write to the Free Software Foundation, Inc., 26 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. 27 * 28 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 29 */ 30 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/init.h> 34 #include <linux/cpufreq.h> 35 #include <linux/proc_fs.h> 36 #include <linux/seq_file.h> 37 #include <linux/acpi.h> 38 #include <linux/dmi.h> 39 #include <linux/moduleparam.h> 40 #include <linux/sched.h> /* need_resched() */ 41 #include <linux/pm_qos_params.h> 42 #include <linux/clockchips.h> 43 #include <linux/cpuidle.h> 44 #include <linux/cpuidle.h> 45 46 /* 47 * Include the apic definitions for x86 to have the APIC timer related defines 48 * available also for UP (on SMP it gets magically included via linux/smp.h). 49 * asm/acpi.h is not an option, as it would require more include magic. Also 50 * creating an empty asm-ia64/apic.h would just trade pest vs. cholera. 51 */ 52 #ifdef CONFIG_X86 53 #include <asm/apic.h> 54 #endif 55 56 #include <asm/io.h> 57 #include <asm/uaccess.h> 58 59 #include <acpi/acpi_bus.h> 60 #include <acpi/processor.h> 61 #include <asm/processor.h> 62 63 #define ACPI_PROCESSOR_COMPONENT 0x01000000 64 #define ACPI_PROCESSOR_CLASS "processor" 65 #define _COMPONENT ACPI_PROCESSOR_COMPONENT 66 ACPI_MODULE_NAME("processor_idle"); 67 #define ACPI_PROCESSOR_FILE_POWER "power" 68 #define US_TO_PM_TIMER_TICKS(t) ((t * (PM_TIMER_FREQUENCY/1000)) / 1000) 69 #define PM_TIMER_TICK_NS (1000000000ULL/PM_TIMER_FREQUENCY) 70 #ifndef CONFIG_CPU_IDLE 71 #define C2_OVERHEAD 4 /* 1us (3.579 ticks per us) */ 72 #define C3_OVERHEAD 4 /* 1us (3.579 ticks per us) */ 73 static void (*pm_idle_save) (void) __read_mostly; 74 #else 75 #define C2_OVERHEAD 1 /* 1us */ 76 #define C3_OVERHEAD 1 /* 1us */ 77 #endif 78 #define PM_TIMER_TICKS_TO_US(p) (((p) * 1000)/(PM_TIMER_FREQUENCY/1000)) 79 80 static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER; 81 #ifdef CONFIG_CPU_IDLE 82 module_param(max_cstate, uint, 0000); 83 #else 84 module_param(max_cstate, uint, 0644); 85 #endif 86 static unsigned int nocst __read_mostly; 87 module_param(nocst, uint, 0000); 88 89 #ifndef CONFIG_CPU_IDLE 90 /* 91 * bm_history -- bit-mask with a bit per jiffy of bus-master activity 92 * 1000 HZ: 0xFFFFFFFF: 32 jiffies = 32ms 93 * 800 HZ: 0xFFFFFFFF: 32 jiffies = 40ms 94 * 100 HZ: 0x0000000F: 4 jiffies = 40ms 95 * reduce history for more aggressive entry into C3 96 */ 97 static unsigned int bm_history __read_mostly = 98 (HZ >= 800 ? 0xFFFFFFFF : ((1U << (HZ / 25)) - 1)); 99 module_param(bm_history, uint, 0644); 100 101 static int acpi_processor_set_power_policy(struct acpi_processor *pr); 102 103 #else /* CONFIG_CPU_IDLE */ 104 static unsigned int latency_factor __read_mostly = 2; 105 module_param(latency_factor, uint, 0644); 106 #endif 107 108 /* 109 * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3. 110 * For now disable this. Probably a bug somewhere else. 111 * 112 * To skip this limit, boot/load with a large max_cstate limit. 113 */ 114 static int set_max_cstate(const struct dmi_system_id *id) 115 { 116 if (max_cstate > ACPI_PROCESSOR_MAX_POWER) 117 return 0; 118 119 printk(KERN_NOTICE PREFIX "%s detected - limiting to C%ld max_cstate." 120 " Override with \"processor.max_cstate=%d\"\n", id->ident, 121 (long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1); 122 123 max_cstate = (long)id->driver_data; 124 125 return 0; 126 } 127 128 /* Actually this shouldn't be __cpuinitdata, would be better to fix the 129 callers to only run once -AK */ 130 static struct dmi_system_id __cpuinitdata processor_power_dmi_table[] = { 131 { set_max_cstate, "IBM ThinkPad R40e", { 132 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), 133 DMI_MATCH(DMI_BIOS_VERSION,"1SET70WW")}, (void *)1}, 134 { set_max_cstate, "IBM ThinkPad R40e", { 135 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), 136 DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW")}, (void *)1}, 137 { set_max_cstate, "IBM ThinkPad R40e", { 138 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), 139 DMI_MATCH(DMI_BIOS_VERSION,"1SET43WW") }, (void*)1}, 140 { set_max_cstate, "IBM ThinkPad R40e", { 141 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), 142 DMI_MATCH(DMI_BIOS_VERSION,"1SET45WW") }, (void*)1}, 143 { set_max_cstate, "IBM ThinkPad R40e", { 144 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), 145 DMI_MATCH(DMI_BIOS_VERSION,"1SET47WW") }, (void*)1}, 146 { set_max_cstate, "IBM ThinkPad R40e", { 147 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), 148 DMI_MATCH(DMI_BIOS_VERSION,"1SET50WW") }, (void*)1}, 149 { set_max_cstate, "IBM ThinkPad R40e", { 150 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), 151 DMI_MATCH(DMI_BIOS_VERSION,"1SET52WW") }, (void*)1}, 152 { set_max_cstate, "IBM ThinkPad R40e", { 153 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), 154 DMI_MATCH(DMI_BIOS_VERSION,"1SET55WW") }, (void*)1}, 155 { set_max_cstate, "IBM ThinkPad R40e", { 156 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), 157 DMI_MATCH(DMI_BIOS_VERSION,"1SET56WW") }, (void*)1}, 158 { set_max_cstate, "IBM ThinkPad R40e", { 159 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), 160 DMI_MATCH(DMI_BIOS_VERSION,"1SET59WW") }, (void*)1}, 161 { set_max_cstate, "IBM ThinkPad R40e", { 162 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), 163 DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW") }, (void*)1}, 164 { set_max_cstate, "IBM ThinkPad R40e", { 165 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), 166 DMI_MATCH(DMI_BIOS_VERSION,"1SET61WW") }, (void*)1}, 167 { set_max_cstate, "IBM ThinkPad R40e", { 168 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), 169 DMI_MATCH(DMI_BIOS_VERSION,"1SET62WW") }, (void*)1}, 170 { set_max_cstate, "IBM ThinkPad R40e", { 171 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), 172 DMI_MATCH(DMI_BIOS_VERSION,"1SET64WW") }, (void*)1}, 173 { set_max_cstate, "IBM ThinkPad R40e", { 174 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), 175 DMI_MATCH(DMI_BIOS_VERSION,"1SET65WW") }, (void*)1}, 176 { set_max_cstate, "IBM ThinkPad R40e", { 177 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), 178 DMI_MATCH(DMI_BIOS_VERSION,"1SET68WW") }, (void*)1}, 179 { set_max_cstate, "Medion 41700", { 180 DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), 181 DMI_MATCH(DMI_BIOS_VERSION,"R01-A1J")}, (void *)1}, 182 { set_max_cstate, "Clevo 5600D", { 183 DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), 184 DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")}, 185 (void *)2}, 186 {}, 187 }; 188 189 static inline u32 ticks_elapsed(u32 t1, u32 t2) 190 { 191 if (t2 >= t1) 192 return (t2 - t1); 193 else if (!(acpi_gbl_FADT.flags & ACPI_FADT_32BIT_TIMER)) 194 return (((0x00FFFFFF - t1) + t2) & 0x00FFFFFF); 195 else 196 return ((0xFFFFFFFF - t1) + t2); 197 } 198 199 static inline u32 ticks_elapsed_in_us(u32 t1, u32 t2) 200 { 201 if (t2 >= t1) 202 return PM_TIMER_TICKS_TO_US(t2 - t1); 203 else if (!(acpi_gbl_FADT.flags & ACPI_FADT_32BIT_TIMER)) 204 return PM_TIMER_TICKS_TO_US(((0x00FFFFFF - t1) + t2) & 0x00FFFFFF); 205 else 206 return PM_TIMER_TICKS_TO_US((0xFFFFFFFF - t1) + t2); 207 } 208 209 /* 210 * Callers should disable interrupts before the call and enable 211 * interrupts after return. 212 */ 213 static void acpi_safe_halt(void) 214 { 215 current_thread_info()->status &= ~TS_POLLING; 216 /* 217 * TS_POLLING-cleared state must be visible before we 218 * test NEED_RESCHED: 219 */ 220 smp_mb(); 221 if (!need_resched()) { 222 safe_halt(); 223 local_irq_disable(); 224 } 225 current_thread_info()->status |= TS_POLLING; 226 } 227 228 #ifndef CONFIG_CPU_IDLE 229 230 static void 231 acpi_processor_power_activate(struct acpi_processor *pr, 232 struct acpi_processor_cx *new) 233 { 234 struct acpi_processor_cx *old; 235 236 if (!pr || !new) 237 return; 238 239 old = pr->power.state; 240 241 if (old) 242 old->promotion.count = 0; 243 new->demotion.count = 0; 244 245 /* Cleanup from old state. */ 246 if (old) { 247 switch (old->type) { 248 case ACPI_STATE_C3: 249 /* Disable bus master reload */ 250 if (new->type != ACPI_STATE_C3 && pr->flags.bm_check) 251 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0); 252 break; 253 } 254 } 255 256 /* Prepare to use new state. */ 257 switch (new->type) { 258 case ACPI_STATE_C3: 259 /* Enable bus master reload */ 260 if (old->type != ACPI_STATE_C3 && pr->flags.bm_check) 261 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 1); 262 break; 263 } 264 265 pr->power.state = new; 266 267 return; 268 } 269 270 static atomic_t c3_cpu_count; 271 272 /* Common C-state entry for C2, C3, .. */ 273 static void acpi_cstate_enter(struct acpi_processor_cx *cstate) 274 { 275 /* Don't trace irqs off for idle */ 276 stop_critical_timings(); 277 if (cstate->entry_method == ACPI_CSTATE_FFH) { 278 /* Call into architectural FFH based C-state */ 279 acpi_processor_ffh_cstate_enter(cstate); 280 } else { 281 int unused; 282 /* IO port based C-state */ 283 inb(cstate->address); 284 /* Dummy wait op - must do something useless after P_LVL2 read 285 because chipsets cannot guarantee that STPCLK# signal 286 gets asserted in time to freeze execution properly. */ 287 unused = inl(acpi_gbl_FADT.xpm_timer_block.address); 288 } 289 start_critical_timings(); 290 } 291 #endif /* !CONFIG_CPU_IDLE */ 292 293 #ifdef ARCH_APICTIMER_STOPS_ON_C3 294 295 /* 296 * Some BIOS implementations switch to C3 in the published C2 state. 297 * This seems to be a common problem on AMD boxen, but other vendors 298 * are affected too. We pick the most conservative approach: we assume 299 * that the local APIC stops in both C2 and C3. 300 */ 301 static void acpi_timer_check_state(int state, struct acpi_processor *pr, 302 struct acpi_processor_cx *cx) 303 { 304 struct acpi_processor_power *pwr = &pr->power; 305 u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2; 306 307 /* 308 * Check, if one of the previous states already marked the lapic 309 * unstable 310 */ 311 if (pwr->timer_broadcast_on_state < state) 312 return; 313 314 if (cx->type >= type) 315 pr->power.timer_broadcast_on_state = state; 316 } 317 318 static void acpi_propagate_timer_broadcast(struct acpi_processor *pr) 319 { 320 unsigned long reason; 321 322 reason = pr->power.timer_broadcast_on_state < INT_MAX ? 323 CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF; 324 325 clockevents_notify(reason, &pr->id); 326 } 327 328 /* Power(C) State timer broadcast control */ 329 static void acpi_state_timer_broadcast(struct acpi_processor *pr, 330 struct acpi_processor_cx *cx, 331 int broadcast) 332 { 333 int state = cx - pr->power.states; 334 335 if (state >= pr->power.timer_broadcast_on_state) { 336 unsigned long reason; 337 338 reason = broadcast ? CLOCK_EVT_NOTIFY_BROADCAST_ENTER : 339 CLOCK_EVT_NOTIFY_BROADCAST_EXIT; 340 clockevents_notify(reason, &pr->id); 341 } 342 } 343 344 #else 345 346 static void acpi_timer_check_state(int state, struct acpi_processor *pr, 347 struct acpi_processor_cx *cstate) { } 348 static void acpi_propagate_timer_broadcast(struct acpi_processor *pr) { } 349 static void acpi_state_timer_broadcast(struct acpi_processor *pr, 350 struct acpi_processor_cx *cx, 351 int broadcast) 352 { 353 } 354 355 #endif 356 357 /* 358 * Suspend / resume control 359 */ 360 static int acpi_idle_suspend; 361 362 int acpi_processor_suspend(struct acpi_device * device, pm_message_t state) 363 { 364 acpi_idle_suspend = 1; 365 return 0; 366 } 367 368 int acpi_processor_resume(struct acpi_device * device) 369 { 370 acpi_idle_suspend = 0; 371 return 0; 372 } 373 374 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86) 375 static int tsc_halts_in_c(int state) 376 { 377 switch (boot_cpu_data.x86_vendor) { 378 case X86_VENDOR_AMD: 379 /* 380 * AMD Fam10h TSC will tick in all 381 * C/P/S0/S1 states when this bit is set. 382 */ 383 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 384 return 0; 385 /*FALL THROUGH*/ 386 case X86_VENDOR_INTEL: 387 /* Several cases known where TSC halts in C2 too */ 388 default: 389 return state > ACPI_STATE_C1; 390 } 391 } 392 #endif 393 394 #ifndef CONFIG_CPU_IDLE 395 static void acpi_processor_idle(void) 396 { 397 struct acpi_processor *pr = NULL; 398 struct acpi_processor_cx *cx = NULL; 399 struct acpi_processor_cx *next_state = NULL; 400 int sleep_ticks = 0; 401 u32 t1, t2 = 0; 402 403 /* 404 * Interrupts must be disabled during bus mastering calculations and 405 * for C2/C3 transitions. 406 */ 407 local_irq_disable(); 408 409 pr = __get_cpu_var(processors); 410 if (!pr) { 411 local_irq_enable(); 412 return; 413 } 414 415 /* 416 * Check whether we truly need to go idle, or should 417 * reschedule: 418 */ 419 if (unlikely(need_resched())) { 420 local_irq_enable(); 421 return; 422 } 423 424 cx = pr->power.state; 425 if (!cx || acpi_idle_suspend) { 426 if (pm_idle_save) { 427 pm_idle_save(); /* enables IRQs */ 428 } else { 429 acpi_safe_halt(); 430 local_irq_enable(); 431 } 432 433 return; 434 } 435 436 /* 437 * Check BM Activity 438 * ----------------- 439 * Check for bus mastering activity (if required), record, and check 440 * for demotion. 441 */ 442 if (pr->flags.bm_check) { 443 u32 bm_status = 0; 444 unsigned long diff = jiffies - pr->power.bm_check_timestamp; 445 446 if (diff > 31) 447 diff = 31; 448 449 pr->power.bm_activity <<= diff; 450 451 acpi_get_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status); 452 if (bm_status) { 453 pr->power.bm_activity |= 0x1; 454 acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS, 1); 455 } 456 /* 457 * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect 458 * the true state of bus mastering activity; forcing us to 459 * manually check the BMIDEA bit of each IDE channel. 460 */ 461 else if (errata.piix4.bmisx) { 462 if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01) 463 || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01)) 464 pr->power.bm_activity |= 0x1; 465 } 466 467 pr->power.bm_check_timestamp = jiffies; 468 469 /* 470 * If bus mastering is or was active this jiffy, demote 471 * to avoid a faulty transition. Note that the processor 472 * won't enter a low-power state during this call (to this 473 * function) but should upon the next. 474 * 475 * TBD: A better policy might be to fallback to the demotion 476 * state (use it for this quantum only) istead of 477 * demoting -- and rely on duration as our sole demotion 478 * qualification. This may, however, introduce DMA 479 * issues (e.g. floppy DMA transfer overrun/underrun). 480 */ 481 if ((pr->power.bm_activity & 0x1) && 482 cx->demotion.threshold.bm) { 483 local_irq_enable(); 484 next_state = cx->demotion.state; 485 goto end; 486 } 487 } 488 489 #ifdef CONFIG_HOTPLUG_CPU 490 /* 491 * Check for P_LVL2_UP flag before entering C2 and above on 492 * an SMP system. We do it here instead of doing it at _CST/P_LVL 493 * detection phase, to work cleanly with logical CPU hotplug. 494 */ 495 if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) && 496 !pr->flags.has_cst && !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) 497 cx = &pr->power.states[ACPI_STATE_C1]; 498 #endif 499 500 /* 501 * Sleep: 502 * ------ 503 * Invoke the current Cx state to put the processor to sleep. 504 */ 505 if (cx->type == ACPI_STATE_C2 || cx->type == ACPI_STATE_C3) { 506 current_thread_info()->status &= ~TS_POLLING; 507 /* 508 * TS_POLLING-cleared state must be visible before we 509 * test NEED_RESCHED: 510 */ 511 smp_mb(); 512 if (need_resched()) { 513 current_thread_info()->status |= TS_POLLING; 514 local_irq_enable(); 515 return; 516 } 517 } 518 519 switch (cx->type) { 520 521 case ACPI_STATE_C1: 522 /* 523 * Invoke C1. 524 * Use the appropriate idle routine, the one that would 525 * be used without acpi C-states. 526 */ 527 if (pm_idle_save) { 528 pm_idle_save(); /* enables IRQs */ 529 } else { 530 acpi_safe_halt(); 531 local_irq_enable(); 532 } 533 534 /* 535 * TBD: Can't get time duration while in C1, as resumes 536 * go to an ISR rather than here. Need to instrument 537 * base interrupt handler. 538 * 539 * Note: the TSC better not stop in C1, sched_clock() will 540 * skew otherwise. 541 */ 542 sleep_ticks = 0xFFFFFFFF; 543 544 break; 545 546 case ACPI_STATE_C2: 547 /* Get start time (ticks) */ 548 t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); 549 /* Tell the scheduler that we are going deep-idle: */ 550 sched_clock_idle_sleep_event(); 551 /* Invoke C2 */ 552 acpi_state_timer_broadcast(pr, cx, 1); 553 acpi_cstate_enter(cx); 554 /* Get end time (ticks) */ 555 t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); 556 557 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86) 558 /* TSC halts in C2, so notify users */ 559 if (tsc_halts_in_c(ACPI_STATE_C2)) 560 mark_tsc_unstable("possible TSC halt in C2"); 561 #endif 562 /* Compute time (ticks) that we were actually asleep */ 563 sleep_ticks = ticks_elapsed(t1, t2); 564 565 /* Tell the scheduler how much we idled: */ 566 sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); 567 568 /* Re-enable interrupts */ 569 local_irq_enable(); 570 /* Do not account our idle-switching overhead: */ 571 sleep_ticks -= cx->latency_ticks + C2_OVERHEAD; 572 573 current_thread_info()->status |= TS_POLLING; 574 acpi_state_timer_broadcast(pr, cx, 0); 575 break; 576 577 case ACPI_STATE_C3: 578 acpi_unlazy_tlb(smp_processor_id()); 579 /* 580 * Must be done before busmaster disable as we might 581 * need to access HPET ! 582 */ 583 acpi_state_timer_broadcast(pr, cx, 1); 584 /* 585 * disable bus master 586 * bm_check implies we need ARB_DIS 587 * !bm_check implies we need cache flush 588 * bm_control implies whether we can do ARB_DIS 589 * 590 * That leaves a case where bm_check is set and bm_control is 591 * not set. In that case we cannot do much, we enter C3 592 * without doing anything. 593 */ 594 if (pr->flags.bm_check && pr->flags.bm_control) { 595 if (atomic_inc_return(&c3_cpu_count) == 596 num_online_cpus()) { 597 /* 598 * All CPUs are trying to go to C3 599 * Disable bus master arbitration 600 */ 601 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1); 602 } 603 } else if (!pr->flags.bm_check) { 604 /* SMP with no shared cache... Invalidate cache */ 605 ACPI_FLUSH_CPU_CACHE(); 606 } 607 608 /* Get start time (ticks) */ 609 t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); 610 /* Invoke C3 */ 611 /* Tell the scheduler that we are going deep-idle: */ 612 sched_clock_idle_sleep_event(); 613 acpi_cstate_enter(cx); 614 /* Get end time (ticks) */ 615 t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); 616 if (pr->flags.bm_check && pr->flags.bm_control) { 617 /* Enable bus master arbitration */ 618 atomic_dec(&c3_cpu_count); 619 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0); 620 } 621 622 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86) 623 /* TSC halts in C3, so notify users */ 624 if (tsc_halts_in_c(ACPI_STATE_C3)) 625 mark_tsc_unstable("TSC halts in C3"); 626 #endif 627 /* Compute time (ticks) that we were actually asleep */ 628 sleep_ticks = ticks_elapsed(t1, t2); 629 /* Tell the scheduler how much we idled: */ 630 sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); 631 632 /* Re-enable interrupts */ 633 local_irq_enable(); 634 /* Do not account our idle-switching overhead: */ 635 sleep_ticks -= cx->latency_ticks + C3_OVERHEAD; 636 637 current_thread_info()->status |= TS_POLLING; 638 acpi_state_timer_broadcast(pr, cx, 0); 639 break; 640 641 default: 642 local_irq_enable(); 643 return; 644 } 645 cx->usage++; 646 if ((cx->type != ACPI_STATE_C1) && (sleep_ticks > 0)) 647 cx->time += sleep_ticks; 648 649 next_state = pr->power.state; 650 651 #ifdef CONFIG_HOTPLUG_CPU 652 /* Don't do promotion/demotion */ 653 if ((cx->type == ACPI_STATE_C1) && (num_online_cpus() > 1) && 654 !pr->flags.has_cst && !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) { 655 next_state = cx; 656 goto end; 657 } 658 #endif 659 660 /* 661 * Promotion? 662 * ---------- 663 * Track the number of longs (time asleep is greater than threshold) 664 * and promote when the count threshold is reached. Note that bus 665 * mastering activity may prevent promotions. 666 * Do not promote above max_cstate. 667 */ 668 if (cx->promotion.state && 669 ((cx->promotion.state - pr->power.states) <= max_cstate)) { 670 if (sleep_ticks > cx->promotion.threshold.ticks && 671 cx->promotion.state->latency <= 672 pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY)) { 673 cx->promotion.count++; 674 cx->demotion.count = 0; 675 if (cx->promotion.count >= 676 cx->promotion.threshold.count) { 677 if (pr->flags.bm_check) { 678 if (! 679 (pr->power.bm_activity & cx-> 680 promotion.threshold.bm)) { 681 next_state = 682 cx->promotion.state; 683 goto end; 684 } 685 } else { 686 next_state = cx->promotion.state; 687 goto end; 688 } 689 } 690 } 691 } 692 693 /* 694 * Demotion? 695 * --------- 696 * Track the number of shorts (time asleep is less than time threshold) 697 * and demote when the usage threshold is reached. 698 */ 699 if (cx->demotion.state) { 700 if (sleep_ticks < cx->demotion.threshold.ticks) { 701 cx->demotion.count++; 702 cx->promotion.count = 0; 703 if (cx->demotion.count >= cx->demotion.threshold.count) { 704 next_state = cx->demotion.state; 705 goto end; 706 } 707 } 708 } 709 710 end: 711 /* 712 * Demote if current state exceeds max_cstate 713 * or if the latency of the current state is unacceptable 714 */ 715 if ((pr->power.state - pr->power.states) > max_cstate || 716 pr->power.state->latency > 717 pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY)) { 718 if (cx->demotion.state) 719 next_state = cx->demotion.state; 720 } 721 722 /* 723 * New Cx State? 724 * ------------- 725 * If we're going to start using a new Cx state we must clean up 726 * from the previous and prepare to use the new. 727 */ 728 if (next_state != pr->power.state) 729 acpi_processor_power_activate(pr, next_state); 730 } 731 732 static int acpi_processor_set_power_policy(struct acpi_processor *pr) 733 { 734 unsigned int i; 735 unsigned int state_is_set = 0; 736 struct acpi_processor_cx *lower = NULL; 737 struct acpi_processor_cx *higher = NULL; 738 struct acpi_processor_cx *cx; 739 740 741 if (!pr) 742 return -EINVAL; 743 744 /* 745 * This function sets the default Cx state policy (OS idle handler). 746 * Our scheme is to promote quickly to C2 but more conservatively 747 * to C3. We're favoring C2 for its characteristics of low latency 748 * (quick response), good power savings, and ability to allow bus 749 * mastering activity. Note that the Cx state policy is completely 750 * customizable and can be altered dynamically. 751 */ 752 753 /* startup state */ 754 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { 755 cx = &pr->power.states[i]; 756 if (!cx->valid) 757 continue; 758 759 if (!state_is_set) 760 pr->power.state = cx; 761 state_is_set++; 762 break; 763 } 764 765 if (!state_is_set) 766 return -ENODEV; 767 768 /* demotion */ 769 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { 770 cx = &pr->power.states[i]; 771 if (!cx->valid) 772 continue; 773 774 if (lower) { 775 cx->demotion.state = lower; 776 cx->demotion.threshold.ticks = cx->latency_ticks; 777 cx->demotion.threshold.count = 1; 778 if (cx->type == ACPI_STATE_C3) 779 cx->demotion.threshold.bm = bm_history; 780 } 781 782 lower = cx; 783 } 784 785 /* promotion */ 786 for (i = (ACPI_PROCESSOR_MAX_POWER - 1); i > 0; i--) { 787 cx = &pr->power.states[i]; 788 if (!cx->valid) 789 continue; 790 791 if (higher) { 792 cx->promotion.state = higher; 793 cx->promotion.threshold.ticks = cx->latency_ticks; 794 if (cx->type >= ACPI_STATE_C2) 795 cx->promotion.threshold.count = 4; 796 else 797 cx->promotion.threshold.count = 10; 798 if (higher->type == ACPI_STATE_C3) 799 cx->promotion.threshold.bm = bm_history; 800 } 801 802 higher = cx; 803 } 804 805 return 0; 806 } 807 #endif /* !CONFIG_CPU_IDLE */ 808 809 static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr) 810 { 811 812 if (!pr) 813 return -EINVAL; 814 815 if (!pr->pblk) 816 return -ENODEV; 817 818 /* if info is obtained from pblk/fadt, type equals state */ 819 pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2; 820 pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3; 821 822 #ifndef CONFIG_HOTPLUG_CPU 823 /* 824 * Check for P_LVL2_UP flag before entering C2 and above on 825 * an SMP system. 826 */ 827 if ((num_online_cpus() > 1) && 828 !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) 829 return -ENODEV; 830 #endif 831 832 /* determine C2 and C3 address from pblk */ 833 pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4; 834 pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5; 835 836 /* determine latencies from FADT */ 837 pr->power.states[ACPI_STATE_C2].latency = acpi_gbl_FADT.C2latency; 838 pr->power.states[ACPI_STATE_C3].latency = acpi_gbl_FADT.C3latency; 839 840 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 841 "lvl2[0x%08x] lvl3[0x%08x]\n", 842 pr->power.states[ACPI_STATE_C2].address, 843 pr->power.states[ACPI_STATE_C3].address)); 844 845 return 0; 846 } 847 848 static int acpi_processor_get_power_info_default(struct acpi_processor *pr) 849 { 850 if (!pr->power.states[ACPI_STATE_C1].valid) { 851 /* set the first C-State to C1 */ 852 /* all processors need to support C1 */ 853 pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1; 854 pr->power.states[ACPI_STATE_C1].valid = 1; 855 pr->power.states[ACPI_STATE_C1].entry_method = ACPI_CSTATE_HALT; 856 } 857 /* the C0 state only exists as a filler in our array */ 858 pr->power.states[ACPI_STATE_C0].valid = 1; 859 return 0; 860 } 861 862 static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) 863 { 864 acpi_status status = 0; 865 acpi_integer count; 866 int current_count; 867 int i; 868 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 869 union acpi_object *cst; 870 871 872 if (nocst) 873 return -ENODEV; 874 875 current_count = 0; 876 877 status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer); 878 if (ACPI_FAILURE(status)) { 879 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _CST, giving up\n")); 880 return -ENODEV; 881 } 882 883 cst = buffer.pointer; 884 885 /* There must be at least 2 elements */ 886 if (!cst || (cst->type != ACPI_TYPE_PACKAGE) || cst->package.count < 2) { 887 printk(KERN_ERR PREFIX "not enough elements in _CST\n"); 888 status = -EFAULT; 889 goto end; 890 } 891 892 count = cst->package.elements[0].integer.value; 893 894 /* Validate number of power states. */ 895 if (count < 1 || count != cst->package.count - 1) { 896 printk(KERN_ERR PREFIX "count given by _CST is not valid\n"); 897 status = -EFAULT; 898 goto end; 899 } 900 901 /* Tell driver that at least _CST is supported. */ 902 pr->flags.has_cst = 1; 903 904 for (i = 1; i <= count; i++) { 905 union acpi_object *element; 906 union acpi_object *obj; 907 struct acpi_power_register *reg; 908 struct acpi_processor_cx cx; 909 910 memset(&cx, 0, sizeof(cx)); 911 912 element = &(cst->package.elements[i]); 913 if (element->type != ACPI_TYPE_PACKAGE) 914 continue; 915 916 if (element->package.count != 4) 917 continue; 918 919 obj = &(element->package.elements[0]); 920 921 if (obj->type != ACPI_TYPE_BUFFER) 922 continue; 923 924 reg = (struct acpi_power_register *)obj->buffer.pointer; 925 926 if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO && 927 (reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) 928 continue; 929 930 /* There should be an easy way to extract an integer... */ 931 obj = &(element->package.elements[1]); 932 if (obj->type != ACPI_TYPE_INTEGER) 933 continue; 934 935 cx.type = obj->integer.value; 936 /* 937 * Some buggy BIOSes won't list C1 in _CST - 938 * Let acpi_processor_get_power_info_default() handle them later 939 */ 940 if (i == 1 && cx.type != ACPI_STATE_C1) 941 current_count++; 942 943 cx.address = reg->address; 944 cx.index = current_count + 1; 945 946 cx.entry_method = ACPI_CSTATE_SYSTEMIO; 947 if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) { 948 if (acpi_processor_ffh_cstate_probe 949 (pr->id, &cx, reg) == 0) { 950 cx.entry_method = ACPI_CSTATE_FFH; 951 } else if (cx.type == ACPI_STATE_C1) { 952 /* 953 * C1 is a special case where FIXED_HARDWARE 954 * can be handled in non-MWAIT way as well. 955 * In that case, save this _CST entry info. 956 * Otherwise, ignore this info and continue. 957 */ 958 cx.entry_method = ACPI_CSTATE_HALT; 959 snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); 960 } else { 961 continue; 962 } 963 if (cx.type == ACPI_STATE_C1 && 964 (idle_halt || idle_nomwait)) { 965 /* 966 * In most cases the C1 space_id obtained from 967 * _CST object is FIXED_HARDWARE access mode. 968 * But when the option of idle=halt is added, 969 * the entry_method type should be changed from 970 * CSTATE_FFH to CSTATE_HALT. 971 * When the option of idle=nomwait is added, 972 * the C1 entry_method type should be 973 * CSTATE_HALT. 974 */ 975 cx.entry_method = ACPI_CSTATE_HALT; 976 snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); 977 } 978 } else { 979 snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI IOPORT 0x%x", 980 cx.address); 981 } 982 983 if (cx.type == ACPI_STATE_C1) { 984 cx.valid = 1; 985 } 986 987 obj = &(element->package.elements[2]); 988 if (obj->type != ACPI_TYPE_INTEGER) 989 continue; 990 991 cx.latency = obj->integer.value; 992 993 obj = &(element->package.elements[3]); 994 if (obj->type != ACPI_TYPE_INTEGER) 995 continue; 996 997 cx.power = obj->integer.value; 998 999 current_count++; 1000 memcpy(&(pr->power.states[current_count]), &cx, sizeof(cx)); 1001 1002 /* 1003 * We support total ACPI_PROCESSOR_MAX_POWER - 1 1004 * (From 1 through ACPI_PROCESSOR_MAX_POWER - 1) 1005 */ 1006 if (current_count >= (ACPI_PROCESSOR_MAX_POWER - 1)) { 1007 printk(KERN_WARNING 1008 "Limiting number of power states to max (%d)\n", 1009 ACPI_PROCESSOR_MAX_POWER); 1010 printk(KERN_WARNING 1011 "Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n"); 1012 break; 1013 } 1014 } 1015 1016 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d power states\n", 1017 current_count)); 1018 1019 /* Validate number of power states discovered */ 1020 if (current_count < 2) 1021 status = -EFAULT; 1022 1023 end: 1024 kfree(buffer.pointer); 1025 1026 return status; 1027 } 1028 1029 static void acpi_processor_power_verify_c2(struct acpi_processor_cx *cx) 1030 { 1031 1032 if (!cx->address) 1033 return; 1034 1035 /* 1036 * C2 latency must be less than or equal to 100 1037 * microseconds. 1038 */ 1039 else if (cx->latency > ACPI_PROCESSOR_MAX_C2_LATENCY) { 1040 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1041 "latency too large [%d]\n", cx->latency)); 1042 return; 1043 } 1044 1045 /* 1046 * Otherwise we've met all of our C2 requirements. 1047 * Normalize the C2 latency to expidite policy 1048 */ 1049 cx->valid = 1; 1050 1051 #ifndef CONFIG_CPU_IDLE 1052 cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency); 1053 #else 1054 cx->latency_ticks = cx->latency; 1055 #endif 1056 1057 return; 1058 } 1059 1060 static void acpi_processor_power_verify_c3(struct acpi_processor *pr, 1061 struct acpi_processor_cx *cx) 1062 { 1063 static int bm_check_flag; 1064 1065 1066 if (!cx->address) 1067 return; 1068 1069 /* 1070 * C3 latency must be less than or equal to 1000 1071 * microseconds. 1072 */ 1073 else if (cx->latency > ACPI_PROCESSOR_MAX_C3_LATENCY) { 1074 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1075 "latency too large [%d]\n", cx->latency)); 1076 return; 1077 } 1078 1079 /* 1080 * PIIX4 Erratum #18: We don't support C3 when Type-F (fast) 1081 * DMA transfers are used by any ISA device to avoid livelock. 1082 * Note that we could disable Type-F DMA (as recommended by 1083 * the erratum), but this is known to disrupt certain ISA 1084 * devices thus we take the conservative approach. 1085 */ 1086 else if (errata.piix4.fdma) { 1087 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1088 "C3 not supported on PIIX4 with Type-F DMA\n")); 1089 return; 1090 } 1091 1092 /* All the logic here assumes flags.bm_check is same across all CPUs */ 1093 if (!bm_check_flag) { 1094 /* Determine whether bm_check is needed based on CPU */ 1095 acpi_processor_power_init_bm_check(&(pr->flags), pr->id); 1096 bm_check_flag = pr->flags.bm_check; 1097 } else { 1098 pr->flags.bm_check = bm_check_flag; 1099 } 1100 1101 if (pr->flags.bm_check) { 1102 if (!pr->flags.bm_control) { 1103 if (pr->flags.has_cst != 1) { 1104 /* bus mastering control is necessary */ 1105 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1106 "C3 support requires BM control\n")); 1107 return; 1108 } else { 1109 /* Here we enter C3 without bus mastering */ 1110 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1111 "C3 support without BM control\n")); 1112 } 1113 } 1114 } else { 1115 /* 1116 * WBINVD should be set in fadt, for C3 state to be 1117 * supported on when bm_check is not required. 1118 */ 1119 if (!(acpi_gbl_FADT.flags & ACPI_FADT_WBINVD)) { 1120 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1121 "Cache invalidation should work properly" 1122 " for C3 to be enabled on SMP systems\n")); 1123 return; 1124 } 1125 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0); 1126 } 1127 1128 /* 1129 * Otherwise we've met all of our C3 requirements. 1130 * Normalize the C3 latency to expidite policy. Enable 1131 * checking of bus mastering status (bm_check) so we can 1132 * use this in our C3 policy 1133 */ 1134 cx->valid = 1; 1135 1136 #ifndef CONFIG_CPU_IDLE 1137 cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency); 1138 #else 1139 cx->latency_ticks = cx->latency; 1140 #endif 1141 1142 return; 1143 } 1144 1145 static int acpi_processor_power_verify(struct acpi_processor *pr) 1146 { 1147 unsigned int i; 1148 unsigned int working = 0; 1149 1150 pr->power.timer_broadcast_on_state = INT_MAX; 1151 1152 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { 1153 struct acpi_processor_cx *cx = &pr->power.states[i]; 1154 1155 switch (cx->type) { 1156 case ACPI_STATE_C1: 1157 cx->valid = 1; 1158 break; 1159 1160 case ACPI_STATE_C2: 1161 acpi_processor_power_verify_c2(cx); 1162 if (cx->valid) 1163 acpi_timer_check_state(i, pr, cx); 1164 break; 1165 1166 case ACPI_STATE_C3: 1167 acpi_processor_power_verify_c3(pr, cx); 1168 if (cx->valid) 1169 acpi_timer_check_state(i, pr, cx); 1170 break; 1171 } 1172 1173 if (cx->valid) 1174 working++; 1175 } 1176 1177 acpi_propagate_timer_broadcast(pr); 1178 1179 return (working); 1180 } 1181 1182 static int acpi_processor_get_power_info(struct acpi_processor *pr) 1183 { 1184 unsigned int i; 1185 int result; 1186 1187 1188 /* NOTE: the idle thread may not be running while calling 1189 * this function */ 1190 1191 /* Zero initialize all the C-states info. */ 1192 memset(pr->power.states, 0, sizeof(pr->power.states)); 1193 1194 result = acpi_processor_get_power_info_cst(pr); 1195 if (result == -ENODEV) 1196 result = acpi_processor_get_power_info_fadt(pr); 1197 1198 if (result) 1199 return result; 1200 1201 acpi_processor_get_power_info_default(pr); 1202 1203 pr->power.count = acpi_processor_power_verify(pr); 1204 1205 #ifndef CONFIG_CPU_IDLE 1206 /* 1207 * Set Default Policy 1208 * ------------------ 1209 * Now that we know which states are supported, set the default 1210 * policy. Note that this policy can be changed dynamically 1211 * (e.g. encourage deeper sleeps to conserve battery life when 1212 * not on AC). 1213 */ 1214 result = acpi_processor_set_power_policy(pr); 1215 if (result) 1216 return result; 1217 #endif 1218 1219 /* 1220 * if one state of type C2 or C3 is available, mark this 1221 * CPU as being "idle manageable" 1222 */ 1223 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { 1224 if (pr->power.states[i].valid) { 1225 pr->power.count = i; 1226 if (pr->power.states[i].type >= ACPI_STATE_C2) 1227 pr->flags.power = 1; 1228 } 1229 } 1230 1231 return 0; 1232 } 1233 1234 static int acpi_processor_power_seq_show(struct seq_file *seq, void *offset) 1235 { 1236 struct acpi_processor *pr = seq->private; 1237 unsigned int i; 1238 1239 1240 if (!pr) 1241 goto end; 1242 1243 seq_printf(seq, "active state: C%zd\n" 1244 "max_cstate: C%d\n" 1245 "bus master activity: %08x\n" 1246 "maximum allowed latency: %d usec\n", 1247 pr->power.state ? pr->power.state - pr->power.states : 0, 1248 max_cstate, (unsigned)pr->power.bm_activity, 1249 pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY)); 1250 1251 seq_puts(seq, "states:\n"); 1252 1253 for (i = 1; i <= pr->power.count; i++) { 1254 seq_printf(seq, " %cC%d: ", 1255 (&pr->power.states[i] == 1256 pr->power.state ? '*' : ' '), i); 1257 1258 if (!pr->power.states[i].valid) { 1259 seq_puts(seq, "<not supported>\n"); 1260 continue; 1261 } 1262 1263 switch (pr->power.states[i].type) { 1264 case ACPI_STATE_C1: 1265 seq_printf(seq, "type[C1] "); 1266 break; 1267 case ACPI_STATE_C2: 1268 seq_printf(seq, "type[C2] "); 1269 break; 1270 case ACPI_STATE_C3: 1271 seq_printf(seq, "type[C3] "); 1272 break; 1273 default: 1274 seq_printf(seq, "type[--] "); 1275 break; 1276 } 1277 1278 if (pr->power.states[i].promotion.state) 1279 seq_printf(seq, "promotion[C%zd] ", 1280 (pr->power.states[i].promotion.state - 1281 pr->power.states)); 1282 else 1283 seq_puts(seq, "promotion[--] "); 1284 1285 if (pr->power.states[i].demotion.state) 1286 seq_printf(seq, "demotion[C%zd] ", 1287 (pr->power.states[i].demotion.state - 1288 pr->power.states)); 1289 else 1290 seq_puts(seq, "demotion[--] "); 1291 1292 seq_printf(seq, "latency[%03d] usage[%08d] duration[%020llu]\n", 1293 pr->power.states[i].latency, 1294 pr->power.states[i].usage, 1295 (unsigned long long)pr->power.states[i].time); 1296 } 1297 1298 end: 1299 return 0; 1300 } 1301 1302 static int acpi_processor_power_open_fs(struct inode *inode, struct file *file) 1303 { 1304 return single_open(file, acpi_processor_power_seq_show, 1305 PDE(inode)->data); 1306 } 1307 1308 static const struct file_operations acpi_processor_power_fops = { 1309 .owner = THIS_MODULE, 1310 .open = acpi_processor_power_open_fs, 1311 .read = seq_read, 1312 .llseek = seq_lseek, 1313 .release = single_release, 1314 }; 1315 1316 #ifndef CONFIG_CPU_IDLE 1317 1318 int acpi_processor_cst_has_changed(struct acpi_processor *pr) 1319 { 1320 int result = 0; 1321 1322 if (boot_option_idle_override) 1323 return 0; 1324 1325 if (!pr) 1326 return -EINVAL; 1327 1328 if (nocst) { 1329 return -ENODEV; 1330 } 1331 1332 if (!pr->flags.power_setup_done) 1333 return -ENODEV; 1334 1335 /* 1336 * Fall back to the default idle loop, when pm_idle_save had 1337 * been initialized. 1338 */ 1339 if (pm_idle_save) { 1340 pm_idle = pm_idle_save; 1341 /* Relies on interrupts forcing exit from idle. */ 1342 synchronize_sched(); 1343 } 1344 1345 pr->flags.power = 0; 1346 result = acpi_processor_get_power_info(pr); 1347 if ((pr->flags.power == 1) && (pr->flags.power_setup_done)) 1348 pm_idle = acpi_processor_idle; 1349 1350 return result; 1351 } 1352 1353 #ifdef CONFIG_SMP 1354 static void smp_callback(void *v) 1355 { 1356 /* we already woke the CPU up, nothing more to do */ 1357 } 1358 1359 /* 1360 * This function gets called when a part of the kernel has a new latency 1361 * requirement. This means we need to get all processors out of their C-state, 1362 * and then recalculate a new suitable C-state. Just do a cross-cpu IPI; that 1363 * wakes them all right up. 1364 */ 1365 static int acpi_processor_latency_notify(struct notifier_block *b, 1366 unsigned long l, void *v) 1367 { 1368 smp_call_function(smp_callback, NULL, 1); 1369 return NOTIFY_OK; 1370 } 1371 1372 static struct notifier_block acpi_processor_latency_notifier = { 1373 .notifier_call = acpi_processor_latency_notify, 1374 }; 1375 1376 #endif 1377 1378 #else /* CONFIG_CPU_IDLE */ 1379 1380 /** 1381 * acpi_idle_bm_check - checks if bus master activity was detected 1382 */ 1383 static int acpi_idle_bm_check(void) 1384 { 1385 u32 bm_status = 0; 1386 1387 acpi_get_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status); 1388 if (bm_status) 1389 acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS, 1); 1390 /* 1391 * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect 1392 * the true state of bus mastering activity; forcing us to 1393 * manually check the BMIDEA bit of each IDE channel. 1394 */ 1395 else if (errata.piix4.bmisx) { 1396 if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01) 1397 || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01)) 1398 bm_status = 1; 1399 } 1400 return bm_status; 1401 } 1402 1403 /** 1404 * acpi_idle_update_bm_rld - updates the BM_RLD bit depending on target state 1405 * @pr: the processor 1406 * @target: the new target state 1407 */ 1408 static inline void acpi_idle_update_bm_rld(struct acpi_processor *pr, 1409 struct acpi_processor_cx *target) 1410 { 1411 if (pr->flags.bm_rld_set && target->type != ACPI_STATE_C3) { 1412 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0); 1413 pr->flags.bm_rld_set = 0; 1414 } 1415 1416 if (!pr->flags.bm_rld_set && target->type == ACPI_STATE_C3) { 1417 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 1); 1418 pr->flags.bm_rld_set = 1; 1419 } 1420 } 1421 1422 /** 1423 * acpi_idle_do_entry - a helper function that does C2 and C3 type entry 1424 * @cx: cstate data 1425 * 1426 * Caller disables interrupt before call and enables interrupt after return. 1427 */ 1428 static inline void acpi_idle_do_entry(struct acpi_processor_cx *cx) 1429 { 1430 /* Don't trace irqs off for idle */ 1431 stop_critical_timings(); 1432 if (cx->entry_method == ACPI_CSTATE_FFH) { 1433 /* Call into architectural FFH based C-state */ 1434 acpi_processor_ffh_cstate_enter(cx); 1435 } else if (cx->entry_method == ACPI_CSTATE_HALT) { 1436 acpi_safe_halt(); 1437 } else { 1438 int unused; 1439 /* IO port based C-state */ 1440 inb(cx->address); 1441 /* Dummy wait op - must do something useless after P_LVL2 read 1442 because chipsets cannot guarantee that STPCLK# signal 1443 gets asserted in time to freeze execution properly. */ 1444 unused = inl(acpi_gbl_FADT.xpm_timer_block.address); 1445 } 1446 start_critical_timings(); 1447 } 1448 1449 /** 1450 * acpi_idle_enter_c1 - enters an ACPI C1 state-type 1451 * @dev: the target CPU 1452 * @state: the state data 1453 * 1454 * This is equivalent to the HALT instruction. 1455 */ 1456 static int acpi_idle_enter_c1(struct cpuidle_device *dev, 1457 struct cpuidle_state *state) 1458 { 1459 u32 t1, t2; 1460 struct acpi_processor *pr; 1461 struct acpi_processor_cx *cx = cpuidle_get_statedata(state); 1462 1463 pr = __get_cpu_var(processors); 1464 1465 if (unlikely(!pr)) 1466 return 0; 1467 1468 local_irq_disable(); 1469 1470 /* Do not access any ACPI IO ports in suspend path */ 1471 if (acpi_idle_suspend) { 1472 acpi_safe_halt(); 1473 local_irq_enable(); 1474 return 0; 1475 } 1476 1477 if (pr->flags.bm_check) 1478 acpi_idle_update_bm_rld(pr, cx); 1479 1480 t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); 1481 acpi_idle_do_entry(cx); 1482 t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); 1483 1484 local_irq_enable(); 1485 cx->usage++; 1486 1487 return ticks_elapsed_in_us(t1, t2); 1488 } 1489 1490 /** 1491 * acpi_idle_enter_simple - enters an ACPI state without BM handling 1492 * @dev: the target CPU 1493 * @state: the state data 1494 */ 1495 static int acpi_idle_enter_simple(struct cpuidle_device *dev, 1496 struct cpuidle_state *state) 1497 { 1498 struct acpi_processor *pr; 1499 struct acpi_processor_cx *cx = cpuidle_get_statedata(state); 1500 u32 t1, t2; 1501 int sleep_ticks = 0; 1502 1503 pr = __get_cpu_var(processors); 1504 1505 if (unlikely(!pr)) 1506 return 0; 1507 1508 if (acpi_idle_suspend) 1509 return(acpi_idle_enter_c1(dev, state)); 1510 1511 local_irq_disable(); 1512 current_thread_info()->status &= ~TS_POLLING; 1513 /* 1514 * TS_POLLING-cleared state must be visible before we test 1515 * NEED_RESCHED: 1516 */ 1517 smp_mb(); 1518 1519 if (unlikely(need_resched())) { 1520 current_thread_info()->status |= TS_POLLING; 1521 local_irq_enable(); 1522 return 0; 1523 } 1524 1525 /* 1526 * Must be done before busmaster disable as we might need to 1527 * access HPET ! 1528 */ 1529 acpi_state_timer_broadcast(pr, cx, 1); 1530 1531 if (pr->flags.bm_check) 1532 acpi_idle_update_bm_rld(pr, cx); 1533 1534 if (cx->type == ACPI_STATE_C3) 1535 ACPI_FLUSH_CPU_CACHE(); 1536 1537 t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); 1538 /* Tell the scheduler that we are going deep-idle: */ 1539 sched_clock_idle_sleep_event(); 1540 acpi_idle_do_entry(cx); 1541 t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); 1542 1543 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86) 1544 /* TSC could halt in idle, so notify users */ 1545 if (tsc_halts_in_c(cx->type)) 1546 mark_tsc_unstable("TSC halts in idle");; 1547 #endif 1548 sleep_ticks = ticks_elapsed(t1, t2); 1549 1550 /* Tell the scheduler how much we idled: */ 1551 sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); 1552 1553 local_irq_enable(); 1554 current_thread_info()->status |= TS_POLLING; 1555 1556 cx->usage++; 1557 1558 acpi_state_timer_broadcast(pr, cx, 0); 1559 cx->time += sleep_ticks; 1560 return ticks_elapsed_in_us(t1, t2); 1561 } 1562 1563 static int c3_cpu_count; 1564 static DEFINE_SPINLOCK(c3_lock); 1565 1566 /** 1567 * acpi_idle_enter_bm - enters C3 with proper BM handling 1568 * @dev: the target CPU 1569 * @state: the state data 1570 * 1571 * If BM is detected, the deepest non-C3 idle state is entered instead. 1572 */ 1573 static int acpi_idle_enter_bm(struct cpuidle_device *dev, 1574 struct cpuidle_state *state) 1575 { 1576 struct acpi_processor *pr; 1577 struct acpi_processor_cx *cx = cpuidle_get_statedata(state); 1578 u32 t1, t2; 1579 int sleep_ticks = 0; 1580 1581 pr = __get_cpu_var(processors); 1582 1583 if (unlikely(!pr)) 1584 return 0; 1585 1586 if (acpi_idle_suspend) 1587 return(acpi_idle_enter_c1(dev, state)); 1588 1589 if (acpi_idle_bm_check()) { 1590 if (dev->safe_state) { 1591 return dev->safe_state->enter(dev, dev->safe_state); 1592 } else { 1593 local_irq_disable(); 1594 acpi_safe_halt(); 1595 local_irq_enable(); 1596 return 0; 1597 } 1598 } 1599 1600 local_irq_disable(); 1601 current_thread_info()->status &= ~TS_POLLING; 1602 /* 1603 * TS_POLLING-cleared state must be visible before we test 1604 * NEED_RESCHED: 1605 */ 1606 smp_mb(); 1607 1608 if (unlikely(need_resched())) { 1609 current_thread_info()->status |= TS_POLLING; 1610 local_irq_enable(); 1611 return 0; 1612 } 1613 1614 acpi_unlazy_tlb(smp_processor_id()); 1615 1616 /* Tell the scheduler that we are going deep-idle: */ 1617 sched_clock_idle_sleep_event(); 1618 /* 1619 * Must be done before busmaster disable as we might need to 1620 * access HPET ! 1621 */ 1622 acpi_state_timer_broadcast(pr, cx, 1); 1623 1624 acpi_idle_update_bm_rld(pr, cx); 1625 1626 /* 1627 * disable bus master 1628 * bm_check implies we need ARB_DIS 1629 * !bm_check implies we need cache flush 1630 * bm_control implies whether we can do ARB_DIS 1631 * 1632 * That leaves a case where bm_check is set and bm_control is 1633 * not set. In that case we cannot do much, we enter C3 1634 * without doing anything. 1635 */ 1636 if (pr->flags.bm_check && pr->flags.bm_control) { 1637 spin_lock(&c3_lock); 1638 c3_cpu_count++; 1639 /* Disable bus master arbitration when all CPUs are in C3 */ 1640 if (c3_cpu_count == num_online_cpus()) 1641 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1); 1642 spin_unlock(&c3_lock); 1643 } else if (!pr->flags.bm_check) { 1644 ACPI_FLUSH_CPU_CACHE(); 1645 } 1646 1647 t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); 1648 acpi_idle_do_entry(cx); 1649 t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); 1650 1651 /* Re-enable bus master arbitration */ 1652 if (pr->flags.bm_check && pr->flags.bm_control) { 1653 spin_lock(&c3_lock); 1654 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0); 1655 c3_cpu_count--; 1656 spin_unlock(&c3_lock); 1657 } 1658 1659 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86) 1660 /* TSC could halt in idle, so notify users */ 1661 if (tsc_halts_in_c(ACPI_STATE_C3)) 1662 mark_tsc_unstable("TSC halts in idle"); 1663 #endif 1664 sleep_ticks = ticks_elapsed(t1, t2); 1665 /* Tell the scheduler how much we idled: */ 1666 sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); 1667 1668 local_irq_enable(); 1669 current_thread_info()->status |= TS_POLLING; 1670 1671 cx->usage++; 1672 1673 acpi_state_timer_broadcast(pr, cx, 0); 1674 cx->time += sleep_ticks; 1675 return ticks_elapsed_in_us(t1, t2); 1676 } 1677 1678 struct cpuidle_driver acpi_idle_driver = { 1679 .name = "acpi_idle", 1680 .owner = THIS_MODULE, 1681 }; 1682 1683 /** 1684 * acpi_processor_setup_cpuidle - prepares and configures CPUIDLE 1685 * @pr: the ACPI processor 1686 */ 1687 static int acpi_processor_setup_cpuidle(struct acpi_processor *pr) 1688 { 1689 int i, count = CPUIDLE_DRIVER_STATE_START; 1690 struct acpi_processor_cx *cx; 1691 struct cpuidle_state *state; 1692 struct cpuidle_device *dev = &pr->power.dev; 1693 1694 if (!pr->flags.power_setup_done) 1695 return -EINVAL; 1696 1697 if (pr->flags.power == 0) { 1698 return -EINVAL; 1699 } 1700 1701 dev->cpu = pr->id; 1702 for (i = 0; i < CPUIDLE_STATE_MAX; i++) { 1703 dev->states[i].name[0] = '\0'; 1704 dev->states[i].desc[0] = '\0'; 1705 } 1706 1707 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { 1708 cx = &pr->power.states[i]; 1709 state = &dev->states[count]; 1710 1711 if (!cx->valid) 1712 continue; 1713 1714 #ifdef CONFIG_HOTPLUG_CPU 1715 if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) && 1716 !pr->flags.has_cst && 1717 !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) 1718 continue; 1719 #endif 1720 cpuidle_set_statedata(state, cx); 1721 1722 snprintf(state->name, CPUIDLE_NAME_LEN, "C%d", i); 1723 strncpy(state->desc, cx->desc, CPUIDLE_DESC_LEN); 1724 state->exit_latency = cx->latency; 1725 state->target_residency = cx->latency * latency_factor; 1726 state->power_usage = cx->power; 1727 1728 state->flags = 0; 1729 switch (cx->type) { 1730 case ACPI_STATE_C1: 1731 state->flags |= CPUIDLE_FLAG_SHALLOW; 1732 if (cx->entry_method == ACPI_CSTATE_FFH) 1733 state->flags |= CPUIDLE_FLAG_TIME_VALID; 1734 1735 state->enter = acpi_idle_enter_c1; 1736 dev->safe_state = state; 1737 break; 1738 1739 case ACPI_STATE_C2: 1740 state->flags |= CPUIDLE_FLAG_BALANCED; 1741 state->flags |= CPUIDLE_FLAG_TIME_VALID; 1742 state->enter = acpi_idle_enter_simple; 1743 dev->safe_state = state; 1744 break; 1745 1746 case ACPI_STATE_C3: 1747 state->flags |= CPUIDLE_FLAG_DEEP; 1748 state->flags |= CPUIDLE_FLAG_TIME_VALID; 1749 state->flags |= CPUIDLE_FLAG_CHECK_BM; 1750 state->enter = pr->flags.bm_check ? 1751 acpi_idle_enter_bm : 1752 acpi_idle_enter_simple; 1753 break; 1754 } 1755 1756 count++; 1757 if (count == CPUIDLE_STATE_MAX) 1758 break; 1759 } 1760 1761 dev->state_count = count; 1762 1763 if (!count) 1764 return -EINVAL; 1765 1766 return 0; 1767 } 1768 1769 int acpi_processor_cst_has_changed(struct acpi_processor *pr) 1770 { 1771 int ret = 0; 1772 1773 if (boot_option_idle_override) 1774 return 0; 1775 1776 if (!pr) 1777 return -EINVAL; 1778 1779 if (nocst) { 1780 return -ENODEV; 1781 } 1782 1783 if (!pr->flags.power_setup_done) 1784 return -ENODEV; 1785 1786 cpuidle_pause_and_lock(); 1787 cpuidle_disable_device(&pr->power.dev); 1788 acpi_processor_get_power_info(pr); 1789 if (pr->flags.power) { 1790 acpi_processor_setup_cpuidle(pr); 1791 ret = cpuidle_enable_device(&pr->power.dev); 1792 } 1793 cpuidle_resume_and_unlock(); 1794 1795 return ret; 1796 } 1797 1798 #endif /* CONFIG_CPU_IDLE */ 1799 1800 int __cpuinit acpi_processor_power_init(struct acpi_processor *pr, 1801 struct acpi_device *device) 1802 { 1803 acpi_status status = 0; 1804 static int first_run; 1805 struct proc_dir_entry *entry = NULL; 1806 unsigned int i; 1807 1808 if (boot_option_idle_override) 1809 return 0; 1810 1811 if (!first_run) { 1812 if (idle_halt) { 1813 /* 1814 * When the boot option of "idle=halt" is added, halt 1815 * is used for CPU IDLE. 1816 * In such case C2/C3 is meaningless. So the max_cstate 1817 * is set to one. 1818 */ 1819 max_cstate = 1; 1820 } 1821 dmi_check_system(processor_power_dmi_table); 1822 max_cstate = acpi_processor_cstate_check(max_cstate); 1823 if (max_cstate < ACPI_C_STATES_MAX) 1824 printk(KERN_NOTICE 1825 "ACPI: processor limited to max C-state %d\n", 1826 max_cstate); 1827 first_run++; 1828 #if !defined(CONFIG_CPU_IDLE) && defined(CONFIG_SMP) 1829 pm_qos_add_notifier(PM_QOS_CPU_DMA_LATENCY, 1830 &acpi_processor_latency_notifier); 1831 #endif 1832 } 1833 1834 if (!pr) 1835 return -EINVAL; 1836 1837 if (acpi_gbl_FADT.cst_control && !nocst) { 1838 status = 1839 acpi_os_write_port(acpi_gbl_FADT.smi_command, acpi_gbl_FADT.cst_control, 8); 1840 if (ACPI_FAILURE(status)) { 1841 ACPI_EXCEPTION((AE_INFO, status, 1842 "Notifying BIOS of _CST ability failed")); 1843 } 1844 } 1845 1846 acpi_processor_get_power_info(pr); 1847 pr->flags.power_setup_done = 1; 1848 1849 /* 1850 * Install the idle handler if processor power management is supported. 1851 * Note that we use previously set idle handler will be used on 1852 * platforms that only support C1. 1853 */ 1854 if (pr->flags.power) { 1855 #ifdef CONFIG_CPU_IDLE 1856 acpi_processor_setup_cpuidle(pr); 1857 if (cpuidle_register_device(&pr->power.dev)) 1858 return -EIO; 1859 #endif 1860 1861 printk(KERN_INFO PREFIX "CPU%d (power states:", pr->id); 1862 for (i = 1; i <= pr->power.count; i++) 1863 if (pr->power.states[i].valid) 1864 printk(" C%d[C%d]", i, 1865 pr->power.states[i].type); 1866 printk(")\n"); 1867 1868 #ifndef CONFIG_CPU_IDLE 1869 if (pr->id == 0) { 1870 pm_idle_save = pm_idle; 1871 pm_idle = acpi_processor_idle; 1872 } 1873 #endif 1874 } 1875 1876 /* 'power' [R] */ 1877 entry = proc_create_data(ACPI_PROCESSOR_FILE_POWER, 1878 S_IRUGO, acpi_device_dir(device), 1879 &acpi_processor_power_fops, 1880 acpi_driver_data(device)); 1881 if (!entry) 1882 return -EIO; 1883 return 0; 1884 } 1885 1886 int acpi_processor_power_exit(struct acpi_processor *pr, 1887 struct acpi_device *device) 1888 { 1889 if (boot_option_idle_override) 1890 return 0; 1891 1892 #ifdef CONFIG_CPU_IDLE 1893 cpuidle_unregister_device(&pr->power.dev); 1894 #endif 1895 pr->flags.power_setup_done = 0; 1896 1897 if (acpi_device_dir(device)) 1898 remove_proc_entry(ACPI_PROCESSOR_FILE_POWER, 1899 acpi_device_dir(device)); 1900 1901 #ifndef CONFIG_CPU_IDLE 1902 1903 /* Unregister the idle handler when processor #0 is removed. */ 1904 if (pr->id == 0) { 1905 if (pm_idle_save) 1906 pm_idle = pm_idle_save; 1907 1908 /* 1909 * We are about to unload the current idle thread pm callback 1910 * (pm_idle), Wait for all processors to update cached/local 1911 * copies of pm_idle before proceeding. 1912 */ 1913 cpu_idle_wait(); 1914 #ifdef CONFIG_SMP 1915 pm_qos_remove_notifier(PM_QOS_CPU_DMA_LATENCY, 1916 &acpi_processor_latency_notifier); 1917 #endif 1918 } 1919 #endif 1920 1921 return 0; 1922 } 1923