1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * pci_root.c - ACPI PCI Root Bridge Driver ($Revision: 40 $) 4 * 5 * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> 6 * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> 7 */ 8 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/init.h> 12 #include <linux/types.h> 13 #include <linux/mutex.h> 14 #include <linux/pm.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/pci.h> 17 #include <linux/pci-acpi.h> 18 #include <linux/dmar.h> 19 #include <linux/acpi.h> 20 #include <linux/slab.h> 21 #include <linux/dmi.h> 22 #include <linux/platform_data/x86/apple.h> 23 #include <acpi/apei.h> /* for acpi_hest_init() */ 24 25 #include "internal.h" 26 27 #define ACPI_PCI_ROOT_CLASS "pci_bridge" 28 #define ACPI_PCI_ROOT_DEVICE_NAME "PCI Root Bridge" 29 static int acpi_pci_root_add(struct acpi_device *device, 30 const struct acpi_device_id *not_used); 31 static void acpi_pci_root_remove(struct acpi_device *device); 32 33 static int acpi_pci_root_scan_dependent(struct acpi_device *adev) 34 { 35 acpiphp_check_host_bridge(adev); 36 return 0; 37 } 38 39 #define ACPI_PCIE_REQ_SUPPORT (OSC_PCI_EXT_CONFIG_SUPPORT \ 40 | OSC_PCI_ASPM_SUPPORT \ 41 | OSC_PCI_CLOCK_PM_SUPPORT \ 42 | OSC_PCI_MSI_SUPPORT) 43 44 static const struct acpi_device_id root_device_ids[] = { 45 {"PNP0A03", 0}, 46 {"", 0}, 47 }; 48 49 static struct acpi_scan_handler pci_root_handler = { 50 .ids = root_device_ids, 51 .attach = acpi_pci_root_add, 52 .detach = acpi_pci_root_remove, 53 .hotplug = { 54 .enabled = true, 55 .scan_dependent = acpi_pci_root_scan_dependent, 56 }, 57 }; 58 59 static DEFINE_MUTEX(osc_lock); 60 61 /** 62 * acpi_is_root_bridge - determine whether an ACPI CA node is a PCI root bridge 63 * @handle: the ACPI CA node in question. 64 * 65 * Note: we could make this API take a struct acpi_device * instead, but 66 * for now, it's more convenient to operate on an acpi_handle. 67 */ 68 int acpi_is_root_bridge(acpi_handle handle) 69 { 70 int ret; 71 struct acpi_device *device; 72 73 ret = acpi_bus_get_device(handle, &device); 74 if (ret) 75 return 0; 76 77 ret = acpi_match_device_ids(device, root_device_ids); 78 if (ret) 79 return 0; 80 else 81 return 1; 82 } 83 EXPORT_SYMBOL_GPL(acpi_is_root_bridge); 84 85 static acpi_status 86 get_root_bridge_busnr_callback(struct acpi_resource *resource, void *data) 87 { 88 struct resource *res = data; 89 struct acpi_resource_address64 address; 90 acpi_status status; 91 92 status = acpi_resource_to_address64(resource, &address); 93 if (ACPI_FAILURE(status)) 94 return AE_OK; 95 96 if ((address.address.address_length > 0) && 97 (address.resource_type == ACPI_BUS_NUMBER_RANGE)) { 98 res->start = address.address.minimum; 99 res->end = address.address.minimum + address.address.address_length - 1; 100 } 101 102 return AE_OK; 103 } 104 105 static acpi_status try_get_root_bridge_busnr(acpi_handle handle, 106 struct resource *res) 107 { 108 acpi_status status; 109 110 res->start = -1; 111 status = 112 acpi_walk_resources(handle, METHOD_NAME__CRS, 113 get_root_bridge_busnr_callback, res); 114 if (ACPI_FAILURE(status)) 115 return status; 116 if (res->start == -1) 117 return AE_ERROR; 118 return AE_OK; 119 } 120 121 struct pci_osc_bit_struct { 122 u32 bit; 123 char *desc; 124 }; 125 126 static struct pci_osc_bit_struct pci_osc_support_bit[] = { 127 { OSC_PCI_EXT_CONFIG_SUPPORT, "ExtendedConfig" }, 128 { OSC_PCI_ASPM_SUPPORT, "ASPM" }, 129 { OSC_PCI_CLOCK_PM_SUPPORT, "ClockPM" }, 130 { OSC_PCI_SEGMENT_GROUPS_SUPPORT, "Segments" }, 131 { OSC_PCI_MSI_SUPPORT, "MSI" }, 132 { OSC_PCI_EDR_SUPPORT, "EDR" }, 133 { OSC_PCI_HPX_TYPE_3_SUPPORT, "HPX-Type3" }, 134 }; 135 136 static struct pci_osc_bit_struct pci_osc_control_bit[] = { 137 { OSC_PCI_EXPRESS_NATIVE_HP_CONTROL, "PCIeHotplug" }, 138 { OSC_PCI_SHPC_NATIVE_HP_CONTROL, "SHPCHotplug" }, 139 { OSC_PCI_EXPRESS_PME_CONTROL, "PME" }, 140 { OSC_PCI_EXPRESS_AER_CONTROL, "AER" }, 141 { OSC_PCI_EXPRESS_CAPABILITY_CONTROL, "PCIeCapability" }, 142 { OSC_PCI_EXPRESS_LTR_CONTROL, "LTR" }, 143 { OSC_PCI_EXPRESS_DPC_CONTROL, "DPC" }, 144 }; 145 146 static void decode_osc_bits(struct acpi_pci_root *root, char *msg, u32 word, 147 struct pci_osc_bit_struct *table, int size) 148 { 149 char buf[80]; 150 int i, len = 0; 151 struct pci_osc_bit_struct *entry; 152 153 buf[0] = '\0'; 154 for (i = 0, entry = table; i < size; i++, entry++) 155 if (word & entry->bit) 156 len += scnprintf(buf + len, sizeof(buf) - len, "%s%s", 157 len ? " " : "", entry->desc); 158 159 dev_info(&root->device->dev, "_OSC: %s [%s]\n", msg, buf); 160 } 161 162 static void decode_osc_support(struct acpi_pci_root *root, char *msg, u32 word) 163 { 164 decode_osc_bits(root, msg, word, pci_osc_support_bit, 165 ARRAY_SIZE(pci_osc_support_bit)); 166 } 167 168 static void decode_osc_control(struct acpi_pci_root *root, char *msg, u32 word) 169 { 170 decode_osc_bits(root, msg, word, pci_osc_control_bit, 171 ARRAY_SIZE(pci_osc_control_bit)); 172 } 173 174 static u8 pci_osc_uuid_str[] = "33DB4D5B-1FF7-401C-9657-7441C03DD766"; 175 176 static acpi_status acpi_pci_run_osc(acpi_handle handle, 177 const u32 *capbuf, u32 *retval) 178 { 179 struct acpi_osc_context context = { 180 .uuid_str = pci_osc_uuid_str, 181 .rev = 1, 182 .cap.length = 12, 183 .cap.pointer = (void *)capbuf, 184 }; 185 acpi_status status; 186 187 status = acpi_run_osc(handle, &context); 188 if (ACPI_SUCCESS(status)) { 189 *retval = *((u32 *)(context.ret.pointer + 8)); 190 kfree(context.ret.pointer); 191 } 192 return status; 193 } 194 195 static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root, 196 u32 support, 197 u32 *control) 198 { 199 acpi_status status; 200 u32 result, capbuf[3]; 201 202 support &= OSC_PCI_SUPPORT_MASKS; 203 support |= root->osc_support_set; 204 205 capbuf[OSC_QUERY_DWORD] = OSC_QUERY_ENABLE; 206 capbuf[OSC_SUPPORT_DWORD] = support; 207 if (control) { 208 *control &= OSC_PCI_CONTROL_MASKS; 209 capbuf[OSC_CONTROL_DWORD] = *control | root->osc_control_set; 210 } else { 211 /* Run _OSC query only with existing controls. */ 212 capbuf[OSC_CONTROL_DWORD] = root->osc_control_set; 213 } 214 215 status = acpi_pci_run_osc(root->device->handle, capbuf, &result); 216 if (ACPI_SUCCESS(status)) { 217 root->osc_support_set = support; 218 if (control) 219 *control = result; 220 } 221 return status; 222 } 223 224 static acpi_status acpi_pci_osc_support(struct acpi_pci_root *root, u32 flags) 225 { 226 acpi_status status; 227 228 mutex_lock(&osc_lock); 229 status = acpi_pci_query_osc(root, flags, NULL); 230 mutex_unlock(&osc_lock); 231 return status; 232 } 233 234 struct acpi_pci_root *acpi_pci_find_root(acpi_handle handle) 235 { 236 struct acpi_pci_root *root; 237 struct acpi_device *device; 238 239 if (acpi_bus_get_device(handle, &device) || 240 acpi_match_device_ids(device, root_device_ids)) 241 return NULL; 242 243 root = acpi_driver_data(device); 244 245 return root; 246 } 247 EXPORT_SYMBOL_GPL(acpi_pci_find_root); 248 249 struct acpi_handle_node { 250 struct list_head node; 251 acpi_handle handle; 252 }; 253 254 /** 255 * acpi_get_pci_dev - convert ACPI CA handle to struct pci_dev 256 * @handle: the handle in question 257 * 258 * Given an ACPI CA handle, the desired PCI device is located in the 259 * list of PCI devices. 260 * 261 * If the device is found, its reference count is increased and this 262 * function returns a pointer to its data structure. The caller must 263 * decrement the reference count by calling pci_dev_put(). 264 * If no device is found, %NULL is returned. 265 */ 266 struct pci_dev *acpi_get_pci_dev(acpi_handle handle) 267 { 268 int dev, fn; 269 unsigned long long adr; 270 acpi_status status; 271 acpi_handle phandle; 272 struct pci_bus *pbus; 273 struct pci_dev *pdev = NULL; 274 struct acpi_handle_node *node, *tmp; 275 struct acpi_pci_root *root; 276 LIST_HEAD(device_list); 277 278 /* 279 * Walk up the ACPI CA namespace until we reach a PCI root bridge. 280 */ 281 phandle = handle; 282 while (!acpi_is_root_bridge(phandle)) { 283 node = kzalloc(sizeof(struct acpi_handle_node), GFP_KERNEL); 284 if (!node) 285 goto out; 286 287 INIT_LIST_HEAD(&node->node); 288 node->handle = phandle; 289 list_add(&node->node, &device_list); 290 291 status = acpi_get_parent(phandle, &phandle); 292 if (ACPI_FAILURE(status)) 293 goto out; 294 } 295 296 root = acpi_pci_find_root(phandle); 297 if (!root) 298 goto out; 299 300 pbus = root->bus; 301 302 /* 303 * Now, walk back down the PCI device tree until we return to our 304 * original handle. Assumes that everything between the PCI root 305 * bridge and the device we're looking for must be a P2P bridge. 306 */ 307 list_for_each_entry(node, &device_list, node) { 308 acpi_handle hnd = node->handle; 309 status = acpi_evaluate_integer(hnd, "_ADR", NULL, &adr); 310 if (ACPI_FAILURE(status)) 311 goto out; 312 dev = (adr >> 16) & 0xffff; 313 fn = adr & 0xffff; 314 315 pdev = pci_get_slot(pbus, PCI_DEVFN(dev, fn)); 316 if (!pdev || hnd == handle) 317 break; 318 319 pbus = pdev->subordinate; 320 pci_dev_put(pdev); 321 322 /* 323 * This function may be called for a non-PCI device that has a 324 * PCI parent (eg. a disk under a PCI SATA controller). In that 325 * case pdev->subordinate will be NULL for the parent. 326 */ 327 if (!pbus) { 328 dev_dbg(&pdev->dev, "Not a PCI-to-PCI bridge\n"); 329 pdev = NULL; 330 break; 331 } 332 } 333 out: 334 list_for_each_entry_safe(node, tmp, &device_list, node) 335 kfree(node); 336 337 return pdev; 338 } 339 EXPORT_SYMBOL_GPL(acpi_get_pci_dev); 340 341 /** 342 * acpi_pci_osc_control_set - Request control of PCI root _OSC features. 343 * @handle: ACPI handle of a PCI root bridge (or PCIe Root Complex). 344 * @mask: Mask of _OSC bits to request control of, place to store control mask. 345 * @req: Mask of _OSC bits the control of is essential to the caller. 346 * 347 * Run _OSC query for @mask and if that is successful, compare the returned 348 * mask of control bits with @req. If all of the @req bits are set in the 349 * returned mask, run _OSC request for it. 350 * 351 * The variable at the @mask address may be modified regardless of whether or 352 * not the function returns success. On success it will contain the mask of 353 * _OSC bits the BIOS has granted control of, but its contents are meaningless 354 * on failure. 355 **/ 356 acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 req) 357 { 358 struct acpi_pci_root *root; 359 acpi_status status = AE_OK; 360 u32 ctrl, capbuf[3]; 361 362 if (!mask) 363 return AE_BAD_PARAMETER; 364 365 ctrl = *mask & OSC_PCI_CONTROL_MASKS; 366 if ((ctrl & req) != req) 367 return AE_TYPE; 368 369 root = acpi_pci_find_root(handle); 370 if (!root) 371 return AE_NOT_EXIST; 372 373 mutex_lock(&osc_lock); 374 375 *mask = ctrl | root->osc_control_set; 376 /* No need to evaluate _OSC if the control was already granted. */ 377 if ((root->osc_control_set & ctrl) == ctrl) 378 goto out; 379 380 /* Need to check the available controls bits before requesting them. */ 381 while (*mask) { 382 status = acpi_pci_query_osc(root, root->osc_support_set, mask); 383 if (ACPI_FAILURE(status)) 384 goto out; 385 if (ctrl == *mask) 386 break; 387 decode_osc_control(root, "platform does not support", 388 ctrl & ~(*mask)); 389 ctrl = *mask; 390 } 391 392 if ((ctrl & req) != req) { 393 decode_osc_control(root, "not requesting control; platform does not support", 394 req & ~(ctrl)); 395 status = AE_SUPPORT; 396 goto out; 397 } 398 399 capbuf[OSC_QUERY_DWORD] = 0; 400 capbuf[OSC_SUPPORT_DWORD] = root->osc_support_set; 401 capbuf[OSC_CONTROL_DWORD] = ctrl; 402 status = acpi_pci_run_osc(handle, capbuf, mask); 403 if (ACPI_SUCCESS(status)) 404 root->osc_control_set = *mask; 405 out: 406 mutex_unlock(&osc_lock); 407 return status; 408 } 409 EXPORT_SYMBOL(acpi_pci_osc_control_set); 410 411 static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm, 412 bool is_pcie) 413 { 414 u32 support, control, requested; 415 acpi_status status; 416 struct acpi_device *device = root->device; 417 acpi_handle handle = device->handle; 418 419 /* 420 * Apple always return failure on _OSC calls when _OSI("Darwin") has 421 * been called successfully. We know the feature set supported by the 422 * platform, so avoid calling _OSC at all 423 */ 424 if (x86_apple_machine) { 425 root->osc_control_set = ~OSC_PCI_EXPRESS_PME_CONTROL; 426 decode_osc_control(root, "OS assumes control of", 427 root->osc_control_set); 428 return; 429 } 430 431 /* 432 * All supported architectures that use ACPI have support for 433 * PCI domains, so we indicate this in _OSC support capabilities. 434 */ 435 support = OSC_PCI_SEGMENT_GROUPS_SUPPORT; 436 support |= OSC_PCI_HPX_TYPE_3_SUPPORT; 437 if (pci_ext_cfg_avail()) 438 support |= OSC_PCI_EXT_CONFIG_SUPPORT; 439 if (pcie_aspm_support_enabled()) 440 support |= OSC_PCI_ASPM_SUPPORT | OSC_PCI_CLOCK_PM_SUPPORT; 441 if (pci_msi_enabled()) 442 support |= OSC_PCI_MSI_SUPPORT; 443 if (IS_ENABLED(CONFIG_PCIE_EDR)) 444 support |= OSC_PCI_EDR_SUPPORT; 445 446 decode_osc_support(root, "OS supports", support); 447 status = acpi_pci_osc_support(root, support); 448 if (ACPI_FAILURE(status)) { 449 *no_aspm = 1; 450 451 /* _OSC is optional for PCI host bridges */ 452 if ((status == AE_NOT_FOUND) && !is_pcie) 453 return; 454 455 dev_info(&device->dev, "_OSC failed (%s)%s\n", 456 acpi_format_exception(status), 457 pcie_aspm_support_enabled() ? "; disabling ASPM" : ""); 458 return; 459 } 460 461 if (pcie_ports_disabled) { 462 dev_info(&device->dev, "PCIe port services disabled; not requesting _OSC control\n"); 463 return; 464 } 465 466 if ((support & ACPI_PCIE_REQ_SUPPORT) != ACPI_PCIE_REQ_SUPPORT) { 467 decode_osc_support(root, "not requesting OS control; OS requires", 468 ACPI_PCIE_REQ_SUPPORT); 469 return; 470 } 471 472 control = OSC_PCI_EXPRESS_CAPABILITY_CONTROL 473 | OSC_PCI_EXPRESS_PME_CONTROL; 474 475 if (IS_ENABLED(CONFIG_PCIEASPM)) 476 control |= OSC_PCI_EXPRESS_LTR_CONTROL; 477 478 if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE)) 479 control |= OSC_PCI_EXPRESS_NATIVE_HP_CONTROL; 480 481 if (IS_ENABLED(CONFIG_HOTPLUG_PCI_SHPC)) 482 control |= OSC_PCI_SHPC_NATIVE_HP_CONTROL; 483 484 if (pci_aer_available()) 485 control |= OSC_PCI_EXPRESS_AER_CONTROL; 486 487 /* 488 * Per the Downstream Port Containment Related Enhancements ECN to 489 * the PCI Firmware Spec, r3.2, sec 4.5.1, table 4-5, 490 * OSC_PCI_EXPRESS_DPC_CONTROL indicates the OS supports both DPC 491 * and EDR. 492 */ 493 if (IS_ENABLED(CONFIG_PCIE_DPC) && IS_ENABLED(CONFIG_PCIE_EDR)) 494 control |= OSC_PCI_EXPRESS_DPC_CONTROL; 495 496 requested = control; 497 status = acpi_pci_osc_control_set(handle, &control, 498 OSC_PCI_EXPRESS_CAPABILITY_CONTROL); 499 if (ACPI_SUCCESS(status)) { 500 decode_osc_control(root, "OS now controls", control); 501 if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) { 502 /* 503 * We have ASPM control, but the FADT indicates that 504 * it's unsupported. Leave existing configuration 505 * intact and prevent the OS from touching it. 506 */ 507 dev_info(&device->dev, "FADT indicates ASPM is unsupported, using BIOS configuration\n"); 508 *no_aspm = 1; 509 } 510 } else { 511 decode_osc_control(root, "OS requested", requested); 512 decode_osc_control(root, "platform willing to grant", control); 513 dev_info(&device->dev, "_OSC failed (%s); disabling ASPM\n", 514 acpi_format_exception(status)); 515 516 /* 517 * We want to disable ASPM here, but aspm_disabled 518 * needs to remain in its state from boot so that we 519 * properly handle PCIe 1.1 devices. So we set this 520 * flag here, to defer the action until after the ACPI 521 * root scan. 522 */ 523 *no_aspm = 1; 524 } 525 } 526 527 static int acpi_pci_root_add(struct acpi_device *device, 528 const struct acpi_device_id *not_used) 529 { 530 unsigned long long segment, bus; 531 acpi_status status; 532 int result; 533 struct acpi_pci_root *root; 534 acpi_handle handle = device->handle; 535 int no_aspm = 0; 536 bool hotadd = system_state == SYSTEM_RUNNING; 537 bool is_pcie; 538 539 root = kzalloc(sizeof(struct acpi_pci_root), GFP_KERNEL); 540 if (!root) 541 return -ENOMEM; 542 543 segment = 0; 544 status = acpi_evaluate_integer(handle, METHOD_NAME__SEG, NULL, 545 &segment); 546 if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) { 547 dev_err(&device->dev, "can't evaluate _SEG\n"); 548 result = -ENODEV; 549 goto end; 550 } 551 552 /* Check _CRS first, then _BBN. If no _BBN, default to zero. */ 553 root->secondary.flags = IORESOURCE_BUS; 554 status = try_get_root_bridge_busnr(handle, &root->secondary); 555 if (ACPI_FAILURE(status)) { 556 /* 557 * We need both the start and end of the downstream bus range 558 * to interpret _CBA (MMCONFIG base address), so it really is 559 * supposed to be in _CRS. If we don't find it there, all we 560 * can do is assume [_BBN-0xFF] or [0-0xFF]. 561 */ 562 root->secondary.end = 0xFF; 563 dev_warn(&device->dev, 564 FW_BUG "no secondary bus range in _CRS\n"); 565 status = acpi_evaluate_integer(handle, METHOD_NAME__BBN, 566 NULL, &bus); 567 if (ACPI_SUCCESS(status)) 568 root->secondary.start = bus; 569 else if (status == AE_NOT_FOUND) 570 root->secondary.start = 0; 571 else { 572 dev_err(&device->dev, "can't evaluate _BBN\n"); 573 result = -ENODEV; 574 goto end; 575 } 576 } 577 578 root->device = device; 579 root->segment = segment & 0xFFFF; 580 strcpy(acpi_device_name(device), ACPI_PCI_ROOT_DEVICE_NAME); 581 strcpy(acpi_device_class(device), ACPI_PCI_ROOT_CLASS); 582 device->driver_data = root; 583 584 if (hotadd && dmar_device_add(handle)) { 585 result = -ENXIO; 586 goto end; 587 } 588 589 pr_info(PREFIX "%s [%s] (domain %04x %pR)\n", 590 acpi_device_name(device), acpi_device_bid(device), 591 root->segment, &root->secondary); 592 593 root->mcfg_addr = acpi_pci_root_get_mcfg_addr(handle); 594 595 is_pcie = strcmp(acpi_device_hid(device), "PNP0A08") == 0; 596 negotiate_os_control(root, &no_aspm, is_pcie); 597 598 /* 599 * TBD: Need PCI interface for enumeration/configuration of roots. 600 */ 601 602 /* 603 * Scan the Root Bridge 604 * -------------------- 605 * Must do this prior to any attempt to bind the root device, as the 606 * PCI namespace does not get created until this call is made (and 607 * thus the root bridge's pci_dev does not exist). 608 */ 609 root->bus = pci_acpi_scan_root(root); 610 if (!root->bus) { 611 dev_err(&device->dev, 612 "Bus %04x:%02x not present in PCI namespace\n", 613 root->segment, (unsigned int)root->secondary.start); 614 device->driver_data = NULL; 615 result = -ENODEV; 616 goto remove_dmar; 617 } 618 619 if (no_aspm) 620 pcie_no_aspm(); 621 622 pci_acpi_add_bus_pm_notifier(device); 623 device_set_wakeup_capable(root->bus->bridge, device->wakeup.flags.valid); 624 625 if (hotadd) { 626 pcibios_resource_survey_bus(root->bus); 627 pci_assign_unassigned_root_bus_resources(root->bus); 628 /* 629 * This is only called for the hotadd case. For the boot-time 630 * case, we need to wait until after PCI initialization in 631 * order to deal with IOAPICs mapped in on a PCI BAR. 632 * 633 * This is currently x86-specific, because acpi_ioapic_add() 634 * is an empty function without CONFIG_ACPI_HOTPLUG_IOAPIC. 635 * And CONFIG_ACPI_HOTPLUG_IOAPIC depends on CONFIG_X86_IO_APIC 636 * (see drivers/acpi/Kconfig). 637 */ 638 acpi_ioapic_add(root->device->handle); 639 } 640 641 pci_lock_rescan_remove(); 642 pci_bus_add_devices(root->bus); 643 pci_unlock_rescan_remove(); 644 return 1; 645 646 remove_dmar: 647 if (hotadd) 648 dmar_device_remove(handle); 649 end: 650 kfree(root); 651 return result; 652 } 653 654 static void acpi_pci_root_remove(struct acpi_device *device) 655 { 656 struct acpi_pci_root *root = acpi_driver_data(device); 657 658 pci_lock_rescan_remove(); 659 660 pci_stop_root_bus(root->bus); 661 662 pci_ioapic_remove(root); 663 device_set_wakeup_capable(root->bus->bridge, false); 664 pci_acpi_remove_bus_pm_notifier(device); 665 666 pci_remove_root_bus(root->bus); 667 WARN_ON(acpi_ioapic_remove(root)); 668 669 dmar_device_remove(device->handle); 670 671 pci_unlock_rescan_remove(); 672 673 kfree(root); 674 } 675 676 /* 677 * Following code to support acpi_pci_root_create() is copied from 678 * arch/x86/pci/acpi.c and modified so it could be reused by x86, IA64 679 * and ARM64. 680 */ 681 static void acpi_pci_root_validate_resources(struct device *dev, 682 struct list_head *resources, 683 unsigned long type) 684 { 685 LIST_HEAD(list); 686 struct resource *res1, *res2, *root = NULL; 687 struct resource_entry *tmp, *entry, *entry2; 688 689 BUG_ON((type & (IORESOURCE_MEM | IORESOURCE_IO)) == 0); 690 root = (type & IORESOURCE_MEM) ? &iomem_resource : &ioport_resource; 691 692 list_splice_init(resources, &list); 693 resource_list_for_each_entry_safe(entry, tmp, &list) { 694 bool free = false; 695 resource_size_t end; 696 697 res1 = entry->res; 698 if (!(res1->flags & type)) 699 goto next; 700 701 /* Exclude non-addressable range or non-addressable portion */ 702 end = min(res1->end, root->end); 703 if (end <= res1->start) { 704 dev_info(dev, "host bridge window %pR (ignored, not CPU addressable)\n", 705 res1); 706 free = true; 707 goto next; 708 } else if (res1->end != end) { 709 dev_info(dev, "host bridge window %pR ([%#llx-%#llx] ignored, not CPU addressable)\n", 710 res1, (unsigned long long)end + 1, 711 (unsigned long long)res1->end); 712 res1->end = end; 713 } 714 715 resource_list_for_each_entry(entry2, resources) { 716 res2 = entry2->res; 717 if (!(res2->flags & type)) 718 continue; 719 720 /* 721 * I don't like throwing away windows because then 722 * our resources no longer match the ACPI _CRS, but 723 * the kernel resource tree doesn't allow overlaps. 724 */ 725 if (resource_union(res1, res2, res2)) { 726 dev_info(dev, "host bridge window expanded to %pR; %pR ignored\n", 727 res2, res1); 728 free = true; 729 goto next; 730 } 731 } 732 733 next: 734 resource_list_del(entry); 735 if (free) 736 resource_list_free_entry(entry); 737 else 738 resource_list_add_tail(entry, resources); 739 } 740 } 741 742 static void acpi_pci_root_remap_iospace(struct fwnode_handle *fwnode, 743 struct resource_entry *entry) 744 { 745 #ifdef PCI_IOBASE 746 struct resource *res = entry->res; 747 resource_size_t cpu_addr = res->start; 748 resource_size_t pci_addr = cpu_addr - entry->offset; 749 resource_size_t length = resource_size(res); 750 unsigned long port; 751 752 if (pci_register_io_range(fwnode, cpu_addr, length)) 753 goto err; 754 755 port = pci_address_to_pio(cpu_addr); 756 if (port == (unsigned long)-1) 757 goto err; 758 759 res->start = port; 760 res->end = port + length - 1; 761 entry->offset = port - pci_addr; 762 763 if (pci_remap_iospace(res, cpu_addr) < 0) 764 goto err; 765 766 pr_info("Remapped I/O %pa to %pR\n", &cpu_addr, res); 767 return; 768 err: 769 res->flags |= IORESOURCE_DISABLED; 770 #endif 771 } 772 773 int acpi_pci_probe_root_resources(struct acpi_pci_root_info *info) 774 { 775 int ret; 776 struct list_head *list = &info->resources; 777 struct acpi_device *device = info->bridge; 778 struct resource_entry *entry, *tmp; 779 unsigned long flags; 780 781 flags = IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT; 782 ret = acpi_dev_get_resources(device, list, 783 acpi_dev_filter_resource_type_cb, 784 (void *)flags); 785 if (ret < 0) 786 dev_warn(&device->dev, 787 "failed to parse _CRS method, error code %d\n", ret); 788 else if (ret == 0) 789 dev_dbg(&device->dev, 790 "no IO and memory resources present in _CRS\n"); 791 else { 792 resource_list_for_each_entry_safe(entry, tmp, list) { 793 if (entry->res->flags & IORESOURCE_IO) 794 acpi_pci_root_remap_iospace(&device->fwnode, 795 entry); 796 797 if (entry->res->flags & IORESOURCE_DISABLED) 798 resource_list_destroy_entry(entry); 799 else 800 entry->res->name = info->name; 801 } 802 acpi_pci_root_validate_resources(&device->dev, list, 803 IORESOURCE_MEM); 804 acpi_pci_root_validate_resources(&device->dev, list, 805 IORESOURCE_IO); 806 } 807 808 return ret; 809 } 810 811 static void pci_acpi_root_add_resources(struct acpi_pci_root_info *info) 812 { 813 struct resource_entry *entry, *tmp; 814 struct resource *res, *conflict, *root = NULL; 815 816 resource_list_for_each_entry_safe(entry, tmp, &info->resources) { 817 res = entry->res; 818 if (res->flags & IORESOURCE_MEM) 819 root = &iomem_resource; 820 else if (res->flags & IORESOURCE_IO) 821 root = &ioport_resource; 822 else 823 continue; 824 825 /* 826 * Some legacy x86 host bridge drivers use iomem_resource and 827 * ioport_resource as default resource pool, skip it. 828 */ 829 if (res == root) 830 continue; 831 832 conflict = insert_resource_conflict(root, res); 833 if (conflict) { 834 dev_info(&info->bridge->dev, 835 "ignoring host bridge window %pR (conflicts with %s %pR)\n", 836 res, conflict->name, conflict); 837 resource_list_destroy_entry(entry); 838 } 839 } 840 } 841 842 static void __acpi_pci_root_release_info(struct acpi_pci_root_info *info) 843 { 844 struct resource *res; 845 struct resource_entry *entry, *tmp; 846 847 if (!info) 848 return; 849 850 resource_list_for_each_entry_safe(entry, tmp, &info->resources) { 851 res = entry->res; 852 if (res->parent && 853 (res->flags & (IORESOURCE_MEM | IORESOURCE_IO))) 854 release_resource(res); 855 resource_list_destroy_entry(entry); 856 } 857 858 info->ops->release_info(info); 859 } 860 861 static void acpi_pci_root_release_info(struct pci_host_bridge *bridge) 862 { 863 struct resource *res; 864 struct resource_entry *entry; 865 866 resource_list_for_each_entry(entry, &bridge->windows) { 867 res = entry->res; 868 if (res->flags & IORESOURCE_IO) 869 pci_unmap_iospace(res); 870 if (res->parent && 871 (res->flags & (IORESOURCE_MEM | IORESOURCE_IO))) 872 release_resource(res); 873 } 874 __acpi_pci_root_release_info(bridge->release_data); 875 } 876 877 struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root, 878 struct acpi_pci_root_ops *ops, 879 struct acpi_pci_root_info *info, 880 void *sysdata) 881 { 882 int ret, busnum = root->secondary.start; 883 struct acpi_device *device = root->device; 884 int node = acpi_get_node(device->handle); 885 struct pci_bus *bus; 886 struct pci_host_bridge *host_bridge; 887 union acpi_object *obj; 888 889 info->root = root; 890 info->bridge = device; 891 info->ops = ops; 892 INIT_LIST_HEAD(&info->resources); 893 snprintf(info->name, sizeof(info->name), "PCI Bus %04x:%02x", 894 root->segment, busnum); 895 896 if (ops->init_info && ops->init_info(info)) 897 goto out_release_info; 898 if (ops->prepare_resources) 899 ret = ops->prepare_resources(info); 900 else 901 ret = acpi_pci_probe_root_resources(info); 902 if (ret < 0) 903 goto out_release_info; 904 905 pci_acpi_root_add_resources(info); 906 pci_add_resource(&info->resources, &root->secondary); 907 bus = pci_create_root_bus(NULL, busnum, ops->pci_ops, 908 sysdata, &info->resources); 909 if (!bus) 910 goto out_release_info; 911 912 host_bridge = to_pci_host_bridge(bus->bridge); 913 if (!(root->osc_control_set & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL)) 914 host_bridge->native_pcie_hotplug = 0; 915 if (!(root->osc_control_set & OSC_PCI_SHPC_NATIVE_HP_CONTROL)) 916 host_bridge->native_shpc_hotplug = 0; 917 if (!(root->osc_control_set & OSC_PCI_EXPRESS_AER_CONTROL)) 918 host_bridge->native_aer = 0; 919 if (!(root->osc_control_set & OSC_PCI_EXPRESS_PME_CONTROL)) 920 host_bridge->native_pme = 0; 921 if (!(root->osc_control_set & OSC_PCI_EXPRESS_LTR_CONTROL)) 922 host_bridge->native_ltr = 0; 923 if (!(root->osc_control_set & OSC_PCI_EXPRESS_DPC_CONTROL)) 924 host_bridge->native_dpc = 0; 925 926 /* 927 * Evaluate the "PCI Boot Configuration" _DSM Function. If it 928 * exists and returns 0, we must preserve any PCI resource 929 * assignments made by firmware for this host bridge. 930 */ 931 obj = acpi_evaluate_dsm(ACPI_HANDLE(bus->bridge), &pci_acpi_dsm_guid, 1, 932 DSM_PCI_PRESERVE_BOOT_CONFIG, NULL); 933 if (obj && obj->type == ACPI_TYPE_INTEGER && obj->integer.value == 0) 934 host_bridge->preserve_config = 1; 935 ACPI_FREE(obj); 936 937 pci_scan_child_bus(bus); 938 pci_set_host_bridge_release(host_bridge, acpi_pci_root_release_info, 939 info); 940 if (node != NUMA_NO_NODE) 941 dev_printk(KERN_DEBUG, &bus->dev, "on NUMA node %d\n", node); 942 return bus; 943 944 out_release_info: 945 __acpi_pci_root_release_info(info); 946 return NULL; 947 } 948 949 void __init acpi_pci_root_init(void) 950 { 951 acpi_hest_init(); 952 if (acpi_pci_disabled) 953 return; 954 955 pci_acpi_crs_quirks(); 956 acpi_scan_add_handler_with_hotplug(&pci_root_handler, "pci_root"); 957 } 958