1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * pci_root.c - ACPI PCI Root Bridge Driver ($Revision: 40 $) 4 * 5 * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> 6 * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> 7 */ 8 9 #define pr_fmt(fmt) "ACPI: " fmt 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/init.h> 14 #include <linux/types.h> 15 #include <linux/mutex.h> 16 #include <linux/pm.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/pci.h> 19 #include <linux/pci-acpi.h> 20 #include <linux/dmar.h> 21 #include <linux/acpi.h> 22 #include <linux/slab.h> 23 #include <linux/dmi.h> 24 #include <linux/platform_data/x86/apple.h> 25 #include <acpi/apei.h> /* for acpi_hest_init() */ 26 27 #include "internal.h" 28 29 #define ACPI_PCI_ROOT_CLASS "pci_bridge" 30 #define ACPI_PCI_ROOT_DEVICE_NAME "PCI Root Bridge" 31 static int acpi_pci_root_add(struct acpi_device *device, 32 const struct acpi_device_id *not_used); 33 static void acpi_pci_root_remove(struct acpi_device *device); 34 35 static int acpi_pci_root_scan_dependent(struct acpi_device *adev) 36 { 37 acpiphp_check_host_bridge(adev); 38 return 0; 39 } 40 41 #define ACPI_PCIE_REQ_SUPPORT (OSC_PCI_EXT_CONFIG_SUPPORT \ 42 | OSC_PCI_ASPM_SUPPORT \ 43 | OSC_PCI_CLOCK_PM_SUPPORT \ 44 | OSC_PCI_MSI_SUPPORT) 45 46 static const struct acpi_device_id root_device_ids[] = { 47 {"PNP0A03", 0}, 48 {"", 0}, 49 }; 50 51 static struct acpi_scan_handler pci_root_handler = { 52 .ids = root_device_ids, 53 .attach = acpi_pci_root_add, 54 .detach = acpi_pci_root_remove, 55 .hotplug = { 56 .enabled = true, 57 .scan_dependent = acpi_pci_root_scan_dependent, 58 }, 59 }; 60 61 /** 62 * acpi_is_root_bridge - determine whether an ACPI CA node is a PCI root bridge 63 * @handle: the ACPI CA node in question. 64 * 65 * Note: we could make this API take a struct acpi_device * instead, but 66 * for now, it's more convenient to operate on an acpi_handle. 67 */ 68 int acpi_is_root_bridge(acpi_handle handle) 69 { 70 int ret; 71 struct acpi_device *device; 72 73 ret = acpi_bus_get_device(handle, &device); 74 if (ret) 75 return 0; 76 77 ret = acpi_match_device_ids(device, root_device_ids); 78 if (ret) 79 return 0; 80 else 81 return 1; 82 } 83 EXPORT_SYMBOL_GPL(acpi_is_root_bridge); 84 85 static acpi_status 86 get_root_bridge_busnr_callback(struct acpi_resource *resource, void *data) 87 { 88 struct resource *res = data; 89 struct acpi_resource_address64 address; 90 acpi_status status; 91 92 status = acpi_resource_to_address64(resource, &address); 93 if (ACPI_FAILURE(status)) 94 return AE_OK; 95 96 if ((address.address.address_length > 0) && 97 (address.resource_type == ACPI_BUS_NUMBER_RANGE)) { 98 res->start = address.address.minimum; 99 res->end = address.address.minimum + address.address.address_length - 1; 100 } 101 102 return AE_OK; 103 } 104 105 static acpi_status try_get_root_bridge_busnr(acpi_handle handle, 106 struct resource *res) 107 { 108 acpi_status status; 109 110 res->start = -1; 111 status = 112 acpi_walk_resources(handle, METHOD_NAME__CRS, 113 get_root_bridge_busnr_callback, res); 114 if (ACPI_FAILURE(status)) 115 return status; 116 if (res->start == -1) 117 return AE_ERROR; 118 return AE_OK; 119 } 120 121 struct pci_osc_bit_struct { 122 u32 bit; 123 char *desc; 124 }; 125 126 static struct pci_osc_bit_struct pci_osc_support_bit[] = { 127 { OSC_PCI_EXT_CONFIG_SUPPORT, "ExtendedConfig" }, 128 { OSC_PCI_ASPM_SUPPORT, "ASPM" }, 129 { OSC_PCI_CLOCK_PM_SUPPORT, "ClockPM" }, 130 { OSC_PCI_SEGMENT_GROUPS_SUPPORT, "Segments" }, 131 { OSC_PCI_MSI_SUPPORT, "MSI" }, 132 { OSC_PCI_EDR_SUPPORT, "EDR" }, 133 { OSC_PCI_HPX_TYPE_3_SUPPORT, "HPX-Type3" }, 134 }; 135 136 static struct pci_osc_bit_struct pci_osc_control_bit[] = { 137 { OSC_PCI_EXPRESS_NATIVE_HP_CONTROL, "PCIeHotplug" }, 138 { OSC_PCI_SHPC_NATIVE_HP_CONTROL, "SHPCHotplug" }, 139 { OSC_PCI_EXPRESS_PME_CONTROL, "PME" }, 140 { OSC_PCI_EXPRESS_AER_CONTROL, "AER" }, 141 { OSC_PCI_EXPRESS_CAPABILITY_CONTROL, "PCIeCapability" }, 142 { OSC_PCI_EXPRESS_LTR_CONTROL, "LTR" }, 143 { OSC_PCI_EXPRESS_DPC_CONTROL, "DPC" }, 144 }; 145 146 static void decode_osc_bits(struct acpi_pci_root *root, char *msg, u32 word, 147 struct pci_osc_bit_struct *table, int size) 148 { 149 char buf[80]; 150 int i, len = 0; 151 struct pci_osc_bit_struct *entry; 152 153 buf[0] = '\0'; 154 for (i = 0, entry = table; i < size; i++, entry++) 155 if (word & entry->bit) 156 len += scnprintf(buf + len, sizeof(buf) - len, "%s%s", 157 len ? " " : "", entry->desc); 158 159 dev_info(&root->device->dev, "_OSC: %s [%s]\n", msg, buf); 160 } 161 162 static void decode_osc_support(struct acpi_pci_root *root, char *msg, u32 word) 163 { 164 decode_osc_bits(root, msg, word, pci_osc_support_bit, 165 ARRAY_SIZE(pci_osc_support_bit)); 166 } 167 168 static void decode_osc_control(struct acpi_pci_root *root, char *msg, u32 word) 169 { 170 decode_osc_bits(root, msg, word, pci_osc_control_bit, 171 ARRAY_SIZE(pci_osc_control_bit)); 172 } 173 174 static u8 pci_osc_uuid_str[] = "33DB4D5B-1FF7-401C-9657-7441C03DD766"; 175 176 static acpi_status acpi_pci_run_osc(acpi_handle handle, 177 const u32 *capbuf, u32 *retval) 178 { 179 struct acpi_osc_context context = { 180 .uuid_str = pci_osc_uuid_str, 181 .rev = 1, 182 .cap.length = 12, 183 .cap.pointer = (void *)capbuf, 184 }; 185 acpi_status status; 186 187 status = acpi_run_osc(handle, &context); 188 if (ACPI_SUCCESS(status)) { 189 *retval = *((u32 *)(context.ret.pointer + 8)); 190 kfree(context.ret.pointer); 191 } 192 return status; 193 } 194 195 static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root, 196 u32 support, 197 u32 *control) 198 { 199 acpi_status status; 200 u32 result, capbuf[3]; 201 202 support |= root->osc_support_set; 203 204 capbuf[OSC_QUERY_DWORD] = OSC_QUERY_ENABLE; 205 capbuf[OSC_SUPPORT_DWORD] = support; 206 if (control) 207 capbuf[OSC_CONTROL_DWORD] = *control | root->osc_control_set; 208 else 209 /* Run _OSC query only with existing controls. */ 210 capbuf[OSC_CONTROL_DWORD] = root->osc_control_set; 211 212 status = acpi_pci_run_osc(root->device->handle, capbuf, &result); 213 if (ACPI_SUCCESS(status)) { 214 root->osc_support_set = support; 215 if (control) 216 *control = result; 217 } 218 return status; 219 } 220 221 static acpi_status acpi_pci_osc_support(struct acpi_pci_root *root, u32 flags) 222 { 223 return acpi_pci_query_osc(root, flags, NULL); 224 } 225 226 struct acpi_pci_root *acpi_pci_find_root(acpi_handle handle) 227 { 228 struct acpi_pci_root *root; 229 struct acpi_device *device; 230 231 if (acpi_bus_get_device(handle, &device) || 232 acpi_match_device_ids(device, root_device_ids)) 233 return NULL; 234 235 root = acpi_driver_data(device); 236 237 return root; 238 } 239 EXPORT_SYMBOL_GPL(acpi_pci_find_root); 240 241 struct acpi_handle_node { 242 struct list_head node; 243 acpi_handle handle; 244 }; 245 246 /** 247 * acpi_get_pci_dev - convert ACPI CA handle to struct pci_dev 248 * @handle: the handle in question 249 * 250 * Given an ACPI CA handle, the desired PCI device is located in the 251 * list of PCI devices. 252 * 253 * If the device is found, its reference count is increased and this 254 * function returns a pointer to its data structure. The caller must 255 * decrement the reference count by calling pci_dev_put(). 256 * If no device is found, %NULL is returned. 257 */ 258 struct pci_dev *acpi_get_pci_dev(acpi_handle handle) 259 { 260 int dev, fn; 261 unsigned long long adr; 262 acpi_status status; 263 acpi_handle phandle; 264 struct pci_bus *pbus; 265 struct pci_dev *pdev = NULL; 266 struct acpi_handle_node *node, *tmp; 267 struct acpi_pci_root *root; 268 LIST_HEAD(device_list); 269 270 /* 271 * Walk up the ACPI CA namespace until we reach a PCI root bridge. 272 */ 273 phandle = handle; 274 while (!acpi_is_root_bridge(phandle)) { 275 node = kzalloc(sizeof(struct acpi_handle_node), GFP_KERNEL); 276 if (!node) 277 goto out; 278 279 INIT_LIST_HEAD(&node->node); 280 node->handle = phandle; 281 list_add(&node->node, &device_list); 282 283 status = acpi_get_parent(phandle, &phandle); 284 if (ACPI_FAILURE(status)) 285 goto out; 286 } 287 288 root = acpi_pci_find_root(phandle); 289 if (!root) 290 goto out; 291 292 pbus = root->bus; 293 294 /* 295 * Now, walk back down the PCI device tree until we return to our 296 * original handle. Assumes that everything between the PCI root 297 * bridge and the device we're looking for must be a P2P bridge. 298 */ 299 list_for_each_entry(node, &device_list, node) { 300 acpi_handle hnd = node->handle; 301 status = acpi_evaluate_integer(hnd, "_ADR", NULL, &adr); 302 if (ACPI_FAILURE(status)) 303 goto out; 304 dev = (adr >> 16) & 0xffff; 305 fn = adr & 0xffff; 306 307 pdev = pci_get_slot(pbus, PCI_DEVFN(dev, fn)); 308 if (!pdev || hnd == handle) 309 break; 310 311 pbus = pdev->subordinate; 312 pci_dev_put(pdev); 313 314 /* 315 * This function may be called for a non-PCI device that has a 316 * PCI parent (eg. a disk under a PCI SATA controller). In that 317 * case pdev->subordinate will be NULL for the parent. 318 */ 319 if (!pbus) { 320 dev_dbg(&pdev->dev, "Not a PCI-to-PCI bridge\n"); 321 pdev = NULL; 322 break; 323 } 324 } 325 out: 326 list_for_each_entry_safe(node, tmp, &device_list, node) 327 kfree(node); 328 329 return pdev; 330 } 331 EXPORT_SYMBOL_GPL(acpi_get_pci_dev); 332 333 /** 334 * acpi_pci_osc_control_set - Request control of PCI root _OSC features. 335 * @handle: ACPI handle of a PCI root bridge (or PCIe Root Complex). 336 * @mask: Mask of _OSC bits to request control of, place to store control mask. 337 * @req: Mask of _OSC bits the control of is essential to the caller. 338 * 339 * Run _OSC query for @mask and if that is successful, compare the returned 340 * mask of control bits with @req. If all of the @req bits are set in the 341 * returned mask, run _OSC request for it. 342 * 343 * The variable at the @mask address may be modified regardless of whether or 344 * not the function returns success. On success it will contain the mask of 345 * _OSC bits the BIOS has granted control of, but its contents are meaningless 346 * on failure. 347 **/ 348 static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 req) 349 { 350 struct acpi_pci_root *root; 351 acpi_status status; 352 u32 ctrl, capbuf[3]; 353 354 if (!mask) 355 return AE_BAD_PARAMETER; 356 357 ctrl = *mask; 358 if ((ctrl & req) != req) 359 return AE_TYPE; 360 361 root = acpi_pci_find_root(handle); 362 if (!root) 363 return AE_NOT_EXIST; 364 365 *mask = ctrl | root->osc_control_set; 366 /* No need to evaluate _OSC if the control was already granted. */ 367 if ((root->osc_control_set & ctrl) == ctrl) 368 return AE_OK; 369 370 /* Need to check the available controls bits before requesting them. */ 371 while (*mask) { 372 status = acpi_pci_query_osc(root, root->osc_support_set, mask); 373 if (ACPI_FAILURE(status)) 374 return status; 375 if (ctrl == *mask) 376 break; 377 decode_osc_control(root, "platform does not support", 378 ctrl & ~(*mask)); 379 ctrl = *mask; 380 } 381 382 if ((ctrl & req) != req) { 383 decode_osc_control(root, "not requesting control; platform does not support", 384 req & ~(ctrl)); 385 return AE_SUPPORT; 386 } 387 388 capbuf[OSC_QUERY_DWORD] = 0; 389 capbuf[OSC_SUPPORT_DWORD] = root->osc_support_set; 390 capbuf[OSC_CONTROL_DWORD] = ctrl; 391 status = acpi_pci_run_osc(handle, capbuf, mask); 392 if (ACPI_FAILURE(status)) 393 return status; 394 395 root->osc_control_set = *mask; 396 return AE_OK; 397 } 398 399 static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm, 400 bool is_pcie) 401 { 402 u32 support, control, requested; 403 acpi_status status; 404 struct acpi_device *device = root->device; 405 acpi_handle handle = device->handle; 406 407 /* 408 * Apple always return failure on _OSC calls when _OSI("Darwin") has 409 * been called successfully. We know the feature set supported by the 410 * platform, so avoid calling _OSC at all 411 */ 412 if (x86_apple_machine) { 413 root->osc_control_set = ~OSC_PCI_EXPRESS_PME_CONTROL; 414 decode_osc_control(root, "OS assumes control of", 415 root->osc_control_set); 416 return; 417 } 418 419 /* 420 * All supported architectures that use ACPI have support for 421 * PCI domains, so we indicate this in _OSC support capabilities. 422 */ 423 support = OSC_PCI_SEGMENT_GROUPS_SUPPORT; 424 support |= OSC_PCI_HPX_TYPE_3_SUPPORT; 425 if (pci_ext_cfg_avail()) 426 support |= OSC_PCI_EXT_CONFIG_SUPPORT; 427 if (pcie_aspm_support_enabled()) 428 support |= OSC_PCI_ASPM_SUPPORT | OSC_PCI_CLOCK_PM_SUPPORT; 429 if (pci_msi_enabled()) 430 support |= OSC_PCI_MSI_SUPPORT; 431 if (IS_ENABLED(CONFIG_PCIE_EDR)) 432 support |= OSC_PCI_EDR_SUPPORT; 433 434 decode_osc_support(root, "OS supports", support); 435 status = acpi_pci_osc_support(root, support); 436 if (ACPI_FAILURE(status)) { 437 *no_aspm = 1; 438 439 /* _OSC is optional for PCI host bridges */ 440 if ((status == AE_NOT_FOUND) && !is_pcie) 441 return; 442 443 dev_info(&device->dev, "_OSC: platform retains control of PCIe features (%s)\n", 444 acpi_format_exception(status)); 445 return; 446 } 447 448 if (pcie_ports_disabled) { 449 dev_info(&device->dev, "PCIe port services disabled; not requesting _OSC control\n"); 450 return; 451 } 452 453 if ((support & ACPI_PCIE_REQ_SUPPORT) != ACPI_PCIE_REQ_SUPPORT) { 454 decode_osc_support(root, "not requesting OS control; OS requires", 455 ACPI_PCIE_REQ_SUPPORT); 456 return; 457 } 458 459 control = OSC_PCI_EXPRESS_CAPABILITY_CONTROL 460 | OSC_PCI_EXPRESS_PME_CONTROL; 461 462 if (IS_ENABLED(CONFIG_PCIEASPM)) 463 control |= OSC_PCI_EXPRESS_LTR_CONTROL; 464 465 if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE)) 466 control |= OSC_PCI_EXPRESS_NATIVE_HP_CONTROL; 467 468 if (IS_ENABLED(CONFIG_HOTPLUG_PCI_SHPC)) 469 control |= OSC_PCI_SHPC_NATIVE_HP_CONTROL; 470 471 if (pci_aer_available()) 472 control |= OSC_PCI_EXPRESS_AER_CONTROL; 473 474 /* 475 * Per the Downstream Port Containment Related Enhancements ECN to 476 * the PCI Firmware Spec, r3.2, sec 4.5.1, table 4-5, 477 * OSC_PCI_EXPRESS_DPC_CONTROL indicates the OS supports both DPC 478 * and EDR. 479 */ 480 if (IS_ENABLED(CONFIG_PCIE_DPC) && IS_ENABLED(CONFIG_PCIE_EDR)) 481 control |= OSC_PCI_EXPRESS_DPC_CONTROL; 482 483 requested = control; 484 status = acpi_pci_osc_control_set(handle, &control, 485 OSC_PCI_EXPRESS_CAPABILITY_CONTROL); 486 if (ACPI_SUCCESS(status)) { 487 decode_osc_control(root, "OS now controls", control); 488 if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) { 489 /* 490 * We have ASPM control, but the FADT indicates that 491 * it's unsupported. Leave existing configuration 492 * intact and prevent the OS from touching it. 493 */ 494 dev_info(&device->dev, "FADT indicates ASPM is unsupported, using BIOS configuration\n"); 495 *no_aspm = 1; 496 } 497 } else { 498 decode_osc_control(root, "OS requested", requested); 499 decode_osc_control(root, "platform willing to grant", control); 500 dev_info(&device->dev, "_OSC: platform retains control of PCIe features (%s)\n", 501 acpi_format_exception(status)); 502 503 /* 504 * We want to disable ASPM here, but aspm_disabled 505 * needs to remain in its state from boot so that we 506 * properly handle PCIe 1.1 devices. So we set this 507 * flag here, to defer the action until after the ACPI 508 * root scan. 509 */ 510 *no_aspm = 1; 511 } 512 } 513 514 static int acpi_pci_root_add(struct acpi_device *device, 515 const struct acpi_device_id *not_used) 516 { 517 unsigned long long segment, bus; 518 acpi_status status; 519 int result; 520 struct acpi_pci_root *root; 521 acpi_handle handle = device->handle; 522 int no_aspm = 0; 523 bool hotadd = system_state == SYSTEM_RUNNING; 524 bool is_pcie; 525 526 root = kzalloc(sizeof(struct acpi_pci_root), GFP_KERNEL); 527 if (!root) 528 return -ENOMEM; 529 530 segment = 0; 531 status = acpi_evaluate_integer(handle, METHOD_NAME__SEG, NULL, 532 &segment); 533 if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) { 534 dev_err(&device->dev, "can't evaluate _SEG\n"); 535 result = -ENODEV; 536 goto end; 537 } 538 539 /* Check _CRS first, then _BBN. If no _BBN, default to zero. */ 540 root->secondary.flags = IORESOURCE_BUS; 541 status = try_get_root_bridge_busnr(handle, &root->secondary); 542 if (ACPI_FAILURE(status)) { 543 /* 544 * We need both the start and end of the downstream bus range 545 * to interpret _CBA (MMCONFIG base address), so it really is 546 * supposed to be in _CRS. If we don't find it there, all we 547 * can do is assume [_BBN-0xFF] or [0-0xFF]. 548 */ 549 root->secondary.end = 0xFF; 550 dev_warn(&device->dev, 551 FW_BUG "no secondary bus range in _CRS\n"); 552 status = acpi_evaluate_integer(handle, METHOD_NAME__BBN, 553 NULL, &bus); 554 if (ACPI_SUCCESS(status)) 555 root->secondary.start = bus; 556 else if (status == AE_NOT_FOUND) 557 root->secondary.start = 0; 558 else { 559 dev_err(&device->dev, "can't evaluate _BBN\n"); 560 result = -ENODEV; 561 goto end; 562 } 563 } 564 565 root->device = device; 566 root->segment = segment & 0xFFFF; 567 strcpy(acpi_device_name(device), ACPI_PCI_ROOT_DEVICE_NAME); 568 strcpy(acpi_device_class(device), ACPI_PCI_ROOT_CLASS); 569 device->driver_data = root; 570 571 if (hotadd && dmar_device_add(handle)) { 572 result = -ENXIO; 573 goto end; 574 } 575 576 pr_info("%s [%s] (domain %04x %pR)\n", 577 acpi_device_name(device), acpi_device_bid(device), 578 root->segment, &root->secondary); 579 580 root->mcfg_addr = acpi_pci_root_get_mcfg_addr(handle); 581 582 is_pcie = strcmp(acpi_device_hid(device), "PNP0A08") == 0; 583 negotiate_os_control(root, &no_aspm, is_pcie); 584 585 /* 586 * TBD: Need PCI interface for enumeration/configuration of roots. 587 */ 588 589 /* 590 * Scan the Root Bridge 591 * -------------------- 592 * Must do this prior to any attempt to bind the root device, as the 593 * PCI namespace does not get created until this call is made (and 594 * thus the root bridge's pci_dev does not exist). 595 */ 596 root->bus = pci_acpi_scan_root(root); 597 if (!root->bus) { 598 dev_err(&device->dev, 599 "Bus %04x:%02x not present in PCI namespace\n", 600 root->segment, (unsigned int)root->secondary.start); 601 device->driver_data = NULL; 602 result = -ENODEV; 603 goto remove_dmar; 604 } 605 606 if (no_aspm) 607 pcie_no_aspm(); 608 609 pci_acpi_add_bus_pm_notifier(device); 610 device_set_wakeup_capable(root->bus->bridge, device->wakeup.flags.valid); 611 612 if (hotadd) { 613 pcibios_resource_survey_bus(root->bus); 614 pci_assign_unassigned_root_bus_resources(root->bus); 615 /* 616 * This is only called for the hotadd case. For the boot-time 617 * case, we need to wait until after PCI initialization in 618 * order to deal with IOAPICs mapped in on a PCI BAR. 619 * 620 * This is currently x86-specific, because acpi_ioapic_add() 621 * is an empty function without CONFIG_ACPI_HOTPLUG_IOAPIC. 622 * And CONFIG_ACPI_HOTPLUG_IOAPIC depends on CONFIG_X86_IO_APIC 623 * (see drivers/acpi/Kconfig). 624 */ 625 acpi_ioapic_add(root->device->handle); 626 } 627 628 pci_lock_rescan_remove(); 629 pci_bus_add_devices(root->bus); 630 pci_unlock_rescan_remove(); 631 return 1; 632 633 remove_dmar: 634 if (hotadd) 635 dmar_device_remove(handle); 636 end: 637 kfree(root); 638 return result; 639 } 640 641 static void acpi_pci_root_remove(struct acpi_device *device) 642 { 643 struct acpi_pci_root *root = acpi_driver_data(device); 644 645 pci_lock_rescan_remove(); 646 647 pci_stop_root_bus(root->bus); 648 649 pci_ioapic_remove(root); 650 device_set_wakeup_capable(root->bus->bridge, false); 651 pci_acpi_remove_bus_pm_notifier(device); 652 653 pci_remove_root_bus(root->bus); 654 WARN_ON(acpi_ioapic_remove(root)); 655 656 dmar_device_remove(device->handle); 657 658 pci_unlock_rescan_remove(); 659 660 kfree(root); 661 } 662 663 /* 664 * Following code to support acpi_pci_root_create() is copied from 665 * arch/x86/pci/acpi.c and modified so it could be reused by x86, IA64 666 * and ARM64. 667 */ 668 static void acpi_pci_root_validate_resources(struct device *dev, 669 struct list_head *resources, 670 unsigned long type) 671 { 672 LIST_HEAD(list); 673 struct resource *res1, *res2, *root = NULL; 674 struct resource_entry *tmp, *entry, *entry2; 675 676 BUG_ON((type & (IORESOURCE_MEM | IORESOURCE_IO)) == 0); 677 root = (type & IORESOURCE_MEM) ? &iomem_resource : &ioport_resource; 678 679 list_splice_init(resources, &list); 680 resource_list_for_each_entry_safe(entry, tmp, &list) { 681 bool free = false; 682 resource_size_t end; 683 684 res1 = entry->res; 685 if (!(res1->flags & type)) 686 goto next; 687 688 /* Exclude non-addressable range or non-addressable portion */ 689 end = min(res1->end, root->end); 690 if (end <= res1->start) { 691 dev_info(dev, "host bridge window %pR (ignored, not CPU addressable)\n", 692 res1); 693 free = true; 694 goto next; 695 } else if (res1->end != end) { 696 dev_info(dev, "host bridge window %pR ([%#llx-%#llx] ignored, not CPU addressable)\n", 697 res1, (unsigned long long)end + 1, 698 (unsigned long long)res1->end); 699 res1->end = end; 700 } 701 702 resource_list_for_each_entry(entry2, resources) { 703 res2 = entry2->res; 704 if (!(res2->flags & type)) 705 continue; 706 707 /* 708 * I don't like throwing away windows because then 709 * our resources no longer match the ACPI _CRS, but 710 * the kernel resource tree doesn't allow overlaps. 711 */ 712 if (resource_union(res1, res2, res2)) { 713 dev_info(dev, "host bridge window expanded to %pR; %pR ignored\n", 714 res2, res1); 715 free = true; 716 goto next; 717 } 718 } 719 720 next: 721 resource_list_del(entry); 722 if (free) 723 resource_list_free_entry(entry); 724 else 725 resource_list_add_tail(entry, resources); 726 } 727 } 728 729 static void acpi_pci_root_remap_iospace(struct fwnode_handle *fwnode, 730 struct resource_entry *entry) 731 { 732 #ifdef PCI_IOBASE 733 struct resource *res = entry->res; 734 resource_size_t cpu_addr = res->start; 735 resource_size_t pci_addr = cpu_addr - entry->offset; 736 resource_size_t length = resource_size(res); 737 unsigned long port; 738 739 if (pci_register_io_range(fwnode, cpu_addr, length)) 740 goto err; 741 742 port = pci_address_to_pio(cpu_addr); 743 if (port == (unsigned long)-1) 744 goto err; 745 746 res->start = port; 747 res->end = port + length - 1; 748 entry->offset = port - pci_addr; 749 750 if (pci_remap_iospace(res, cpu_addr) < 0) 751 goto err; 752 753 pr_info("Remapped I/O %pa to %pR\n", &cpu_addr, res); 754 return; 755 err: 756 res->flags |= IORESOURCE_DISABLED; 757 #endif 758 } 759 760 int acpi_pci_probe_root_resources(struct acpi_pci_root_info *info) 761 { 762 int ret; 763 struct list_head *list = &info->resources; 764 struct acpi_device *device = info->bridge; 765 struct resource_entry *entry, *tmp; 766 unsigned long flags; 767 768 flags = IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT; 769 ret = acpi_dev_get_resources(device, list, 770 acpi_dev_filter_resource_type_cb, 771 (void *)flags); 772 if (ret < 0) 773 dev_warn(&device->dev, 774 "failed to parse _CRS method, error code %d\n", ret); 775 else if (ret == 0) 776 dev_dbg(&device->dev, 777 "no IO and memory resources present in _CRS\n"); 778 else { 779 resource_list_for_each_entry_safe(entry, tmp, list) { 780 if (entry->res->flags & IORESOURCE_IO) 781 acpi_pci_root_remap_iospace(&device->fwnode, 782 entry); 783 784 if (entry->res->flags & IORESOURCE_DISABLED) 785 resource_list_destroy_entry(entry); 786 else 787 entry->res->name = info->name; 788 } 789 acpi_pci_root_validate_resources(&device->dev, list, 790 IORESOURCE_MEM); 791 acpi_pci_root_validate_resources(&device->dev, list, 792 IORESOURCE_IO); 793 } 794 795 return ret; 796 } 797 798 static void pci_acpi_root_add_resources(struct acpi_pci_root_info *info) 799 { 800 struct resource_entry *entry, *tmp; 801 struct resource *res, *conflict, *root = NULL; 802 803 resource_list_for_each_entry_safe(entry, tmp, &info->resources) { 804 res = entry->res; 805 if (res->flags & IORESOURCE_MEM) 806 root = &iomem_resource; 807 else if (res->flags & IORESOURCE_IO) 808 root = &ioport_resource; 809 else 810 continue; 811 812 /* 813 * Some legacy x86 host bridge drivers use iomem_resource and 814 * ioport_resource as default resource pool, skip it. 815 */ 816 if (res == root) 817 continue; 818 819 conflict = insert_resource_conflict(root, res); 820 if (conflict) { 821 dev_info(&info->bridge->dev, 822 "ignoring host bridge window %pR (conflicts with %s %pR)\n", 823 res, conflict->name, conflict); 824 resource_list_destroy_entry(entry); 825 } 826 } 827 } 828 829 static void __acpi_pci_root_release_info(struct acpi_pci_root_info *info) 830 { 831 struct resource *res; 832 struct resource_entry *entry, *tmp; 833 834 if (!info) 835 return; 836 837 resource_list_for_each_entry_safe(entry, tmp, &info->resources) { 838 res = entry->res; 839 if (res->parent && 840 (res->flags & (IORESOURCE_MEM | IORESOURCE_IO))) 841 release_resource(res); 842 resource_list_destroy_entry(entry); 843 } 844 845 info->ops->release_info(info); 846 } 847 848 static void acpi_pci_root_release_info(struct pci_host_bridge *bridge) 849 { 850 struct resource *res; 851 struct resource_entry *entry; 852 853 resource_list_for_each_entry(entry, &bridge->windows) { 854 res = entry->res; 855 if (res->flags & IORESOURCE_IO) 856 pci_unmap_iospace(res); 857 if (res->parent && 858 (res->flags & (IORESOURCE_MEM | IORESOURCE_IO))) 859 release_resource(res); 860 } 861 __acpi_pci_root_release_info(bridge->release_data); 862 } 863 864 struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root, 865 struct acpi_pci_root_ops *ops, 866 struct acpi_pci_root_info *info, 867 void *sysdata) 868 { 869 int ret, busnum = root->secondary.start; 870 struct acpi_device *device = root->device; 871 int node = acpi_get_node(device->handle); 872 struct pci_bus *bus; 873 struct pci_host_bridge *host_bridge; 874 union acpi_object *obj; 875 876 info->root = root; 877 info->bridge = device; 878 info->ops = ops; 879 INIT_LIST_HEAD(&info->resources); 880 snprintf(info->name, sizeof(info->name), "PCI Bus %04x:%02x", 881 root->segment, busnum); 882 883 if (ops->init_info && ops->init_info(info)) 884 goto out_release_info; 885 if (ops->prepare_resources) 886 ret = ops->prepare_resources(info); 887 else 888 ret = acpi_pci_probe_root_resources(info); 889 if (ret < 0) 890 goto out_release_info; 891 892 pci_acpi_root_add_resources(info); 893 pci_add_resource(&info->resources, &root->secondary); 894 bus = pci_create_root_bus(NULL, busnum, ops->pci_ops, 895 sysdata, &info->resources); 896 if (!bus) 897 goto out_release_info; 898 899 host_bridge = to_pci_host_bridge(bus->bridge); 900 if (!(root->osc_control_set & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL)) 901 host_bridge->native_pcie_hotplug = 0; 902 if (!(root->osc_control_set & OSC_PCI_SHPC_NATIVE_HP_CONTROL)) 903 host_bridge->native_shpc_hotplug = 0; 904 if (!(root->osc_control_set & OSC_PCI_EXPRESS_AER_CONTROL)) 905 host_bridge->native_aer = 0; 906 if (!(root->osc_control_set & OSC_PCI_EXPRESS_PME_CONTROL)) 907 host_bridge->native_pme = 0; 908 if (!(root->osc_control_set & OSC_PCI_EXPRESS_LTR_CONTROL)) 909 host_bridge->native_ltr = 0; 910 if (!(root->osc_control_set & OSC_PCI_EXPRESS_DPC_CONTROL)) 911 host_bridge->native_dpc = 0; 912 913 /* 914 * Evaluate the "PCI Boot Configuration" _DSM Function. If it 915 * exists and returns 0, we must preserve any PCI resource 916 * assignments made by firmware for this host bridge. 917 */ 918 obj = acpi_evaluate_dsm(ACPI_HANDLE(bus->bridge), &pci_acpi_dsm_guid, 1, 919 DSM_PCI_PRESERVE_BOOT_CONFIG, NULL); 920 if (obj && obj->type == ACPI_TYPE_INTEGER && obj->integer.value == 0) 921 host_bridge->preserve_config = 1; 922 ACPI_FREE(obj); 923 924 pci_scan_child_bus(bus); 925 pci_set_host_bridge_release(host_bridge, acpi_pci_root_release_info, 926 info); 927 if (node != NUMA_NO_NODE) 928 dev_printk(KERN_DEBUG, &bus->dev, "on NUMA node %d\n", node); 929 return bus; 930 931 out_release_info: 932 __acpi_pci_root_release_info(info); 933 return NULL; 934 } 935 936 void __init acpi_pci_root_init(void) 937 { 938 acpi_hest_init(); 939 if (acpi_pci_disabled) 940 return; 941 942 pci_acpi_crs_quirks(); 943 acpi_scan_add_handler_with_hotplug(&pci_root_handler, "pci_root"); 944 } 945