1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * pci_root.c - ACPI PCI Root Bridge Driver ($Revision: 40 $) 4 * 5 * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> 6 * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> 7 */ 8 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/init.h> 12 #include <linux/types.h> 13 #include <linux/mutex.h> 14 #include <linux/pm.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/pci.h> 17 #include <linux/pci-acpi.h> 18 #include <linux/dmar.h> 19 #include <linux/acpi.h> 20 #include <linux/slab.h> 21 #include <linux/dmi.h> 22 #include <linux/platform_data/x86/apple.h> 23 #include <acpi/apei.h> /* for acpi_hest_init() */ 24 25 #include "internal.h" 26 27 #define _COMPONENT ACPI_PCI_COMPONENT 28 ACPI_MODULE_NAME("pci_root"); 29 #define ACPI_PCI_ROOT_CLASS "pci_bridge" 30 #define ACPI_PCI_ROOT_DEVICE_NAME "PCI Root Bridge" 31 static int acpi_pci_root_add(struct acpi_device *device, 32 const struct acpi_device_id *not_used); 33 static void acpi_pci_root_remove(struct acpi_device *device); 34 35 static int acpi_pci_root_scan_dependent(struct acpi_device *adev) 36 { 37 acpiphp_check_host_bridge(adev); 38 return 0; 39 } 40 41 #define ACPI_PCIE_REQ_SUPPORT (OSC_PCI_EXT_CONFIG_SUPPORT \ 42 | OSC_PCI_ASPM_SUPPORT \ 43 | OSC_PCI_CLOCK_PM_SUPPORT \ 44 | OSC_PCI_MSI_SUPPORT) 45 46 static const struct acpi_device_id root_device_ids[] = { 47 {"PNP0A03", 0}, 48 {"", 0}, 49 }; 50 51 static struct acpi_scan_handler pci_root_handler = { 52 .ids = root_device_ids, 53 .attach = acpi_pci_root_add, 54 .detach = acpi_pci_root_remove, 55 .hotplug = { 56 .enabled = true, 57 .scan_dependent = acpi_pci_root_scan_dependent, 58 }, 59 }; 60 61 static DEFINE_MUTEX(osc_lock); 62 63 /** 64 * acpi_is_root_bridge - determine whether an ACPI CA node is a PCI root bridge 65 * @handle - the ACPI CA node in question. 66 * 67 * Note: we could make this API take a struct acpi_device * instead, but 68 * for now, it's more convenient to operate on an acpi_handle. 69 */ 70 int acpi_is_root_bridge(acpi_handle handle) 71 { 72 int ret; 73 struct acpi_device *device; 74 75 ret = acpi_bus_get_device(handle, &device); 76 if (ret) 77 return 0; 78 79 ret = acpi_match_device_ids(device, root_device_ids); 80 if (ret) 81 return 0; 82 else 83 return 1; 84 } 85 EXPORT_SYMBOL_GPL(acpi_is_root_bridge); 86 87 static acpi_status 88 get_root_bridge_busnr_callback(struct acpi_resource *resource, void *data) 89 { 90 struct resource *res = data; 91 struct acpi_resource_address64 address; 92 acpi_status status; 93 94 status = acpi_resource_to_address64(resource, &address); 95 if (ACPI_FAILURE(status)) 96 return AE_OK; 97 98 if ((address.address.address_length > 0) && 99 (address.resource_type == ACPI_BUS_NUMBER_RANGE)) { 100 res->start = address.address.minimum; 101 res->end = address.address.minimum + address.address.address_length - 1; 102 } 103 104 return AE_OK; 105 } 106 107 static acpi_status try_get_root_bridge_busnr(acpi_handle handle, 108 struct resource *res) 109 { 110 acpi_status status; 111 112 res->start = -1; 113 status = 114 acpi_walk_resources(handle, METHOD_NAME__CRS, 115 get_root_bridge_busnr_callback, res); 116 if (ACPI_FAILURE(status)) 117 return status; 118 if (res->start == -1) 119 return AE_ERROR; 120 return AE_OK; 121 } 122 123 struct pci_osc_bit_struct { 124 u32 bit; 125 char *desc; 126 }; 127 128 static struct pci_osc_bit_struct pci_osc_support_bit[] = { 129 { OSC_PCI_EXT_CONFIG_SUPPORT, "ExtendedConfig" }, 130 { OSC_PCI_ASPM_SUPPORT, "ASPM" }, 131 { OSC_PCI_CLOCK_PM_SUPPORT, "ClockPM" }, 132 { OSC_PCI_SEGMENT_GROUPS_SUPPORT, "Segments" }, 133 { OSC_PCI_MSI_SUPPORT, "MSI" }, 134 { OSC_PCI_EDR_SUPPORT, "EDR" }, 135 { OSC_PCI_HPX_TYPE_3_SUPPORT, "HPX-Type3" }, 136 }; 137 138 static struct pci_osc_bit_struct pci_osc_control_bit[] = { 139 { OSC_PCI_EXPRESS_NATIVE_HP_CONTROL, "PCIeHotplug" }, 140 { OSC_PCI_SHPC_NATIVE_HP_CONTROL, "SHPCHotplug" }, 141 { OSC_PCI_EXPRESS_PME_CONTROL, "PME" }, 142 { OSC_PCI_EXPRESS_AER_CONTROL, "AER" }, 143 { OSC_PCI_EXPRESS_CAPABILITY_CONTROL, "PCIeCapability" }, 144 { OSC_PCI_EXPRESS_LTR_CONTROL, "LTR" }, 145 { OSC_PCI_EXPRESS_DPC_CONTROL, "DPC" }, 146 }; 147 148 static void decode_osc_bits(struct acpi_pci_root *root, char *msg, u32 word, 149 struct pci_osc_bit_struct *table, int size) 150 { 151 char buf[80]; 152 int i, len = 0; 153 struct pci_osc_bit_struct *entry; 154 155 buf[0] = '\0'; 156 for (i = 0, entry = table; i < size; i++, entry++) 157 if (word & entry->bit) 158 len += scnprintf(buf + len, sizeof(buf) - len, "%s%s", 159 len ? " " : "", entry->desc); 160 161 dev_info(&root->device->dev, "_OSC: %s [%s]\n", msg, buf); 162 } 163 164 static void decode_osc_support(struct acpi_pci_root *root, char *msg, u32 word) 165 { 166 decode_osc_bits(root, msg, word, pci_osc_support_bit, 167 ARRAY_SIZE(pci_osc_support_bit)); 168 } 169 170 static void decode_osc_control(struct acpi_pci_root *root, char *msg, u32 word) 171 { 172 decode_osc_bits(root, msg, word, pci_osc_control_bit, 173 ARRAY_SIZE(pci_osc_control_bit)); 174 } 175 176 static u8 pci_osc_uuid_str[] = "33DB4D5B-1FF7-401C-9657-7441C03DD766"; 177 178 static acpi_status acpi_pci_run_osc(acpi_handle handle, 179 const u32 *capbuf, u32 *retval) 180 { 181 struct acpi_osc_context context = { 182 .uuid_str = pci_osc_uuid_str, 183 .rev = 1, 184 .cap.length = 12, 185 .cap.pointer = (void *)capbuf, 186 }; 187 acpi_status status; 188 189 status = acpi_run_osc(handle, &context); 190 if (ACPI_SUCCESS(status)) { 191 *retval = *((u32 *)(context.ret.pointer + 8)); 192 kfree(context.ret.pointer); 193 } 194 return status; 195 } 196 197 static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root, 198 u32 support, 199 u32 *control) 200 { 201 acpi_status status; 202 u32 result, capbuf[3]; 203 204 support &= OSC_PCI_SUPPORT_MASKS; 205 support |= root->osc_support_set; 206 207 capbuf[OSC_QUERY_DWORD] = OSC_QUERY_ENABLE; 208 capbuf[OSC_SUPPORT_DWORD] = support; 209 if (control) { 210 *control &= OSC_PCI_CONTROL_MASKS; 211 capbuf[OSC_CONTROL_DWORD] = *control | root->osc_control_set; 212 } else { 213 /* Run _OSC query only with existing controls. */ 214 capbuf[OSC_CONTROL_DWORD] = root->osc_control_set; 215 } 216 217 status = acpi_pci_run_osc(root->device->handle, capbuf, &result); 218 if (ACPI_SUCCESS(status)) { 219 root->osc_support_set = support; 220 if (control) 221 *control = result; 222 } 223 return status; 224 } 225 226 static acpi_status acpi_pci_osc_support(struct acpi_pci_root *root, u32 flags) 227 { 228 acpi_status status; 229 230 mutex_lock(&osc_lock); 231 status = acpi_pci_query_osc(root, flags, NULL); 232 mutex_unlock(&osc_lock); 233 return status; 234 } 235 236 struct acpi_pci_root *acpi_pci_find_root(acpi_handle handle) 237 { 238 struct acpi_pci_root *root; 239 struct acpi_device *device; 240 241 if (acpi_bus_get_device(handle, &device) || 242 acpi_match_device_ids(device, root_device_ids)) 243 return NULL; 244 245 root = acpi_driver_data(device); 246 247 return root; 248 } 249 EXPORT_SYMBOL_GPL(acpi_pci_find_root); 250 251 struct acpi_handle_node { 252 struct list_head node; 253 acpi_handle handle; 254 }; 255 256 /** 257 * acpi_get_pci_dev - convert ACPI CA handle to struct pci_dev 258 * @handle: the handle in question 259 * 260 * Given an ACPI CA handle, the desired PCI device is located in the 261 * list of PCI devices. 262 * 263 * If the device is found, its reference count is increased and this 264 * function returns a pointer to its data structure. The caller must 265 * decrement the reference count by calling pci_dev_put(). 266 * If no device is found, %NULL is returned. 267 */ 268 struct pci_dev *acpi_get_pci_dev(acpi_handle handle) 269 { 270 int dev, fn; 271 unsigned long long adr; 272 acpi_status status; 273 acpi_handle phandle; 274 struct pci_bus *pbus; 275 struct pci_dev *pdev = NULL; 276 struct acpi_handle_node *node, *tmp; 277 struct acpi_pci_root *root; 278 LIST_HEAD(device_list); 279 280 /* 281 * Walk up the ACPI CA namespace until we reach a PCI root bridge. 282 */ 283 phandle = handle; 284 while (!acpi_is_root_bridge(phandle)) { 285 node = kzalloc(sizeof(struct acpi_handle_node), GFP_KERNEL); 286 if (!node) 287 goto out; 288 289 INIT_LIST_HEAD(&node->node); 290 node->handle = phandle; 291 list_add(&node->node, &device_list); 292 293 status = acpi_get_parent(phandle, &phandle); 294 if (ACPI_FAILURE(status)) 295 goto out; 296 } 297 298 root = acpi_pci_find_root(phandle); 299 if (!root) 300 goto out; 301 302 pbus = root->bus; 303 304 /* 305 * Now, walk back down the PCI device tree until we return to our 306 * original handle. Assumes that everything between the PCI root 307 * bridge and the device we're looking for must be a P2P bridge. 308 */ 309 list_for_each_entry(node, &device_list, node) { 310 acpi_handle hnd = node->handle; 311 status = acpi_evaluate_integer(hnd, "_ADR", NULL, &adr); 312 if (ACPI_FAILURE(status)) 313 goto out; 314 dev = (adr >> 16) & 0xffff; 315 fn = adr & 0xffff; 316 317 pdev = pci_get_slot(pbus, PCI_DEVFN(dev, fn)); 318 if (!pdev || hnd == handle) 319 break; 320 321 pbus = pdev->subordinate; 322 pci_dev_put(pdev); 323 324 /* 325 * This function may be called for a non-PCI device that has a 326 * PCI parent (eg. a disk under a PCI SATA controller). In that 327 * case pdev->subordinate will be NULL for the parent. 328 */ 329 if (!pbus) { 330 dev_dbg(&pdev->dev, "Not a PCI-to-PCI bridge\n"); 331 pdev = NULL; 332 break; 333 } 334 } 335 out: 336 list_for_each_entry_safe(node, tmp, &device_list, node) 337 kfree(node); 338 339 return pdev; 340 } 341 EXPORT_SYMBOL_GPL(acpi_get_pci_dev); 342 343 /** 344 * acpi_pci_osc_control_set - Request control of PCI root _OSC features. 345 * @handle: ACPI handle of a PCI root bridge (or PCIe Root Complex). 346 * @mask: Mask of _OSC bits to request control of, place to store control mask. 347 * @req: Mask of _OSC bits the control of is essential to the caller. 348 * 349 * Run _OSC query for @mask and if that is successful, compare the returned 350 * mask of control bits with @req. If all of the @req bits are set in the 351 * returned mask, run _OSC request for it. 352 * 353 * The variable at the @mask address may be modified regardless of whether or 354 * not the function returns success. On success it will contain the mask of 355 * _OSC bits the BIOS has granted control of, but its contents are meaningless 356 * on failure. 357 **/ 358 acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 req) 359 { 360 struct acpi_pci_root *root; 361 acpi_status status = AE_OK; 362 u32 ctrl, capbuf[3]; 363 364 if (!mask) 365 return AE_BAD_PARAMETER; 366 367 ctrl = *mask & OSC_PCI_CONTROL_MASKS; 368 if ((ctrl & req) != req) 369 return AE_TYPE; 370 371 root = acpi_pci_find_root(handle); 372 if (!root) 373 return AE_NOT_EXIST; 374 375 mutex_lock(&osc_lock); 376 377 *mask = ctrl | root->osc_control_set; 378 /* No need to evaluate _OSC if the control was already granted. */ 379 if ((root->osc_control_set & ctrl) == ctrl) 380 goto out; 381 382 /* Need to check the available controls bits before requesting them. */ 383 while (*mask) { 384 status = acpi_pci_query_osc(root, root->osc_support_set, mask); 385 if (ACPI_FAILURE(status)) 386 goto out; 387 if (ctrl == *mask) 388 break; 389 decode_osc_control(root, "platform does not support", 390 ctrl & ~(*mask)); 391 ctrl = *mask; 392 } 393 394 if ((ctrl & req) != req) { 395 decode_osc_control(root, "not requesting control; platform does not support", 396 req & ~(ctrl)); 397 status = AE_SUPPORT; 398 goto out; 399 } 400 401 capbuf[OSC_QUERY_DWORD] = 0; 402 capbuf[OSC_SUPPORT_DWORD] = root->osc_support_set; 403 capbuf[OSC_CONTROL_DWORD] = ctrl; 404 status = acpi_pci_run_osc(handle, capbuf, mask); 405 if (ACPI_SUCCESS(status)) 406 root->osc_control_set = *mask; 407 out: 408 mutex_unlock(&osc_lock); 409 return status; 410 } 411 EXPORT_SYMBOL(acpi_pci_osc_control_set); 412 413 static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm, 414 bool is_pcie) 415 { 416 u32 support, control, requested; 417 acpi_status status; 418 struct acpi_device *device = root->device; 419 acpi_handle handle = device->handle; 420 421 /* 422 * Apple always return failure on _OSC calls when _OSI("Darwin") has 423 * been called successfully. We know the feature set supported by the 424 * platform, so avoid calling _OSC at all 425 */ 426 if (x86_apple_machine) { 427 root->osc_control_set = ~OSC_PCI_EXPRESS_PME_CONTROL; 428 decode_osc_control(root, "OS assumes control of", 429 root->osc_control_set); 430 return; 431 } 432 433 /* 434 * All supported architectures that use ACPI have support for 435 * PCI domains, so we indicate this in _OSC support capabilities. 436 */ 437 support = OSC_PCI_SEGMENT_GROUPS_SUPPORT; 438 support |= OSC_PCI_HPX_TYPE_3_SUPPORT; 439 if (pci_ext_cfg_avail()) 440 support |= OSC_PCI_EXT_CONFIG_SUPPORT; 441 if (pcie_aspm_support_enabled()) 442 support |= OSC_PCI_ASPM_SUPPORT | OSC_PCI_CLOCK_PM_SUPPORT; 443 if (pci_msi_enabled()) 444 support |= OSC_PCI_MSI_SUPPORT; 445 if (IS_ENABLED(CONFIG_PCIE_EDR)) 446 support |= OSC_PCI_EDR_SUPPORT; 447 448 decode_osc_support(root, "OS supports", support); 449 status = acpi_pci_osc_support(root, support); 450 if (ACPI_FAILURE(status)) { 451 *no_aspm = 1; 452 453 /* _OSC is optional for PCI host bridges */ 454 if ((status == AE_NOT_FOUND) && !is_pcie) 455 return; 456 457 dev_info(&device->dev, "_OSC failed (%s)%s\n", 458 acpi_format_exception(status), 459 pcie_aspm_support_enabled() ? "; disabling ASPM" : ""); 460 return; 461 } 462 463 if (pcie_ports_disabled) { 464 dev_info(&device->dev, "PCIe port services disabled; not requesting _OSC control\n"); 465 return; 466 } 467 468 if ((support & ACPI_PCIE_REQ_SUPPORT) != ACPI_PCIE_REQ_SUPPORT) { 469 decode_osc_support(root, "not requesting OS control; OS requires", 470 ACPI_PCIE_REQ_SUPPORT); 471 return; 472 } 473 474 control = OSC_PCI_EXPRESS_CAPABILITY_CONTROL 475 | OSC_PCI_EXPRESS_PME_CONTROL; 476 477 if (IS_ENABLED(CONFIG_PCIEASPM)) 478 control |= OSC_PCI_EXPRESS_LTR_CONTROL; 479 480 if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE)) 481 control |= OSC_PCI_EXPRESS_NATIVE_HP_CONTROL; 482 483 if (IS_ENABLED(CONFIG_HOTPLUG_PCI_SHPC)) 484 control |= OSC_PCI_SHPC_NATIVE_HP_CONTROL; 485 486 if (pci_aer_available()) { 487 if (aer_acpi_firmware_first()) 488 dev_info(&device->dev, 489 "PCIe AER handled by firmware\n"); 490 else 491 control |= OSC_PCI_EXPRESS_AER_CONTROL; 492 } 493 494 /* 495 * Per the Downstream Port Containment Related Enhancements ECN to 496 * the PCI Firmware Spec, r3.2, sec 4.5.1, table 4-5, 497 * OSC_PCI_EXPRESS_DPC_CONTROL indicates the OS supports both DPC 498 * and EDR. 499 */ 500 if (IS_ENABLED(CONFIG_PCIE_DPC) && IS_ENABLED(CONFIG_PCIE_EDR)) 501 control |= OSC_PCI_EXPRESS_DPC_CONTROL; 502 503 requested = control; 504 status = acpi_pci_osc_control_set(handle, &control, 505 OSC_PCI_EXPRESS_CAPABILITY_CONTROL); 506 if (ACPI_SUCCESS(status)) { 507 decode_osc_control(root, "OS now controls", control); 508 if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) { 509 /* 510 * We have ASPM control, but the FADT indicates that 511 * it's unsupported. Leave existing configuration 512 * intact and prevent the OS from touching it. 513 */ 514 dev_info(&device->dev, "FADT indicates ASPM is unsupported, using BIOS configuration\n"); 515 *no_aspm = 1; 516 } 517 } else { 518 decode_osc_control(root, "OS requested", requested); 519 decode_osc_control(root, "platform willing to grant", control); 520 dev_info(&device->dev, "_OSC failed (%s); disabling ASPM\n", 521 acpi_format_exception(status)); 522 523 /* 524 * We want to disable ASPM here, but aspm_disabled 525 * needs to remain in its state from boot so that we 526 * properly handle PCIe 1.1 devices. So we set this 527 * flag here, to defer the action until after the ACPI 528 * root scan. 529 */ 530 *no_aspm = 1; 531 } 532 } 533 534 static int acpi_pci_root_add(struct acpi_device *device, 535 const struct acpi_device_id *not_used) 536 { 537 unsigned long long segment, bus; 538 acpi_status status; 539 int result; 540 struct acpi_pci_root *root; 541 acpi_handle handle = device->handle; 542 int no_aspm = 0; 543 bool hotadd = system_state == SYSTEM_RUNNING; 544 bool is_pcie; 545 546 root = kzalloc(sizeof(struct acpi_pci_root), GFP_KERNEL); 547 if (!root) 548 return -ENOMEM; 549 550 segment = 0; 551 status = acpi_evaluate_integer(handle, METHOD_NAME__SEG, NULL, 552 &segment); 553 if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) { 554 dev_err(&device->dev, "can't evaluate _SEG\n"); 555 result = -ENODEV; 556 goto end; 557 } 558 559 /* Check _CRS first, then _BBN. If no _BBN, default to zero. */ 560 root->secondary.flags = IORESOURCE_BUS; 561 status = try_get_root_bridge_busnr(handle, &root->secondary); 562 if (ACPI_FAILURE(status)) { 563 /* 564 * We need both the start and end of the downstream bus range 565 * to interpret _CBA (MMCONFIG base address), so it really is 566 * supposed to be in _CRS. If we don't find it there, all we 567 * can do is assume [_BBN-0xFF] or [0-0xFF]. 568 */ 569 root->secondary.end = 0xFF; 570 dev_warn(&device->dev, 571 FW_BUG "no secondary bus range in _CRS\n"); 572 status = acpi_evaluate_integer(handle, METHOD_NAME__BBN, 573 NULL, &bus); 574 if (ACPI_SUCCESS(status)) 575 root->secondary.start = bus; 576 else if (status == AE_NOT_FOUND) 577 root->secondary.start = 0; 578 else { 579 dev_err(&device->dev, "can't evaluate _BBN\n"); 580 result = -ENODEV; 581 goto end; 582 } 583 } 584 585 root->device = device; 586 root->segment = segment & 0xFFFF; 587 strcpy(acpi_device_name(device), ACPI_PCI_ROOT_DEVICE_NAME); 588 strcpy(acpi_device_class(device), ACPI_PCI_ROOT_CLASS); 589 device->driver_data = root; 590 591 if (hotadd && dmar_device_add(handle)) { 592 result = -ENXIO; 593 goto end; 594 } 595 596 pr_info(PREFIX "%s [%s] (domain %04x %pR)\n", 597 acpi_device_name(device), acpi_device_bid(device), 598 root->segment, &root->secondary); 599 600 root->mcfg_addr = acpi_pci_root_get_mcfg_addr(handle); 601 602 is_pcie = strcmp(acpi_device_hid(device), "PNP0A08") == 0; 603 negotiate_os_control(root, &no_aspm, is_pcie); 604 605 /* 606 * TBD: Need PCI interface for enumeration/configuration of roots. 607 */ 608 609 /* 610 * Scan the Root Bridge 611 * -------------------- 612 * Must do this prior to any attempt to bind the root device, as the 613 * PCI namespace does not get created until this call is made (and 614 * thus the root bridge's pci_dev does not exist). 615 */ 616 root->bus = pci_acpi_scan_root(root); 617 if (!root->bus) { 618 dev_err(&device->dev, 619 "Bus %04x:%02x not present in PCI namespace\n", 620 root->segment, (unsigned int)root->secondary.start); 621 device->driver_data = NULL; 622 result = -ENODEV; 623 goto remove_dmar; 624 } 625 626 if (no_aspm) 627 pcie_no_aspm(); 628 629 pci_acpi_add_bus_pm_notifier(device); 630 device_set_wakeup_capable(root->bus->bridge, device->wakeup.flags.valid); 631 632 if (hotadd) { 633 pcibios_resource_survey_bus(root->bus); 634 pci_assign_unassigned_root_bus_resources(root->bus); 635 /* 636 * This is only called for the hotadd case. For the boot-time 637 * case, we need to wait until after PCI initialization in 638 * order to deal with IOAPICs mapped in on a PCI BAR. 639 * 640 * This is currently x86-specific, because acpi_ioapic_add() 641 * is an empty function without CONFIG_ACPI_HOTPLUG_IOAPIC. 642 * And CONFIG_ACPI_HOTPLUG_IOAPIC depends on CONFIG_X86_IO_APIC 643 * (see drivers/acpi/Kconfig). 644 */ 645 acpi_ioapic_add(root->device->handle); 646 } 647 648 pci_lock_rescan_remove(); 649 pci_bus_add_devices(root->bus); 650 pci_unlock_rescan_remove(); 651 return 1; 652 653 remove_dmar: 654 if (hotadd) 655 dmar_device_remove(handle); 656 end: 657 kfree(root); 658 return result; 659 } 660 661 static void acpi_pci_root_remove(struct acpi_device *device) 662 { 663 struct acpi_pci_root *root = acpi_driver_data(device); 664 665 pci_lock_rescan_remove(); 666 667 pci_stop_root_bus(root->bus); 668 669 pci_ioapic_remove(root); 670 device_set_wakeup_capable(root->bus->bridge, false); 671 pci_acpi_remove_bus_pm_notifier(device); 672 673 pci_remove_root_bus(root->bus); 674 WARN_ON(acpi_ioapic_remove(root)); 675 676 dmar_device_remove(device->handle); 677 678 pci_unlock_rescan_remove(); 679 680 kfree(root); 681 } 682 683 /* 684 * Following code to support acpi_pci_root_create() is copied from 685 * arch/x86/pci/acpi.c and modified so it could be reused by x86, IA64 686 * and ARM64. 687 */ 688 static void acpi_pci_root_validate_resources(struct device *dev, 689 struct list_head *resources, 690 unsigned long type) 691 { 692 LIST_HEAD(list); 693 struct resource *res1, *res2, *root = NULL; 694 struct resource_entry *tmp, *entry, *entry2; 695 696 BUG_ON((type & (IORESOURCE_MEM | IORESOURCE_IO)) == 0); 697 root = (type & IORESOURCE_MEM) ? &iomem_resource : &ioport_resource; 698 699 list_splice_init(resources, &list); 700 resource_list_for_each_entry_safe(entry, tmp, &list) { 701 bool free = false; 702 resource_size_t end; 703 704 res1 = entry->res; 705 if (!(res1->flags & type)) 706 goto next; 707 708 /* Exclude non-addressable range or non-addressable portion */ 709 end = min(res1->end, root->end); 710 if (end <= res1->start) { 711 dev_info(dev, "host bridge window %pR (ignored, not CPU addressable)\n", 712 res1); 713 free = true; 714 goto next; 715 } else if (res1->end != end) { 716 dev_info(dev, "host bridge window %pR ([%#llx-%#llx] ignored, not CPU addressable)\n", 717 res1, (unsigned long long)end + 1, 718 (unsigned long long)res1->end); 719 res1->end = end; 720 } 721 722 resource_list_for_each_entry(entry2, resources) { 723 res2 = entry2->res; 724 if (!(res2->flags & type)) 725 continue; 726 727 /* 728 * I don't like throwing away windows because then 729 * our resources no longer match the ACPI _CRS, but 730 * the kernel resource tree doesn't allow overlaps. 731 */ 732 if (resource_overlaps(res1, res2)) { 733 res2->start = min(res1->start, res2->start); 734 res2->end = max(res1->end, res2->end); 735 dev_info(dev, "host bridge window expanded to %pR; %pR ignored\n", 736 res2, res1); 737 free = true; 738 goto next; 739 } 740 } 741 742 next: 743 resource_list_del(entry); 744 if (free) 745 resource_list_free_entry(entry); 746 else 747 resource_list_add_tail(entry, resources); 748 } 749 } 750 751 static void acpi_pci_root_remap_iospace(struct fwnode_handle *fwnode, 752 struct resource_entry *entry) 753 { 754 #ifdef PCI_IOBASE 755 struct resource *res = entry->res; 756 resource_size_t cpu_addr = res->start; 757 resource_size_t pci_addr = cpu_addr - entry->offset; 758 resource_size_t length = resource_size(res); 759 unsigned long port; 760 761 if (pci_register_io_range(fwnode, cpu_addr, length)) 762 goto err; 763 764 port = pci_address_to_pio(cpu_addr); 765 if (port == (unsigned long)-1) 766 goto err; 767 768 res->start = port; 769 res->end = port + length - 1; 770 entry->offset = port - pci_addr; 771 772 if (pci_remap_iospace(res, cpu_addr) < 0) 773 goto err; 774 775 pr_info("Remapped I/O %pa to %pR\n", &cpu_addr, res); 776 return; 777 err: 778 res->flags |= IORESOURCE_DISABLED; 779 #endif 780 } 781 782 int acpi_pci_probe_root_resources(struct acpi_pci_root_info *info) 783 { 784 int ret; 785 struct list_head *list = &info->resources; 786 struct acpi_device *device = info->bridge; 787 struct resource_entry *entry, *tmp; 788 unsigned long flags; 789 790 flags = IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT; 791 ret = acpi_dev_get_resources(device, list, 792 acpi_dev_filter_resource_type_cb, 793 (void *)flags); 794 if (ret < 0) 795 dev_warn(&device->dev, 796 "failed to parse _CRS method, error code %d\n", ret); 797 else if (ret == 0) 798 dev_dbg(&device->dev, 799 "no IO and memory resources present in _CRS\n"); 800 else { 801 resource_list_for_each_entry_safe(entry, tmp, list) { 802 if (entry->res->flags & IORESOURCE_IO) 803 acpi_pci_root_remap_iospace(&device->fwnode, 804 entry); 805 806 if (entry->res->flags & IORESOURCE_DISABLED) 807 resource_list_destroy_entry(entry); 808 else 809 entry->res->name = info->name; 810 } 811 acpi_pci_root_validate_resources(&device->dev, list, 812 IORESOURCE_MEM); 813 acpi_pci_root_validate_resources(&device->dev, list, 814 IORESOURCE_IO); 815 } 816 817 return ret; 818 } 819 820 static void pci_acpi_root_add_resources(struct acpi_pci_root_info *info) 821 { 822 struct resource_entry *entry, *tmp; 823 struct resource *res, *conflict, *root = NULL; 824 825 resource_list_for_each_entry_safe(entry, tmp, &info->resources) { 826 res = entry->res; 827 if (res->flags & IORESOURCE_MEM) 828 root = &iomem_resource; 829 else if (res->flags & IORESOURCE_IO) 830 root = &ioport_resource; 831 else 832 continue; 833 834 /* 835 * Some legacy x86 host bridge drivers use iomem_resource and 836 * ioport_resource as default resource pool, skip it. 837 */ 838 if (res == root) 839 continue; 840 841 conflict = insert_resource_conflict(root, res); 842 if (conflict) { 843 dev_info(&info->bridge->dev, 844 "ignoring host bridge window %pR (conflicts with %s %pR)\n", 845 res, conflict->name, conflict); 846 resource_list_destroy_entry(entry); 847 } 848 } 849 } 850 851 static void __acpi_pci_root_release_info(struct acpi_pci_root_info *info) 852 { 853 struct resource *res; 854 struct resource_entry *entry, *tmp; 855 856 if (!info) 857 return; 858 859 resource_list_for_each_entry_safe(entry, tmp, &info->resources) { 860 res = entry->res; 861 if (res->parent && 862 (res->flags & (IORESOURCE_MEM | IORESOURCE_IO))) 863 release_resource(res); 864 resource_list_destroy_entry(entry); 865 } 866 867 info->ops->release_info(info); 868 } 869 870 static void acpi_pci_root_release_info(struct pci_host_bridge *bridge) 871 { 872 struct resource *res; 873 struct resource_entry *entry; 874 875 resource_list_for_each_entry(entry, &bridge->windows) { 876 res = entry->res; 877 if (res->flags & IORESOURCE_IO) 878 pci_unmap_iospace(res); 879 if (res->parent && 880 (res->flags & (IORESOURCE_MEM | IORESOURCE_IO))) 881 release_resource(res); 882 } 883 __acpi_pci_root_release_info(bridge->release_data); 884 } 885 886 struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root, 887 struct acpi_pci_root_ops *ops, 888 struct acpi_pci_root_info *info, 889 void *sysdata) 890 { 891 int ret, busnum = root->secondary.start; 892 struct acpi_device *device = root->device; 893 int node = acpi_get_node(device->handle); 894 struct pci_bus *bus; 895 struct pci_host_bridge *host_bridge; 896 union acpi_object *obj; 897 898 info->root = root; 899 info->bridge = device; 900 info->ops = ops; 901 INIT_LIST_HEAD(&info->resources); 902 snprintf(info->name, sizeof(info->name), "PCI Bus %04x:%02x", 903 root->segment, busnum); 904 905 if (ops->init_info && ops->init_info(info)) 906 goto out_release_info; 907 if (ops->prepare_resources) 908 ret = ops->prepare_resources(info); 909 else 910 ret = acpi_pci_probe_root_resources(info); 911 if (ret < 0) 912 goto out_release_info; 913 914 pci_acpi_root_add_resources(info); 915 pci_add_resource(&info->resources, &root->secondary); 916 bus = pci_create_root_bus(NULL, busnum, ops->pci_ops, 917 sysdata, &info->resources); 918 if (!bus) 919 goto out_release_info; 920 921 host_bridge = to_pci_host_bridge(bus->bridge); 922 if (!(root->osc_control_set & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL)) 923 host_bridge->native_pcie_hotplug = 0; 924 if (!(root->osc_control_set & OSC_PCI_SHPC_NATIVE_HP_CONTROL)) 925 host_bridge->native_shpc_hotplug = 0; 926 if (!(root->osc_control_set & OSC_PCI_EXPRESS_AER_CONTROL)) 927 host_bridge->native_aer = 0; 928 if (!(root->osc_control_set & OSC_PCI_EXPRESS_PME_CONTROL)) 929 host_bridge->native_pme = 0; 930 if (!(root->osc_control_set & OSC_PCI_EXPRESS_LTR_CONTROL)) 931 host_bridge->native_ltr = 0; 932 if (!(root->osc_control_set & OSC_PCI_EXPRESS_DPC_CONTROL)) 933 host_bridge->native_dpc = 0; 934 935 /* 936 * Evaluate the "PCI Boot Configuration" _DSM Function. If it 937 * exists and returns 0, we must preserve any PCI resource 938 * assignments made by firmware for this host bridge. 939 */ 940 obj = acpi_evaluate_dsm(ACPI_HANDLE(bus->bridge), &pci_acpi_dsm_guid, 1, 941 DSM_PCI_PRESERVE_BOOT_CONFIG, NULL); 942 if (obj && obj->type == ACPI_TYPE_INTEGER && obj->integer.value == 0) 943 host_bridge->preserve_config = 1; 944 ACPI_FREE(obj); 945 946 pci_scan_child_bus(bus); 947 pci_set_host_bridge_release(host_bridge, acpi_pci_root_release_info, 948 info); 949 if (node != NUMA_NO_NODE) 950 dev_printk(KERN_DEBUG, &bus->dev, "on NUMA node %d\n", node); 951 return bus; 952 953 out_release_info: 954 __acpi_pci_root_release_info(info); 955 return NULL; 956 } 957 958 void __init acpi_pci_root_init(void) 959 { 960 acpi_hest_init(); 961 if (acpi_pci_disabled) 962 return; 963 964 pci_acpi_crs_quirks(); 965 acpi_scan_add_handler_with_hotplug(&pci_root_handler, "pci_root"); 966 } 967