1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * pci_root.c - ACPI PCI Root Bridge Driver ($Revision: 40 $) 4 * 5 * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> 6 * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> 7 */ 8 9 #define pr_fmt(fmt) "ACPI: " fmt 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/init.h> 14 #include <linux/types.h> 15 #include <linux/mutex.h> 16 #include <linux/pm.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/pci.h> 19 #include <linux/pci-acpi.h> 20 #include <linux/dmar.h> 21 #include <linux/acpi.h> 22 #include <linux/slab.h> 23 #include <linux/dmi.h> 24 #include <linux/platform_data/x86/apple.h> 25 #include "internal.h" 26 27 #define ACPI_PCI_ROOT_CLASS "pci_bridge" 28 #define ACPI_PCI_ROOT_DEVICE_NAME "PCI Root Bridge" 29 static int acpi_pci_root_add(struct acpi_device *device, 30 const struct acpi_device_id *not_used); 31 static void acpi_pci_root_remove(struct acpi_device *device); 32 33 static int acpi_pci_root_scan_dependent(struct acpi_device *adev) 34 { 35 acpiphp_check_host_bridge(adev); 36 return 0; 37 } 38 39 #define ACPI_PCIE_REQ_SUPPORT (OSC_PCI_EXT_CONFIG_SUPPORT \ 40 | OSC_PCI_ASPM_SUPPORT \ 41 | OSC_PCI_CLOCK_PM_SUPPORT \ 42 | OSC_PCI_MSI_SUPPORT) 43 44 static const struct acpi_device_id root_device_ids[] = { 45 {"PNP0A03", 0}, 46 {"", 0}, 47 }; 48 49 static struct acpi_scan_handler pci_root_handler = { 50 .ids = root_device_ids, 51 .attach = acpi_pci_root_add, 52 .detach = acpi_pci_root_remove, 53 .hotplug = { 54 .enabled = true, 55 .scan_dependent = acpi_pci_root_scan_dependent, 56 }, 57 }; 58 59 /** 60 * acpi_is_root_bridge - determine whether an ACPI CA node is a PCI root bridge 61 * @handle: the ACPI CA node in question. 62 * 63 * Note: we could make this API take a struct acpi_device * instead, but 64 * for now, it's more convenient to operate on an acpi_handle. 65 */ 66 int acpi_is_root_bridge(acpi_handle handle) 67 { 68 struct acpi_device *device = acpi_fetch_acpi_dev(handle); 69 int ret; 70 71 if (!device) 72 return 0; 73 74 ret = acpi_match_device_ids(device, root_device_ids); 75 if (ret) 76 return 0; 77 else 78 return 1; 79 } 80 EXPORT_SYMBOL_GPL(acpi_is_root_bridge); 81 82 static acpi_status 83 get_root_bridge_busnr_callback(struct acpi_resource *resource, void *data) 84 { 85 struct resource *res = data; 86 struct acpi_resource_address64 address; 87 acpi_status status; 88 89 status = acpi_resource_to_address64(resource, &address); 90 if (ACPI_FAILURE(status)) 91 return AE_OK; 92 93 if ((address.address.address_length > 0) && 94 (address.resource_type == ACPI_BUS_NUMBER_RANGE)) { 95 res->start = address.address.minimum; 96 res->end = address.address.minimum + address.address.address_length - 1; 97 } 98 99 return AE_OK; 100 } 101 102 static acpi_status try_get_root_bridge_busnr(acpi_handle handle, 103 struct resource *res) 104 { 105 acpi_status status; 106 107 res->start = -1; 108 status = 109 acpi_walk_resources(handle, METHOD_NAME__CRS, 110 get_root_bridge_busnr_callback, res); 111 if (ACPI_FAILURE(status)) 112 return status; 113 if (res->start == -1) 114 return AE_ERROR; 115 return AE_OK; 116 } 117 118 struct pci_osc_bit_struct { 119 u32 bit; 120 char *desc; 121 }; 122 123 static struct pci_osc_bit_struct pci_osc_support_bit[] = { 124 { OSC_PCI_EXT_CONFIG_SUPPORT, "ExtendedConfig" }, 125 { OSC_PCI_ASPM_SUPPORT, "ASPM" }, 126 { OSC_PCI_CLOCK_PM_SUPPORT, "ClockPM" }, 127 { OSC_PCI_SEGMENT_GROUPS_SUPPORT, "Segments" }, 128 { OSC_PCI_MSI_SUPPORT, "MSI" }, 129 { OSC_PCI_EDR_SUPPORT, "EDR" }, 130 { OSC_PCI_HPX_TYPE_3_SUPPORT, "HPX-Type3" }, 131 }; 132 133 static struct pci_osc_bit_struct pci_osc_control_bit[] = { 134 { OSC_PCI_EXPRESS_NATIVE_HP_CONTROL, "PCIeHotplug" }, 135 { OSC_PCI_SHPC_NATIVE_HP_CONTROL, "SHPCHotplug" }, 136 { OSC_PCI_EXPRESS_PME_CONTROL, "PME" }, 137 { OSC_PCI_EXPRESS_AER_CONTROL, "AER" }, 138 { OSC_PCI_EXPRESS_CAPABILITY_CONTROL, "PCIeCapability" }, 139 { OSC_PCI_EXPRESS_LTR_CONTROL, "LTR" }, 140 { OSC_PCI_EXPRESS_DPC_CONTROL, "DPC" }, 141 }; 142 143 static void decode_osc_bits(struct acpi_pci_root *root, char *msg, u32 word, 144 struct pci_osc_bit_struct *table, int size) 145 { 146 char buf[80]; 147 int i, len = 0; 148 struct pci_osc_bit_struct *entry; 149 150 buf[0] = '\0'; 151 for (i = 0, entry = table; i < size; i++, entry++) 152 if (word & entry->bit) 153 len += scnprintf(buf + len, sizeof(buf) - len, "%s%s", 154 len ? " " : "", entry->desc); 155 156 dev_info(&root->device->dev, "_OSC: %s [%s]\n", msg, buf); 157 } 158 159 static void decode_osc_support(struct acpi_pci_root *root, char *msg, u32 word) 160 { 161 decode_osc_bits(root, msg, word, pci_osc_support_bit, 162 ARRAY_SIZE(pci_osc_support_bit)); 163 } 164 165 static void decode_osc_control(struct acpi_pci_root *root, char *msg, u32 word) 166 { 167 decode_osc_bits(root, msg, word, pci_osc_control_bit, 168 ARRAY_SIZE(pci_osc_control_bit)); 169 } 170 171 static u8 pci_osc_uuid_str[] = "33DB4D5B-1FF7-401C-9657-7441C03DD766"; 172 173 static acpi_status acpi_pci_run_osc(acpi_handle handle, 174 const u32 *capbuf, u32 *retval) 175 { 176 struct acpi_osc_context context = { 177 .uuid_str = pci_osc_uuid_str, 178 .rev = 1, 179 .cap.length = 12, 180 .cap.pointer = (void *)capbuf, 181 }; 182 acpi_status status; 183 184 status = acpi_run_osc(handle, &context); 185 if (ACPI_SUCCESS(status)) { 186 *retval = *((u32 *)(context.ret.pointer + 8)); 187 kfree(context.ret.pointer); 188 } 189 return status; 190 } 191 192 static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root, 193 u32 support, 194 u32 *control) 195 { 196 acpi_status status; 197 u32 result, capbuf[3]; 198 199 support |= root->osc_support_set; 200 201 capbuf[OSC_QUERY_DWORD] = OSC_QUERY_ENABLE; 202 capbuf[OSC_SUPPORT_DWORD] = support; 203 capbuf[OSC_CONTROL_DWORD] = *control | root->osc_control_set; 204 205 status = acpi_pci_run_osc(root->device->handle, capbuf, &result); 206 if (ACPI_SUCCESS(status)) { 207 root->osc_support_set = support; 208 *control = result; 209 } 210 return status; 211 } 212 213 struct acpi_pci_root *acpi_pci_find_root(acpi_handle handle) 214 { 215 struct acpi_device *device = acpi_fetch_acpi_dev(handle); 216 struct acpi_pci_root *root; 217 218 if (!device || acpi_match_device_ids(device, root_device_ids)) 219 return NULL; 220 221 root = acpi_driver_data(device); 222 223 return root; 224 } 225 EXPORT_SYMBOL_GPL(acpi_pci_find_root); 226 227 struct acpi_handle_node { 228 struct list_head node; 229 acpi_handle handle; 230 }; 231 232 /** 233 * acpi_get_pci_dev - convert ACPI CA handle to struct pci_dev 234 * @handle: the handle in question 235 * 236 * Given an ACPI CA handle, the desired PCI device is located in the 237 * list of PCI devices. 238 * 239 * If the device is found, its reference count is increased and this 240 * function returns a pointer to its data structure. The caller must 241 * decrement the reference count by calling pci_dev_put(). 242 * If no device is found, %NULL is returned. 243 */ 244 struct pci_dev *acpi_get_pci_dev(acpi_handle handle) 245 { 246 int dev, fn; 247 unsigned long long adr; 248 acpi_status status; 249 acpi_handle phandle; 250 struct pci_bus *pbus; 251 struct pci_dev *pdev = NULL; 252 struct acpi_handle_node *node, *tmp; 253 struct acpi_pci_root *root; 254 LIST_HEAD(device_list); 255 256 /* 257 * Walk up the ACPI CA namespace until we reach a PCI root bridge. 258 */ 259 phandle = handle; 260 while (!acpi_is_root_bridge(phandle)) { 261 node = kzalloc(sizeof(struct acpi_handle_node), GFP_KERNEL); 262 if (!node) 263 goto out; 264 265 INIT_LIST_HEAD(&node->node); 266 node->handle = phandle; 267 list_add(&node->node, &device_list); 268 269 status = acpi_get_parent(phandle, &phandle); 270 if (ACPI_FAILURE(status)) 271 goto out; 272 } 273 274 root = acpi_pci_find_root(phandle); 275 if (!root) 276 goto out; 277 278 pbus = root->bus; 279 280 /* 281 * Now, walk back down the PCI device tree until we return to our 282 * original handle. Assumes that everything between the PCI root 283 * bridge and the device we're looking for must be a P2P bridge. 284 */ 285 list_for_each_entry(node, &device_list, node) { 286 acpi_handle hnd = node->handle; 287 status = acpi_evaluate_integer(hnd, "_ADR", NULL, &adr); 288 if (ACPI_FAILURE(status)) 289 goto out; 290 dev = (adr >> 16) & 0xffff; 291 fn = adr & 0xffff; 292 293 pdev = pci_get_slot(pbus, PCI_DEVFN(dev, fn)); 294 if (!pdev || hnd == handle) 295 break; 296 297 pbus = pdev->subordinate; 298 pci_dev_put(pdev); 299 300 /* 301 * This function may be called for a non-PCI device that has a 302 * PCI parent (eg. a disk under a PCI SATA controller). In that 303 * case pdev->subordinate will be NULL for the parent. 304 */ 305 if (!pbus) { 306 dev_dbg(&pdev->dev, "Not a PCI-to-PCI bridge\n"); 307 pdev = NULL; 308 break; 309 } 310 } 311 out: 312 list_for_each_entry_safe(node, tmp, &device_list, node) 313 kfree(node); 314 315 return pdev; 316 } 317 EXPORT_SYMBOL_GPL(acpi_get_pci_dev); 318 319 /** 320 * acpi_pci_osc_control_set - Request control of PCI root _OSC features. 321 * @handle: ACPI handle of a PCI root bridge (or PCIe Root Complex). 322 * @mask: Mask of _OSC bits to request control of, place to store control mask. 323 * @support: _OSC supported capability. 324 * 325 * Run _OSC query for @mask and if that is successful, compare the returned 326 * mask of control bits with @req. If all of the @req bits are set in the 327 * returned mask, run _OSC request for it. 328 * 329 * The variable at the @mask address may be modified regardless of whether or 330 * not the function returns success. On success it will contain the mask of 331 * _OSC bits the BIOS has granted control of, but its contents are meaningless 332 * on failure. 333 **/ 334 static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 support) 335 { 336 u32 req = OSC_PCI_EXPRESS_CAPABILITY_CONTROL; 337 struct acpi_pci_root *root; 338 acpi_status status; 339 u32 ctrl, capbuf[3]; 340 341 if (!mask) 342 return AE_BAD_PARAMETER; 343 344 root = acpi_pci_find_root(handle); 345 if (!root) 346 return AE_NOT_EXIST; 347 348 ctrl = *mask; 349 *mask |= root->osc_control_set; 350 351 /* Need to check the available controls bits before requesting them. */ 352 do { 353 status = acpi_pci_query_osc(root, support, mask); 354 if (ACPI_FAILURE(status)) 355 return status; 356 if (ctrl == *mask) 357 break; 358 decode_osc_control(root, "platform does not support", 359 ctrl & ~(*mask)); 360 ctrl = *mask; 361 } while (*mask); 362 363 /* No need to request _OSC if the control was already granted. */ 364 if ((root->osc_control_set & ctrl) == ctrl) 365 return AE_OK; 366 367 if ((ctrl & req) != req) { 368 decode_osc_control(root, "not requesting control; platform does not support", 369 req & ~(ctrl)); 370 return AE_SUPPORT; 371 } 372 373 capbuf[OSC_QUERY_DWORD] = 0; 374 capbuf[OSC_SUPPORT_DWORD] = root->osc_support_set; 375 capbuf[OSC_CONTROL_DWORD] = ctrl; 376 status = acpi_pci_run_osc(handle, capbuf, mask); 377 if (ACPI_FAILURE(status)) 378 return status; 379 380 root->osc_control_set = *mask; 381 return AE_OK; 382 } 383 384 static u32 calculate_support(void) 385 { 386 u32 support; 387 388 /* 389 * All supported architectures that use ACPI have support for 390 * PCI domains, so we indicate this in _OSC support capabilities. 391 */ 392 support = OSC_PCI_SEGMENT_GROUPS_SUPPORT; 393 support |= OSC_PCI_HPX_TYPE_3_SUPPORT; 394 if (pci_ext_cfg_avail()) 395 support |= OSC_PCI_EXT_CONFIG_SUPPORT; 396 if (pcie_aspm_support_enabled()) 397 support |= OSC_PCI_ASPM_SUPPORT | OSC_PCI_CLOCK_PM_SUPPORT; 398 if (pci_msi_enabled()) 399 support |= OSC_PCI_MSI_SUPPORT; 400 if (IS_ENABLED(CONFIG_PCIE_EDR)) 401 support |= OSC_PCI_EDR_SUPPORT; 402 403 return support; 404 } 405 406 static u32 calculate_control(void) 407 { 408 u32 control; 409 410 control = OSC_PCI_EXPRESS_CAPABILITY_CONTROL 411 | OSC_PCI_EXPRESS_PME_CONTROL; 412 413 if (IS_ENABLED(CONFIG_PCIEASPM)) 414 control |= OSC_PCI_EXPRESS_LTR_CONTROL; 415 416 if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE)) 417 control |= OSC_PCI_EXPRESS_NATIVE_HP_CONTROL; 418 419 if (IS_ENABLED(CONFIG_HOTPLUG_PCI_SHPC)) 420 control |= OSC_PCI_SHPC_NATIVE_HP_CONTROL; 421 422 if (pci_aer_available()) 423 control |= OSC_PCI_EXPRESS_AER_CONTROL; 424 425 /* 426 * Per the Downstream Port Containment Related Enhancements ECN to 427 * the PCI Firmware Spec, r3.2, sec 4.5.1, table 4-5, 428 * OSC_PCI_EXPRESS_DPC_CONTROL indicates the OS supports both DPC 429 * and EDR. 430 */ 431 if (IS_ENABLED(CONFIG_PCIE_DPC) && IS_ENABLED(CONFIG_PCIE_EDR)) 432 control |= OSC_PCI_EXPRESS_DPC_CONTROL; 433 434 return control; 435 } 436 437 static bool os_control_query_checks(struct acpi_pci_root *root, u32 support) 438 { 439 struct acpi_device *device = root->device; 440 441 if (pcie_ports_disabled) { 442 dev_info(&device->dev, "PCIe port services disabled; not requesting _OSC control\n"); 443 return false; 444 } 445 446 if ((support & ACPI_PCIE_REQ_SUPPORT) != ACPI_PCIE_REQ_SUPPORT) { 447 decode_osc_support(root, "not requesting OS control; OS requires", 448 ACPI_PCIE_REQ_SUPPORT); 449 return false; 450 } 451 452 return true; 453 } 454 455 static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm, 456 bool is_pcie) 457 { 458 u32 support, control = 0, requested = 0; 459 acpi_status status; 460 struct acpi_device *device = root->device; 461 acpi_handle handle = device->handle; 462 463 /* 464 * Apple always return failure on _OSC calls when _OSI("Darwin") has 465 * been called successfully. We know the feature set supported by the 466 * platform, so avoid calling _OSC at all 467 */ 468 if (x86_apple_machine) { 469 root->osc_control_set = ~OSC_PCI_EXPRESS_PME_CONTROL; 470 decode_osc_control(root, "OS assumes control of", 471 root->osc_control_set); 472 return; 473 } 474 475 support = calculate_support(); 476 477 decode_osc_support(root, "OS supports", support); 478 479 if (os_control_query_checks(root, support)) 480 requested = control = calculate_control(); 481 482 status = acpi_pci_osc_control_set(handle, &control, support); 483 if (ACPI_SUCCESS(status)) { 484 if (control) 485 decode_osc_control(root, "OS now controls", control); 486 487 if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) { 488 /* 489 * We have ASPM control, but the FADT indicates that 490 * it's unsupported. Leave existing configuration 491 * intact and prevent the OS from touching it. 492 */ 493 dev_info(&device->dev, "FADT indicates ASPM is unsupported, using BIOS configuration\n"); 494 *no_aspm = 1; 495 } 496 } else { 497 /* 498 * We want to disable ASPM here, but aspm_disabled 499 * needs to remain in its state from boot so that we 500 * properly handle PCIe 1.1 devices. So we set this 501 * flag here, to defer the action until after the ACPI 502 * root scan. 503 */ 504 *no_aspm = 1; 505 506 /* _OSC is optional for PCI host bridges */ 507 if ((status == AE_NOT_FOUND) && !is_pcie) 508 return; 509 510 if (control) { 511 decode_osc_control(root, "OS requested", requested); 512 decode_osc_control(root, "platform willing to grant", control); 513 } 514 515 dev_info(&device->dev, "_OSC: platform retains control of PCIe features (%s)\n", 516 acpi_format_exception(status)); 517 } 518 } 519 520 static int acpi_pci_root_add(struct acpi_device *device, 521 const struct acpi_device_id *not_used) 522 { 523 unsigned long long segment, bus; 524 acpi_status status; 525 int result; 526 struct acpi_pci_root *root; 527 acpi_handle handle = device->handle; 528 int no_aspm = 0; 529 bool hotadd = system_state == SYSTEM_RUNNING; 530 bool is_pcie; 531 532 root = kzalloc(sizeof(struct acpi_pci_root), GFP_KERNEL); 533 if (!root) 534 return -ENOMEM; 535 536 segment = 0; 537 status = acpi_evaluate_integer(handle, METHOD_NAME__SEG, NULL, 538 &segment); 539 if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) { 540 dev_err(&device->dev, "can't evaluate _SEG\n"); 541 result = -ENODEV; 542 goto end; 543 } 544 545 /* Check _CRS first, then _BBN. If no _BBN, default to zero. */ 546 root->secondary.flags = IORESOURCE_BUS; 547 status = try_get_root_bridge_busnr(handle, &root->secondary); 548 if (ACPI_FAILURE(status)) { 549 /* 550 * We need both the start and end of the downstream bus range 551 * to interpret _CBA (MMCONFIG base address), so it really is 552 * supposed to be in _CRS. If we don't find it there, all we 553 * can do is assume [_BBN-0xFF] or [0-0xFF]. 554 */ 555 root->secondary.end = 0xFF; 556 dev_warn(&device->dev, 557 FW_BUG "no secondary bus range in _CRS\n"); 558 status = acpi_evaluate_integer(handle, METHOD_NAME__BBN, 559 NULL, &bus); 560 if (ACPI_SUCCESS(status)) 561 root->secondary.start = bus; 562 else if (status == AE_NOT_FOUND) 563 root->secondary.start = 0; 564 else { 565 dev_err(&device->dev, "can't evaluate _BBN\n"); 566 result = -ENODEV; 567 goto end; 568 } 569 } 570 571 root->device = device; 572 root->segment = segment & 0xFFFF; 573 strcpy(acpi_device_name(device), ACPI_PCI_ROOT_DEVICE_NAME); 574 strcpy(acpi_device_class(device), ACPI_PCI_ROOT_CLASS); 575 device->driver_data = root; 576 577 if (hotadd && dmar_device_add(handle)) { 578 result = -ENXIO; 579 goto end; 580 } 581 582 pr_info("%s [%s] (domain %04x %pR)\n", 583 acpi_device_name(device), acpi_device_bid(device), 584 root->segment, &root->secondary); 585 586 root->mcfg_addr = acpi_pci_root_get_mcfg_addr(handle); 587 588 is_pcie = strcmp(acpi_device_hid(device), "PNP0A08") == 0; 589 negotiate_os_control(root, &no_aspm, is_pcie); 590 591 /* 592 * TBD: Need PCI interface for enumeration/configuration of roots. 593 */ 594 595 /* 596 * Scan the Root Bridge 597 * -------------------- 598 * Must do this prior to any attempt to bind the root device, as the 599 * PCI namespace does not get created until this call is made (and 600 * thus the root bridge's pci_dev does not exist). 601 */ 602 root->bus = pci_acpi_scan_root(root); 603 if (!root->bus) { 604 dev_err(&device->dev, 605 "Bus %04x:%02x not present in PCI namespace\n", 606 root->segment, (unsigned int)root->secondary.start); 607 device->driver_data = NULL; 608 result = -ENODEV; 609 goto remove_dmar; 610 } 611 612 if (no_aspm) 613 pcie_no_aspm(); 614 615 pci_acpi_add_bus_pm_notifier(device); 616 device_set_wakeup_capable(root->bus->bridge, device->wakeup.flags.valid); 617 618 if (hotadd) { 619 pcibios_resource_survey_bus(root->bus); 620 pci_assign_unassigned_root_bus_resources(root->bus); 621 /* 622 * This is only called for the hotadd case. For the boot-time 623 * case, we need to wait until after PCI initialization in 624 * order to deal with IOAPICs mapped in on a PCI BAR. 625 * 626 * This is currently x86-specific, because acpi_ioapic_add() 627 * is an empty function without CONFIG_ACPI_HOTPLUG_IOAPIC. 628 * And CONFIG_ACPI_HOTPLUG_IOAPIC depends on CONFIG_X86_IO_APIC 629 * (see drivers/acpi/Kconfig). 630 */ 631 acpi_ioapic_add(root->device->handle); 632 } 633 634 pci_lock_rescan_remove(); 635 pci_bus_add_devices(root->bus); 636 pci_unlock_rescan_remove(); 637 return 1; 638 639 remove_dmar: 640 if (hotadd) 641 dmar_device_remove(handle); 642 end: 643 kfree(root); 644 return result; 645 } 646 647 static void acpi_pci_root_remove(struct acpi_device *device) 648 { 649 struct acpi_pci_root *root = acpi_driver_data(device); 650 651 pci_lock_rescan_remove(); 652 653 pci_stop_root_bus(root->bus); 654 655 pci_ioapic_remove(root); 656 device_set_wakeup_capable(root->bus->bridge, false); 657 pci_acpi_remove_bus_pm_notifier(device); 658 659 pci_remove_root_bus(root->bus); 660 WARN_ON(acpi_ioapic_remove(root)); 661 662 dmar_device_remove(device->handle); 663 664 pci_unlock_rescan_remove(); 665 666 kfree(root); 667 } 668 669 /* 670 * Following code to support acpi_pci_root_create() is copied from 671 * arch/x86/pci/acpi.c and modified so it could be reused by x86, IA64 672 * and ARM64. 673 */ 674 static void acpi_pci_root_validate_resources(struct device *dev, 675 struct list_head *resources, 676 unsigned long type) 677 { 678 LIST_HEAD(list); 679 struct resource *res1, *res2, *root = NULL; 680 struct resource_entry *tmp, *entry, *entry2; 681 682 BUG_ON((type & (IORESOURCE_MEM | IORESOURCE_IO)) == 0); 683 root = (type & IORESOURCE_MEM) ? &iomem_resource : &ioport_resource; 684 685 list_splice_init(resources, &list); 686 resource_list_for_each_entry_safe(entry, tmp, &list) { 687 bool free = false; 688 resource_size_t end; 689 690 res1 = entry->res; 691 if (!(res1->flags & type)) 692 goto next; 693 694 /* Exclude non-addressable range or non-addressable portion */ 695 end = min(res1->end, root->end); 696 if (end <= res1->start) { 697 dev_info(dev, "host bridge window %pR (ignored, not CPU addressable)\n", 698 res1); 699 free = true; 700 goto next; 701 } else if (res1->end != end) { 702 dev_info(dev, "host bridge window %pR ([%#llx-%#llx] ignored, not CPU addressable)\n", 703 res1, (unsigned long long)end + 1, 704 (unsigned long long)res1->end); 705 res1->end = end; 706 } 707 708 resource_list_for_each_entry(entry2, resources) { 709 res2 = entry2->res; 710 if (!(res2->flags & type)) 711 continue; 712 713 /* 714 * I don't like throwing away windows because then 715 * our resources no longer match the ACPI _CRS, but 716 * the kernel resource tree doesn't allow overlaps. 717 */ 718 if (resource_union(res1, res2, res2)) { 719 dev_info(dev, "host bridge window expanded to %pR; %pR ignored\n", 720 res2, res1); 721 free = true; 722 goto next; 723 } 724 } 725 726 next: 727 resource_list_del(entry); 728 if (free) 729 resource_list_free_entry(entry); 730 else 731 resource_list_add_tail(entry, resources); 732 } 733 } 734 735 static void acpi_pci_root_remap_iospace(struct fwnode_handle *fwnode, 736 struct resource_entry *entry) 737 { 738 #ifdef PCI_IOBASE 739 struct resource *res = entry->res; 740 resource_size_t cpu_addr = res->start; 741 resource_size_t pci_addr = cpu_addr - entry->offset; 742 resource_size_t length = resource_size(res); 743 unsigned long port; 744 745 if (pci_register_io_range(fwnode, cpu_addr, length)) 746 goto err; 747 748 port = pci_address_to_pio(cpu_addr); 749 if (port == (unsigned long)-1) 750 goto err; 751 752 res->start = port; 753 res->end = port + length - 1; 754 entry->offset = port - pci_addr; 755 756 if (pci_remap_iospace(res, cpu_addr) < 0) 757 goto err; 758 759 pr_info("Remapped I/O %pa to %pR\n", &cpu_addr, res); 760 return; 761 err: 762 res->flags |= IORESOURCE_DISABLED; 763 #endif 764 } 765 766 int acpi_pci_probe_root_resources(struct acpi_pci_root_info *info) 767 { 768 int ret; 769 struct list_head *list = &info->resources; 770 struct acpi_device *device = info->bridge; 771 struct resource_entry *entry, *tmp; 772 unsigned long flags; 773 774 flags = IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT; 775 ret = acpi_dev_get_resources(device, list, 776 acpi_dev_filter_resource_type_cb, 777 (void *)flags); 778 if (ret < 0) 779 dev_warn(&device->dev, 780 "failed to parse _CRS method, error code %d\n", ret); 781 else if (ret == 0) 782 dev_dbg(&device->dev, 783 "no IO and memory resources present in _CRS\n"); 784 else { 785 resource_list_for_each_entry_safe(entry, tmp, list) { 786 if (entry->res->flags & IORESOURCE_IO) 787 acpi_pci_root_remap_iospace(&device->fwnode, 788 entry); 789 790 if (entry->res->flags & IORESOURCE_DISABLED) 791 resource_list_destroy_entry(entry); 792 else 793 entry->res->name = info->name; 794 } 795 acpi_pci_root_validate_resources(&device->dev, list, 796 IORESOURCE_MEM); 797 acpi_pci_root_validate_resources(&device->dev, list, 798 IORESOURCE_IO); 799 } 800 801 return ret; 802 } 803 804 static void pci_acpi_root_add_resources(struct acpi_pci_root_info *info) 805 { 806 struct resource_entry *entry, *tmp; 807 struct resource *res, *conflict, *root = NULL; 808 809 resource_list_for_each_entry_safe(entry, tmp, &info->resources) { 810 res = entry->res; 811 if (res->flags & IORESOURCE_MEM) 812 root = &iomem_resource; 813 else if (res->flags & IORESOURCE_IO) 814 root = &ioport_resource; 815 else 816 continue; 817 818 /* 819 * Some legacy x86 host bridge drivers use iomem_resource and 820 * ioport_resource as default resource pool, skip it. 821 */ 822 if (res == root) 823 continue; 824 825 conflict = insert_resource_conflict(root, res); 826 if (conflict) { 827 dev_info(&info->bridge->dev, 828 "ignoring host bridge window %pR (conflicts with %s %pR)\n", 829 res, conflict->name, conflict); 830 resource_list_destroy_entry(entry); 831 } 832 } 833 } 834 835 static void __acpi_pci_root_release_info(struct acpi_pci_root_info *info) 836 { 837 struct resource *res; 838 struct resource_entry *entry, *tmp; 839 840 if (!info) 841 return; 842 843 resource_list_for_each_entry_safe(entry, tmp, &info->resources) { 844 res = entry->res; 845 if (res->parent && 846 (res->flags & (IORESOURCE_MEM | IORESOURCE_IO))) 847 release_resource(res); 848 resource_list_destroy_entry(entry); 849 } 850 851 info->ops->release_info(info); 852 } 853 854 static void acpi_pci_root_release_info(struct pci_host_bridge *bridge) 855 { 856 struct resource *res; 857 struct resource_entry *entry; 858 859 resource_list_for_each_entry(entry, &bridge->windows) { 860 res = entry->res; 861 if (res->flags & IORESOURCE_IO) 862 pci_unmap_iospace(res); 863 if (res->parent && 864 (res->flags & (IORESOURCE_MEM | IORESOURCE_IO))) 865 release_resource(res); 866 } 867 __acpi_pci_root_release_info(bridge->release_data); 868 } 869 870 struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root, 871 struct acpi_pci_root_ops *ops, 872 struct acpi_pci_root_info *info, 873 void *sysdata) 874 { 875 int ret, busnum = root->secondary.start; 876 struct acpi_device *device = root->device; 877 int node = acpi_get_node(device->handle); 878 struct pci_bus *bus; 879 struct pci_host_bridge *host_bridge; 880 union acpi_object *obj; 881 882 info->root = root; 883 info->bridge = device; 884 info->ops = ops; 885 INIT_LIST_HEAD(&info->resources); 886 snprintf(info->name, sizeof(info->name), "PCI Bus %04x:%02x", 887 root->segment, busnum); 888 889 if (ops->init_info && ops->init_info(info)) 890 goto out_release_info; 891 if (ops->prepare_resources) 892 ret = ops->prepare_resources(info); 893 else 894 ret = acpi_pci_probe_root_resources(info); 895 if (ret < 0) 896 goto out_release_info; 897 898 pci_acpi_root_add_resources(info); 899 pci_add_resource(&info->resources, &root->secondary); 900 bus = pci_create_root_bus(NULL, busnum, ops->pci_ops, 901 sysdata, &info->resources); 902 if (!bus) 903 goto out_release_info; 904 905 host_bridge = to_pci_host_bridge(bus->bridge); 906 if (!(root->osc_control_set & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL)) 907 host_bridge->native_pcie_hotplug = 0; 908 if (!(root->osc_control_set & OSC_PCI_SHPC_NATIVE_HP_CONTROL)) 909 host_bridge->native_shpc_hotplug = 0; 910 if (!(root->osc_control_set & OSC_PCI_EXPRESS_AER_CONTROL)) 911 host_bridge->native_aer = 0; 912 if (!(root->osc_control_set & OSC_PCI_EXPRESS_PME_CONTROL)) 913 host_bridge->native_pme = 0; 914 if (!(root->osc_control_set & OSC_PCI_EXPRESS_LTR_CONTROL)) 915 host_bridge->native_ltr = 0; 916 if (!(root->osc_control_set & OSC_PCI_EXPRESS_DPC_CONTROL)) 917 host_bridge->native_dpc = 0; 918 919 /* 920 * Evaluate the "PCI Boot Configuration" _DSM Function. If it 921 * exists and returns 0, we must preserve any PCI resource 922 * assignments made by firmware for this host bridge. 923 */ 924 obj = acpi_evaluate_dsm(ACPI_HANDLE(bus->bridge), &pci_acpi_dsm_guid, 1, 925 DSM_PCI_PRESERVE_BOOT_CONFIG, NULL); 926 if (obj && obj->type == ACPI_TYPE_INTEGER && obj->integer.value == 0) 927 host_bridge->preserve_config = 1; 928 ACPI_FREE(obj); 929 930 pci_scan_child_bus(bus); 931 pci_set_host_bridge_release(host_bridge, acpi_pci_root_release_info, 932 info); 933 if (node != NUMA_NO_NODE) 934 dev_printk(KERN_DEBUG, &bus->dev, "on NUMA node %d\n", node); 935 return bus; 936 937 out_release_info: 938 __acpi_pci_root_release_info(info); 939 return NULL; 940 } 941 942 void __init acpi_pci_root_init(void) 943 { 944 if (acpi_pci_disabled) 945 return; 946 947 pci_acpi_crs_quirks(); 948 acpi_scan_add_handler_with_hotplug(&pci_root_handler, "pci_root"); 949 } 950