1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * pci_root.c - ACPI PCI Root Bridge Driver ($Revision: 40 $) 4 * 5 * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> 6 * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> 7 */ 8 9 #define pr_fmt(fmt) "ACPI: " fmt 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/init.h> 14 #include <linux/types.h> 15 #include <linux/mutex.h> 16 #include <linux/pm.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/pci.h> 19 #include <linux/pci-acpi.h> 20 #include <linux/dmar.h> 21 #include <linux/acpi.h> 22 #include <linux/slab.h> 23 #include <linux/dmi.h> 24 #include <linux/platform_data/x86/apple.h> 25 #include "internal.h" 26 27 #define ACPI_PCI_ROOT_CLASS "pci_bridge" 28 #define ACPI_PCI_ROOT_DEVICE_NAME "PCI Root Bridge" 29 static int acpi_pci_root_add(struct acpi_device *device, 30 const struct acpi_device_id *not_used); 31 static void acpi_pci_root_remove(struct acpi_device *device); 32 33 static int acpi_pci_root_scan_dependent(struct acpi_device *adev) 34 { 35 acpiphp_check_host_bridge(adev); 36 return 0; 37 } 38 39 #define ACPI_PCIE_REQ_SUPPORT (OSC_PCI_EXT_CONFIG_SUPPORT \ 40 | OSC_PCI_ASPM_SUPPORT \ 41 | OSC_PCI_CLOCK_PM_SUPPORT \ 42 | OSC_PCI_MSI_SUPPORT) 43 44 static const struct acpi_device_id root_device_ids[] = { 45 {"PNP0A03", 0}, 46 {"", 0}, 47 }; 48 49 static struct acpi_scan_handler pci_root_handler = { 50 .ids = root_device_ids, 51 .attach = acpi_pci_root_add, 52 .detach = acpi_pci_root_remove, 53 .hotplug = { 54 .enabled = true, 55 .scan_dependent = acpi_pci_root_scan_dependent, 56 }, 57 }; 58 59 /** 60 * acpi_is_root_bridge - determine whether an ACPI CA node is a PCI root bridge 61 * @handle: the ACPI CA node in question. 62 * 63 * Note: we could make this API take a struct acpi_device * instead, but 64 * for now, it's more convenient to operate on an acpi_handle. 65 */ 66 int acpi_is_root_bridge(acpi_handle handle) 67 { 68 struct acpi_device *device = acpi_fetch_acpi_dev(handle); 69 int ret; 70 71 if (!device) 72 return 0; 73 74 ret = acpi_match_device_ids(device, root_device_ids); 75 if (ret) 76 return 0; 77 else 78 return 1; 79 } 80 EXPORT_SYMBOL_GPL(acpi_is_root_bridge); 81 82 static acpi_status 83 get_root_bridge_busnr_callback(struct acpi_resource *resource, void *data) 84 { 85 struct resource *res = data; 86 struct acpi_resource_address64 address; 87 acpi_status status; 88 89 status = acpi_resource_to_address64(resource, &address); 90 if (ACPI_FAILURE(status)) 91 return AE_OK; 92 93 if ((address.address.address_length > 0) && 94 (address.resource_type == ACPI_BUS_NUMBER_RANGE)) { 95 res->start = address.address.minimum; 96 res->end = address.address.minimum + address.address.address_length - 1; 97 } 98 99 return AE_OK; 100 } 101 102 static acpi_status try_get_root_bridge_busnr(acpi_handle handle, 103 struct resource *res) 104 { 105 acpi_status status; 106 107 res->start = -1; 108 status = 109 acpi_walk_resources(handle, METHOD_NAME__CRS, 110 get_root_bridge_busnr_callback, res); 111 if (ACPI_FAILURE(status)) 112 return status; 113 if (res->start == -1) 114 return AE_ERROR; 115 return AE_OK; 116 } 117 118 struct pci_osc_bit_struct { 119 u32 bit; 120 char *desc; 121 }; 122 123 static struct pci_osc_bit_struct pci_osc_support_bit[] = { 124 { OSC_PCI_EXT_CONFIG_SUPPORT, "ExtendedConfig" }, 125 { OSC_PCI_ASPM_SUPPORT, "ASPM" }, 126 { OSC_PCI_CLOCK_PM_SUPPORT, "ClockPM" }, 127 { OSC_PCI_SEGMENT_GROUPS_SUPPORT, "Segments" }, 128 { OSC_PCI_MSI_SUPPORT, "MSI" }, 129 { OSC_PCI_EDR_SUPPORT, "EDR" }, 130 { OSC_PCI_HPX_TYPE_3_SUPPORT, "HPX-Type3" }, 131 }; 132 133 static struct pci_osc_bit_struct pci_osc_control_bit[] = { 134 { OSC_PCI_EXPRESS_NATIVE_HP_CONTROL, "PCIeHotplug" }, 135 { OSC_PCI_SHPC_NATIVE_HP_CONTROL, "SHPCHotplug" }, 136 { OSC_PCI_EXPRESS_PME_CONTROL, "PME" }, 137 { OSC_PCI_EXPRESS_AER_CONTROL, "AER" }, 138 { OSC_PCI_EXPRESS_CAPABILITY_CONTROL, "PCIeCapability" }, 139 { OSC_PCI_EXPRESS_LTR_CONTROL, "LTR" }, 140 { OSC_PCI_EXPRESS_DPC_CONTROL, "DPC" }, 141 }; 142 143 static struct pci_osc_bit_struct cxl_osc_support_bit[] = { 144 { OSC_CXL_1_1_PORT_REG_ACCESS_SUPPORT, "CXL11PortRegAccess" }, 145 { OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT, "CXL20PortDevRegAccess" }, 146 { OSC_CXL_PROTOCOL_ERR_REPORTING_SUPPORT, "CXLProtocolErrorReporting" }, 147 { OSC_CXL_NATIVE_HP_SUPPORT, "CXLNativeHotPlug" }, 148 }; 149 150 static struct pci_osc_bit_struct cxl_osc_control_bit[] = { 151 { OSC_CXL_ERROR_REPORTING_CONTROL, "CXLMemErrorReporting" }, 152 }; 153 154 static void decode_osc_bits(struct acpi_pci_root *root, char *msg, u32 word, 155 struct pci_osc_bit_struct *table, int size) 156 { 157 char buf[80]; 158 int i, len = 0; 159 struct pci_osc_bit_struct *entry; 160 161 buf[0] = '\0'; 162 for (i = 0, entry = table; i < size; i++, entry++) 163 if (word & entry->bit) 164 len += scnprintf(buf + len, sizeof(buf) - len, "%s%s", 165 len ? " " : "", entry->desc); 166 167 dev_info(&root->device->dev, "_OSC: %s [%s]\n", msg, buf); 168 } 169 170 static void decode_osc_support(struct acpi_pci_root *root, char *msg, u32 word) 171 { 172 decode_osc_bits(root, msg, word, pci_osc_support_bit, 173 ARRAY_SIZE(pci_osc_support_bit)); 174 } 175 176 static void decode_osc_control(struct acpi_pci_root *root, char *msg, u32 word) 177 { 178 decode_osc_bits(root, msg, word, pci_osc_control_bit, 179 ARRAY_SIZE(pci_osc_control_bit)); 180 } 181 182 static void decode_cxl_osc_support(struct acpi_pci_root *root, char *msg, u32 word) 183 { 184 decode_osc_bits(root, msg, word, cxl_osc_support_bit, 185 ARRAY_SIZE(cxl_osc_support_bit)); 186 } 187 188 static void decode_cxl_osc_control(struct acpi_pci_root *root, char *msg, u32 word) 189 { 190 decode_osc_bits(root, msg, word, cxl_osc_control_bit, 191 ARRAY_SIZE(cxl_osc_control_bit)); 192 } 193 194 static inline bool is_pcie(struct acpi_pci_root *root) 195 { 196 return root->bridge_type == ACPI_BRIDGE_TYPE_PCIE; 197 } 198 199 static inline bool is_cxl(struct acpi_pci_root *root) 200 { 201 return root->bridge_type == ACPI_BRIDGE_TYPE_CXL; 202 } 203 204 static u8 pci_osc_uuid_str[] = "33DB4D5B-1FF7-401C-9657-7441C03DD766"; 205 static u8 cxl_osc_uuid_str[] = "68F2D50B-C469-4d8A-BD3D-941A103FD3FC"; 206 207 static char *to_uuid(struct acpi_pci_root *root) 208 { 209 if (is_cxl(root)) 210 return cxl_osc_uuid_str; 211 return pci_osc_uuid_str; 212 } 213 214 static int cap_length(struct acpi_pci_root *root) 215 { 216 if (is_cxl(root)) 217 return sizeof(u32) * OSC_CXL_CAPABILITY_DWORDS; 218 return sizeof(u32) * OSC_PCI_CAPABILITY_DWORDS; 219 } 220 221 static acpi_status acpi_pci_run_osc(struct acpi_pci_root *root, 222 const u32 *capbuf, u32 *pci_control, 223 u32 *cxl_control) 224 { 225 struct acpi_osc_context context = { 226 .uuid_str = to_uuid(root), 227 .rev = 1, 228 .cap.length = cap_length(root), 229 .cap.pointer = (void *)capbuf, 230 }; 231 acpi_status status; 232 233 status = acpi_run_osc(root->device->handle, &context); 234 if (ACPI_SUCCESS(status)) { 235 *pci_control = acpi_osc_ctx_get_pci_control(&context); 236 if (is_cxl(root)) 237 *cxl_control = acpi_osc_ctx_get_cxl_control(&context); 238 kfree(context.ret.pointer); 239 } 240 return status; 241 } 242 243 static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root, u32 support, 244 u32 *control, u32 cxl_support, 245 u32 *cxl_control) 246 { 247 acpi_status status; 248 u32 pci_result, cxl_result, capbuf[OSC_CXL_CAPABILITY_DWORDS]; 249 250 support |= root->osc_support_set; 251 252 capbuf[OSC_QUERY_DWORD] = OSC_QUERY_ENABLE; 253 capbuf[OSC_SUPPORT_DWORD] = support; 254 capbuf[OSC_CONTROL_DWORD] = *control | root->osc_control_set; 255 256 if (is_cxl(root)) { 257 cxl_support |= root->osc_ext_support_set; 258 capbuf[OSC_EXT_SUPPORT_DWORD] = cxl_support; 259 capbuf[OSC_EXT_CONTROL_DWORD] = *cxl_control | root->osc_ext_control_set; 260 } 261 262 retry: 263 status = acpi_pci_run_osc(root, capbuf, &pci_result, &cxl_result); 264 if (ACPI_SUCCESS(status)) { 265 root->osc_support_set = support; 266 *control = pci_result; 267 if (is_cxl(root)) { 268 root->osc_ext_support_set = cxl_support; 269 *cxl_control = cxl_result; 270 } 271 } else if (is_cxl(root)) { 272 /* 273 * CXL _OSC is optional on CXL 1.1 hosts. Fall back to PCIe _OSC 274 * upon any failure using CXL _OSC. 275 */ 276 root->bridge_type = ACPI_BRIDGE_TYPE_PCIE; 277 goto retry; 278 } 279 return status; 280 } 281 282 struct acpi_pci_root *acpi_pci_find_root(acpi_handle handle) 283 { 284 struct acpi_device *device = acpi_fetch_acpi_dev(handle); 285 struct acpi_pci_root *root; 286 287 if (!device || acpi_match_device_ids(device, root_device_ids)) 288 return NULL; 289 290 root = acpi_driver_data(device); 291 292 return root; 293 } 294 EXPORT_SYMBOL_GPL(acpi_pci_find_root); 295 296 struct acpi_handle_node { 297 struct list_head node; 298 acpi_handle handle; 299 }; 300 301 /** 302 * acpi_get_pci_dev - convert ACPI CA handle to struct pci_dev 303 * @handle: the handle in question 304 * 305 * Given an ACPI CA handle, the desired PCI device is located in the 306 * list of PCI devices. 307 * 308 * If the device is found, its reference count is increased and this 309 * function returns a pointer to its data structure. The caller must 310 * decrement the reference count by calling pci_dev_put(). 311 * If no device is found, %NULL is returned. 312 */ 313 struct pci_dev *acpi_get_pci_dev(acpi_handle handle) 314 { 315 struct acpi_device *adev = acpi_fetch_acpi_dev(handle); 316 struct acpi_device_physical_node *pn; 317 struct pci_dev *pci_dev = NULL; 318 319 if (!adev) 320 return NULL; 321 322 mutex_lock(&adev->physical_node_lock); 323 324 list_for_each_entry(pn, &adev->physical_node_list, node) { 325 if (dev_is_pci(pn->dev)) { 326 get_device(pn->dev); 327 pci_dev = to_pci_dev(pn->dev); 328 break; 329 } 330 } 331 332 mutex_unlock(&adev->physical_node_lock); 333 334 return pci_dev; 335 } 336 EXPORT_SYMBOL_GPL(acpi_get_pci_dev); 337 338 /** 339 * acpi_pci_osc_control_set - Request control of PCI root _OSC features. 340 * @handle: ACPI handle of a PCI root bridge (or PCIe Root Complex). 341 * @mask: Mask of _OSC bits to request control of, place to store control mask. 342 * @support: _OSC supported capability. 343 * @cxl_mask: Mask of CXL _OSC control bits, place to store control mask. 344 * @cxl_support: CXL _OSC supported capability. 345 * 346 * Run _OSC query for @mask and if that is successful, compare the returned 347 * mask of control bits with @req. If all of the @req bits are set in the 348 * returned mask, run _OSC request for it. 349 * 350 * The variable at the @mask address may be modified regardless of whether or 351 * not the function returns success. On success it will contain the mask of 352 * _OSC bits the BIOS has granted control of, but its contents are meaningless 353 * on failure. 354 **/ 355 static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, 356 u32 support, u32 *cxl_mask, 357 u32 cxl_support) 358 { 359 u32 req = OSC_PCI_EXPRESS_CAPABILITY_CONTROL; 360 struct acpi_pci_root *root; 361 acpi_status status; 362 u32 ctrl, cxl_ctrl = 0, capbuf[OSC_CXL_CAPABILITY_DWORDS]; 363 364 if (!mask) 365 return AE_BAD_PARAMETER; 366 367 root = acpi_pci_find_root(handle); 368 if (!root) 369 return AE_NOT_EXIST; 370 371 ctrl = *mask; 372 *mask |= root->osc_control_set; 373 374 if (is_cxl(root)) { 375 cxl_ctrl = *cxl_mask; 376 *cxl_mask |= root->osc_ext_control_set; 377 } 378 379 /* Need to check the available controls bits before requesting them. */ 380 do { 381 u32 pci_missing = 0, cxl_missing = 0; 382 383 status = acpi_pci_query_osc(root, support, mask, cxl_support, 384 cxl_mask); 385 if (ACPI_FAILURE(status)) 386 return status; 387 if (is_cxl(root)) { 388 if (ctrl == *mask && cxl_ctrl == *cxl_mask) 389 break; 390 pci_missing = ctrl & ~(*mask); 391 cxl_missing = cxl_ctrl & ~(*cxl_mask); 392 } else { 393 if (ctrl == *mask) 394 break; 395 pci_missing = ctrl & ~(*mask); 396 } 397 if (pci_missing) 398 decode_osc_control(root, "platform does not support", 399 pci_missing); 400 if (cxl_missing) 401 decode_cxl_osc_control(root, "CXL platform does not support", 402 cxl_missing); 403 ctrl = *mask; 404 cxl_ctrl = *cxl_mask; 405 } while (*mask || *cxl_mask); 406 407 /* No need to request _OSC if the control was already granted. */ 408 if ((root->osc_control_set & ctrl) == ctrl && 409 (root->osc_ext_control_set & cxl_ctrl) == cxl_ctrl) 410 return AE_OK; 411 412 if ((ctrl & req) != req) { 413 decode_osc_control(root, "not requesting control; platform does not support", 414 req & ~(ctrl)); 415 return AE_SUPPORT; 416 } 417 418 capbuf[OSC_QUERY_DWORD] = 0; 419 capbuf[OSC_SUPPORT_DWORD] = root->osc_support_set; 420 capbuf[OSC_CONTROL_DWORD] = ctrl; 421 if (is_cxl(root)) { 422 capbuf[OSC_EXT_SUPPORT_DWORD] = root->osc_ext_support_set; 423 capbuf[OSC_EXT_CONTROL_DWORD] = cxl_ctrl; 424 } 425 426 status = acpi_pci_run_osc(root, capbuf, mask, cxl_mask); 427 if (ACPI_FAILURE(status)) 428 return status; 429 430 root->osc_control_set = *mask; 431 root->osc_ext_control_set = *cxl_mask; 432 return AE_OK; 433 } 434 435 static u32 calculate_support(void) 436 { 437 u32 support; 438 439 /* 440 * All supported architectures that use ACPI have support for 441 * PCI domains, so we indicate this in _OSC support capabilities. 442 */ 443 support = OSC_PCI_SEGMENT_GROUPS_SUPPORT; 444 support |= OSC_PCI_HPX_TYPE_3_SUPPORT; 445 if (pci_ext_cfg_avail()) 446 support |= OSC_PCI_EXT_CONFIG_SUPPORT; 447 if (pcie_aspm_support_enabled()) 448 support |= OSC_PCI_ASPM_SUPPORT | OSC_PCI_CLOCK_PM_SUPPORT; 449 if (pci_msi_enabled()) 450 support |= OSC_PCI_MSI_SUPPORT; 451 if (IS_ENABLED(CONFIG_PCIE_EDR)) 452 support |= OSC_PCI_EDR_SUPPORT; 453 454 return support; 455 } 456 457 /* 458 * Background on hotplug support, and making it depend on only 459 * CONFIG_HOTPLUG_PCI_PCIE vs. also considering CONFIG_MEMORY_HOTPLUG: 460 * 461 * CONFIG_ACPI_HOTPLUG_MEMORY does depend on CONFIG_MEMORY_HOTPLUG, but 462 * there is no existing _OSC for memory hotplug support. The reason is that 463 * ACPI memory hotplug requires the OS to acknowledge / coordinate with 464 * memory plug events via a scan handler. On the CXL side the equivalent 465 * would be if Linux supported the Mechanical Retention Lock [1], or 466 * otherwise had some coordination for the driver of a PCI device 467 * undergoing hotplug to be consulted on whether the hotplug should 468 * proceed or not. 469 * 470 * The concern is that if Linux says no to supporting CXL hotplug then 471 * the BIOS may say no to giving the OS hotplug control of any other PCIe 472 * device. So the question here is not whether hotplug is enabled, it's 473 * whether it is handled natively by the at all OS, and if 474 * CONFIG_HOTPLUG_PCI_PCIE is enabled then the answer is "yes". 475 * 476 * Otherwise, the plan for CXL coordinated remove, since the kernel does 477 * not support blocking hotplug, is to require the memory device to be 478 * disabled before hotplug is attempted. When CONFIG_MEMORY_HOTPLUG is 479 * disabled that step will fail and the remove attempt cancelled by the 480 * user. If that is not honored and the card is removed anyway then it 481 * does not matter if CONFIG_MEMORY_HOTPLUG is enabled or not, it will 482 * cause a crash and other badness. 483 * 484 * Therefore, just say yes to CXL hotplug and require removal to 485 * be coordinated by userspace unless and until the kernel grows better 486 * mechanisms for doing "managed" removal of devices in consultation with 487 * the driver. 488 * 489 * [1]: https://lore.kernel.org/all/20201122014203.4706-1-ashok.raj@intel.com/ 490 */ 491 static u32 calculate_cxl_support(void) 492 { 493 u32 support; 494 495 support = OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT; 496 if (pci_aer_available()) 497 support |= OSC_CXL_PROTOCOL_ERR_REPORTING_SUPPORT; 498 if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE)) 499 support |= OSC_CXL_NATIVE_HP_SUPPORT; 500 501 return support; 502 } 503 504 static u32 calculate_control(void) 505 { 506 u32 control; 507 508 control = OSC_PCI_EXPRESS_CAPABILITY_CONTROL 509 | OSC_PCI_EXPRESS_PME_CONTROL; 510 511 if (IS_ENABLED(CONFIG_PCIEASPM)) 512 control |= OSC_PCI_EXPRESS_LTR_CONTROL; 513 514 if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE)) 515 control |= OSC_PCI_EXPRESS_NATIVE_HP_CONTROL; 516 517 if (IS_ENABLED(CONFIG_HOTPLUG_PCI_SHPC)) 518 control |= OSC_PCI_SHPC_NATIVE_HP_CONTROL; 519 520 if (pci_aer_available()) 521 control |= OSC_PCI_EXPRESS_AER_CONTROL; 522 523 /* 524 * Per the Downstream Port Containment Related Enhancements ECN to 525 * the PCI Firmware Spec, r3.2, sec 4.5.1, table 4-5, 526 * OSC_PCI_EXPRESS_DPC_CONTROL indicates the OS supports both DPC 527 * and EDR. 528 */ 529 if (IS_ENABLED(CONFIG_PCIE_DPC) && IS_ENABLED(CONFIG_PCIE_EDR)) 530 control |= OSC_PCI_EXPRESS_DPC_CONTROL; 531 532 return control; 533 } 534 535 static u32 calculate_cxl_control(void) 536 { 537 u32 control = 0; 538 539 if (IS_ENABLED(CONFIG_MEMORY_FAILURE)) 540 control |= OSC_CXL_ERROR_REPORTING_CONTROL; 541 542 return control; 543 } 544 545 static bool os_control_query_checks(struct acpi_pci_root *root, u32 support) 546 { 547 struct acpi_device *device = root->device; 548 549 if (pcie_ports_disabled) { 550 dev_info(&device->dev, "PCIe port services disabled; not requesting _OSC control\n"); 551 return false; 552 } 553 554 if ((support & ACPI_PCIE_REQ_SUPPORT) != ACPI_PCIE_REQ_SUPPORT) { 555 decode_osc_support(root, "not requesting OS control; OS requires", 556 ACPI_PCIE_REQ_SUPPORT); 557 return false; 558 } 559 560 return true; 561 } 562 563 static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm) 564 { 565 u32 support, control = 0, requested = 0; 566 u32 cxl_support = 0, cxl_control = 0, cxl_requested = 0; 567 acpi_status status; 568 struct acpi_device *device = root->device; 569 acpi_handle handle = device->handle; 570 571 /* 572 * Apple always return failure on _OSC calls when _OSI("Darwin") has 573 * been called successfully. We know the feature set supported by the 574 * platform, so avoid calling _OSC at all 575 */ 576 if (x86_apple_machine) { 577 root->osc_control_set = ~OSC_PCI_EXPRESS_PME_CONTROL; 578 decode_osc_control(root, "OS assumes control of", 579 root->osc_control_set); 580 return; 581 } 582 583 support = calculate_support(); 584 585 decode_osc_support(root, "OS supports", support); 586 587 if (os_control_query_checks(root, support)) 588 requested = control = calculate_control(); 589 590 if (is_cxl(root)) { 591 cxl_support = calculate_cxl_support(); 592 decode_cxl_osc_support(root, "OS supports", cxl_support); 593 cxl_requested = cxl_control = calculate_cxl_control(); 594 } 595 596 status = acpi_pci_osc_control_set(handle, &control, support, 597 &cxl_control, cxl_support); 598 if (ACPI_SUCCESS(status)) { 599 if (control) 600 decode_osc_control(root, "OS now controls", control); 601 if (cxl_control) 602 decode_cxl_osc_control(root, "OS now controls", 603 cxl_control); 604 605 if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) { 606 /* 607 * We have ASPM control, but the FADT indicates that 608 * it's unsupported. Leave existing configuration 609 * intact and prevent the OS from touching it. 610 */ 611 dev_info(&device->dev, "FADT indicates ASPM is unsupported, using BIOS configuration\n"); 612 *no_aspm = 1; 613 } 614 } else { 615 /* 616 * We want to disable ASPM here, but aspm_disabled 617 * needs to remain in its state from boot so that we 618 * properly handle PCIe 1.1 devices. So we set this 619 * flag here, to defer the action until after the ACPI 620 * root scan. 621 */ 622 *no_aspm = 1; 623 624 /* _OSC is optional for PCI host bridges */ 625 if (status == AE_NOT_FOUND && !is_pcie(root)) 626 return; 627 628 if (control) { 629 decode_osc_control(root, "OS requested", requested); 630 decode_osc_control(root, "platform willing to grant", control); 631 } 632 if (cxl_control) { 633 decode_cxl_osc_control(root, "OS requested", cxl_requested); 634 decode_cxl_osc_control(root, "platform willing to grant", 635 cxl_control); 636 } 637 638 dev_info(&device->dev, "_OSC: platform retains control of PCIe features (%s)\n", 639 acpi_format_exception(status)); 640 } 641 } 642 643 static int acpi_pci_root_add(struct acpi_device *device, 644 const struct acpi_device_id *not_used) 645 { 646 unsigned long long segment, bus; 647 acpi_status status; 648 int result; 649 struct acpi_pci_root *root; 650 acpi_handle handle = device->handle; 651 int no_aspm = 0; 652 bool hotadd = system_state == SYSTEM_RUNNING; 653 const char *acpi_hid; 654 655 root = kzalloc(sizeof(struct acpi_pci_root), GFP_KERNEL); 656 if (!root) 657 return -ENOMEM; 658 659 segment = 0; 660 status = acpi_evaluate_integer(handle, METHOD_NAME__SEG, NULL, 661 &segment); 662 if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) { 663 dev_err(&device->dev, "can't evaluate _SEG\n"); 664 result = -ENODEV; 665 goto end; 666 } 667 668 /* Check _CRS first, then _BBN. If no _BBN, default to zero. */ 669 root->secondary.flags = IORESOURCE_BUS; 670 status = try_get_root_bridge_busnr(handle, &root->secondary); 671 if (ACPI_FAILURE(status)) { 672 /* 673 * We need both the start and end of the downstream bus range 674 * to interpret _CBA (MMCONFIG base address), so it really is 675 * supposed to be in _CRS. If we don't find it there, all we 676 * can do is assume [_BBN-0xFF] or [0-0xFF]. 677 */ 678 root->secondary.end = 0xFF; 679 dev_warn(&device->dev, 680 FW_BUG "no secondary bus range in _CRS\n"); 681 status = acpi_evaluate_integer(handle, METHOD_NAME__BBN, 682 NULL, &bus); 683 if (ACPI_SUCCESS(status)) 684 root->secondary.start = bus; 685 else if (status == AE_NOT_FOUND) 686 root->secondary.start = 0; 687 else { 688 dev_err(&device->dev, "can't evaluate _BBN\n"); 689 result = -ENODEV; 690 goto end; 691 } 692 } 693 694 root->device = device; 695 root->segment = segment & 0xFFFF; 696 strcpy(acpi_device_name(device), ACPI_PCI_ROOT_DEVICE_NAME); 697 strcpy(acpi_device_class(device), ACPI_PCI_ROOT_CLASS); 698 device->driver_data = root; 699 700 if (hotadd && dmar_device_add(handle)) { 701 result = -ENXIO; 702 goto end; 703 } 704 705 pr_info("%s [%s] (domain %04x %pR)\n", 706 acpi_device_name(device), acpi_device_bid(device), 707 root->segment, &root->secondary); 708 709 root->mcfg_addr = acpi_pci_root_get_mcfg_addr(handle); 710 711 acpi_hid = acpi_device_hid(root->device); 712 if (strcmp(acpi_hid, "PNP0A08") == 0) 713 root->bridge_type = ACPI_BRIDGE_TYPE_PCIE; 714 else if (strcmp(acpi_hid, "ACPI0016") == 0) 715 root->bridge_type = ACPI_BRIDGE_TYPE_CXL; 716 else 717 dev_dbg(&device->dev, "Assuming non-PCIe host bridge\n"); 718 719 negotiate_os_control(root, &no_aspm); 720 721 /* 722 * TBD: Need PCI interface for enumeration/configuration of roots. 723 */ 724 725 /* 726 * Scan the Root Bridge 727 * -------------------- 728 * Must do this prior to any attempt to bind the root device, as the 729 * PCI namespace does not get created until this call is made (and 730 * thus the root bridge's pci_dev does not exist). 731 */ 732 root->bus = pci_acpi_scan_root(root); 733 if (!root->bus) { 734 dev_err(&device->dev, 735 "Bus %04x:%02x not present in PCI namespace\n", 736 root->segment, (unsigned int)root->secondary.start); 737 device->driver_data = NULL; 738 result = -ENODEV; 739 goto remove_dmar; 740 } 741 742 if (no_aspm) 743 pcie_no_aspm(); 744 745 pci_acpi_add_bus_pm_notifier(device); 746 device_set_wakeup_capable(root->bus->bridge, device->wakeup.flags.valid); 747 748 if (hotadd) { 749 pcibios_resource_survey_bus(root->bus); 750 pci_assign_unassigned_root_bus_resources(root->bus); 751 /* 752 * This is only called for the hotadd case. For the boot-time 753 * case, we need to wait until after PCI initialization in 754 * order to deal with IOAPICs mapped in on a PCI BAR. 755 * 756 * This is currently x86-specific, because acpi_ioapic_add() 757 * is an empty function without CONFIG_ACPI_HOTPLUG_IOAPIC. 758 * And CONFIG_ACPI_HOTPLUG_IOAPIC depends on CONFIG_X86_IO_APIC 759 * (see drivers/acpi/Kconfig). 760 */ 761 acpi_ioapic_add(root->device->handle); 762 } 763 764 pci_lock_rescan_remove(); 765 pci_bus_add_devices(root->bus); 766 pci_unlock_rescan_remove(); 767 return 1; 768 769 remove_dmar: 770 if (hotadd) 771 dmar_device_remove(handle); 772 end: 773 kfree(root); 774 return result; 775 } 776 777 static void acpi_pci_root_remove(struct acpi_device *device) 778 { 779 struct acpi_pci_root *root = acpi_driver_data(device); 780 781 pci_lock_rescan_remove(); 782 783 pci_stop_root_bus(root->bus); 784 785 pci_ioapic_remove(root); 786 device_set_wakeup_capable(root->bus->bridge, false); 787 pci_acpi_remove_bus_pm_notifier(device); 788 789 pci_remove_root_bus(root->bus); 790 WARN_ON(acpi_ioapic_remove(root)); 791 792 dmar_device_remove(device->handle); 793 794 pci_unlock_rescan_remove(); 795 796 kfree(root); 797 } 798 799 /* 800 * Following code to support acpi_pci_root_create() is copied from 801 * arch/x86/pci/acpi.c and modified so it could be reused by x86, IA64 802 * and ARM64. 803 */ 804 static void acpi_pci_root_validate_resources(struct device *dev, 805 struct list_head *resources, 806 unsigned long type) 807 { 808 LIST_HEAD(list); 809 struct resource *res1, *res2, *root = NULL; 810 struct resource_entry *tmp, *entry, *entry2; 811 812 BUG_ON((type & (IORESOURCE_MEM | IORESOURCE_IO)) == 0); 813 root = (type & IORESOURCE_MEM) ? &iomem_resource : &ioport_resource; 814 815 list_splice_init(resources, &list); 816 resource_list_for_each_entry_safe(entry, tmp, &list) { 817 bool free = false; 818 resource_size_t end; 819 820 res1 = entry->res; 821 if (!(res1->flags & type)) 822 goto next; 823 824 /* Exclude non-addressable range or non-addressable portion */ 825 end = min(res1->end, root->end); 826 if (end <= res1->start) { 827 dev_info(dev, "host bridge window %pR (ignored, not CPU addressable)\n", 828 res1); 829 free = true; 830 goto next; 831 } else if (res1->end != end) { 832 dev_info(dev, "host bridge window %pR ([%#llx-%#llx] ignored, not CPU addressable)\n", 833 res1, (unsigned long long)end + 1, 834 (unsigned long long)res1->end); 835 res1->end = end; 836 } 837 838 resource_list_for_each_entry(entry2, resources) { 839 res2 = entry2->res; 840 if (!(res2->flags & type)) 841 continue; 842 843 /* 844 * I don't like throwing away windows because then 845 * our resources no longer match the ACPI _CRS, but 846 * the kernel resource tree doesn't allow overlaps. 847 */ 848 if (resource_union(res1, res2, res2)) { 849 dev_info(dev, "host bridge window expanded to %pR; %pR ignored\n", 850 res2, res1); 851 free = true; 852 goto next; 853 } 854 } 855 856 next: 857 resource_list_del(entry); 858 if (free) 859 resource_list_free_entry(entry); 860 else 861 resource_list_add_tail(entry, resources); 862 } 863 } 864 865 static void acpi_pci_root_remap_iospace(struct fwnode_handle *fwnode, 866 struct resource_entry *entry) 867 { 868 #ifdef PCI_IOBASE 869 struct resource *res = entry->res; 870 resource_size_t cpu_addr = res->start; 871 resource_size_t pci_addr = cpu_addr - entry->offset; 872 resource_size_t length = resource_size(res); 873 unsigned long port; 874 875 if (pci_register_io_range(fwnode, cpu_addr, length)) 876 goto err; 877 878 port = pci_address_to_pio(cpu_addr); 879 if (port == (unsigned long)-1) 880 goto err; 881 882 res->start = port; 883 res->end = port + length - 1; 884 entry->offset = port - pci_addr; 885 886 if (pci_remap_iospace(res, cpu_addr) < 0) 887 goto err; 888 889 pr_info("Remapped I/O %pa to %pR\n", &cpu_addr, res); 890 return; 891 err: 892 res->flags |= IORESOURCE_DISABLED; 893 #endif 894 } 895 896 int acpi_pci_probe_root_resources(struct acpi_pci_root_info *info) 897 { 898 int ret; 899 struct list_head *list = &info->resources; 900 struct acpi_device *device = info->bridge; 901 struct resource_entry *entry, *tmp; 902 unsigned long flags; 903 904 flags = IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT; 905 ret = acpi_dev_get_resources(device, list, 906 acpi_dev_filter_resource_type_cb, 907 (void *)flags); 908 if (ret < 0) 909 dev_warn(&device->dev, 910 "failed to parse _CRS method, error code %d\n", ret); 911 else if (ret == 0) 912 dev_dbg(&device->dev, 913 "no IO and memory resources present in _CRS\n"); 914 else { 915 resource_list_for_each_entry_safe(entry, tmp, list) { 916 if (entry->res->flags & IORESOURCE_IO) 917 acpi_pci_root_remap_iospace(&device->fwnode, 918 entry); 919 920 if (entry->res->flags & IORESOURCE_DISABLED) 921 resource_list_destroy_entry(entry); 922 else 923 entry->res->name = info->name; 924 } 925 acpi_pci_root_validate_resources(&device->dev, list, 926 IORESOURCE_MEM); 927 acpi_pci_root_validate_resources(&device->dev, list, 928 IORESOURCE_IO); 929 } 930 931 return ret; 932 } 933 934 static void pci_acpi_root_add_resources(struct acpi_pci_root_info *info) 935 { 936 struct resource_entry *entry, *tmp; 937 struct resource *res, *conflict, *root = NULL; 938 939 resource_list_for_each_entry_safe(entry, tmp, &info->resources) { 940 res = entry->res; 941 if (res->flags & IORESOURCE_MEM) 942 root = &iomem_resource; 943 else if (res->flags & IORESOURCE_IO) 944 root = &ioport_resource; 945 else 946 continue; 947 948 /* 949 * Some legacy x86 host bridge drivers use iomem_resource and 950 * ioport_resource as default resource pool, skip it. 951 */ 952 if (res == root) 953 continue; 954 955 conflict = insert_resource_conflict(root, res); 956 if (conflict) { 957 dev_info(&info->bridge->dev, 958 "ignoring host bridge window %pR (conflicts with %s %pR)\n", 959 res, conflict->name, conflict); 960 resource_list_destroy_entry(entry); 961 } 962 } 963 } 964 965 static void __acpi_pci_root_release_info(struct acpi_pci_root_info *info) 966 { 967 struct resource *res; 968 struct resource_entry *entry, *tmp; 969 970 if (!info) 971 return; 972 973 resource_list_for_each_entry_safe(entry, tmp, &info->resources) { 974 res = entry->res; 975 if (res->parent && 976 (res->flags & (IORESOURCE_MEM | IORESOURCE_IO))) 977 release_resource(res); 978 resource_list_destroy_entry(entry); 979 } 980 981 info->ops->release_info(info); 982 } 983 984 static void acpi_pci_root_release_info(struct pci_host_bridge *bridge) 985 { 986 struct resource *res; 987 struct resource_entry *entry; 988 989 resource_list_for_each_entry(entry, &bridge->windows) { 990 res = entry->res; 991 if (res->flags & IORESOURCE_IO) 992 pci_unmap_iospace(res); 993 if (res->parent && 994 (res->flags & (IORESOURCE_MEM | IORESOURCE_IO))) 995 release_resource(res); 996 } 997 __acpi_pci_root_release_info(bridge->release_data); 998 } 999 1000 struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root, 1001 struct acpi_pci_root_ops *ops, 1002 struct acpi_pci_root_info *info, 1003 void *sysdata) 1004 { 1005 int ret, busnum = root->secondary.start; 1006 struct acpi_device *device = root->device; 1007 int node = acpi_get_node(device->handle); 1008 struct pci_bus *bus; 1009 struct pci_host_bridge *host_bridge; 1010 union acpi_object *obj; 1011 1012 info->root = root; 1013 info->bridge = device; 1014 info->ops = ops; 1015 INIT_LIST_HEAD(&info->resources); 1016 snprintf(info->name, sizeof(info->name), "PCI Bus %04x:%02x", 1017 root->segment, busnum); 1018 1019 if (ops->init_info && ops->init_info(info)) 1020 goto out_release_info; 1021 if (ops->prepare_resources) 1022 ret = ops->prepare_resources(info); 1023 else 1024 ret = acpi_pci_probe_root_resources(info); 1025 if (ret < 0) 1026 goto out_release_info; 1027 1028 pci_acpi_root_add_resources(info); 1029 pci_add_resource(&info->resources, &root->secondary); 1030 bus = pci_create_root_bus(NULL, busnum, ops->pci_ops, 1031 sysdata, &info->resources); 1032 if (!bus) 1033 goto out_release_info; 1034 1035 host_bridge = to_pci_host_bridge(bus->bridge); 1036 if (!(root->osc_control_set & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL)) 1037 host_bridge->native_pcie_hotplug = 0; 1038 if (!(root->osc_control_set & OSC_PCI_SHPC_NATIVE_HP_CONTROL)) 1039 host_bridge->native_shpc_hotplug = 0; 1040 if (!(root->osc_control_set & OSC_PCI_EXPRESS_AER_CONTROL)) 1041 host_bridge->native_aer = 0; 1042 if (!(root->osc_control_set & OSC_PCI_EXPRESS_PME_CONTROL)) 1043 host_bridge->native_pme = 0; 1044 if (!(root->osc_control_set & OSC_PCI_EXPRESS_LTR_CONTROL)) 1045 host_bridge->native_ltr = 0; 1046 if (!(root->osc_control_set & OSC_PCI_EXPRESS_DPC_CONTROL)) 1047 host_bridge->native_dpc = 0; 1048 1049 /* 1050 * Evaluate the "PCI Boot Configuration" _DSM Function. If it 1051 * exists and returns 0, we must preserve any PCI resource 1052 * assignments made by firmware for this host bridge. 1053 */ 1054 obj = acpi_evaluate_dsm(ACPI_HANDLE(bus->bridge), &pci_acpi_dsm_guid, 1, 1055 DSM_PCI_PRESERVE_BOOT_CONFIG, NULL); 1056 if (obj && obj->type == ACPI_TYPE_INTEGER && obj->integer.value == 0) 1057 host_bridge->preserve_config = 1; 1058 ACPI_FREE(obj); 1059 1060 acpi_dev_power_up_children_with_adr(device); 1061 1062 pci_scan_child_bus(bus); 1063 pci_set_host_bridge_release(host_bridge, acpi_pci_root_release_info, 1064 info); 1065 if (node != NUMA_NO_NODE) 1066 dev_printk(KERN_DEBUG, &bus->dev, "on NUMA node %d\n", node); 1067 return bus; 1068 1069 out_release_info: 1070 __acpi_pci_root_release_info(info); 1071 return NULL; 1072 } 1073 1074 void __init acpi_pci_root_init(void) 1075 { 1076 if (acpi_pci_disabled) 1077 return; 1078 1079 pci_acpi_crs_quirks(); 1080 acpi_scan_add_handler_with_hotplug(&pci_root_handler, "pci_root"); 1081 } 1082