1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers. 4 * 5 * (C) Copyright 2014, 2015 Linaro Ltd. 6 * Author: Ashwin Chaugule <ashwin.chaugule@linaro.org> 7 * 8 * CPPC describes a few methods for controlling CPU performance using 9 * information from a per CPU table called CPC. This table is described in 10 * the ACPI v5.0+ specification. The table consists of a list of 11 * registers which may be memory mapped or hardware registers and also may 12 * include some static integer values. 13 * 14 * CPU performance is on an abstract continuous scale as against a discretized 15 * P-state scale which is tied to CPU frequency only. In brief, the basic 16 * operation involves: 17 * 18 * - OS makes a CPU performance request. (Can provide min and max bounds) 19 * 20 * - Platform (such as BMC) is free to optimize request within requested bounds 21 * depending on power/thermal budgets etc. 22 * 23 * - Platform conveys its decision back to OS 24 * 25 * The communication between OS and platform occurs through another medium 26 * called (PCC) Platform Communication Channel. This is a generic mailbox like 27 * mechanism which includes doorbell semantics to indicate register updates. 28 * See drivers/mailbox/pcc.c for details on PCC. 29 * 30 * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and 31 * above specifications. 32 */ 33 34 #define pr_fmt(fmt) "ACPI CPPC: " fmt 35 36 #include <linux/delay.h> 37 #include <linux/iopoll.h> 38 #include <linux/ktime.h> 39 #include <linux/rwsem.h> 40 #include <linux/wait.h> 41 #include <linux/topology.h> 42 43 #include <acpi/cppc_acpi.h> 44 45 struct cppc_pcc_data { 46 struct pcc_mbox_chan *pcc_channel; 47 void __iomem *pcc_comm_addr; 48 bool pcc_channel_acquired; 49 unsigned int deadline_us; 50 unsigned int pcc_mpar, pcc_mrtt, pcc_nominal; 51 52 bool pending_pcc_write_cmd; /* Any pending/batched PCC write cmds? */ 53 bool platform_owns_pcc; /* Ownership of PCC subspace */ 54 unsigned int pcc_write_cnt; /* Running count of PCC write commands */ 55 56 /* 57 * Lock to provide controlled access to the PCC channel. 58 * 59 * For performance critical usecases(currently cppc_set_perf) 60 * We need to take read_lock and check if channel belongs to OSPM 61 * before reading or writing to PCC subspace 62 * We need to take write_lock before transferring the channel 63 * ownership to the platform via a Doorbell 64 * This allows us to batch a number of CPPC requests if they happen 65 * to originate in about the same time 66 * 67 * For non-performance critical usecases(init) 68 * Take write_lock for all purposes which gives exclusive access 69 */ 70 struct rw_semaphore pcc_lock; 71 72 /* Wait queue for CPUs whose requests were batched */ 73 wait_queue_head_t pcc_write_wait_q; 74 ktime_t last_cmd_cmpl_time; 75 ktime_t last_mpar_reset; 76 int mpar_count; 77 int refcount; 78 }; 79 80 /* Array to represent the PCC channel per subspace ID */ 81 static struct cppc_pcc_data *pcc_data[MAX_PCC_SUBSPACES]; 82 /* The cpu_pcc_subspace_idx contains per CPU subspace ID */ 83 static DEFINE_PER_CPU(int, cpu_pcc_subspace_idx); 84 85 /* 86 * The cpc_desc structure contains the ACPI register details 87 * as described in the per CPU _CPC tables. The details 88 * include the type of register (e.g. PCC, System IO, FFH etc.) 89 * and destination addresses which lets us READ/WRITE CPU performance 90 * information using the appropriate I/O methods. 91 */ 92 static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr); 93 94 /* pcc mapped address + header size + offset within PCC subspace */ 95 #define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_comm_addr + \ 96 0x8 + (offs)) 97 98 /* Check if a CPC register is in PCC */ 99 #define CPC_IN_PCC(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \ 100 (cpc)->cpc_entry.reg.space_id == \ 101 ACPI_ADR_SPACE_PLATFORM_COMM) 102 103 /* Check if a CPC register is in SystemMemory */ 104 #define CPC_IN_SYSTEM_MEMORY(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \ 105 (cpc)->cpc_entry.reg.space_id == \ 106 ACPI_ADR_SPACE_SYSTEM_MEMORY) 107 108 /* Check if a CPC register is in SystemIo */ 109 #define CPC_IN_SYSTEM_IO(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \ 110 (cpc)->cpc_entry.reg.space_id == \ 111 ACPI_ADR_SPACE_SYSTEM_IO) 112 113 /* Evaluates to True if reg is a NULL register descriptor */ 114 #define IS_NULL_REG(reg) ((reg)->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY && \ 115 (reg)->address == 0 && \ 116 (reg)->bit_width == 0 && \ 117 (reg)->bit_offset == 0 && \ 118 (reg)->access_width == 0) 119 120 /* Evaluates to True if an optional cpc field is supported */ 121 #define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ? \ 122 !!(cpc)->cpc_entry.int_value : \ 123 !IS_NULL_REG(&(cpc)->cpc_entry.reg)) 124 /* 125 * Arbitrary Retries in case the remote processor is slow to respond 126 * to PCC commands. Keeping it high enough to cover emulators where 127 * the processors run painfully slow. 128 */ 129 #define NUM_RETRIES 500ULL 130 131 #define OVER_16BTS_MASK ~0xFFFFULL 132 133 #define define_one_cppc_ro(_name) \ 134 static struct kobj_attribute _name = \ 135 __ATTR(_name, 0444, show_##_name, NULL) 136 137 #define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj) 138 139 #define show_cppc_data(access_fn, struct_name, member_name) \ 140 static ssize_t show_##member_name(struct kobject *kobj, \ 141 struct kobj_attribute *attr, char *buf) \ 142 { \ 143 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); \ 144 struct struct_name st_name = {0}; \ 145 int ret; \ 146 \ 147 ret = access_fn(cpc_ptr->cpu_id, &st_name); \ 148 if (ret) \ 149 return ret; \ 150 \ 151 return sysfs_emit(buf, "%llu\n", \ 152 (u64)st_name.member_name); \ 153 } \ 154 define_one_cppc_ro(member_name) 155 156 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf); 157 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf); 158 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf); 159 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf); 160 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq); 161 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq); 162 163 show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf); 164 show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time); 165 166 /* Check for valid access_width, otherwise, fallback to using bit_width */ 167 #define GET_BIT_WIDTH(reg) ((reg)->access_width ? (8 << ((reg)->access_width - 1)) : (reg)->bit_width) 168 169 /* Shift and apply the mask for CPC reads/writes */ 170 #define MASK_VAL_READ(reg, val) (((val) >> (reg)->bit_offset) & \ 171 GENMASK(((reg)->bit_width) - 1, 0)) 172 #define MASK_VAL_WRITE(reg, prev_val, val) \ 173 ((((val) & GENMASK(((reg)->bit_width) - 1, 0)) << (reg)->bit_offset) | \ 174 ((prev_val) & ~(GENMASK(((reg)->bit_width) - 1, 0) << (reg)->bit_offset))) \ 175 176 static ssize_t show_feedback_ctrs(struct kobject *kobj, 177 struct kobj_attribute *attr, char *buf) 178 { 179 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); 180 struct cppc_perf_fb_ctrs fb_ctrs = {0}; 181 int ret; 182 183 ret = cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs); 184 if (ret) 185 return ret; 186 187 return sysfs_emit(buf, "ref:%llu del:%llu\n", 188 fb_ctrs.reference, fb_ctrs.delivered); 189 } 190 define_one_cppc_ro(feedback_ctrs); 191 192 static struct attribute *cppc_attrs[] = { 193 &feedback_ctrs.attr, 194 &reference_perf.attr, 195 &wraparound_time.attr, 196 &highest_perf.attr, 197 &lowest_perf.attr, 198 &lowest_nonlinear_perf.attr, 199 &nominal_perf.attr, 200 &nominal_freq.attr, 201 &lowest_freq.attr, 202 NULL 203 }; 204 ATTRIBUTE_GROUPS(cppc); 205 206 static const struct kobj_type cppc_ktype = { 207 .sysfs_ops = &kobj_sysfs_ops, 208 .default_groups = cppc_groups, 209 }; 210 211 static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit) 212 { 213 int ret, status; 214 struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id]; 215 struct acpi_pcct_shared_memory __iomem *generic_comm_base = 216 pcc_ss_data->pcc_comm_addr; 217 218 if (!pcc_ss_data->platform_owns_pcc) 219 return 0; 220 221 /* 222 * Poll PCC status register every 3us(delay_us) for maximum of 223 * deadline_us(timeout_us) until PCC command complete bit is set(cond) 224 */ 225 ret = readw_relaxed_poll_timeout(&generic_comm_base->status, status, 226 status & PCC_CMD_COMPLETE_MASK, 3, 227 pcc_ss_data->deadline_us); 228 229 if (likely(!ret)) { 230 pcc_ss_data->platform_owns_pcc = false; 231 if (chk_err_bit && (status & PCC_ERROR_MASK)) 232 ret = -EIO; 233 } 234 235 if (unlikely(ret)) 236 pr_err("PCC check channel failed for ss: %d. ret=%d\n", 237 pcc_ss_id, ret); 238 239 return ret; 240 } 241 242 /* 243 * This function transfers the ownership of the PCC to the platform 244 * So it must be called while holding write_lock(pcc_lock) 245 */ 246 static int send_pcc_cmd(int pcc_ss_id, u16 cmd) 247 { 248 int ret = -EIO, i; 249 struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id]; 250 struct acpi_pcct_shared_memory __iomem *generic_comm_base = 251 pcc_ss_data->pcc_comm_addr; 252 unsigned int time_delta; 253 254 /* 255 * For CMD_WRITE we know for a fact the caller should have checked 256 * the channel before writing to PCC space 257 */ 258 if (cmd == CMD_READ) { 259 /* 260 * If there are pending cpc_writes, then we stole the channel 261 * before write completion, so first send a WRITE command to 262 * platform 263 */ 264 if (pcc_ss_data->pending_pcc_write_cmd) 265 send_pcc_cmd(pcc_ss_id, CMD_WRITE); 266 267 ret = check_pcc_chan(pcc_ss_id, false); 268 if (ret) 269 goto end; 270 } else /* CMD_WRITE */ 271 pcc_ss_data->pending_pcc_write_cmd = FALSE; 272 273 /* 274 * Handle the Minimum Request Turnaround Time(MRTT) 275 * "The minimum amount of time that OSPM must wait after the completion 276 * of a command before issuing the next command, in microseconds" 277 */ 278 if (pcc_ss_data->pcc_mrtt) { 279 time_delta = ktime_us_delta(ktime_get(), 280 pcc_ss_data->last_cmd_cmpl_time); 281 if (pcc_ss_data->pcc_mrtt > time_delta) 282 udelay(pcc_ss_data->pcc_mrtt - time_delta); 283 } 284 285 /* 286 * Handle the non-zero Maximum Periodic Access Rate(MPAR) 287 * "The maximum number of periodic requests that the subspace channel can 288 * support, reported in commands per minute. 0 indicates no limitation." 289 * 290 * This parameter should be ideally zero or large enough so that it can 291 * handle maximum number of requests that all the cores in the system can 292 * collectively generate. If it is not, we will follow the spec and just 293 * not send the request to the platform after hitting the MPAR limit in 294 * any 60s window 295 */ 296 if (pcc_ss_data->pcc_mpar) { 297 if (pcc_ss_data->mpar_count == 0) { 298 time_delta = ktime_ms_delta(ktime_get(), 299 pcc_ss_data->last_mpar_reset); 300 if ((time_delta < 60 * MSEC_PER_SEC) && pcc_ss_data->last_mpar_reset) { 301 pr_debug("PCC cmd for subspace %d not sent due to MPAR limit", 302 pcc_ss_id); 303 ret = -EIO; 304 goto end; 305 } 306 pcc_ss_data->last_mpar_reset = ktime_get(); 307 pcc_ss_data->mpar_count = pcc_ss_data->pcc_mpar; 308 } 309 pcc_ss_data->mpar_count--; 310 } 311 312 /* Write to the shared comm region. */ 313 writew_relaxed(cmd, &generic_comm_base->command); 314 315 /* Flip CMD COMPLETE bit */ 316 writew_relaxed(0, &generic_comm_base->status); 317 318 pcc_ss_data->platform_owns_pcc = true; 319 320 /* Ring doorbell */ 321 ret = mbox_send_message(pcc_ss_data->pcc_channel->mchan, &cmd); 322 if (ret < 0) { 323 pr_err("Err sending PCC mbox message. ss: %d cmd:%d, ret:%d\n", 324 pcc_ss_id, cmd, ret); 325 goto end; 326 } 327 328 /* wait for completion and check for PCC error bit */ 329 ret = check_pcc_chan(pcc_ss_id, true); 330 331 if (pcc_ss_data->pcc_mrtt) 332 pcc_ss_data->last_cmd_cmpl_time = ktime_get(); 333 334 if (pcc_ss_data->pcc_channel->mchan->mbox->txdone_irq) 335 mbox_chan_txdone(pcc_ss_data->pcc_channel->mchan, ret); 336 else 337 mbox_client_txdone(pcc_ss_data->pcc_channel->mchan, ret); 338 339 end: 340 if (cmd == CMD_WRITE) { 341 if (unlikely(ret)) { 342 for_each_possible_cpu(i) { 343 struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i); 344 345 if (!desc) 346 continue; 347 348 if (desc->write_cmd_id == pcc_ss_data->pcc_write_cnt) 349 desc->write_cmd_status = ret; 350 } 351 } 352 pcc_ss_data->pcc_write_cnt++; 353 wake_up_all(&pcc_ss_data->pcc_write_wait_q); 354 } 355 356 return ret; 357 } 358 359 static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret) 360 { 361 if (ret < 0) 362 pr_debug("TX did not complete: CMD sent:%x, ret:%d\n", 363 *(u16 *)msg, ret); 364 else 365 pr_debug("TX completed. CMD sent:%x, ret:%d\n", 366 *(u16 *)msg, ret); 367 } 368 369 static struct mbox_client cppc_mbox_cl = { 370 .tx_done = cppc_chan_tx_done, 371 .knows_txdone = true, 372 }; 373 374 static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle) 375 { 376 int result = -EFAULT; 377 acpi_status status = AE_OK; 378 struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL}; 379 struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"}; 380 struct acpi_buffer state = {0, NULL}; 381 union acpi_object *psd = NULL; 382 struct acpi_psd_package *pdomain; 383 384 status = acpi_evaluate_object_typed(handle, "_PSD", NULL, 385 &buffer, ACPI_TYPE_PACKAGE); 386 if (status == AE_NOT_FOUND) /* _PSD is optional */ 387 return 0; 388 if (ACPI_FAILURE(status)) 389 return -ENODEV; 390 391 psd = buffer.pointer; 392 if (!psd || psd->package.count != 1) { 393 pr_debug("Invalid _PSD data\n"); 394 goto end; 395 } 396 397 pdomain = &(cpc_ptr->domain_info); 398 399 state.length = sizeof(struct acpi_psd_package); 400 state.pointer = pdomain; 401 402 status = acpi_extract_package(&(psd->package.elements[0]), 403 &format, &state); 404 if (ACPI_FAILURE(status)) { 405 pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id); 406 goto end; 407 } 408 409 if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) { 410 pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id); 411 goto end; 412 } 413 414 if (pdomain->revision != ACPI_PSD_REV0_REVISION) { 415 pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id); 416 goto end; 417 } 418 419 if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL && 420 pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY && 421 pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) { 422 pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id); 423 goto end; 424 } 425 426 result = 0; 427 end: 428 kfree(buffer.pointer); 429 return result; 430 } 431 432 bool acpi_cpc_valid(void) 433 { 434 struct cpc_desc *cpc_ptr; 435 int cpu; 436 437 if (acpi_disabled) 438 return false; 439 440 for_each_present_cpu(cpu) { 441 cpc_ptr = per_cpu(cpc_desc_ptr, cpu); 442 if (!cpc_ptr) 443 return false; 444 } 445 446 return true; 447 } 448 EXPORT_SYMBOL_GPL(acpi_cpc_valid); 449 450 bool cppc_allow_fast_switch(void) 451 { 452 struct cpc_register_resource *desired_reg; 453 struct cpc_desc *cpc_ptr; 454 int cpu; 455 456 for_each_possible_cpu(cpu) { 457 cpc_ptr = per_cpu(cpc_desc_ptr, cpu); 458 desired_reg = &cpc_ptr->cpc_regs[DESIRED_PERF]; 459 if (!CPC_IN_SYSTEM_MEMORY(desired_reg) && 460 !CPC_IN_SYSTEM_IO(desired_reg)) 461 return false; 462 } 463 464 return true; 465 } 466 EXPORT_SYMBOL_GPL(cppc_allow_fast_switch); 467 468 /** 469 * acpi_get_psd_map - Map the CPUs in the freq domain of a given cpu 470 * @cpu: Find all CPUs that share a domain with cpu. 471 * @cpu_data: Pointer to CPU specific CPPC data including PSD info. 472 * 473 * Return: 0 for success or negative value for err. 474 */ 475 int acpi_get_psd_map(unsigned int cpu, struct cppc_cpudata *cpu_data) 476 { 477 struct cpc_desc *cpc_ptr, *match_cpc_ptr; 478 struct acpi_psd_package *match_pdomain; 479 struct acpi_psd_package *pdomain; 480 int count_target, i; 481 482 /* 483 * Now that we have _PSD data from all CPUs, let's setup P-state 484 * domain info. 485 */ 486 cpc_ptr = per_cpu(cpc_desc_ptr, cpu); 487 if (!cpc_ptr) 488 return -EFAULT; 489 490 pdomain = &(cpc_ptr->domain_info); 491 cpumask_set_cpu(cpu, cpu_data->shared_cpu_map); 492 if (pdomain->num_processors <= 1) 493 return 0; 494 495 /* Validate the Domain info */ 496 count_target = pdomain->num_processors; 497 if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL) 498 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ALL; 499 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL) 500 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_HW; 501 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY) 502 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ANY; 503 504 for_each_possible_cpu(i) { 505 if (i == cpu) 506 continue; 507 508 match_cpc_ptr = per_cpu(cpc_desc_ptr, i); 509 if (!match_cpc_ptr) 510 goto err_fault; 511 512 match_pdomain = &(match_cpc_ptr->domain_info); 513 if (match_pdomain->domain != pdomain->domain) 514 continue; 515 516 /* Here i and cpu are in the same domain */ 517 if (match_pdomain->num_processors != count_target) 518 goto err_fault; 519 520 if (pdomain->coord_type != match_pdomain->coord_type) 521 goto err_fault; 522 523 cpumask_set_cpu(i, cpu_data->shared_cpu_map); 524 } 525 526 return 0; 527 528 err_fault: 529 /* Assume no coordination on any error parsing domain info */ 530 cpumask_clear(cpu_data->shared_cpu_map); 531 cpumask_set_cpu(cpu, cpu_data->shared_cpu_map); 532 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_NONE; 533 534 return -EFAULT; 535 } 536 EXPORT_SYMBOL_GPL(acpi_get_psd_map); 537 538 static int register_pcc_channel(int pcc_ss_idx) 539 { 540 struct pcc_mbox_chan *pcc_chan; 541 u64 usecs_lat; 542 543 if (pcc_ss_idx >= 0) { 544 pcc_chan = pcc_mbox_request_channel(&cppc_mbox_cl, pcc_ss_idx); 545 546 if (IS_ERR(pcc_chan)) { 547 pr_err("Failed to find PCC channel for subspace %d\n", 548 pcc_ss_idx); 549 return -ENODEV; 550 } 551 552 pcc_data[pcc_ss_idx]->pcc_channel = pcc_chan; 553 /* 554 * cppc_ss->latency is just a Nominal value. In reality 555 * the remote processor could be much slower to reply. 556 * So add an arbitrary amount of wait on top of Nominal. 557 */ 558 usecs_lat = NUM_RETRIES * pcc_chan->latency; 559 pcc_data[pcc_ss_idx]->deadline_us = usecs_lat; 560 pcc_data[pcc_ss_idx]->pcc_mrtt = pcc_chan->min_turnaround_time; 561 pcc_data[pcc_ss_idx]->pcc_mpar = pcc_chan->max_access_rate; 562 pcc_data[pcc_ss_idx]->pcc_nominal = pcc_chan->latency; 563 564 pcc_data[pcc_ss_idx]->pcc_comm_addr = 565 acpi_os_ioremap(pcc_chan->shmem_base_addr, 566 pcc_chan->shmem_size); 567 if (!pcc_data[pcc_ss_idx]->pcc_comm_addr) { 568 pr_err("Failed to ioremap PCC comm region mem for %d\n", 569 pcc_ss_idx); 570 return -ENOMEM; 571 } 572 573 /* Set flag so that we don't come here for each CPU. */ 574 pcc_data[pcc_ss_idx]->pcc_channel_acquired = true; 575 } 576 577 return 0; 578 } 579 580 /** 581 * cpc_ffh_supported() - check if FFH reading supported 582 * 583 * Check if the architecture has support for functional fixed hardware 584 * read/write capability. 585 * 586 * Return: true for supported, false for not supported 587 */ 588 bool __weak cpc_ffh_supported(void) 589 { 590 return false; 591 } 592 593 /** 594 * cpc_supported_by_cpu() - check if CPPC is supported by CPU 595 * 596 * Check if the architectural support for CPPC is present even 597 * if the _OSC hasn't prescribed it 598 * 599 * Return: true for supported, false for not supported 600 */ 601 bool __weak cpc_supported_by_cpu(void) 602 { 603 return false; 604 } 605 606 /** 607 * pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace 608 * @pcc_ss_id: PCC Subspace index as in the PCC client ACPI package. 609 * 610 * Check and allocate the cppc_pcc_data memory. 611 * In some processor configurations it is possible that same subspace 612 * is shared between multiple CPUs. This is seen especially in CPUs 613 * with hardware multi-threading support. 614 * 615 * Return: 0 for success, errno for failure 616 */ 617 static int pcc_data_alloc(int pcc_ss_id) 618 { 619 if (pcc_ss_id < 0 || pcc_ss_id >= MAX_PCC_SUBSPACES) 620 return -EINVAL; 621 622 if (pcc_data[pcc_ss_id]) { 623 pcc_data[pcc_ss_id]->refcount++; 624 } else { 625 pcc_data[pcc_ss_id] = kzalloc(sizeof(struct cppc_pcc_data), 626 GFP_KERNEL); 627 if (!pcc_data[pcc_ss_id]) 628 return -ENOMEM; 629 pcc_data[pcc_ss_id]->refcount++; 630 } 631 632 return 0; 633 } 634 635 /* 636 * An example CPC table looks like the following. 637 * 638 * Name (_CPC, Package() { 639 * 17, // NumEntries 640 * 1, // Revision 641 * ResourceTemplate() {Register(PCC, 32, 0, 0x120, 2)}, // Highest Performance 642 * ResourceTemplate() {Register(PCC, 32, 0, 0x124, 2)}, // Nominal Performance 643 * ResourceTemplate() {Register(PCC, 32, 0, 0x128, 2)}, // Lowest Nonlinear Performance 644 * ResourceTemplate() {Register(PCC, 32, 0, 0x12C, 2)}, // Lowest Performance 645 * ResourceTemplate() {Register(PCC, 32, 0, 0x130, 2)}, // Guaranteed Performance Register 646 * ResourceTemplate() {Register(PCC, 32, 0, 0x110, 2)}, // Desired Performance Register 647 * ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, 648 * ... 649 * ... 650 * ... 651 * } 652 * Each Register() encodes how to access that specific register. 653 * e.g. a sample PCC entry has the following encoding: 654 * 655 * Register ( 656 * PCC, // AddressSpaceKeyword 657 * 8, // RegisterBitWidth 658 * 8, // RegisterBitOffset 659 * 0x30, // RegisterAddress 660 * 9, // AccessSize (subspace ID) 661 * ) 662 */ 663 664 #ifndef arch_init_invariance_cppc 665 static inline void arch_init_invariance_cppc(void) { } 666 #endif 667 668 /** 669 * acpi_cppc_processor_probe - Search for per CPU _CPC objects. 670 * @pr: Ptr to acpi_processor containing this CPU's logical ID. 671 * 672 * Return: 0 for success or negative value for err. 673 */ 674 int acpi_cppc_processor_probe(struct acpi_processor *pr) 675 { 676 struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL}; 677 union acpi_object *out_obj, *cpc_obj; 678 struct cpc_desc *cpc_ptr; 679 struct cpc_reg *gas_t; 680 struct device *cpu_dev; 681 acpi_handle handle = pr->handle; 682 unsigned int num_ent, i, cpc_rev; 683 int pcc_subspace_id = -1; 684 acpi_status status; 685 int ret = -ENODATA; 686 687 if (!osc_sb_cppc2_support_acked) { 688 pr_debug("CPPC v2 _OSC not acked\n"); 689 if (!cpc_supported_by_cpu()) 690 return -ENODEV; 691 } 692 693 /* Parse the ACPI _CPC table for this CPU. */ 694 status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output, 695 ACPI_TYPE_PACKAGE); 696 if (ACPI_FAILURE(status)) { 697 ret = -ENODEV; 698 goto out_buf_free; 699 } 700 701 out_obj = (union acpi_object *) output.pointer; 702 703 cpc_ptr = kzalloc(sizeof(struct cpc_desc), GFP_KERNEL); 704 if (!cpc_ptr) { 705 ret = -ENOMEM; 706 goto out_buf_free; 707 } 708 709 /* First entry is NumEntries. */ 710 cpc_obj = &out_obj->package.elements[0]; 711 if (cpc_obj->type == ACPI_TYPE_INTEGER) { 712 num_ent = cpc_obj->integer.value; 713 if (num_ent <= 1) { 714 pr_debug("Unexpected _CPC NumEntries value (%d) for CPU:%d\n", 715 num_ent, pr->id); 716 goto out_free; 717 } 718 } else { 719 pr_debug("Unexpected _CPC NumEntries entry type (%d) for CPU:%d\n", 720 cpc_obj->type, pr->id); 721 goto out_free; 722 } 723 724 /* Second entry should be revision. */ 725 cpc_obj = &out_obj->package.elements[1]; 726 if (cpc_obj->type == ACPI_TYPE_INTEGER) { 727 cpc_rev = cpc_obj->integer.value; 728 } else { 729 pr_debug("Unexpected _CPC Revision entry type (%d) for CPU:%d\n", 730 cpc_obj->type, pr->id); 731 goto out_free; 732 } 733 734 if (cpc_rev < CPPC_V2_REV) { 735 pr_debug("Unsupported _CPC Revision (%d) for CPU:%d\n", cpc_rev, 736 pr->id); 737 goto out_free; 738 } 739 740 /* 741 * Disregard _CPC if the number of entries in the return pachage is not 742 * as expected, but support future revisions being proper supersets of 743 * the v3 and only causing more entries to be returned by _CPC. 744 */ 745 if ((cpc_rev == CPPC_V2_REV && num_ent != CPPC_V2_NUM_ENT) || 746 (cpc_rev == CPPC_V3_REV && num_ent != CPPC_V3_NUM_ENT) || 747 (cpc_rev > CPPC_V3_REV && num_ent <= CPPC_V3_NUM_ENT)) { 748 pr_debug("Unexpected number of _CPC return package entries (%d) for CPU:%d\n", 749 num_ent, pr->id); 750 goto out_free; 751 } 752 if (cpc_rev > CPPC_V3_REV) { 753 num_ent = CPPC_V3_NUM_ENT; 754 cpc_rev = CPPC_V3_REV; 755 } 756 757 cpc_ptr->num_entries = num_ent; 758 cpc_ptr->version = cpc_rev; 759 760 /* Iterate through remaining entries in _CPC */ 761 for (i = 2; i < num_ent; i++) { 762 cpc_obj = &out_obj->package.elements[i]; 763 764 if (cpc_obj->type == ACPI_TYPE_INTEGER) { 765 cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER; 766 cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value; 767 } else if (cpc_obj->type == ACPI_TYPE_BUFFER) { 768 gas_t = (struct cpc_reg *) 769 cpc_obj->buffer.pointer; 770 771 /* 772 * The PCC Subspace index is encoded inside 773 * the CPC table entries. The same PCC index 774 * will be used for all the PCC entries, 775 * so extract it only once. 776 */ 777 if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) { 778 if (pcc_subspace_id < 0) { 779 pcc_subspace_id = gas_t->access_width; 780 if (pcc_data_alloc(pcc_subspace_id)) 781 goto out_free; 782 } else if (pcc_subspace_id != gas_t->access_width) { 783 pr_debug("Mismatched PCC ids in _CPC for CPU:%d\n", 784 pr->id); 785 goto out_free; 786 } 787 } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) { 788 if (gas_t->address) { 789 void __iomem *addr; 790 size_t access_width; 791 792 if (!osc_cpc_flexible_adr_space_confirmed) { 793 pr_debug("Flexible address space capability not supported\n"); 794 if (!cpc_supported_by_cpu()) 795 goto out_free; 796 } 797 798 access_width = GET_BIT_WIDTH(gas_t) / 8; 799 addr = ioremap(gas_t->address, access_width); 800 if (!addr) 801 goto out_free; 802 cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr; 803 } 804 } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_IO) { 805 if (gas_t->access_width < 1 || gas_t->access_width > 3) { 806 /* 807 * 1 = 8-bit, 2 = 16-bit, and 3 = 32-bit. 808 * SystemIO doesn't implement 64-bit 809 * registers. 810 */ 811 pr_debug("Invalid access width %d for SystemIO register in _CPC\n", 812 gas_t->access_width); 813 goto out_free; 814 } 815 if (gas_t->address & OVER_16BTS_MASK) { 816 /* SystemIO registers use 16-bit integer addresses */ 817 pr_debug("Invalid IO port %llu for SystemIO register in _CPC\n", 818 gas_t->address); 819 goto out_free; 820 } 821 if (!osc_cpc_flexible_adr_space_confirmed) { 822 pr_debug("Flexible address space capability not supported\n"); 823 if (!cpc_supported_by_cpu()) 824 goto out_free; 825 } 826 } else { 827 if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) { 828 /* Support only PCC, SystemMemory, SystemIO, and FFH type regs. */ 829 pr_debug("Unsupported register type (%d) in _CPC\n", 830 gas_t->space_id); 831 goto out_free; 832 } 833 } 834 835 cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER; 836 memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t)); 837 } else { 838 pr_debug("Invalid entry type (%d) in _CPC for CPU:%d\n", 839 i, pr->id); 840 goto out_free; 841 } 842 } 843 per_cpu(cpu_pcc_subspace_idx, pr->id) = pcc_subspace_id; 844 845 /* 846 * Initialize the remaining cpc_regs as unsupported. 847 * Example: In case FW exposes CPPC v2, the below loop will initialize 848 * LOWEST_FREQ and NOMINAL_FREQ regs as unsupported 849 */ 850 for (i = num_ent - 2; i < MAX_CPC_REG_ENT; i++) { 851 cpc_ptr->cpc_regs[i].type = ACPI_TYPE_INTEGER; 852 cpc_ptr->cpc_regs[i].cpc_entry.int_value = 0; 853 } 854 855 856 /* Store CPU Logical ID */ 857 cpc_ptr->cpu_id = pr->id; 858 spin_lock_init(&cpc_ptr->rmw_lock); 859 860 /* Parse PSD data for this CPU */ 861 ret = acpi_get_psd(cpc_ptr, handle); 862 if (ret) 863 goto out_free; 864 865 /* Register PCC channel once for all PCC subspace ID. */ 866 if (pcc_subspace_id >= 0 && !pcc_data[pcc_subspace_id]->pcc_channel_acquired) { 867 ret = register_pcc_channel(pcc_subspace_id); 868 if (ret) 869 goto out_free; 870 871 init_rwsem(&pcc_data[pcc_subspace_id]->pcc_lock); 872 init_waitqueue_head(&pcc_data[pcc_subspace_id]->pcc_write_wait_q); 873 } 874 875 /* Everything looks okay */ 876 pr_debug("Parsed CPC struct for CPU: %d\n", pr->id); 877 878 /* Add per logical CPU nodes for reading its feedback counters. */ 879 cpu_dev = get_cpu_device(pr->id); 880 if (!cpu_dev) { 881 ret = -EINVAL; 882 goto out_free; 883 } 884 885 /* Plug PSD data into this CPU's CPC descriptor. */ 886 per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr; 887 888 ret = kobject_init_and_add(&cpc_ptr->kobj, &cppc_ktype, &cpu_dev->kobj, 889 "acpi_cppc"); 890 if (ret) { 891 per_cpu(cpc_desc_ptr, pr->id) = NULL; 892 kobject_put(&cpc_ptr->kobj); 893 goto out_free; 894 } 895 896 arch_init_invariance_cppc(); 897 898 kfree(output.pointer); 899 return 0; 900 901 out_free: 902 /* Free all the mapped sys mem areas for this CPU */ 903 for (i = 2; i < cpc_ptr->num_entries; i++) { 904 void __iomem *addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr; 905 906 if (addr) 907 iounmap(addr); 908 } 909 kfree(cpc_ptr); 910 911 out_buf_free: 912 kfree(output.pointer); 913 return ret; 914 } 915 EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe); 916 917 /** 918 * acpi_cppc_processor_exit - Cleanup CPC structs. 919 * @pr: Ptr to acpi_processor containing this CPU's logical ID. 920 * 921 * Return: Void 922 */ 923 void acpi_cppc_processor_exit(struct acpi_processor *pr) 924 { 925 struct cpc_desc *cpc_ptr; 926 unsigned int i; 927 void __iomem *addr; 928 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id); 929 930 if (pcc_ss_id >= 0 && pcc_data[pcc_ss_id]) { 931 if (pcc_data[pcc_ss_id]->pcc_channel_acquired) { 932 pcc_data[pcc_ss_id]->refcount--; 933 if (!pcc_data[pcc_ss_id]->refcount) { 934 pcc_mbox_free_channel(pcc_data[pcc_ss_id]->pcc_channel); 935 kfree(pcc_data[pcc_ss_id]); 936 pcc_data[pcc_ss_id] = NULL; 937 } 938 } 939 } 940 941 cpc_ptr = per_cpu(cpc_desc_ptr, pr->id); 942 if (!cpc_ptr) 943 return; 944 945 /* Free all the mapped sys mem areas for this CPU */ 946 for (i = 2; i < cpc_ptr->num_entries; i++) { 947 addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr; 948 if (addr) 949 iounmap(addr); 950 } 951 952 kobject_put(&cpc_ptr->kobj); 953 kfree(cpc_ptr); 954 } 955 EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit); 956 957 /** 958 * cpc_read_ffh() - Read FFH register 959 * @cpunum: CPU number to read 960 * @reg: cppc register information 961 * @val: place holder for return value 962 * 963 * Read bit_width bits from a specified address and bit_offset 964 * 965 * Return: 0 for success and error code 966 */ 967 int __weak cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val) 968 { 969 return -ENOTSUPP; 970 } 971 972 /** 973 * cpc_write_ffh() - Write FFH register 974 * @cpunum: CPU number to write 975 * @reg: cppc register information 976 * @val: value to write 977 * 978 * Write value of bit_width bits to a specified address and bit_offset 979 * 980 * Return: 0 for success and error code 981 */ 982 int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val) 983 { 984 return -ENOTSUPP; 985 } 986 987 /* 988 * Since cpc_read and cpc_write are called while holding pcc_lock, it should be 989 * as fast as possible. We have already mapped the PCC subspace during init, so 990 * we can directly write to it. 991 */ 992 993 static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val) 994 { 995 void __iomem *vaddr = NULL; 996 int size; 997 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); 998 struct cpc_reg *reg = ®_res->cpc_entry.reg; 999 1000 if (reg_res->type == ACPI_TYPE_INTEGER) { 1001 *val = reg_res->cpc_entry.int_value; 1002 return 0; 1003 } 1004 1005 *val = 0; 1006 size = GET_BIT_WIDTH(reg); 1007 1008 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) { 1009 u32 val_u32; 1010 acpi_status status; 1011 1012 status = acpi_os_read_port((acpi_io_address)reg->address, 1013 &val_u32, size); 1014 if (ACPI_FAILURE(status)) { 1015 pr_debug("Error: Failed to read SystemIO port %llx\n", 1016 reg->address); 1017 return -EFAULT; 1018 } 1019 1020 *val = val_u32; 1021 return 0; 1022 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) { 1023 /* 1024 * For registers in PCC space, the register size is determined 1025 * by the bit width field; the access size is used to indicate 1026 * the PCC subspace id. 1027 */ 1028 size = reg->bit_width; 1029 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id); 1030 } 1031 else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) 1032 vaddr = reg_res->sys_mem_vaddr; 1033 else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) 1034 return cpc_read_ffh(cpu, reg, val); 1035 else 1036 return acpi_os_read_memory((acpi_physical_address)reg->address, 1037 val, size); 1038 1039 switch (size) { 1040 case 8: 1041 *val = readb_relaxed(vaddr); 1042 break; 1043 case 16: 1044 *val = readw_relaxed(vaddr); 1045 break; 1046 case 32: 1047 *val = readl_relaxed(vaddr); 1048 break; 1049 case 64: 1050 *val = readq_relaxed(vaddr); 1051 break; 1052 default: 1053 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) { 1054 pr_debug("Error: Cannot read %u bit width from system memory: 0x%llx\n", 1055 size, reg->address); 1056 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) { 1057 pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n", 1058 size, pcc_ss_id); 1059 } 1060 return -EFAULT; 1061 } 1062 1063 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) 1064 *val = MASK_VAL_READ(reg, *val); 1065 1066 return 0; 1067 } 1068 1069 static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val) 1070 { 1071 int ret_val = 0; 1072 int size; 1073 u64 prev_val; 1074 void __iomem *vaddr = NULL; 1075 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); 1076 struct cpc_reg *reg = ®_res->cpc_entry.reg; 1077 struct cpc_desc *cpc_desc; 1078 1079 size = GET_BIT_WIDTH(reg); 1080 1081 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) { 1082 acpi_status status; 1083 1084 status = acpi_os_write_port((acpi_io_address)reg->address, 1085 (u32)val, size); 1086 if (ACPI_FAILURE(status)) { 1087 pr_debug("Error: Failed to write SystemIO port %llx\n", 1088 reg->address); 1089 return -EFAULT; 1090 } 1091 1092 return 0; 1093 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) { 1094 /* 1095 * For registers in PCC space, the register size is determined 1096 * by the bit width field; the access size is used to indicate 1097 * the PCC subspace id. 1098 */ 1099 size = reg->bit_width; 1100 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id); 1101 } 1102 else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) 1103 vaddr = reg_res->sys_mem_vaddr; 1104 else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) 1105 return cpc_write_ffh(cpu, reg, val); 1106 else 1107 return acpi_os_write_memory((acpi_physical_address)reg->address, 1108 val, size); 1109 1110 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) { 1111 cpc_desc = per_cpu(cpc_desc_ptr, cpu); 1112 if (!cpc_desc) { 1113 pr_debug("No CPC descriptor for CPU:%d\n", cpu); 1114 return -ENODEV; 1115 } 1116 1117 spin_lock(&cpc_desc->rmw_lock); 1118 switch (size) { 1119 case 8: 1120 prev_val = readb_relaxed(vaddr); 1121 break; 1122 case 16: 1123 prev_val = readw_relaxed(vaddr); 1124 break; 1125 case 32: 1126 prev_val = readl_relaxed(vaddr); 1127 break; 1128 case 64: 1129 prev_val = readq_relaxed(vaddr); 1130 break; 1131 default: 1132 spin_unlock(&cpc_desc->rmw_lock); 1133 return -EFAULT; 1134 } 1135 val = MASK_VAL_WRITE(reg, prev_val, val); 1136 val |= prev_val; 1137 } 1138 1139 switch (size) { 1140 case 8: 1141 writeb_relaxed(val, vaddr); 1142 break; 1143 case 16: 1144 writew_relaxed(val, vaddr); 1145 break; 1146 case 32: 1147 writel_relaxed(val, vaddr); 1148 break; 1149 case 64: 1150 writeq_relaxed(val, vaddr); 1151 break; 1152 default: 1153 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) { 1154 pr_debug("Error: Cannot write %u bit width to system memory: 0x%llx\n", 1155 size, reg->address); 1156 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) { 1157 pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n", 1158 size, pcc_ss_id); 1159 } 1160 ret_val = -EFAULT; 1161 break; 1162 } 1163 1164 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) 1165 spin_unlock(&cpc_desc->rmw_lock); 1166 1167 return ret_val; 1168 } 1169 1170 static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf) 1171 { 1172 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); 1173 struct cpc_register_resource *reg; 1174 1175 if (!cpc_desc) { 1176 pr_debug("No CPC descriptor for CPU:%d\n", cpunum); 1177 return -ENODEV; 1178 } 1179 1180 reg = &cpc_desc->cpc_regs[reg_idx]; 1181 1182 if (CPC_IN_PCC(reg)) { 1183 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); 1184 struct cppc_pcc_data *pcc_ss_data = NULL; 1185 int ret = 0; 1186 1187 if (pcc_ss_id < 0) 1188 return -EIO; 1189 1190 pcc_ss_data = pcc_data[pcc_ss_id]; 1191 1192 down_write(&pcc_ss_data->pcc_lock); 1193 1194 if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) 1195 cpc_read(cpunum, reg, perf); 1196 else 1197 ret = -EIO; 1198 1199 up_write(&pcc_ss_data->pcc_lock); 1200 1201 return ret; 1202 } 1203 1204 cpc_read(cpunum, reg, perf); 1205 1206 return 0; 1207 } 1208 1209 /** 1210 * cppc_get_desired_perf - Get the desired performance register value. 1211 * @cpunum: CPU from which to get desired performance. 1212 * @desired_perf: Return address. 1213 * 1214 * Return: 0 for success, -EIO otherwise. 1215 */ 1216 int cppc_get_desired_perf(int cpunum, u64 *desired_perf) 1217 { 1218 return cppc_get_perf(cpunum, DESIRED_PERF, desired_perf); 1219 } 1220 EXPORT_SYMBOL_GPL(cppc_get_desired_perf); 1221 1222 /** 1223 * cppc_get_nominal_perf - Get the nominal performance register value. 1224 * @cpunum: CPU from which to get nominal performance. 1225 * @nominal_perf: Return address. 1226 * 1227 * Return: 0 for success, -EIO otherwise. 1228 */ 1229 int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf) 1230 { 1231 return cppc_get_perf(cpunum, NOMINAL_PERF, nominal_perf); 1232 } 1233 1234 /** 1235 * cppc_get_highest_perf - Get the highest performance register value. 1236 * @cpunum: CPU from which to get highest performance. 1237 * @highest_perf: Return address. 1238 * 1239 * Return: 0 for success, -EIO otherwise. 1240 */ 1241 int cppc_get_highest_perf(int cpunum, u64 *highest_perf) 1242 { 1243 return cppc_get_perf(cpunum, HIGHEST_PERF, highest_perf); 1244 } 1245 EXPORT_SYMBOL_GPL(cppc_get_highest_perf); 1246 1247 /** 1248 * cppc_get_epp_perf - Get the epp register value. 1249 * @cpunum: CPU from which to get epp preference value. 1250 * @epp_perf: Return address. 1251 * 1252 * Return: 0 for success, -EIO otherwise. 1253 */ 1254 int cppc_get_epp_perf(int cpunum, u64 *epp_perf) 1255 { 1256 return cppc_get_perf(cpunum, ENERGY_PERF, epp_perf); 1257 } 1258 EXPORT_SYMBOL_GPL(cppc_get_epp_perf); 1259 1260 /** 1261 * cppc_get_perf_caps - Get a CPU's performance capabilities. 1262 * @cpunum: CPU from which to get capabilities info. 1263 * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h 1264 * 1265 * Return: 0 for success with perf_caps populated else -ERRNO. 1266 */ 1267 int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps) 1268 { 1269 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); 1270 struct cpc_register_resource *highest_reg, *lowest_reg, 1271 *lowest_non_linear_reg, *nominal_reg, *guaranteed_reg, 1272 *low_freq_reg = NULL, *nom_freq_reg = NULL; 1273 u64 high, low, guaranteed, nom, min_nonlinear, low_f = 0, nom_f = 0; 1274 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); 1275 struct cppc_pcc_data *pcc_ss_data = NULL; 1276 int ret = 0, regs_in_pcc = 0; 1277 1278 if (!cpc_desc) { 1279 pr_debug("No CPC descriptor for CPU:%d\n", cpunum); 1280 return -ENODEV; 1281 } 1282 1283 highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF]; 1284 lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF]; 1285 lowest_non_linear_reg = &cpc_desc->cpc_regs[LOW_NON_LINEAR_PERF]; 1286 nominal_reg = &cpc_desc->cpc_regs[NOMINAL_PERF]; 1287 low_freq_reg = &cpc_desc->cpc_regs[LOWEST_FREQ]; 1288 nom_freq_reg = &cpc_desc->cpc_regs[NOMINAL_FREQ]; 1289 guaranteed_reg = &cpc_desc->cpc_regs[GUARANTEED_PERF]; 1290 1291 /* Are any of the regs PCC ?*/ 1292 if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) || 1293 CPC_IN_PCC(lowest_non_linear_reg) || CPC_IN_PCC(nominal_reg) || 1294 CPC_IN_PCC(low_freq_reg) || CPC_IN_PCC(nom_freq_reg)) { 1295 if (pcc_ss_id < 0) { 1296 pr_debug("Invalid pcc_ss_id\n"); 1297 return -ENODEV; 1298 } 1299 pcc_ss_data = pcc_data[pcc_ss_id]; 1300 regs_in_pcc = 1; 1301 down_write(&pcc_ss_data->pcc_lock); 1302 /* Ring doorbell once to update PCC subspace */ 1303 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) { 1304 ret = -EIO; 1305 goto out_err; 1306 } 1307 } 1308 1309 cpc_read(cpunum, highest_reg, &high); 1310 perf_caps->highest_perf = high; 1311 1312 cpc_read(cpunum, lowest_reg, &low); 1313 perf_caps->lowest_perf = low; 1314 1315 cpc_read(cpunum, nominal_reg, &nom); 1316 perf_caps->nominal_perf = nom; 1317 1318 if (guaranteed_reg->type != ACPI_TYPE_BUFFER || 1319 IS_NULL_REG(&guaranteed_reg->cpc_entry.reg)) { 1320 perf_caps->guaranteed_perf = 0; 1321 } else { 1322 cpc_read(cpunum, guaranteed_reg, &guaranteed); 1323 perf_caps->guaranteed_perf = guaranteed; 1324 } 1325 1326 cpc_read(cpunum, lowest_non_linear_reg, &min_nonlinear); 1327 perf_caps->lowest_nonlinear_perf = min_nonlinear; 1328 1329 if (!high || !low || !nom || !min_nonlinear) 1330 ret = -EFAULT; 1331 1332 /* Read optional lowest and nominal frequencies if present */ 1333 if (CPC_SUPPORTED(low_freq_reg)) 1334 cpc_read(cpunum, low_freq_reg, &low_f); 1335 1336 if (CPC_SUPPORTED(nom_freq_reg)) 1337 cpc_read(cpunum, nom_freq_reg, &nom_f); 1338 1339 perf_caps->lowest_freq = low_f; 1340 perf_caps->nominal_freq = nom_f; 1341 1342 1343 out_err: 1344 if (regs_in_pcc) 1345 up_write(&pcc_ss_data->pcc_lock); 1346 return ret; 1347 } 1348 EXPORT_SYMBOL_GPL(cppc_get_perf_caps); 1349 1350 /** 1351 * cppc_perf_ctrs_in_pcc - Check if any perf counters are in a PCC region. 1352 * 1353 * CPPC has flexibility about how CPU performance counters are accessed. 1354 * One of the choices is PCC regions, which can have a high access latency. This 1355 * routine allows callers of cppc_get_perf_ctrs() to know this ahead of time. 1356 * 1357 * Return: true if any of the counters are in PCC regions, false otherwise 1358 */ 1359 bool cppc_perf_ctrs_in_pcc(void) 1360 { 1361 int cpu; 1362 1363 for_each_present_cpu(cpu) { 1364 struct cpc_register_resource *ref_perf_reg; 1365 struct cpc_desc *cpc_desc; 1366 1367 cpc_desc = per_cpu(cpc_desc_ptr, cpu); 1368 1369 if (CPC_IN_PCC(&cpc_desc->cpc_regs[DELIVERED_CTR]) || 1370 CPC_IN_PCC(&cpc_desc->cpc_regs[REFERENCE_CTR]) || 1371 CPC_IN_PCC(&cpc_desc->cpc_regs[CTR_WRAP_TIME])) 1372 return true; 1373 1374 1375 ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF]; 1376 1377 /* 1378 * If reference perf register is not supported then we should 1379 * use the nominal perf value 1380 */ 1381 if (!CPC_SUPPORTED(ref_perf_reg)) 1382 ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF]; 1383 1384 if (CPC_IN_PCC(ref_perf_reg)) 1385 return true; 1386 } 1387 1388 return false; 1389 } 1390 EXPORT_SYMBOL_GPL(cppc_perf_ctrs_in_pcc); 1391 1392 /** 1393 * cppc_get_perf_ctrs - Read a CPU's performance feedback counters. 1394 * @cpunum: CPU from which to read counters. 1395 * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h 1396 * 1397 * Return: 0 for success with perf_fb_ctrs populated else -ERRNO. 1398 */ 1399 int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) 1400 { 1401 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); 1402 struct cpc_register_resource *delivered_reg, *reference_reg, 1403 *ref_perf_reg, *ctr_wrap_reg; 1404 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); 1405 struct cppc_pcc_data *pcc_ss_data = NULL; 1406 u64 delivered, reference, ref_perf, ctr_wrap_time; 1407 int ret = 0, regs_in_pcc = 0; 1408 1409 if (!cpc_desc) { 1410 pr_debug("No CPC descriptor for CPU:%d\n", cpunum); 1411 return -ENODEV; 1412 } 1413 1414 delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR]; 1415 reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR]; 1416 ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF]; 1417 ctr_wrap_reg = &cpc_desc->cpc_regs[CTR_WRAP_TIME]; 1418 1419 /* 1420 * If reference perf register is not supported then we should 1421 * use the nominal perf value 1422 */ 1423 if (!CPC_SUPPORTED(ref_perf_reg)) 1424 ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF]; 1425 1426 /* Are any of the regs PCC ?*/ 1427 if (CPC_IN_PCC(delivered_reg) || CPC_IN_PCC(reference_reg) || 1428 CPC_IN_PCC(ctr_wrap_reg) || CPC_IN_PCC(ref_perf_reg)) { 1429 if (pcc_ss_id < 0) { 1430 pr_debug("Invalid pcc_ss_id\n"); 1431 return -ENODEV; 1432 } 1433 pcc_ss_data = pcc_data[pcc_ss_id]; 1434 down_write(&pcc_ss_data->pcc_lock); 1435 regs_in_pcc = 1; 1436 /* Ring doorbell once to update PCC subspace */ 1437 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) { 1438 ret = -EIO; 1439 goto out_err; 1440 } 1441 } 1442 1443 cpc_read(cpunum, delivered_reg, &delivered); 1444 cpc_read(cpunum, reference_reg, &reference); 1445 cpc_read(cpunum, ref_perf_reg, &ref_perf); 1446 1447 /* 1448 * Per spec, if ctr_wrap_time optional register is unsupported, then the 1449 * performance counters are assumed to never wrap during the lifetime of 1450 * platform 1451 */ 1452 ctr_wrap_time = (u64)(~((u64)0)); 1453 if (CPC_SUPPORTED(ctr_wrap_reg)) 1454 cpc_read(cpunum, ctr_wrap_reg, &ctr_wrap_time); 1455 1456 if (!delivered || !reference || !ref_perf) { 1457 ret = -EFAULT; 1458 goto out_err; 1459 } 1460 1461 perf_fb_ctrs->delivered = delivered; 1462 perf_fb_ctrs->reference = reference; 1463 perf_fb_ctrs->reference_perf = ref_perf; 1464 perf_fb_ctrs->wraparound_time = ctr_wrap_time; 1465 out_err: 1466 if (regs_in_pcc) 1467 up_write(&pcc_ss_data->pcc_lock); 1468 return ret; 1469 } 1470 EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs); 1471 1472 /* 1473 * Set Energy Performance Preference Register value through 1474 * Performance Controls Interface 1475 */ 1476 int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable) 1477 { 1478 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); 1479 struct cpc_register_resource *epp_set_reg; 1480 struct cpc_register_resource *auto_sel_reg; 1481 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); 1482 struct cppc_pcc_data *pcc_ss_data = NULL; 1483 int ret; 1484 1485 if (!cpc_desc) { 1486 pr_debug("No CPC descriptor for CPU:%d\n", cpu); 1487 return -ENODEV; 1488 } 1489 1490 auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE]; 1491 epp_set_reg = &cpc_desc->cpc_regs[ENERGY_PERF]; 1492 1493 if (CPC_IN_PCC(epp_set_reg) || CPC_IN_PCC(auto_sel_reg)) { 1494 if (pcc_ss_id < 0) { 1495 pr_debug("Invalid pcc_ss_id for CPU:%d\n", cpu); 1496 return -ENODEV; 1497 } 1498 1499 if (CPC_SUPPORTED(auto_sel_reg)) { 1500 ret = cpc_write(cpu, auto_sel_reg, enable); 1501 if (ret) 1502 return ret; 1503 } 1504 1505 if (CPC_SUPPORTED(epp_set_reg)) { 1506 ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf); 1507 if (ret) 1508 return ret; 1509 } 1510 1511 pcc_ss_data = pcc_data[pcc_ss_id]; 1512 1513 down_write(&pcc_ss_data->pcc_lock); 1514 /* after writing CPC, transfer the ownership of PCC to platform */ 1515 ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE); 1516 up_write(&pcc_ss_data->pcc_lock); 1517 } else { 1518 ret = -ENOTSUPP; 1519 pr_debug("_CPC in PCC is not supported\n"); 1520 } 1521 1522 return ret; 1523 } 1524 EXPORT_SYMBOL_GPL(cppc_set_epp_perf); 1525 1526 /** 1527 * cppc_get_auto_sel_caps - Read autonomous selection register. 1528 * @cpunum : CPU from which to read register. 1529 * @perf_caps : struct where autonomous selection register value is updated. 1530 */ 1531 int cppc_get_auto_sel_caps(int cpunum, struct cppc_perf_caps *perf_caps) 1532 { 1533 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); 1534 struct cpc_register_resource *auto_sel_reg; 1535 u64 auto_sel; 1536 1537 if (!cpc_desc) { 1538 pr_debug("No CPC descriptor for CPU:%d\n", cpunum); 1539 return -ENODEV; 1540 } 1541 1542 auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE]; 1543 1544 if (!CPC_SUPPORTED(auto_sel_reg)) 1545 pr_warn_once("Autonomous mode is not unsupported!\n"); 1546 1547 if (CPC_IN_PCC(auto_sel_reg)) { 1548 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); 1549 struct cppc_pcc_data *pcc_ss_data = NULL; 1550 int ret = 0; 1551 1552 if (pcc_ss_id < 0) 1553 return -ENODEV; 1554 1555 pcc_ss_data = pcc_data[pcc_ss_id]; 1556 1557 down_write(&pcc_ss_data->pcc_lock); 1558 1559 if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) { 1560 cpc_read(cpunum, auto_sel_reg, &auto_sel); 1561 perf_caps->auto_sel = (bool)auto_sel; 1562 } else { 1563 ret = -EIO; 1564 } 1565 1566 up_write(&pcc_ss_data->pcc_lock); 1567 1568 return ret; 1569 } 1570 1571 return 0; 1572 } 1573 EXPORT_SYMBOL_GPL(cppc_get_auto_sel_caps); 1574 1575 /** 1576 * cppc_set_auto_sel - Write autonomous selection register. 1577 * @cpu : CPU to which to write register. 1578 * @enable : the desired value of autonomous selection resiter to be updated. 1579 */ 1580 int cppc_set_auto_sel(int cpu, bool enable) 1581 { 1582 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); 1583 struct cpc_register_resource *auto_sel_reg; 1584 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); 1585 struct cppc_pcc_data *pcc_ss_data = NULL; 1586 int ret = -EINVAL; 1587 1588 if (!cpc_desc) { 1589 pr_debug("No CPC descriptor for CPU:%d\n", cpu); 1590 return -ENODEV; 1591 } 1592 1593 auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE]; 1594 1595 if (CPC_IN_PCC(auto_sel_reg)) { 1596 if (pcc_ss_id < 0) { 1597 pr_debug("Invalid pcc_ss_id\n"); 1598 return -ENODEV; 1599 } 1600 1601 if (CPC_SUPPORTED(auto_sel_reg)) { 1602 ret = cpc_write(cpu, auto_sel_reg, enable); 1603 if (ret) 1604 return ret; 1605 } 1606 1607 pcc_ss_data = pcc_data[pcc_ss_id]; 1608 1609 down_write(&pcc_ss_data->pcc_lock); 1610 /* after writing CPC, transfer the ownership of PCC to platform */ 1611 ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE); 1612 up_write(&pcc_ss_data->pcc_lock); 1613 } else { 1614 ret = -ENOTSUPP; 1615 pr_debug("_CPC in PCC is not supported\n"); 1616 } 1617 1618 return ret; 1619 } 1620 EXPORT_SYMBOL_GPL(cppc_set_auto_sel); 1621 1622 /** 1623 * cppc_set_enable - Set to enable CPPC on the processor by writing the 1624 * Continuous Performance Control package EnableRegister field. 1625 * @cpu: CPU for which to enable CPPC register. 1626 * @enable: 0 - disable, 1 - enable CPPC feature on the processor. 1627 * 1628 * Return: 0 for success, -ERRNO or -EIO otherwise. 1629 */ 1630 int cppc_set_enable(int cpu, bool enable) 1631 { 1632 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); 1633 struct cpc_register_resource *enable_reg; 1634 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); 1635 struct cppc_pcc_data *pcc_ss_data = NULL; 1636 int ret = -EINVAL; 1637 1638 if (!cpc_desc) { 1639 pr_debug("No CPC descriptor for CPU:%d\n", cpu); 1640 return -EINVAL; 1641 } 1642 1643 enable_reg = &cpc_desc->cpc_regs[ENABLE]; 1644 1645 if (CPC_IN_PCC(enable_reg)) { 1646 1647 if (pcc_ss_id < 0) 1648 return -EIO; 1649 1650 ret = cpc_write(cpu, enable_reg, enable); 1651 if (ret) 1652 return ret; 1653 1654 pcc_ss_data = pcc_data[pcc_ss_id]; 1655 1656 down_write(&pcc_ss_data->pcc_lock); 1657 /* after writing CPC, transfer the ownership of PCC to platfrom */ 1658 ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE); 1659 up_write(&pcc_ss_data->pcc_lock); 1660 return ret; 1661 } 1662 1663 return cpc_write(cpu, enable_reg, enable); 1664 } 1665 EXPORT_SYMBOL_GPL(cppc_set_enable); 1666 1667 /** 1668 * cppc_set_perf - Set a CPU's performance controls. 1669 * @cpu: CPU for which to set performance controls. 1670 * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h 1671 * 1672 * Return: 0 for success, -ERRNO otherwise. 1673 */ 1674 int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) 1675 { 1676 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); 1677 struct cpc_register_resource *desired_reg, *min_perf_reg, *max_perf_reg; 1678 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); 1679 struct cppc_pcc_data *pcc_ss_data = NULL; 1680 int ret = 0; 1681 1682 if (!cpc_desc) { 1683 pr_debug("No CPC descriptor for CPU:%d\n", cpu); 1684 return -ENODEV; 1685 } 1686 1687 desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; 1688 min_perf_reg = &cpc_desc->cpc_regs[MIN_PERF]; 1689 max_perf_reg = &cpc_desc->cpc_regs[MAX_PERF]; 1690 1691 /* 1692 * This is Phase-I where we want to write to CPC registers 1693 * -> We want all CPUs to be able to execute this phase in parallel 1694 * 1695 * Since read_lock can be acquired by multiple CPUs simultaneously we 1696 * achieve that goal here 1697 */ 1698 if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg)) { 1699 if (pcc_ss_id < 0) { 1700 pr_debug("Invalid pcc_ss_id\n"); 1701 return -ENODEV; 1702 } 1703 pcc_ss_data = pcc_data[pcc_ss_id]; 1704 down_read(&pcc_ss_data->pcc_lock); /* BEGIN Phase-I */ 1705 if (pcc_ss_data->platform_owns_pcc) { 1706 ret = check_pcc_chan(pcc_ss_id, false); 1707 if (ret) { 1708 up_read(&pcc_ss_data->pcc_lock); 1709 return ret; 1710 } 1711 } 1712 /* 1713 * Update the pending_write to make sure a PCC CMD_READ will not 1714 * arrive and steal the channel during the switch to write lock 1715 */ 1716 pcc_ss_data->pending_pcc_write_cmd = true; 1717 cpc_desc->write_cmd_id = pcc_ss_data->pcc_write_cnt; 1718 cpc_desc->write_cmd_status = 0; 1719 } 1720 1721 cpc_write(cpu, desired_reg, perf_ctrls->desired_perf); 1722 1723 /* 1724 * Only write if min_perf and max_perf not zero. Some drivers pass zero 1725 * value to min and max perf, but they don't mean to set the zero value, 1726 * they just don't want to write to those registers. 1727 */ 1728 if (perf_ctrls->min_perf) 1729 cpc_write(cpu, min_perf_reg, perf_ctrls->min_perf); 1730 if (perf_ctrls->max_perf) 1731 cpc_write(cpu, max_perf_reg, perf_ctrls->max_perf); 1732 1733 if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg)) 1734 up_read(&pcc_ss_data->pcc_lock); /* END Phase-I */ 1735 /* 1736 * This is Phase-II where we transfer the ownership of PCC to Platform 1737 * 1738 * Short Summary: Basically if we think of a group of cppc_set_perf 1739 * requests that happened in short overlapping interval. The last CPU to 1740 * come out of Phase-I will enter Phase-II and ring the doorbell. 1741 * 1742 * We have the following requirements for Phase-II: 1743 * 1. We want to execute Phase-II only when there are no CPUs 1744 * currently executing in Phase-I 1745 * 2. Once we start Phase-II we want to avoid all other CPUs from 1746 * entering Phase-I. 1747 * 3. We want only one CPU among all those who went through Phase-I 1748 * to run phase-II 1749 * 1750 * If write_trylock fails to get the lock and doesn't transfer the 1751 * PCC ownership to the platform, then one of the following will be TRUE 1752 * 1. There is at-least one CPU in Phase-I which will later execute 1753 * write_trylock, so the CPUs in Phase-I will be responsible for 1754 * executing the Phase-II. 1755 * 2. Some other CPU has beaten this CPU to successfully execute the 1756 * write_trylock and has already acquired the write_lock. We know for a 1757 * fact it (other CPU acquiring the write_lock) couldn't have happened 1758 * before this CPU's Phase-I as we held the read_lock. 1759 * 3. Some other CPU executing pcc CMD_READ has stolen the 1760 * down_write, in which case, send_pcc_cmd will check for pending 1761 * CMD_WRITE commands by checking the pending_pcc_write_cmd. 1762 * So this CPU can be certain that its request will be delivered 1763 * So in all cases, this CPU knows that its request will be delivered 1764 * by another CPU and can return 1765 * 1766 * After getting the down_write we still need to check for 1767 * pending_pcc_write_cmd to take care of the following scenario 1768 * The thread running this code could be scheduled out between 1769 * Phase-I and Phase-II. Before it is scheduled back on, another CPU 1770 * could have delivered the request to Platform by triggering the 1771 * doorbell and transferred the ownership of PCC to platform. So this 1772 * avoids triggering an unnecessary doorbell and more importantly before 1773 * triggering the doorbell it makes sure that the PCC channel ownership 1774 * is still with OSPM. 1775 * pending_pcc_write_cmd can also be cleared by a different CPU, if 1776 * there was a pcc CMD_READ waiting on down_write and it steals the lock 1777 * before the pcc CMD_WRITE is completed. send_pcc_cmd checks for this 1778 * case during a CMD_READ and if there are pending writes it delivers 1779 * the write command before servicing the read command 1780 */ 1781 if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg)) { 1782 if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */ 1783 /* Update only if there are pending write commands */ 1784 if (pcc_ss_data->pending_pcc_write_cmd) 1785 send_pcc_cmd(pcc_ss_id, CMD_WRITE); 1786 up_write(&pcc_ss_data->pcc_lock); /* END Phase-II */ 1787 } else 1788 /* Wait until pcc_write_cnt is updated by send_pcc_cmd */ 1789 wait_event(pcc_ss_data->pcc_write_wait_q, 1790 cpc_desc->write_cmd_id != pcc_ss_data->pcc_write_cnt); 1791 1792 /* send_pcc_cmd updates the status in case of failure */ 1793 ret = cpc_desc->write_cmd_status; 1794 } 1795 return ret; 1796 } 1797 EXPORT_SYMBOL_GPL(cppc_set_perf); 1798 1799 /** 1800 * cppc_get_transition_latency - returns frequency transition latency in ns 1801 * @cpu_num: CPU number for per_cpu(). 1802 * 1803 * ACPI CPPC does not explicitly specify how a platform can specify the 1804 * transition latency for performance change requests. The closest we have 1805 * is the timing information from the PCCT tables which provides the info 1806 * on the number and frequency of PCC commands the platform can handle. 1807 * 1808 * If desired_reg is in the SystemMemory or SystemIo ACPI address space, 1809 * then assume there is no latency. 1810 */ 1811 unsigned int cppc_get_transition_latency(int cpu_num) 1812 { 1813 /* 1814 * Expected transition latency is based on the PCCT timing values 1815 * Below are definition from ACPI spec: 1816 * pcc_nominal- Expected latency to process a command, in microseconds 1817 * pcc_mpar - The maximum number of periodic requests that the subspace 1818 * channel can support, reported in commands per minute. 0 1819 * indicates no limitation. 1820 * pcc_mrtt - The minimum amount of time that OSPM must wait after the 1821 * completion of a command before issuing the next command, 1822 * in microseconds. 1823 */ 1824 unsigned int latency_ns = 0; 1825 struct cpc_desc *cpc_desc; 1826 struct cpc_register_resource *desired_reg; 1827 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu_num); 1828 struct cppc_pcc_data *pcc_ss_data; 1829 1830 cpc_desc = per_cpu(cpc_desc_ptr, cpu_num); 1831 if (!cpc_desc) 1832 return CPUFREQ_ETERNAL; 1833 1834 desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; 1835 if (CPC_IN_SYSTEM_MEMORY(desired_reg) || CPC_IN_SYSTEM_IO(desired_reg)) 1836 return 0; 1837 else if (!CPC_IN_PCC(desired_reg)) 1838 return CPUFREQ_ETERNAL; 1839 1840 if (pcc_ss_id < 0) 1841 return CPUFREQ_ETERNAL; 1842 1843 pcc_ss_data = pcc_data[pcc_ss_id]; 1844 if (pcc_ss_data->pcc_mpar) 1845 latency_ns = 60 * (1000 * 1000 * 1000 / pcc_ss_data->pcc_mpar); 1846 1847 latency_ns = max(latency_ns, pcc_ss_data->pcc_nominal * 1000); 1848 latency_ns = max(latency_ns, pcc_ss_data->pcc_mrtt * 1000); 1849 1850 return latency_ns; 1851 } 1852 EXPORT_SYMBOL_GPL(cppc_get_transition_latency); 1853