1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers. 4 * 5 * (C) Copyright 2014, 2015 Linaro Ltd. 6 * Author: Ashwin Chaugule <ashwin.chaugule@linaro.org> 7 * 8 * CPPC describes a few methods for controlling CPU performance using 9 * information from a per CPU table called CPC. This table is described in 10 * the ACPI v5.0+ specification. The table consists of a list of 11 * registers which may be memory mapped or hardware registers and also may 12 * include some static integer values. 13 * 14 * CPU performance is on an abstract continuous scale as against a discretized 15 * P-state scale which is tied to CPU frequency only. In brief, the basic 16 * operation involves: 17 * 18 * - OS makes a CPU performance request. (Can provide min and max bounds) 19 * 20 * - Platform (such as BMC) is free to optimize request within requested bounds 21 * depending on power/thermal budgets etc. 22 * 23 * - Platform conveys its decision back to OS 24 * 25 * The communication between OS and platform occurs through another medium 26 * called (PCC) Platform Communication Channel. This is a generic mailbox like 27 * mechanism which includes doorbell semantics to indicate register updates. 28 * See drivers/mailbox/pcc.c for details on PCC. 29 * 30 * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and 31 * above specifications. 32 */ 33 34 #define pr_fmt(fmt) "ACPI CPPC: " fmt 35 36 #include <linux/delay.h> 37 #include <linux/iopoll.h> 38 #include <linux/ktime.h> 39 #include <linux/rwsem.h> 40 #include <linux/wait.h> 41 #include <linux/topology.h> 42 43 #include <acpi/cppc_acpi.h> 44 45 struct cppc_pcc_data { 46 struct pcc_mbox_chan *pcc_channel; 47 void __iomem *pcc_comm_addr; 48 bool pcc_channel_acquired; 49 unsigned int deadline_us; 50 unsigned int pcc_mpar, pcc_mrtt, pcc_nominal; 51 52 bool pending_pcc_write_cmd; /* Any pending/batched PCC write cmds? */ 53 bool platform_owns_pcc; /* Ownership of PCC subspace */ 54 unsigned int pcc_write_cnt; /* Running count of PCC write commands */ 55 56 /* 57 * Lock to provide controlled access to the PCC channel. 58 * 59 * For performance critical usecases(currently cppc_set_perf) 60 * We need to take read_lock and check if channel belongs to OSPM 61 * before reading or writing to PCC subspace 62 * We need to take write_lock before transferring the channel 63 * ownership to the platform via a Doorbell 64 * This allows us to batch a number of CPPC requests if they happen 65 * to originate in about the same time 66 * 67 * For non-performance critical usecases(init) 68 * Take write_lock for all purposes which gives exclusive access 69 */ 70 struct rw_semaphore pcc_lock; 71 72 /* Wait queue for CPUs whose requests were batched */ 73 wait_queue_head_t pcc_write_wait_q; 74 ktime_t last_cmd_cmpl_time; 75 ktime_t last_mpar_reset; 76 int mpar_count; 77 int refcount; 78 }; 79 80 /* Array to represent the PCC channel per subspace ID */ 81 static struct cppc_pcc_data *pcc_data[MAX_PCC_SUBSPACES]; 82 /* The cpu_pcc_subspace_idx contains per CPU subspace ID */ 83 static DEFINE_PER_CPU(int, cpu_pcc_subspace_idx); 84 85 /* 86 * The cpc_desc structure contains the ACPI register details 87 * as described in the per CPU _CPC tables. The details 88 * include the type of register (e.g. PCC, System IO, FFH etc.) 89 * and destination addresses which lets us READ/WRITE CPU performance 90 * information using the appropriate I/O methods. 91 */ 92 static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr); 93 94 /* pcc mapped address + header size + offset within PCC subspace */ 95 #define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_comm_addr + \ 96 0x8 + (offs)) 97 98 /* Check if a CPC register is in PCC */ 99 #define CPC_IN_PCC(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \ 100 (cpc)->cpc_entry.reg.space_id == \ 101 ACPI_ADR_SPACE_PLATFORM_COMM) 102 103 /* Evaluates to True if reg is a NULL register descriptor */ 104 #define IS_NULL_REG(reg) ((reg)->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY && \ 105 (reg)->address == 0 && \ 106 (reg)->bit_width == 0 && \ 107 (reg)->bit_offset == 0 && \ 108 (reg)->access_width == 0) 109 110 /* Evaluates to True if an optional cpc field is supported */ 111 #define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ? \ 112 !!(cpc)->cpc_entry.int_value : \ 113 !IS_NULL_REG(&(cpc)->cpc_entry.reg)) 114 /* 115 * Arbitrary Retries in case the remote processor is slow to respond 116 * to PCC commands. Keeping it high enough to cover emulators where 117 * the processors run painfully slow. 118 */ 119 #define NUM_RETRIES 500ULL 120 121 #define OVER_16BTS_MASK ~0xFFFFULL 122 123 #define define_one_cppc_ro(_name) \ 124 static struct kobj_attribute _name = \ 125 __ATTR(_name, 0444, show_##_name, NULL) 126 127 #define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj) 128 129 #define show_cppc_data(access_fn, struct_name, member_name) \ 130 static ssize_t show_##member_name(struct kobject *kobj, \ 131 struct kobj_attribute *attr, char *buf) \ 132 { \ 133 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); \ 134 struct struct_name st_name = {0}; \ 135 int ret; \ 136 \ 137 ret = access_fn(cpc_ptr->cpu_id, &st_name); \ 138 if (ret) \ 139 return ret; \ 140 \ 141 return scnprintf(buf, PAGE_SIZE, "%llu\n", \ 142 (u64)st_name.member_name); \ 143 } \ 144 define_one_cppc_ro(member_name) 145 146 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf); 147 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf); 148 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf); 149 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf); 150 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq); 151 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq); 152 153 show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf); 154 show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time); 155 156 static ssize_t show_feedback_ctrs(struct kobject *kobj, 157 struct kobj_attribute *attr, char *buf) 158 { 159 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); 160 struct cppc_perf_fb_ctrs fb_ctrs = {0}; 161 int ret; 162 163 ret = cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs); 164 if (ret) 165 return ret; 166 167 return scnprintf(buf, PAGE_SIZE, "ref:%llu del:%llu\n", 168 fb_ctrs.reference, fb_ctrs.delivered); 169 } 170 define_one_cppc_ro(feedback_ctrs); 171 172 static struct attribute *cppc_attrs[] = { 173 &feedback_ctrs.attr, 174 &reference_perf.attr, 175 &wraparound_time.attr, 176 &highest_perf.attr, 177 &lowest_perf.attr, 178 &lowest_nonlinear_perf.attr, 179 &nominal_perf.attr, 180 &nominal_freq.attr, 181 &lowest_freq.attr, 182 NULL 183 }; 184 ATTRIBUTE_GROUPS(cppc); 185 186 static struct kobj_type cppc_ktype = { 187 .sysfs_ops = &kobj_sysfs_ops, 188 .default_groups = cppc_groups, 189 }; 190 191 static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit) 192 { 193 int ret, status; 194 struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id]; 195 struct acpi_pcct_shared_memory __iomem *generic_comm_base = 196 pcc_ss_data->pcc_comm_addr; 197 198 if (!pcc_ss_data->platform_owns_pcc) 199 return 0; 200 201 /* 202 * Poll PCC status register every 3us(delay_us) for maximum of 203 * deadline_us(timeout_us) until PCC command complete bit is set(cond) 204 */ 205 ret = readw_relaxed_poll_timeout(&generic_comm_base->status, status, 206 status & PCC_CMD_COMPLETE_MASK, 3, 207 pcc_ss_data->deadline_us); 208 209 if (likely(!ret)) { 210 pcc_ss_data->platform_owns_pcc = false; 211 if (chk_err_bit && (status & PCC_ERROR_MASK)) 212 ret = -EIO; 213 } 214 215 if (unlikely(ret)) 216 pr_err("PCC check channel failed for ss: %d. ret=%d\n", 217 pcc_ss_id, ret); 218 219 return ret; 220 } 221 222 /* 223 * This function transfers the ownership of the PCC to the platform 224 * So it must be called while holding write_lock(pcc_lock) 225 */ 226 static int send_pcc_cmd(int pcc_ss_id, u16 cmd) 227 { 228 int ret = -EIO, i; 229 struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id]; 230 struct acpi_pcct_shared_memory __iomem *generic_comm_base = 231 pcc_ss_data->pcc_comm_addr; 232 unsigned int time_delta; 233 234 /* 235 * For CMD_WRITE we know for a fact the caller should have checked 236 * the channel before writing to PCC space 237 */ 238 if (cmd == CMD_READ) { 239 /* 240 * If there are pending cpc_writes, then we stole the channel 241 * before write completion, so first send a WRITE command to 242 * platform 243 */ 244 if (pcc_ss_data->pending_pcc_write_cmd) 245 send_pcc_cmd(pcc_ss_id, CMD_WRITE); 246 247 ret = check_pcc_chan(pcc_ss_id, false); 248 if (ret) 249 goto end; 250 } else /* CMD_WRITE */ 251 pcc_ss_data->pending_pcc_write_cmd = FALSE; 252 253 /* 254 * Handle the Minimum Request Turnaround Time(MRTT) 255 * "The minimum amount of time that OSPM must wait after the completion 256 * of a command before issuing the next command, in microseconds" 257 */ 258 if (pcc_ss_data->pcc_mrtt) { 259 time_delta = ktime_us_delta(ktime_get(), 260 pcc_ss_data->last_cmd_cmpl_time); 261 if (pcc_ss_data->pcc_mrtt > time_delta) 262 udelay(pcc_ss_data->pcc_mrtt - time_delta); 263 } 264 265 /* 266 * Handle the non-zero Maximum Periodic Access Rate(MPAR) 267 * "The maximum number of periodic requests that the subspace channel can 268 * support, reported in commands per minute. 0 indicates no limitation." 269 * 270 * This parameter should be ideally zero or large enough so that it can 271 * handle maximum number of requests that all the cores in the system can 272 * collectively generate. If it is not, we will follow the spec and just 273 * not send the request to the platform after hitting the MPAR limit in 274 * any 60s window 275 */ 276 if (pcc_ss_data->pcc_mpar) { 277 if (pcc_ss_data->mpar_count == 0) { 278 time_delta = ktime_ms_delta(ktime_get(), 279 pcc_ss_data->last_mpar_reset); 280 if ((time_delta < 60 * MSEC_PER_SEC) && pcc_ss_data->last_mpar_reset) { 281 pr_debug("PCC cmd for subspace %d not sent due to MPAR limit", 282 pcc_ss_id); 283 ret = -EIO; 284 goto end; 285 } 286 pcc_ss_data->last_mpar_reset = ktime_get(); 287 pcc_ss_data->mpar_count = pcc_ss_data->pcc_mpar; 288 } 289 pcc_ss_data->mpar_count--; 290 } 291 292 /* Write to the shared comm region. */ 293 writew_relaxed(cmd, &generic_comm_base->command); 294 295 /* Flip CMD COMPLETE bit */ 296 writew_relaxed(0, &generic_comm_base->status); 297 298 pcc_ss_data->platform_owns_pcc = true; 299 300 /* Ring doorbell */ 301 ret = mbox_send_message(pcc_ss_data->pcc_channel->mchan, &cmd); 302 if (ret < 0) { 303 pr_err("Err sending PCC mbox message. ss: %d cmd:%d, ret:%d\n", 304 pcc_ss_id, cmd, ret); 305 goto end; 306 } 307 308 /* wait for completion and check for PCC errro bit */ 309 ret = check_pcc_chan(pcc_ss_id, true); 310 311 if (pcc_ss_data->pcc_mrtt) 312 pcc_ss_data->last_cmd_cmpl_time = ktime_get(); 313 314 if (pcc_ss_data->pcc_channel->mchan->mbox->txdone_irq) 315 mbox_chan_txdone(pcc_ss_data->pcc_channel->mchan, ret); 316 else 317 mbox_client_txdone(pcc_ss_data->pcc_channel->mchan, ret); 318 319 end: 320 if (cmd == CMD_WRITE) { 321 if (unlikely(ret)) { 322 for_each_possible_cpu(i) { 323 struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i); 324 325 if (!desc) 326 continue; 327 328 if (desc->write_cmd_id == pcc_ss_data->pcc_write_cnt) 329 desc->write_cmd_status = ret; 330 } 331 } 332 pcc_ss_data->pcc_write_cnt++; 333 wake_up_all(&pcc_ss_data->pcc_write_wait_q); 334 } 335 336 return ret; 337 } 338 339 static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret) 340 { 341 if (ret < 0) 342 pr_debug("TX did not complete: CMD sent:%x, ret:%d\n", 343 *(u16 *)msg, ret); 344 else 345 pr_debug("TX completed. CMD sent:%x, ret:%d\n", 346 *(u16 *)msg, ret); 347 } 348 349 static struct mbox_client cppc_mbox_cl = { 350 .tx_done = cppc_chan_tx_done, 351 .knows_txdone = true, 352 }; 353 354 static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle) 355 { 356 int result = -EFAULT; 357 acpi_status status = AE_OK; 358 struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL}; 359 struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"}; 360 struct acpi_buffer state = {0, NULL}; 361 union acpi_object *psd = NULL; 362 struct acpi_psd_package *pdomain; 363 364 status = acpi_evaluate_object_typed(handle, "_PSD", NULL, 365 &buffer, ACPI_TYPE_PACKAGE); 366 if (status == AE_NOT_FOUND) /* _PSD is optional */ 367 return 0; 368 if (ACPI_FAILURE(status)) 369 return -ENODEV; 370 371 psd = buffer.pointer; 372 if (!psd || psd->package.count != 1) { 373 pr_debug("Invalid _PSD data\n"); 374 goto end; 375 } 376 377 pdomain = &(cpc_ptr->domain_info); 378 379 state.length = sizeof(struct acpi_psd_package); 380 state.pointer = pdomain; 381 382 status = acpi_extract_package(&(psd->package.elements[0]), 383 &format, &state); 384 if (ACPI_FAILURE(status)) { 385 pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id); 386 goto end; 387 } 388 389 if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) { 390 pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id); 391 goto end; 392 } 393 394 if (pdomain->revision != ACPI_PSD_REV0_REVISION) { 395 pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id); 396 goto end; 397 } 398 399 if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL && 400 pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY && 401 pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) { 402 pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id); 403 goto end; 404 } 405 406 result = 0; 407 end: 408 kfree(buffer.pointer); 409 return result; 410 } 411 412 bool acpi_cpc_valid(void) 413 { 414 struct cpc_desc *cpc_ptr; 415 int cpu; 416 417 for_each_present_cpu(cpu) { 418 cpc_ptr = per_cpu(cpc_desc_ptr, cpu); 419 if (!cpc_ptr) 420 return false; 421 } 422 423 return true; 424 } 425 EXPORT_SYMBOL_GPL(acpi_cpc_valid); 426 427 /** 428 * acpi_get_psd_map - Map the CPUs in the freq domain of a given cpu 429 * @cpu: Find all CPUs that share a domain with cpu. 430 * @cpu_data: Pointer to CPU specific CPPC data including PSD info. 431 * 432 * Return: 0 for success or negative value for err. 433 */ 434 int acpi_get_psd_map(unsigned int cpu, struct cppc_cpudata *cpu_data) 435 { 436 struct cpc_desc *cpc_ptr, *match_cpc_ptr; 437 struct acpi_psd_package *match_pdomain; 438 struct acpi_psd_package *pdomain; 439 int count_target, i; 440 441 /* 442 * Now that we have _PSD data from all CPUs, let's setup P-state 443 * domain info. 444 */ 445 cpc_ptr = per_cpu(cpc_desc_ptr, cpu); 446 if (!cpc_ptr) 447 return -EFAULT; 448 449 pdomain = &(cpc_ptr->domain_info); 450 cpumask_set_cpu(cpu, cpu_data->shared_cpu_map); 451 if (pdomain->num_processors <= 1) 452 return 0; 453 454 /* Validate the Domain info */ 455 count_target = pdomain->num_processors; 456 if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL) 457 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ALL; 458 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL) 459 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_HW; 460 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY) 461 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ANY; 462 463 for_each_possible_cpu(i) { 464 if (i == cpu) 465 continue; 466 467 match_cpc_ptr = per_cpu(cpc_desc_ptr, i); 468 if (!match_cpc_ptr) 469 goto err_fault; 470 471 match_pdomain = &(match_cpc_ptr->domain_info); 472 if (match_pdomain->domain != pdomain->domain) 473 continue; 474 475 /* Here i and cpu are in the same domain */ 476 if (match_pdomain->num_processors != count_target) 477 goto err_fault; 478 479 if (pdomain->coord_type != match_pdomain->coord_type) 480 goto err_fault; 481 482 cpumask_set_cpu(i, cpu_data->shared_cpu_map); 483 } 484 485 return 0; 486 487 err_fault: 488 /* Assume no coordination on any error parsing domain info */ 489 cpumask_clear(cpu_data->shared_cpu_map); 490 cpumask_set_cpu(cpu, cpu_data->shared_cpu_map); 491 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_NONE; 492 493 return -EFAULT; 494 } 495 EXPORT_SYMBOL_GPL(acpi_get_psd_map); 496 497 static int register_pcc_channel(int pcc_ss_idx) 498 { 499 struct pcc_mbox_chan *pcc_chan; 500 u64 usecs_lat; 501 502 if (pcc_ss_idx >= 0) { 503 pcc_chan = pcc_mbox_request_channel(&cppc_mbox_cl, pcc_ss_idx); 504 505 if (IS_ERR(pcc_chan)) { 506 pr_err("Failed to find PCC channel for subspace %d\n", 507 pcc_ss_idx); 508 return -ENODEV; 509 } 510 511 pcc_data[pcc_ss_idx]->pcc_channel = pcc_chan; 512 /* 513 * cppc_ss->latency is just a Nominal value. In reality 514 * the remote processor could be much slower to reply. 515 * So add an arbitrary amount of wait on top of Nominal. 516 */ 517 usecs_lat = NUM_RETRIES * pcc_chan->latency; 518 pcc_data[pcc_ss_idx]->deadline_us = usecs_lat; 519 pcc_data[pcc_ss_idx]->pcc_mrtt = pcc_chan->min_turnaround_time; 520 pcc_data[pcc_ss_idx]->pcc_mpar = pcc_chan->max_access_rate; 521 pcc_data[pcc_ss_idx]->pcc_nominal = pcc_chan->latency; 522 523 pcc_data[pcc_ss_idx]->pcc_comm_addr = 524 acpi_os_ioremap(pcc_chan->shmem_base_addr, 525 pcc_chan->shmem_size); 526 if (!pcc_data[pcc_ss_idx]->pcc_comm_addr) { 527 pr_err("Failed to ioremap PCC comm region mem for %d\n", 528 pcc_ss_idx); 529 return -ENOMEM; 530 } 531 532 /* Set flag so that we don't come here for each CPU. */ 533 pcc_data[pcc_ss_idx]->pcc_channel_acquired = true; 534 } 535 536 return 0; 537 } 538 539 /** 540 * cpc_ffh_supported() - check if FFH reading supported 541 * 542 * Check if the architecture has support for functional fixed hardware 543 * read/write capability. 544 * 545 * Return: true for supported, false for not supported 546 */ 547 bool __weak cpc_ffh_supported(void) 548 { 549 return false; 550 } 551 552 /** 553 * pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace 554 * 555 * Check and allocate the cppc_pcc_data memory. 556 * In some processor configurations it is possible that same subspace 557 * is shared between multiple CPUs. This is seen especially in CPUs 558 * with hardware multi-threading support. 559 * 560 * Return: 0 for success, errno for failure 561 */ 562 static int pcc_data_alloc(int pcc_ss_id) 563 { 564 if (pcc_ss_id < 0 || pcc_ss_id >= MAX_PCC_SUBSPACES) 565 return -EINVAL; 566 567 if (pcc_data[pcc_ss_id]) { 568 pcc_data[pcc_ss_id]->refcount++; 569 } else { 570 pcc_data[pcc_ss_id] = kzalloc(sizeof(struct cppc_pcc_data), 571 GFP_KERNEL); 572 if (!pcc_data[pcc_ss_id]) 573 return -ENOMEM; 574 pcc_data[pcc_ss_id]->refcount++; 575 } 576 577 return 0; 578 } 579 580 /* Check if CPPC revision + num_ent combination is supported */ 581 static bool is_cppc_supported(int revision, int num_ent) 582 { 583 int expected_num_ent; 584 585 switch (revision) { 586 case CPPC_V2_REV: 587 expected_num_ent = CPPC_V2_NUM_ENT; 588 break; 589 case CPPC_V3_REV: 590 expected_num_ent = CPPC_V3_NUM_ENT; 591 break; 592 default: 593 pr_debug("Firmware exports unsupported CPPC revision: %d\n", 594 revision); 595 return false; 596 } 597 598 if (expected_num_ent != num_ent) { 599 pr_debug("Firmware exports %d entries. Expected: %d for CPPC rev:%d\n", 600 num_ent, expected_num_ent, revision); 601 return false; 602 } 603 604 return true; 605 } 606 607 /* 608 * An example CPC table looks like the following. 609 * 610 * Name (_CPC, Package() { 611 * 17, // NumEntries 612 * 1, // Revision 613 * ResourceTemplate() {Register(PCC, 32, 0, 0x120, 2)}, // Highest Performance 614 * ResourceTemplate() {Register(PCC, 32, 0, 0x124, 2)}, // Nominal Performance 615 * ResourceTemplate() {Register(PCC, 32, 0, 0x128, 2)}, // Lowest Nonlinear Performance 616 * ResourceTemplate() {Register(PCC, 32, 0, 0x12C, 2)}, // Lowest Performance 617 * ResourceTemplate() {Register(PCC, 32, 0, 0x130, 2)}, // Guaranteed Performance Register 618 * ResourceTemplate() {Register(PCC, 32, 0, 0x110, 2)}, // Desired Performance Register 619 * ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, 620 * ... 621 * ... 622 * ... 623 * } 624 * Each Register() encodes how to access that specific register. 625 * e.g. a sample PCC entry has the following encoding: 626 * 627 * Register ( 628 * PCC, // AddressSpaceKeyword 629 * 8, // RegisterBitWidth 630 * 8, // RegisterBitOffset 631 * 0x30, // RegisterAddress 632 * 9, // AccessSize (subspace ID) 633 * ) 634 */ 635 636 #ifndef arch_init_invariance_cppc 637 static inline void arch_init_invariance_cppc(void) { } 638 #endif 639 640 /** 641 * acpi_cppc_processor_probe - Search for per CPU _CPC objects. 642 * @pr: Ptr to acpi_processor containing this CPU's logical ID. 643 * 644 * Return: 0 for success or negative value for err. 645 */ 646 int acpi_cppc_processor_probe(struct acpi_processor *pr) 647 { 648 struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL}; 649 union acpi_object *out_obj, *cpc_obj; 650 struct cpc_desc *cpc_ptr; 651 struct cpc_reg *gas_t; 652 struct device *cpu_dev; 653 acpi_handle handle = pr->handle; 654 unsigned int num_ent, i, cpc_rev; 655 int pcc_subspace_id = -1; 656 acpi_status status; 657 int ret = -ENODATA; 658 659 if (osc_sb_cppc_not_supported) 660 return -ENODEV; 661 662 /* Parse the ACPI _CPC table for this CPU. */ 663 status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output, 664 ACPI_TYPE_PACKAGE); 665 if (ACPI_FAILURE(status)) { 666 ret = -ENODEV; 667 goto out_buf_free; 668 } 669 670 out_obj = (union acpi_object *) output.pointer; 671 672 cpc_ptr = kzalloc(sizeof(struct cpc_desc), GFP_KERNEL); 673 if (!cpc_ptr) { 674 ret = -ENOMEM; 675 goto out_buf_free; 676 } 677 678 /* First entry is NumEntries. */ 679 cpc_obj = &out_obj->package.elements[0]; 680 if (cpc_obj->type == ACPI_TYPE_INTEGER) { 681 num_ent = cpc_obj->integer.value; 682 if (num_ent <= 1) { 683 pr_debug("Unexpected _CPC NumEntries value (%d) for CPU:%d\n", 684 num_ent, pr->id); 685 goto out_free; 686 } 687 } else { 688 pr_debug("Unexpected _CPC NumEntries entry type (%d) for CPU:%d\n", 689 cpc_obj->type, pr->id); 690 goto out_free; 691 } 692 cpc_ptr->num_entries = num_ent; 693 694 /* Second entry should be revision. */ 695 cpc_obj = &out_obj->package.elements[1]; 696 if (cpc_obj->type == ACPI_TYPE_INTEGER) { 697 cpc_rev = cpc_obj->integer.value; 698 } else { 699 pr_debug("Unexpected _CPC Revision entry type (%d) for CPU:%d\n", 700 cpc_obj->type, pr->id); 701 goto out_free; 702 } 703 cpc_ptr->version = cpc_rev; 704 705 if (!is_cppc_supported(cpc_rev, num_ent)) 706 goto out_free; 707 708 /* Iterate through remaining entries in _CPC */ 709 for (i = 2; i < num_ent; i++) { 710 cpc_obj = &out_obj->package.elements[i]; 711 712 if (cpc_obj->type == ACPI_TYPE_INTEGER) { 713 cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER; 714 cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value; 715 } else if (cpc_obj->type == ACPI_TYPE_BUFFER) { 716 gas_t = (struct cpc_reg *) 717 cpc_obj->buffer.pointer; 718 719 /* 720 * The PCC Subspace index is encoded inside 721 * the CPC table entries. The same PCC index 722 * will be used for all the PCC entries, 723 * so extract it only once. 724 */ 725 if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) { 726 if (pcc_subspace_id < 0) { 727 pcc_subspace_id = gas_t->access_width; 728 if (pcc_data_alloc(pcc_subspace_id)) 729 goto out_free; 730 } else if (pcc_subspace_id != gas_t->access_width) { 731 pr_debug("Mismatched PCC ids in _CPC for CPU:%d\n", 732 pr->id); 733 goto out_free; 734 } 735 } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) { 736 if (gas_t->address) { 737 void __iomem *addr; 738 739 addr = ioremap(gas_t->address, gas_t->bit_width/8); 740 if (!addr) 741 goto out_free; 742 cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr; 743 } 744 } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_IO) { 745 if (gas_t->access_width < 1 || gas_t->access_width > 3) { 746 /* 747 * 1 = 8-bit, 2 = 16-bit, and 3 = 32-bit. 748 * SystemIO doesn't implement 64-bit 749 * registers. 750 */ 751 pr_debug("Invalid access width %d for SystemIO register in _CPC\n", 752 gas_t->access_width); 753 goto out_free; 754 } 755 if (gas_t->address & OVER_16BTS_MASK) { 756 /* SystemIO registers use 16-bit integer addresses */ 757 pr_debug("Invalid IO port %llu for SystemIO register in _CPC\n", 758 gas_t->address); 759 goto out_free; 760 } 761 } else { 762 if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) { 763 /* Support only PCC, SystemMemory, SystemIO, and FFH type regs. */ 764 pr_debug("Unsupported register type (%d) in _CPC\n", 765 gas_t->space_id); 766 goto out_free; 767 } 768 } 769 770 cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER; 771 memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t)); 772 } else { 773 pr_debug("Invalid entry type (%d) in _CPC for CPU:%d\n", 774 i, pr->id); 775 goto out_free; 776 } 777 } 778 per_cpu(cpu_pcc_subspace_idx, pr->id) = pcc_subspace_id; 779 780 /* 781 * Initialize the remaining cpc_regs as unsupported. 782 * Example: In case FW exposes CPPC v2, the below loop will initialize 783 * LOWEST_FREQ and NOMINAL_FREQ regs as unsupported 784 */ 785 for (i = num_ent - 2; i < MAX_CPC_REG_ENT; i++) { 786 cpc_ptr->cpc_regs[i].type = ACPI_TYPE_INTEGER; 787 cpc_ptr->cpc_regs[i].cpc_entry.int_value = 0; 788 } 789 790 791 /* Store CPU Logical ID */ 792 cpc_ptr->cpu_id = pr->id; 793 794 /* Parse PSD data for this CPU */ 795 ret = acpi_get_psd(cpc_ptr, handle); 796 if (ret) 797 goto out_free; 798 799 /* Register PCC channel once for all PCC subspace ID. */ 800 if (pcc_subspace_id >= 0 && !pcc_data[pcc_subspace_id]->pcc_channel_acquired) { 801 ret = register_pcc_channel(pcc_subspace_id); 802 if (ret) 803 goto out_free; 804 805 init_rwsem(&pcc_data[pcc_subspace_id]->pcc_lock); 806 init_waitqueue_head(&pcc_data[pcc_subspace_id]->pcc_write_wait_q); 807 } 808 809 /* Everything looks okay */ 810 pr_debug("Parsed CPC struct for CPU: %d\n", pr->id); 811 812 /* Add per logical CPU nodes for reading its feedback counters. */ 813 cpu_dev = get_cpu_device(pr->id); 814 if (!cpu_dev) { 815 ret = -EINVAL; 816 goto out_free; 817 } 818 819 /* Plug PSD data into this CPU's CPC descriptor. */ 820 per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr; 821 822 ret = kobject_init_and_add(&cpc_ptr->kobj, &cppc_ktype, &cpu_dev->kobj, 823 "acpi_cppc"); 824 if (ret) { 825 per_cpu(cpc_desc_ptr, pr->id) = NULL; 826 kobject_put(&cpc_ptr->kobj); 827 goto out_free; 828 } 829 830 arch_init_invariance_cppc(); 831 832 kfree(output.pointer); 833 return 0; 834 835 out_free: 836 /* Free all the mapped sys mem areas for this CPU */ 837 for (i = 2; i < cpc_ptr->num_entries; i++) { 838 void __iomem *addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr; 839 840 if (addr) 841 iounmap(addr); 842 } 843 kfree(cpc_ptr); 844 845 out_buf_free: 846 kfree(output.pointer); 847 return ret; 848 } 849 EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe); 850 851 /** 852 * acpi_cppc_processor_exit - Cleanup CPC structs. 853 * @pr: Ptr to acpi_processor containing this CPU's logical ID. 854 * 855 * Return: Void 856 */ 857 void acpi_cppc_processor_exit(struct acpi_processor *pr) 858 { 859 struct cpc_desc *cpc_ptr; 860 unsigned int i; 861 void __iomem *addr; 862 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id); 863 864 if (pcc_ss_id >= 0 && pcc_data[pcc_ss_id]) { 865 if (pcc_data[pcc_ss_id]->pcc_channel_acquired) { 866 pcc_data[pcc_ss_id]->refcount--; 867 if (!pcc_data[pcc_ss_id]->refcount) { 868 pcc_mbox_free_channel(pcc_data[pcc_ss_id]->pcc_channel); 869 kfree(pcc_data[pcc_ss_id]); 870 pcc_data[pcc_ss_id] = NULL; 871 } 872 } 873 } 874 875 cpc_ptr = per_cpu(cpc_desc_ptr, pr->id); 876 if (!cpc_ptr) 877 return; 878 879 /* Free all the mapped sys mem areas for this CPU */ 880 for (i = 2; i < cpc_ptr->num_entries; i++) { 881 addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr; 882 if (addr) 883 iounmap(addr); 884 } 885 886 kobject_put(&cpc_ptr->kobj); 887 kfree(cpc_ptr); 888 } 889 EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit); 890 891 /** 892 * cpc_read_ffh() - Read FFH register 893 * @cpunum: CPU number to read 894 * @reg: cppc register information 895 * @val: place holder for return value 896 * 897 * Read bit_width bits from a specified address and bit_offset 898 * 899 * Return: 0 for success and error code 900 */ 901 int __weak cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val) 902 { 903 return -ENOTSUPP; 904 } 905 906 /** 907 * cpc_write_ffh() - Write FFH register 908 * @cpunum: CPU number to write 909 * @reg: cppc register information 910 * @val: value to write 911 * 912 * Write value of bit_width bits to a specified address and bit_offset 913 * 914 * Return: 0 for success and error code 915 */ 916 int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val) 917 { 918 return -ENOTSUPP; 919 } 920 921 /* 922 * Since cpc_read and cpc_write are called while holding pcc_lock, it should be 923 * as fast as possible. We have already mapped the PCC subspace during init, so 924 * we can directly write to it. 925 */ 926 927 static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val) 928 { 929 void __iomem *vaddr = NULL; 930 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); 931 struct cpc_reg *reg = ®_res->cpc_entry.reg; 932 933 if (reg_res->type == ACPI_TYPE_INTEGER) { 934 *val = reg_res->cpc_entry.int_value; 935 return 0; 936 } 937 938 *val = 0; 939 940 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) { 941 u32 width = 8 << (reg->access_width - 1); 942 u32 val_u32; 943 acpi_status status; 944 945 status = acpi_os_read_port((acpi_io_address)reg->address, 946 &val_u32, width); 947 if (ACPI_FAILURE(status)) { 948 pr_debug("Error: Failed to read SystemIO port %llx\n", 949 reg->address); 950 return -EFAULT; 951 } 952 953 *val = val_u32; 954 return 0; 955 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) 956 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id); 957 else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) 958 vaddr = reg_res->sys_mem_vaddr; 959 else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) 960 return cpc_read_ffh(cpu, reg, val); 961 else 962 return acpi_os_read_memory((acpi_physical_address)reg->address, 963 val, reg->bit_width); 964 965 switch (reg->bit_width) { 966 case 8: 967 *val = readb_relaxed(vaddr); 968 break; 969 case 16: 970 *val = readw_relaxed(vaddr); 971 break; 972 case 32: 973 *val = readl_relaxed(vaddr); 974 break; 975 case 64: 976 *val = readq_relaxed(vaddr); 977 break; 978 default: 979 pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n", 980 reg->bit_width, pcc_ss_id); 981 return -EFAULT; 982 } 983 984 return 0; 985 } 986 987 static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val) 988 { 989 int ret_val = 0; 990 void __iomem *vaddr = NULL; 991 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); 992 struct cpc_reg *reg = ®_res->cpc_entry.reg; 993 994 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) { 995 u32 width = 8 << (reg->access_width - 1); 996 acpi_status status; 997 998 status = acpi_os_write_port((acpi_io_address)reg->address, 999 (u32)val, width); 1000 if (ACPI_FAILURE(status)) { 1001 pr_debug("Error: Failed to write SystemIO port %llx\n", 1002 reg->address); 1003 return -EFAULT; 1004 } 1005 1006 return 0; 1007 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) 1008 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id); 1009 else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) 1010 vaddr = reg_res->sys_mem_vaddr; 1011 else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) 1012 return cpc_write_ffh(cpu, reg, val); 1013 else 1014 return acpi_os_write_memory((acpi_physical_address)reg->address, 1015 val, reg->bit_width); 1016 1017 switch (reg->bit_width) { 1018 case 8: 1019 writeb_relaxed(val, vaddr); 1020 break; 1021 case 16: 1022 writew_relaxed(val, vaddr); 1023 break; 1024 case 32: 1025 writel_relaxed(val, vaddr); 1026 break; 1027 case 64: 1028 writeq_relaxed(val, vaddr); 1029 break; 1030 default: 1031 pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n", 1032 reg->bit_width, pcc_ss_id); 1033 ret_val = -EFAULT; 1034 break; 1035 } 1036 1037 return ret_val; 1038 } 1039 1040 static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf) 1041 { 1042 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); 1043 struct cpc_register_resource *reg; 1044 1045 if (!cpc_desc) { 1046 pr_debug("No CPC descriptor for CPU:%d\n", cpunum); 1047 return -ENODEV; 1048 } 1049 1050 reg = &cpc_desc->cpc_regs[reg_idx]; 1051 1052 if (CPC_IN_PCC(reg)) { 1053 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); 1054 struct cppc_pcc_data *pcc_ss_data = NULL; 1055 int ret = 0; 1056 1057 if (pcc_ss_id < 0) 1058 return -EIO; 1059 1060 pcc_ss_data = pcc_data[pcc_ss_id]; 1061 1062 down_write(&pcc_ss_data->pcc_lock); 1063 1064 if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) 1065 cpc_read(cpunum, reg, perf); 1066 else 1067 ret = -EIO; 1068 1069 up_write(&pcc_ss_data->pcc_lock); 1070 1071 return ret; 1072 } 1073 1074 cpc_read(cpunum, reg, perf); 1075 1076 return 0; 1077 } 1078 1079 /** 1080 * cppc_get_desired_perf - Get the desired performance register value. 1081 * @cpunum: CPU from which to get desired performance. 1082 * @desired_perf: Return address. 1083 * 1084 * Return: 0 for success, -EIO otherwise. 1085 */ 1086 int cppc_get_desired_perf(int cpunum, u64 *desired_perf) 1087 { 1088 return cppc_get_perf(cpunum, DESIRED_PERF, desired_perf); 1089 } 1090 EXPORT_SYMBOL_GPL(cppc_get_desired_perf); 1091 1092 /** 1093 * cppc_get_nominal_perf - Get the nominal performance register value. 1094 * @cpunum: CPU from which to get nominal performance. 1095 * @nominal_perf: Return address. 1096 * 1097 * Return: 0 for success, -EIO otherwise. 1098 */ 1099 int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf) 1100 { 1101 return cppc_get_perf(cpunum, NOMINAL_PERF, nominal_perf); 1102 } 1103 1104 /** 1105 * cppc_get_perf_caps - Get a CPU's performance capabilities. 1106 * @cpunum: CPU from which to get capabilities info. 1107 * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h 1108 * 1109 * Return: 0 for success with perf_caps populated else -ERRNO. 1110 */ 1111 int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps) 1112 { 1113 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); 1114 struct cpc_register_resource *highest_reg, *lowest_reg, 1115 *lowest_non_linear_reg, *nominal_reg, *guaranteed_reg, 1116 *low_freq_reg = NULL, *nom_freq_reg = NULL; 1117 u64 high, low, guaranteed, nom, min_nonlinear, low_f = 0, nom_f = 0; 1118 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); 1119 struct cppc_pcc_data *pcc_ss_data = NULL; 1120 int ret = 0, regs_in_pcc = 0; 1121 1122 if (!cpc_desc) { 1123 pr_debug("No CPC descriptor for CPU:%d\n", cpunum); 1124 return -ENODEV; 1125 } 1126 1127 highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF]; 1128 lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF]; 1129 lowest_non_linear_reg = &cpc_desc->cpc_regs[LOW_NON_LINEAR_PERF]; 1130 nominal_reg = &cpc_desc->cpc_regs[NOMINAL_PERF]; 1131 low_freq_reg = &cpc_desc->cpc_regs[LOWEST_FREQ]; 1132 nom_freq_reg = &cpc_desc->cpc_regs[NOMINAL_FREQ]; 1133 guaranteed_reg = &cpc_desc->cpc_regs[GUARANTEED_PERF]; 1134 1135 /* Are any of the regs PCC ?*/ 1136 if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) || 1137 CPC_IN_PCC(lowest_non_linear_reg) || CPC_IN_PCC(nominal_reg) || 1138 CPC_IN_PCC(low_freq_reg) || CPC_IN_PCC(nom_freq_reg)) { 1139 if (pcc_ss_id < 0) { 1140 pr_debug("Invalid pcc_ss_id\n"); 1141 return -ENODEV; 1142 } 1143 pcc_ss_data = pcc_data[pcc_ss_id]; 1144 regs_in_pcc = 1; 1145 down_write(&pcc_ss_data->pcc_lock); 1146 /* Ring doorbell once to update PCC subspace */ 1147 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) { 1148 ret = -EIO; 1149 goto out_err; 1150 } 1151 } 1152 1153 cpc_read(cpunum, highest_reg, &high); 1154 perf_caps->highest_perf = high; 1155 1156 cpc_read(cpunum, lowest_reg, &low); 1157 perf_caps->lowest_perf = low; 1158 1159 cpc_read(cpunum, nominal_reg, &nom); 1160 perf_caps->nominal_perf = nom; 1161 1162 if (guaranteed_reg->type != ACPI_TYPE_BUFFER || 1163 IS_NULL_REG(&guaranteed_reg->cpc_entry.reg)) { 1164 perf_caps->guaranteed_perf = 0; 1165 } else { 1166 cpc_read(cpunum, guaranteed_reg, &guaranteed); 1167 perf_caps->guaranteed_perf = guaranteed; 1168 } 1169 1170 cpc_read(cpunum, lowest_non_linear_reg, &min_nonlinear); 1171 perf_caps->lowest_nonlinear_perf = min_nonlinear; 1172 1173 if (!high || !low || !nom || !min_nonlinear) 1174 ret = -EFAULT; 1175 1176 /* Read optional lowest and nominal frequencies if present */ 1177 if (CPC_SUPPORTED(low_freq_reg)) 1178 cpc_read(cpunum, low_freq_reg, &low_f); 1179 1180 if (CPC_SUPPORTED(nom_freq_reg)) 1181 cpc_read(cpunum, nom_freq_reg, &nom_f); 1182 1183 perf_caps->lowest_freq = low_f; 1184 perf_caps->nominal_freq = nom_f; 1185 1186 1187 out_err: 1188 if (regs_in_pcc) 1189 up_write(&pcc_ss_data->pcc_lock); 1190 return ret; 1191 } 1192 EXPORT_SYMBOL_GPL(cppc_get_perf_caps); 1193 1194 /** 1195 * cppc_get_perf_ctrs - Read a CPU's performance feedback counters. 1196 * @cpunum: CPU from which to read counters. 1197 * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h 1198 * 1199 * Return: 0 for success with perf_fb_ctrs populated else -ERRNO. 1200 */ 1201 int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) 1202 { 1203 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); 1204 struct cpc_register_resource *delivered_reg, *reference_reg, 1205 *ref_perf_reg, *ctr_wrap_reg; 1206 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); 1207 struct cppc_pcc_data *pcc_ss_data = NULL; 1208 u64 delivered, reference, ref_perf, ctr_wrap_time; 1209 int ret = 0, regs_in_pcc = 0; 1210 1211 if (!cpc_desc) { 1212 pr_debug("No CPC descriptor for CPU:%d\n", cpunum); 1213 return -ENODEV; 1214 } 1215 1216 delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR]; 1217 reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR]; 1218 ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF]; 1219 ctr_wrap_reg = &cpc_desc->cpc_regs[CTR_WRAP_TIME]; 1220 1221 /* 1222 * If reference perf register is not supported then we should 1223 * use the nominal perf value 1224 */ 1225 if (!CPC_SUPPORTED(ref_perf_reg)) 1226 ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF]; 1227 1228 /* Are any of the regs PCC ?*/ 1229 if (CPC_IN_PCC(delivered_reg) || CPC_IN_PCC(reference_reg) || 1230 CPC_IN_PCC(ctr_wrap_reg) || CPC_IN_PCC(ref_perf_reg)) { 1231 if (pcc_ss_id < 0) { 1232 pr_debug("Invalid pcc_ss_id\n"); 1233 return -ENODEV; 1234 } 1235 pcc_ss_data = pcc_data[pcc_ss_id]; 1236 down_write(&pcc_ss_data->pcc_lock); 1237 regs_in_pcc = 1; 1238 /* Ring doorbell once to update PCC subspace */ 1239 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) { 1240 ret = -EIO; 1241 goto out_err; 1242 } 1243 } 1244 1245 cpc_read(cpunum, delivered_reg, &delivered); 1246 cpc_read(cpunum, reference_reg, &reference); 1247 cpc_read(cpunum, ref_perf_reg, &ref_perf); 1248 1249 /* 1250 * Per spec, if ctr_wrap_time optional register is unsupported, then the 1251 * performance counters are assumed to never wrap during the lifetime of 1252 * platform 1253 */ 1254 ctr_wrap_time = (u64)(~((u64)0)); 1255 if (CPC_SUPPORTED(ctr_wrap_reg)) 1256 cpc_read(cpunum, ctr_wrap_reg, &ctr_wrap_time); 1257 1258 if (!delivered || !reference || !ref_perf) { 1259 ret = -EFAULT; 1260 goto out_err; 1261 } 1262 1263 perf_fb_ctrs->delivered = delivered; 1264 perf_fb_ctrs->reference = reference; 1265 perf_fb_ctrs->reference_perf = ref_perf; 1266 perf_fb_ctrs->wraparound_time = ctr_wrap_time; 1267 out_err: 1268 if (regs_in_pcc) 1269 up_write(&pcc_ss_data->pcc_lock); 1270 return ret; 1271 } 1272 EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs); 1273 1274 /** 1275 * cppc_set_enable - Set to enable CPPC on the processor by writing the 1276 * Continuous Performance Control package EnableRegister field. 1277 * @cpu: CPU for which to enable CPPC register. 1278 * @enable: 0 - disable, 1 - enable CPPC feature on the processor. 1279 * 1280 * Return: 0 for success, -ERRNO or -EIO otherwise. 1281 */ 1282 int cppc_set_enable(int cpu, bool enable) 1283 { 1284 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); 1285 struct cpc_register_resource *enable_reg; 1286 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); 1287 struct cppc_pcc_data *pcc_ss_data = NULL; 1288 int ret = -EINVAL; 1289 1290 if (!cpc_desc) { 1291 pr_debug("No CPC descriptor for CPU:%d\n", cpu); 1292 return -EINVAL; 1293 } 1294 1295 enable_reg = &cpc_desc->cpc_regs[ENABLE]; 1296 1297 if (CPC_IN_PCC(enable_reg)) { 1298 1299 if (pcc_ss_id < 0) 1300 return -EIO; 1301 1302 ret = cpc_write(cpu, enable_reg, enable); 1303 if (ret) 1304 return ret; 1305 1306 pcc_ss_data = pcc_data[pcc_ss_id]; 1307 1308 down_write(&pcc_ss_data->pcc_lock); 1309 /* after writing CPC, transfer the ownership of PCC to platfrom */ 1310 ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE); 1311 up_write(&pcc_ss_data->pcc_lock); 1312 return ret; 1313 } 1314 1315 return cpc_write(cpu, enable_reg, enable); 1316 } 1317 EXPORT_SYMBOL_GPL(cppc_set_enable); 1318 1319 /** 1320 * cppc_set_perf - Set a CPU's performance controls. 1321 * @cpu: CPU for which to set performance controls. 1322 * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h 1323 * 1324 * Return: 0 for success, -ERRNO otherwise. 1325 */ 1326 int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) 1327 { 1328 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); 1329 struct cpc_register_resource *desired_reg; 1330 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); 1331 struct cppc_pcc_data *pcc_ss_data = NULL; 1332 int ret = 0; 1333 1334 if (!cpc_desc) { 1335 pr_debug("No CPC descriptor for CPU:%d\n", cpu); 1336 return -ENODEV; 1337 } 1338 1339 desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; 1340 1341 /* 1342 * This is Phase-I where we want to write to CPC registers 1343 * -> We want all CPUs to be able to execute this phase in parallel 1344 * 1345 * Since read_lock can be acquired by multiple CPUs simultaneously we 1346 * achieve that goal here 1347 */ 1348 if (CPC_IN_PCC(desired_reg)) { 1349 if (pcc_ss_id < 0) { 1350 pr_debug("Invalid pcc_ss_id\n"); 1351 return -ENODEV; 1352 } 1353 pcc_ss_data = pcc_data[pcc_ss_id]; 1354 down_read(&pcc_ss_data->pcc_lock); /* BEGIN Phase-I */ 1355 if (pcc_ss_data->platform_owns_pcc) { 1356 ret = check_pcc_chan(pcc_ss_id, false); 1357 if (ret) { 1358 up_read(&pcc_ss_data->pcc_lock); 1359 return ret; 1360 } 1361 } 1362 /* 1363 * Update the pending_write to make sure a PCC CMD_READ will not 1364 * arrive and steal the channel during the switch to write lock 1365 */ 1366 pcc_ss_data->pending_pcc_write_cmd = true; 1367 cpc_desc->write_cmd_id = pcc_ss_data->pcc_write_cnt; 1368 cpc_desc->write_cmd_status = 0; 1369 } 1370 1371 /* 1372 * Skip writing MIN/MAX until Linux knows how to come up with 1373 * useful values. 1374 */ 1375 cpc_write(cpu, desired_reg, perf_ctrls->desired_perf); 1376 1377 if (CPC_IN_PCC(desired_reg)) 1378 up_read(&pcc_ss_data->pcc_lock); /* END Phase-I */ 1379 /* 1380 * This is Phase-II where we transfer the ownership of PCC to Platform 1381 * 1382 * Short Summary: Basically if we think of a group of cppc_set_perf 1383 * requests that happened in short overlapping interval. The last CPU to 1384 * come out of Phase-I will enter Phase-II and ring the doorbell. 1385 * 1386 * We have the following requirements for Phase-II: 1387 * 1. We want to execute Phase-II only when there are no CPUs 1388 * currently executing in Phase-I 1389 * 2. Once we start Phase-II we want to avoid all other CPUs from 1390 * entering Phase-I. 1391 * 3. We want only one CPU among all those who went through Phase-I 1392 * to run phase-II 1393 * 1394 * If write_trylock fails to get the lock and doesn't transfer the 1395 * PCC ownership to the platform, then one of the following will be TRUE 1396 * 1. There is at-least one CPU in Phase-I which will later execute 1397 * write_trylock, so the CPUs in Phase-I will be responsible for 1398 * executing the Phase-II. 1399 * 2. Some other CPU has beaten this CPU to successfully execute the 1400 * write_trylock and has already acquired the write_lock. We know for a 1401 * fact it (other CPU acquiring the write_lock) couldn't have happened 1402 * before this CPU's Phase-I as we held the read_lock. 1403 * 3. Some other CPU executing pcc CMD_READ has stolen the 1404 * down_write, in which case, send_pcc_cmd will check for pending 1405 * CMD_WRITE commands by checking the pending_pcc_write_cmd. 1406 * So this CPU can be certain that its request will be delivered 1407 * So in all cases, this CPU knows that its request will be delivered 1408 * by another CPU and can return 1409 * 1410 * After getting the down_write we still need to check for 1411 * pending_pcc_write_cmd to take care of the following scenario 1412 * The thread running this code could be scheduled out between 1413 * Phase-I and Phase-II. Before it is scheduled back on, another CPU 1414 * could have delivered the request to Platform by triggering the 1415 * doorbell and transferred the ownership of PCC to platform. So this 1416 * avoids triggering an unnecessary doorbell and more importantly before 1417 * triggering the doorbell it makes sure that the PCC channel ownership 1418 * is still with OSPM. 1419 * pending_pcc_write_cmd can also be cleared by a different CPU, if 1420 * there was a pcc CMD_READ waiting on down_write and it steals the lock 1421 * before the pcc CMD_WRITE is completed. send_pcc_cmd checks for this 1422 * case during a CMD_READ and if there are pending writes it delivers 1423 * the write command before servicing the read command 1424 */ 1425 if (CPC_IN_PCC(desired_reg)) { 1426 if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */ 1427 /* Update only if there are pending write commands */ 1428 if (pcc_ss_data->pending_pcc_write_cmd) 1429 send_pcc_cmd(pcc_ss_id, CMD_WRITE); 1430 up_write(&pcc_ss_data->pcc_lock); /* END Phase-II */ 1431 } else 1432 /* Wait until pcc_write_cnt is updated by send_pcc_cmd */ 1433 wait_event(pcc_ss_data->pcc_write_wait_q, 1434 cpc_desc->write_cmd_id != pcc_ss_data->pcc_write_cnt); 1435 1436 /* send_pcc_cmd updates the status in case of failure */ 1437 ret = cpc_desc->write_cmd_status; 1438 } 1439 return ret; 1440 } 1441 EXPORT_SYMBOL_GPL(cppc_set_perf); 1442 1443 /** 1444 * cppc_get_transition_latency - returns frequency transition latency in ns 1445 * 1446 * ACPI CPPC does not explicitly specify how a platform can specify the 1447 * transition latency for performance change requests. The closest we have 1448 * is the timing information from the PCCT tables which provides the info 1449 * on the number and frequency of PCC commands the platform can handle. 1450 */ 1451 unsigned int cppc_get_transition_latency(int cpu_num) 1452 { 1453 /* 1454 * Expected transition latency is based on the PCCT timing values 1455 * Below are definition from ACPI spec: 1456 * pcc_nominal- Expected latency to process a command, in microseconds 1457 * pcc_mpar - The maximum number of periodic requests that the subspace 1458 * channel can support, reported in commands per minute. 0 1459 * indicates no limitation. 1460 * pcc_mrtt - The minimum amount of time that OSPM must wait after the 1461 * completion of a command before issuing the next command, 1462 * in microseconds. 1463 */ 1464 unsigned int latency_ns = 0; 1465 struct cpc_desc *cpc_desc; 1466 struct cpc_register_resource *desired_reg; 1467 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu_num); 1468 struct cppc_pcc_data *pcc_ss_data; 1469 1470 cpc_desc = per_cpu(cpc_desc_ptr, cpu_num); 1471 if (!cpc_desc) 1472 return CPUFREQ_ETERNAL; 1473 1474 desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; 1475 if (!CPC_IN_PCC(desired_reg)) 1476 return CPUFREQ_ETERNAL; 1477 1478 if (pcc_ss_id < 0) 1479 return CPUFREQ_ETERNAL; 1480 1481 pcc_ss_data = pcc_data[pcc_ss_id]; 1482 if (pcc_ss_data->pcc_mpar) 1483 latency_ns = 60 * (1000 * 1000 * 1000 / pcc_ss_data->pcc_mpar); 1484 1485 latency_ns = max(latency_ns, pcc_ss_data->pcc_nominal * 1000); 1486 latency_ns = max(latency_ns, pcc_ss_data->pcc_mrtt * 1000); 1487 1488 return latency_ns; 1489 } 1490 EXPORT_SYMBOL_GPL(cppc_get_transition_latency); 1491