1b886d83cSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2337aadffSAshwin Chaugule /*
3337aadffSAshwin Chaugule * CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers.
4337aadffSAshwin Chaugule *
5337aadffSAshwin Chaugule * (C) Copyright 2014, 2015 Linaro Ltd.
6337aadffSAshwin Chaugule * Author: Ashwin Chaugule <ashwin.chaugule@linaro.org>
7337aadffSAshwin Chaugule *
8337aadffSAshwin Chaugule * CPPC describes a few methods for controlling CPU performance using
9337aadffSAshwin Chaugule * information from a per CPU table called CPC. This table is described in
10337aadffSAshwin Chaugule * the ACPI v5.0+ specification. The table consists of a list of
11337aadffSAshwin Chaugule * registers which may be memory mapped or hardware registers and also may
12337aadffSAshwin Chaugule * include some static integer values.
13337aadffSAshwin Chaugule *
14337aadffSAshwin Chaugule * CPU performance is on an abstract continuous scale as against a discretized
15337aadffSAshwin Chaugule * P-state scale which is tied to CPU frequency only. In brief, the basic
16337aadffSAshwin Chaugule * operation involves:
17337aadffSAshwin Chaugule *
18337aadffSAshwin Chaugule * - OS makes a CPU performance request. (Can provide min and max bounds)
19337aadffSAshwin Chaugule *
20337aadffSAshwin Chaugule * - Platform (such as BMC) is free to optimize request within requested bounds
21337aadffSAshwin Chaugule * depending on power/thermal budgets etc.
22337aadffSAshwin Chaugule *
23337aadffSAshwin Chaugule * - Platform conveys its decision back to OS
24337aadffSAshwin Chaugule *
25337aadffSAshwin Chaugule * The communication between OS and platform occurs through another medium
26337aadffSAshwin Chaugule * called (PCC) Platform Communication Channel. This is a generic mailbox like
27337aadffSAshwin Chaugule * mechanism which includes doorbell semantics to indicate register updates.
28337aadffSAshwin Chaugule * See drivers/mailbox/pcc.c for details on PCC.
29337aadffSAshwin Chaugule *
30337aadffSAshwin Chaugule * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and
31337aadffSAshwin Chaugule * above specifications.
32337aadffSAshwin Chaugule */
33337aadffSAshwin Chaugule
34337aadffSAshwin Chaugule #define pr_fmt(fmt) "ACPI CPPC: " fmt
35337aadffSAshwin Chaugule
36337aadffSAshwin Chaugule #include <linux/delay.h>
3758e1c035SPrakash, Prashanth #include <linux/iopoll.h>
38ad62e1e6SAshwin Chaugule #include <linux/ktime.h>
3980b8286aSPrakash, Prashanth #include <linux/rwsem.h>
4080b8286aSPrakash, Prashanth #include <linux/wait.h>
4141ea6672SNathan Fontenot #include <linux/topology.h>
42337aadffSAshwin Chaugule
43337aadffSAshwin Chaugule #include <acpi/cppc_acpi.h>
4480b8286aSPrakash, Prashanth
458482ef8cSPrakash, Prashanth struct cppc_pcc_data {
467b6da7feSSudeep Holla struct pcc_mbox_chan *pcc_channel;
478482ef8cSPrakash, Prashanth void __iomem *pcc_comm_addr;
488482ef8cSPrakash, Prashanth bool pcc_channel_acquired;
4958e1c035SPrakash, Prashanth unsigned int deadline_us;
508482ef8cSPrakash, Prashanth unsigned int pcc_mpar, pcc_mrtt, pcc_nominal;
518482ef8cSPrakash, Prashanth
528482ef8cSPrakash, Prashanth bool pending_pcc_write_cmd; /* Any pending/batched PCC write cmds? */
53139aee73SPrakash, Prashanth bool platform_owns_pcc; /* Ownership of PCC subspace */
548482ef8cSPrakash, Prashanth unsigned int pcc_write_cnt; /* Running count of PCC write commands */
558482ef8cSPrakash, Prashanth
56337aadffSAshwin Chaugule /*
5780b8286aSPrakash, Prashanth * Lock to provide controlled access to the PCC channel.
5880b8286aSPrakash, Prashanth *
5980b8286aSPrakash, Prashanth * For performance critical usecases(currently cppc_set_perf)
608482ef8cSPrakash, Prashanth * We need to take read_lock and check if channel belongs to OSPM
618482ef8cSPrakash, Prashanth * before reading or writing to PCC subspace
628482ef8cSPrakash, Prashanth * We need to take write_lock before transferring the channel
638482ef8cSPrakash, Prashanth * ownership to the platform via a Doorbell
648482ef8cSPrakash, Prashanth * This allows us to batch a number of CPPC requests if they happen
658482ef8cSPrakash, Prashanth * to originate in about the same time
6680b8286aSPrakash, Prashanth *
6780b8286aSPrakash, Prashanth * For non-performance critical usecases(init)
6880b8286aSPrakash, Prashanth * Take write_lock for all purposes which gives exclusive access
69337aadffSAshwin Chaugule */
708482ef8cSPrakash, Prashanth struct rw_semaphore pcc_lock;
7180b8286aSPrakash, Prashanth
7280b8286aSPrakash, Prashanth /* Wait queue for CPUs whose requests were batched */
738482ef8cSPrakash, Prashanth wait_queue_head_t pcc_write_wait_q;
7485b1407bSGeorge Cherian ktime_t last_cmd_cmpl_time;
7585b1407bSGeorge Cherian ktime_t last_mpar_reset;
7685b1407bSGeorge Cherian int mpar_count;
7785b1407bSGeorge Cherian int refcount;
788482ef8cSPrakash, Prashanth };
7980b8286aSPrakash, Prashanth
80603fadf3SBjorn Helgaas /* Array to represent the PCC channel per subspace ID */
8185b1407bSGeorge Cherian static struct cppc_pcc_data *pcc_data[MAX_PCC_SUBSPACES];
82603fadf3SBjorn Helgaas /* The cpu_pcc_subspace_idx contains per CPU subspace ID */
8385b1407bSGeorge Cherian static DEFINE_PER_CPU(int, cpu_pcc_subspace_idx);
84337aadffSAshwin Chaugule
85337aadffSAshwin Chaugule /*
86337aadffSAshwin Chaugule * The cpc_desc structure contains the ACPI register details
87337aadffSAshwin Chaugule * as described in the per CPU _CPC tables. The details
88337aadffSAshwin Chaugule * include the type of register (e.g. PCC, System IO, FFH etc.)
89337aadffSAshwin Chaugule * and destination addresses which lets us READ/WRITE CPU performance
90337aadffSAshwin Chaugule * information using the appropriate I/O methods.
91337aadffSAshwin Chaugule */
92337aadffSAshwin Chaugule static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
93337aadffSAshwin Chaugule
9477e3d86fSPrakash, Prashanth /* pcc mapped address + header size + offset within PCC subspace */
9585b1407bSGeorge Cherian #define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_comm_addr + \
9685b1407bSGeorge Cherian 0x8 + (offs))
9777e3d86fSPrakash, Prashanth
98ad61dd30SStephen Boyd /* Check if a CPC register is in PCC */
9980b8286aSPrakash, Prashanth #define CPC_IN_PCC(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
10080b8286aSPrakash, Prashanth (cpc)->cpc_entry.reg.space_id == \
10180b8286aSPrakash, Prashanth ACPI_ADR_SPACE_PLATFORM_COMM)
10280b8286aSPrakash, Prashanth
1036380b7b2SPierre Gondois /* Check if a CPC register is in SystemMemory */
1046380b7b2SPierre Gondois #define CPC_IN_SYSTEM_MEMORY(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
1056380b7b2SPierre Gondois (cpc)->cpc_entry.reg.space_id == \
1066380b7b2SPierre Gondois ACPI_ADR_SPACE_SYSTEM_MEMORY)
1076380b7b2SPierre Gondois
1086380b7b2SPierre Gondois /* Check if a CPC register is in SystemIo */
1096380b7b2SPierre Gondois #define CPC_IN_SYSTEM_IO(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
1106380b7b2SPierre Gondois (cpc)->cpc_entry.reg.space_id == \
1116380b7b2SPierre Gondois ACPI_ADR_SPACE_SYSTEM_IO)
1126380b7b2SPierre Gondois
113935ab850STom Saeger /* Evaluates to True if reg is a NULL register descriptor */
114158c998eSAshwin Chaugule #define IS_NULL_REG(reg) ((reg)->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY && \
115158c998eSAshwin Chaugule (reg)->address == 0 && \
116158c998eSAshwin Chaugule (reg)->bit_width == 0 && \
117158c998eSAshwin Chaugule (reg)->bit_offset == 0 && \
118158c998eSAshwin Chaugule (reg)->access_width == 0)
119158c998eSAshwin Chaugule
120935ab850STom Saeger /* Evaluates to True if an optional cpc field is supported */
121158c998eSAshwin Chaugule #define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ? \
122158c998eSAshwin Chaugule !!(cpc)->cpc_entry.int_value : \
123158c998eSAshwin Chaugule !IS_NULL_REG(&(cpc)->cpc_entry.reg))
124337aadffSAshwin Chaugule /*
125337aadffSAshwin Chaugule * Arbitrary Retries in case the remote processor is slow to respond
126ad62e1e6SAshwin Chaugule * to PCC commands. Keeping it high enough to cover emulators where
127ad62e1e6SAshwin Chaugule * the processors run painfully slow.
128337aadffSAshwin Chaugule */
129b52f4511SGustavo A. R. Silva #define NUM_RETRIES 500ULL
130337aadffSAshwin Chaugule
131a2c8f92bSSteven Noonan #define OVER_16BTS_MASK ~0xFFFFULL
132a2c8f92bSSteven Noonan
133158c998eSAshwin Chaugule #define define_one_cppc_ro(_name) \
1342bc6262cSNathan Chancellor static struct kobj_attribute _name = \
135158c998eSAshwin Chaugule __ATTR(_name, 0444, show_##_name, NULL)
136158c998eSAshwin Chaugule
137158c998eSAshwin Chaugule #define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj)
138158c998eSAshwin Chaugule
1392c74d847SPrakash, Prashanth #define show_cppc_data(access_fn, struct_name, member_name) \
1402c74d847SPrakash, Prashanth static ssize_t show_##member_name(struct kobject *kobj, \
1412bc6262cSNathan Chancellor struct kobj_attribute *attr, char *buf) \
1422c74d847SPrakash, Prashanth { \
1432c74d847SPrakash, Prashanth struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); \
1442c74d847SPrakash, Prashanth struct struct_name st_name = {0}; \
1452c74d847SPrakash, Prashanth int ret; \
1462c74d847SPrakash, Prashanth \
1472c74d847SPrakash, Prashanth ret = access_fn(cpc_ptr->cpu_id, &st_name); \
1482c74d847SPrakash, Prashanth if (ret) \
1492c74d847SPrakash, Prashanth return ret; \
1502c74d847SPrakash, Prashanth \
15192266c65Sye xingchen return sysfs_emit(buf, "%llu\n", \
1522c74d847SPrakash, Prashanth (u64)st_name.member_name); \
1532c74d847SPrakash, Prashanth } \
1542c74d847SPrakash, Prashanth define_one_cppc_ro(member_name)
1552c74d847SPrakash, Prashanth
1562c74d847SPrakash, Prashanth show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf);
1572c74d847SPrakash, Prashanth show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf);
1582c74d847SPrakash, Prashanth show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf);
1592c74d847SPrakash, Prashanth show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf);
1604773e77cSPrashanth Prakash show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq);
1614773e77cSPrashanth Prakash show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq);
1624773e77cSPrashanth Prakash
1632c74d847SPrakash, Prashanth show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf);
1642c74d847SPrakash, Prashanth show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time);
1652c74d847SPrakash, Prashanth
1661b890ae4SJarred White /* Check for valid access_width, otherwise, fallback to using bit_width */
1671b890ae4SJarred White #define GET_BIT_WIDTH(reg) ((reg)->access_width ? (8 << ((reg)->access_width - 1)) : (reg)->bit_width)
1681b890ae4SJarred White
1691b890ae4SJarred White /* Shift and apply the mask for CPC reads/writes */
1706a8fda8aSJarred White #define MASK_VAL(reg, val) (((val) >> (reg)->bit_offset) & \
1716a8fda8aSJarred White GENMASK(((reg)->bit_width) - 1, 0))
1721b890ae4SJarred White
show_feedback_ctrs(struct kobject * kobj,struct kobj_attribute * attr,char * buf)173158c998eSAshwin Chaugule static ssize_t show_feedback_ctrs(struct kobject *kobj,
1742bc6262cSNathan Chancellor struct kobj_attribute *attr, char *buf)
175158c998eSAshwin Chaugule {
176158c998eSAshwin Chaugule struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);
177158c998eSAshwin Chaugule struct cppc_perf_fb_ctrs fb_ctrs = {0};
1782c74d847SPrakash, Prashanth int ret;
179158c998eSAshwin Chaugule
1802c74d847SPrakash, Prashanth ret = cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs);
1812c74d847SPrakash, Prashanth if (ret)
1822c74d847SPrakash, Prashanth return ret;
183158c998eSAshwin Chaugule
18492266c65Sye xingchen return sysfs_emit(buf, "ref:%llu del:%llu\n",
185158c998eSAshwin Chaugule fb_ctrs.reference, fb_ctrs.delivered);
186158c998eSAshwin Chaugule }
187158c998eSAshwin Chaugule define_one_cppc_ro(feedback_ctrs);
188158c998eSAshwin Chaugule
189158c998eSAshwin Chaugule static struct attribute *cppc_attrs[] = {
190158c998eSAshwin Chaugule &feedback_ctrs.attr,
191158c998eSAshwin Chaugule &reference_perf.attr,
192158c998eSAshwin Chaugule &wraparound_time.attr,
1932c74d847SPrakash, Prashanth &highest_perf.attr,
1942c74d847SPrakash, Prashanth &lowest_perf.attr,
1952c74d847SPrakash, Prashanth &lowest_nonlinear_perf.attr,
1962c74d847SPrakash, Prashanth &nominal_perf.attr,
1974773e77cSPrashanth Prakash &nominal_freq.attr,
1984773e77cSPrashanth Prakash &lowest_freq.attr,
199158c998eSAshwin Chaugule NULL
200158c998eSAshwin Chaugule };
20117f18417SGreg Kroah-Hartman ATTRIBUTE_GROUPS(cppc);
202158c998eSAshwin Chaugule
203a527b011SThomas Weißschuh static const struct kobj_type cppc_ktype = {
204158c998eSAshwin Chaugule .sysfs_ops = &kobj_sysfs_ops,
20517f18417SGreg Kroah-Hartman .default_groups = cppc_groups,
206158c998eSAshwin Chaugule };
207158c998eSAshwin Chaugule
check_pcc_chan(int pcc_ss_id,bool chk_err_bit)20885b1407bSGeorge Cherian static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit)
209ad62e1e6SAshwin Chaugule {
21058e1c035SPrakash, Prashanth int ret, status;
21185b1407bSGeorge Cherian struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
21285b1407bSGeorge Cherian struct acpi_pcct_shared_memory __iomem *generic_comm_base =
21385b1407bSGeorge Cherian pcc_ss_data->pcc_comm_addr;
214ad62e1e6SAshwin Chaugule
21585b1407bSGeorge Cherian if (!pcc_ss_data->platform_owns_pcc)
216139aee73SPrakash, Prashanth return 0;
217139aee73SPrakash, Prashanth
218f387e5b9SPrakash, Prashanth /*
21958e1c035SPrakash, Prashanth * Poll PCC status register every 3us(delay_us) for maximum of
22058e1c035SPrakash, Prashanth * deadline_us(timeout_us) until PCC command complete bit is set(cond)
221f387e5b9SPrakash, Prashanth */
22258e1c035SPrakash, Prashanth ret = readw_relaxed_poll_timeout(&generic_comm_base->status, status,
22358e1c035SPrakash, Prashanth status & PCC_CMD_COMPLETE_MASK, 3,
22458e1c035SPrakash, Prashanth pcc_ss_data->deadline_us);
22558e1c035SPrakash, Prashanth
22658e1c035SPrakash, Prashanth if (likely(!ret)) {
22758e1c035SPrakash, Prashanth pcc_ss_data->platform_owns_pcc = false;
228139aee73SPrakash, Prashanth if (chk_err_bit && (status & PCC_ERROR_MASK))
229139aee73SPrakash, Prashanth ret = -EIO;
230ad62e1e6SAshwin Chaugule }
231ad62e1e6SAshwin Chaugule
23258e1c035SPrakash, Prashanth if (unlikely(ret))
23358e1c035SPrakash, Prashanth pr_err("PCC check channel failed for ss: %d. ret=%d\n",
23458e1c035SPrakash, Prashanth pcc_ss_id, ret);
235139aee73SPrakash, Prashanth
236ad62e1e6SAshwin Chaugule return ret;
237ad62e1e6SAshwin Chaugule }
238ad62e1e6SAshwin Chaugule
23980b8286aSPrakash, Prashanth /*
24080b8286aSPrakash, Prashanth * This function transfers the ownership of the PCC to the platform
24180b8286aSPrakash, Prashanth * So it must be called while holding write_lock(pcc_lock)
24280b8286aSPrakash, Prashanth */
send_pcc_cmd(int pcc_ss_id,u16 cmd)24385b1407bSGeorge Cherian static int send_pcc_cmd(int pcc_ss_id, u16 cmd)
244337aadffSAshwin Chaugule {
24580b8286aSPrakash, Prashanth int ret = -EIO, i;
24685b1407bSGeorge Cherian struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
2471d9b4abeSIonela Voinescu struct acpi_pcct_shared_memory __iomem *generic_comm_base =
2481d9b4abeSIonela Voinescu pcc_ss_data->pcc_comm_addr;
249f387e5b9SPrakash, Prashanth unsigned int time_delta;
250337aadffSAshwin Chaugule
251ad62e1e6SAshwin Chaugule /*
252ad62e1e6SAshwin Chaugule * For CMD_WRITE we know for a fact the caller should have checked
253ad62e1e6SAshwin Chaugule * the channel before writing to PCC space
254ad62e1e6SAshwin Chaugule */
255ad62e1e6SAshwin Chaugule if (cmd == CMD_READ) {
25680b8286aSPrakash, Prashanth /*
25780b8286aSPrakash, Prashanth * If there are pending cpc_writes, then we stole the channel
25880b8286aSPrakash, Prashanth * before write completion, so first send a WRITE command to
25980b8286aSPrakash, Prashanth * platform
26080b8286aSPrakash, Prashanth */
26185b1407bSGeorge Cherian if (pcc_ss_data->pending_pcc_write_cmd)
26285b1407bSGeorge Cherian send_pcc_cmd(pcc_ss_id, CMD_WRITE);
26380b8286aSPrakash, Prashanth
26485b1407bSGeorge Cherian ret = check_pcc_chan(pcc_ss_id, false);
265ad62e1e6SAshwin Chaugule if (ret)
26680b8286aSPrakash, Prashanth goto end;
26780b8286aSPrakash, Prashanth } else /* CMD_WRITE */
26885b1407bSGeorge Cherian pcc_ss_data->pending_pcc_write_cmd = FALSE;
269337aadffSAshwin Chaugule
270f387e5b9SPrakash, Prashanth /*
271f387e5b9SPrakash, Prashanth * Handle the Minimum Request Turnaround Time(MRTT)
272f387e5b9SPrakash, Prashanth * "The minimum amount of time that OSPM must wait after the completion
273f387e5b9SPrakash, Prashanth * of a command before issuing the next command, in microseconds"
274f387e5b9SPrakash, Prashanth */
27585b1407bSGeorge Cherian if (pcc_ss_data->pcc_mrtt) {
27685b1407bSGeorge Cherian time_delta = ktime_us_delta(ktime_get(),
27785b1407bSGeorge Cherian pcc_ss_data->last_cmd_cmpl_time);
27885b1407bSGeorge Cherian if (pcc_ss_data->pcc_mrtt > time_delta)
27985b1407bSGeorge Cherian udelay(pcc_ss_data->pcc_mrtt - time_delta);
280f387e5b9SPrakash, Prashanth }
281f387e5b9SPrakash, Prashanth
282f387e5b9SPrakash, Prashanth /*
283f387e5b9SPrakash, Prashanth * Handle the non-zero Maximum Periodic Access Rate(MPAR)
284f387e5b9SPrakash, Prashanth * "The maximum number of periodic requests that the subspace channel can
285f387e5b9SPrakash, Prashanth * support, reported in commands per minute. 0 indicates no limitation."
286f387e5b9SPrakash, Prashanth *
287f387e5b9SPrakash, Prashanth * This parameter should be ideally zero or large enough so that it can
288f387e5b9SPrakash, Prashanth * handle maximum number of requests that all the cores in the system can
289f387e5b9SPrakash, Prashanth * collectively generate. If it is not, we will follow the spec and just
290f387e5b9SPrakash, Prashanth * not send the request to the platform after hitting the MPAR limit in
291f387e5b9SPrakash, Prashanth * any 60s window
292f387e5b9SPrakash, Prashanth */
29385b1407bSGeorge Cherian if (pcc_ss_data->pcc_mpar) {
29485b1407bSGeorge Cherian if (pcc_ss_data->mpar_count == 0) {
29585b1407bSGeorge Cherian time_delta = ktime_ms_delta(ktime_get(),
29685b1407bSGeorge Cherian pcc_ss_data->last_mpar_reset);
29785b1407bSGeorge Cherian if ((time_delta < 60 * MSEC_PER_SEC) && pcc_ss_data->last_mpar_reset) {
298d29abc83SGeorge Cherian pr_debug("PCC cmd for subspace %d not sent due to MPAR limit",
299d29abc83SGeorge Cherian pcc_ss_id);
30080b8286aSPrakash, Prashanth ret = -EIO;
30180b8286aSPrakash, Prashanth goto end;
302f387e5b9SPrakash, Prashanth }
30385b1407bSGeorge Cherian pcc_ss_data->last_mpar_reset = ktime_get();
30485b1407bSGeorge Cherian pcc_ss_data->mpar_count = pcc_ss_data->pcc_mpar;
305f387e5b9SPrakash, Prashanth }
30685b1407bSGeorge Cherian pcc_ss_data->mpar_count--;
307f387e5b9SPrakash, Prashanth }
308f387e5b9SPrakash, Prashanth
309337aadffSAshwin Chaugule /* Write to the shared comm region. */
310beee23aeSPrakash, Prashanth writew_relaxed(cmd, &generic_comm_base->command);
311337aadffSAshwin Chaugule
312337aadffSAshwin Chaugule /* Flip CMD COMPLETE bit */
313beee23aeSPrakash, Prashanth writew_relaxed(0, &generic_comm_base->status);
314337aadffSAshwin Chaugule
31585b1407bSGeorge Cherian pcc_ss_data->platform_owns_pcc = true;
316139aee73SPrakash, Prashanth
317337aadffSAshwin Chaugule /* Ring doorbell */
3187b6da7feSSudeep Holla ret = mbox_send_message(pcc_ss_data->pcc_channel->mchan, &cmd);
319ad62e1e6SAshwin Chaugule if (ret < 0) {
320d29abc83SGeorge Cherian pr_err("Err sending PCC mbox message. ss: %d cmd:%d, ret:%d\n",
321d29abc83SGeorge Cherian pcc_ss_id, cmd, ret);
32280b8286aSPrakash, Prashanth goto end;
323337aadffSAshwin Chaugule }
324337aadffSAshwin Chaugule
3259e12eb82SJulia Lawall /* wait for completion and check for PCC error bit */
32685b1407bSGeorge Cherian ret = check_pcc_chan(pcc_ss_id, true);
327139aee73SPrakash, Prashanth
32885b1407bSGeorge Cherian if (pcc_ss_data->pcc_mrtt)
32985b1407bSGeorge Cherian pcc_ss_data->last_cmd_cmpl_time = ktime_get();
330337aadffSAshwin Chaugule
3317b6da7feSSudeep Holla if (pcc_ss_data->pcc_channel->mchan->mbox->txdone_irq)
3327b6da7feSSudeep Holla mbox_chan_txdone(pcc_ss_data->pcc_channel->mchan, ret);
333b59c4b3dSHoan Tran else
3347b6da7feSSudeep Holla mbox_client_txdone(pcc_ss_data->pcc_channel->mchan, ret);
33580b8286aSPrakash, Prashanth
33680b8286aSPrakash, Prashanth end:
33780b8286aSPrakash, Prashanth if (cmd == CMD_WRITE) {
33880b8286aSPrakash, Prashanth if (unlikely(ret)) {
33980b8286aSPrakash, Prashanth for_each_possible_cpu(i) {
34080b8286aSPrakash, Prashanth struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i);
341e69ae675SXiaofei Tan
34280b8286aSPrakash, Prashanth if (!desc)
34380b8286aSPrakash, Prashanth continue;
34480b8286aSPrakash, Prashanth
34585b1407bSGeorge Cherian if (desc->write_cmd_id == pcc_ss_data->pcc_write_cnt)
34680b8286aSPrakash, Prashanth desc->write_cmd_status = ret;
34780b8286aSPrakash, Prashanth }
34880b8286aSPrakash, Prashanth }
34985b1407bSGeorge Cherian pcc_ss_data->pcc_write_cnt++;
35085b1407bSGeorge Cherian wake_up_all(&pcc_ss_data->pcc_write_wait_q);
35180b8286aSPrakash, Prashanth }
35280b8286aSPrakash, Prashanth
353ad62e1e6SAshwin Chaugule return ret;
354337aadffSAshwin Chaugule }
355337aadffSAshwin Chaugule
cppc_chan_tx_done(struct mbox_client * cl,void * msg,int ret)356337aadffSAshwin Chaugule static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret)
357337aadffSAshwin Chaugule {
358ad62e1e6SAshwin Chaugule if (ret < 0)
359337aadffSAshwin Chaugule pr_debug("TX did not complete: CMD sent:%x, ret:%d\n",
360337aadffSAshwin Chaugule *(u16 *)msg, ret);
361337aadffSAshwin Chaugule else
362337aadffSAshwin Chaugule pr_debug("TX completed. CMD sent:%x, ret:%d\n",
363337aadffSAshwin Chaugule *(u16 *)msg, ret);
364337aadffSAshwin Chaugule }
365337aadffSAshwin Chaugule
3665c447c18SZou Wei static struct mbox_client cppc_mbox_cl = {
367337aadffSAshwin Chaugule .tx_done = cppc_chan_tx_done,
368337aadffSAshwin Chaugule .knows_txdone = true,
369337aadffSAshwin Chaugule };
370337aadffSAshwin Chaugule
acpi_get_psd(struct cpc_desc * cpc_ptr,acpi_handle handle)371337aadffSAshwin Chaugule static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle)
372337aadffSAshwin Chaugule {
373337aadffSAshwin Chaugule int result = -EFAULT;
374337aadffSAshwin Chaugule acpi_status status = AE_OK;
375337aadffSAshwin Chaugule struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
376337aadffSAshwin Chaugule struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"};
377337aadffSAshwin Chaugule struct acpi_buffer state = {0, NULL};
378337aadffSAshwin Chaugule union acpi_object *psd = NULL;
379337aadffSAshwin Chaugule struct acpi_psd_package *pdomain;
380337aadffSAshwin Chaugule
3814c4cdc4cSAl Stone status = acpi_evaluate_object_typed(handle, "_PSD", NULL,
3824c4cdc4cSAl Stone &buffer, ACPI_TYPE_PACKAGE);
3834c4cdc4cSAl Stone if (status == AE_NOT_FOUND) /* _PSD is optional */
3844c4cdc4cSAl Stone return 0;
385337aadffSAshwin Chaugule if (ACPI_FAILURE(status))
386337aadffSAshwin Chaugule return -ENODEV;
387337aadffSAshwin Chaugule
388337aadffSAshwin Chaugule psd = buffer.pointer;
389337aadffSAshwin Chaugule if (!psd || psd->package.count != 1) {
390337aadffSAshwin Chaugule pr_debug("Invalid _PSD data\n");
391337aadffSAshwin Chaugule goto end;
392337aadffSAshwin Chaugule }
393337aadffSAshwin Chaugule
394337aadffSAshwin Chaugule pdomain = &(cpc_ptr->domain_info);
395337aadffSAshwin Chaugule
396337aadffSAshwin Chaugule state.length = sizeof(struct acpi_psd_package);
397337aadffSAshwin Chaugule state.pointer = pdomain;
398337aadffSAshwin Chaugule
399337aadffSAshwin Chaugule status = acpi_extract_package(&(psd->package.elements[0]),
400337aadffSAshwin Chaugule &format, &state);
401337aadffSAshwin Chaugule if (ACPI_FAILURE(status)) {
402337aadffSAshwin Chaugule pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id);
403337aadffSAshwin Chaugule goto end;
404337aadffSAshwin Chaugule }
405337aadffSAshwin Chaugule
406337aadffSAshwin Chaugule if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) {
407337aadffSAshwin Chaugule pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id);
408337aadffSAshwin Chaugule goto end;
409337aadffSAshwin Chaugule }
410337aadffSAshwin Chaugule
411337aadffSAshwin Chaugule if (pdomain->revision != ACPI_PSD_REV0_REVISION) {
412337aadffSAshwin Chaugule pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id);
413337aadffSAshwin Chaugule goto end;
414337aadffSAshwin Chaugule }
415337aadffSAshwin Chaugule
416337aadffSAshwin Chaugule if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL &&
417337aadffSAshwin Chaugule pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY &&
418337aadffSAshwin Chaugule pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) {
419337aadffSAshwin Chaugule pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id);
420337aadffSAshwin Chaugule goto end;
421337aadffSAshwin Chaugule }
422337aadffSAshwin Chaugule
423337aadffSAshwin Chaugule result = 0;
424337aadffSAshwin Chaugule end:
425337aadffSAshwin Chaugule kfree(buffer.pointer);
426337aadffSAshwin Chaugule return result;
427337aadffSAshwin Chaugule }
428337aadffSAshwin Chaugule
acpi_cpc_valid(void)429a28b2bfcSIonela Voinescu bool acpi_cpc_valid(void)
430a28b2bfcSIonela Voinescu {
431a28b2bfcSIonela Voinescu struct cpc_desc *cpc_ptr;
432a28b2bfcSIonela Voinescu int cpu;
433a28b2bfcSIonela Voinescu
434a2a9d185SPerry Yuan if (acpi_disabled)
435a2a9d185SPerry Yuan return false;
436a2a9d185SPerry Yuan
4372aeca6bdSMario Limonciello for_each_present_cpu(cpu) {
438a28b2bfcSIonela Voinescu cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
439a28b2bfcSIonela Voinescu if (!cpc_ptr)
440a28b2bfcSIonela Voinescu return false;
441a28b2bfcSIonela Voinescu }
442a28b2bfcSIonela Voinescu
443a28b2bfcSIonela Voinescu return true;
444a28b2bfcSIonela Voinescu }
445a28b2bfcSIonela Voinescu EXPORT_SYMBOL_GPL(acpi_cpc_valid);
446a28b2bfcSIonela Voinescu
cppc_allow_fast_switch(void)4473cc30dd0SPierre Gondois bool cppc_allow_fast_switch(void)
4483cc30dd0SPierre Gondois {
4493cc30dd0SPierre Gondois struct cpc_register_resource *desired_reg;
4503cc30dd0SPierre Gondois struct cpc_desc *cpc_ptr;
4513cc30dd0SPierre Gondois int cpu;
4523cc30dd0SPierre Gondois
4533cc30dd0SPierre Gondois for_each_possible_cpu(cpu) {
4543cc30dd0SPierre Gondois cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
4553cc30dd0SPierre Gondois desired_reg = &cpc_ptr->cpc_regs[DESIRED_PERF];
4563cc30dd0SPierre Gondois if (!CPC_IN_SYSTEM_MEMORY(desired_reg) &&
4573cc30dd0SPierre Gondois !CPC_IN_SYSTEM_IO(desired_reg))
4583cc30dd0SPierre Gondois return false;
4593cc30dd0SPierre Gondois }
4603cc30dd0SPierre Gondois
4613cc30dd0SPierre Gondois return true;
4623cc30dd0SPierre Gondois }
4633cc30dd0SPierre Gondois EXPORT_SYMBOL_GPL(cppc_allow_fast_switch);
4643cc30dd0SPierre Gondois
465337aadffSAshwin Chaugule /**
466a28b2bfcSIonela Voinescu * acpi_get_psd_map - Map the CPUs in the freq domain of a given cpu
467a28b2bfcSIonela Voinescu * @cpu: Find all CPUs that share a domain with cpu.
468a28b2bfcSIonela Voinescu * @cpu_data: Pointer to CPU specific CPPC data including PSD info.
469337aadffSAshwin Chaugule *
470337aadffSAshwin Chaugule * Return: 0 for success or negative value for err.
471337aadffSAshwin Chaugule */
acpi_get_psd_map(unsigned int cpu,struct cppc_cpudata * cpu_data)472a28b2bfcSIonela Voinescu int acpi_get_psd_map(unsigned int cpu, struct cppc_cpudata *cpu_data)
473337aadffSAshwin Chaugule {
474337aadffSAshwin Chaugule struct cpc_desc *cpc_ptr, *match_cpc_ptr;
475a28b2bfcSIonela Voinescu struct acpi_psd_package *match_pdomain;
476a28b2bfcSIonela Voinescu struct acpi_psd_package *pdomain;
477a28b2bfcSIonela Voinescu int count_target, i;
478337aadffSAshwin Chaugule
479337aadffSAshwin Chaugule /*
480603fadf3SBjorn Helgaas * Now that we have _PSD data from all CPUs, let's setup P-state
481337aadffSAshwin Chaugule * domain info.
482337aadffSAshwin Chaugule */
483a28b2bfcSIonela Voinescu cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
484a28b2bfcSIonela Voinescu if (!cpc_ptr)
485a28b2bfcSIonela Voinescu return -EFAULT;
486337aadffSAshwin Chaugule
487337aadffSAshwin Chaugule pdomain = &(cpc_ptr->domain_info);
488a28b2bfcSIonela Voinescu cpumask_set_cpu(cpu, cpu_data->shared_cpu_map);
489337aadffSAshwin Chaugule if (pdomain->num_processors <= 1)
490a28b2bfcSIonela Voinescu return 0;
491337aadffSAshwin Chaugule
492337aadffSAshwin Chaugule /* Validate the Domain info */
493337aadffSAshwin Chaugule count_target = pdomain->num_processors;
494337aadffSAshwin Chaugule if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL)
495a28b2bfcSIonela Voinescu cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ALL;
496337aadffSAshwin Chaugule else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL)
497a28b2bfcSIonela Voinescu cpu_data->shared_type = CPUFREQ_SHARED_TYPE_HW;
498337aadffSAshwin Chaugule else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY)
499a28b2bfcSIonela Voinescu cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ANY;
500337aadffSAshwin Chaugule
501a28b2bfcSIonela Voinescu for_each_possible_cpu(i) {
502a28b2bfcSIonela Voinescu if (i == cpu)
503337aadffSAshwin Chaugule continue;
504337aadffSAshwin Chaugule
505a28b2bfcSIonela Voinescu match_cpc_ptr = per_cpu(cpc_desc_ptr, i);
506a28b2bfcSIonela Voinescu if (!match_cpc_ptr)
507a28b2bfcSIonela Voinescu goto err_fault;
508337aadffSAshwin Chaugule
509337aadffSAshwin Chaugule match_pdomain = &(match_cpc_ptr->domain_info);
510337aadffSAshwin Chaugule if (match_pdomain->domain != pdomain->domain)
511337aadffSAshwin Chaugule continue;
512337aadffSAshwin Chaugule
513a28b2bfcSIonela Voinescu /* Here i and cpu are in the same domain */
514a28b2bfcSIonela Voinescu if (match_pdomain->num_processors != count_target)
515a28b2bfcSIonela Voinescu goto err_fault;
516a28b2bfcSIonela Voinescu
517a28b2bfcSIonela Voinescu if (pdomain->coord_type != match_pdomain->coord_type)
518a28b2bfcSIonela Voinescu goto err_fault;
519a28b2bfcSIonela Voinescu
520a28b2bfcSIonela Voinescu cpumask_set_cpu(i, cpu_data->shared_cpu_map);
521337aadffSAshwin Chaugule }
522337aadffSAshwin Chaugule
523a28b2bfcSIonela Voinescu return 0;
524337aadffSAshwin Chaugule
525a28b2bfcSIonela Voinescu err_fault:
526337aadffSAshwin Chaugule /* Assume no coordination on any error parsing domain info */
527a28b2bfcSIonela Voinescu cpumask_clear(cpu_data->shared_cpu_map);
528a28b2bfcSIonela Voinescu cpumask_set_cpu(cpu, cpu_data->shared_cpu_map);
529a28b2bfcSIonela Voinescu cpu_data->shared_type = CPUFREQ_SHARED_TYPE_NONE;
530a28b2bfcSIonela Voinescu
531a28b2bfcSIonela Voinescu return -EFAULT;
532337aadffSAshwin Chaugule }
533337aadffSAshwin Chaugule EXPORT_SYMBOL_GPL(acpi_get_psd_map);
534337aadffSAshwin Chaugule
register_pcc_channel(int pcc_ss_idx)53585b1407bSGeorge Cherian static int register_pcc_channel(int pcc_ss_idx)
536337aadffSAshwin Chaugule {
5377b6da7feSSudeep Holla struct pcc_mbox_chan *pcc_chan;
538ad62e1e6SAshwin Chaugule u64 usecs_lat;
539337aadffSAshwin Chaugule
54085b1407bSGeorge Cherian if (pcc_ss_idx >= 0) {
5417b6da7feSSudeep Holla pcc_chan = pcc_mbox_request_channel(&cppc_mbox_cl, pcc_ss_idx);
542337aadffSAshwin Chaugule
5437b6da7feSSudeep Holla if (IS_ERR(pcc_chan)) {
544d29abc83SGeorge Cherian pr_err("Failed to find PCC channel for subspace %d\n",
545d29abc83SGeorge Cherian pcc_ss_idx);
546337aadffSAshwin Chaugule return -ENODEV;
547337aadffSAshwin Chaugule }
548337aadffSAshwin Chaugule
5497b6da7feSSudeep Holla pcc_data[pcc_ss_idx]->pcc_channel = pcc_chan;
550ad62e1e6SAshwin Chaugule /*
551ad62e1e6SAshwin Chaugule * cppc_ss->latency is just a Nominal value. In reality
552ad62e1e6SAshwin Chaugule * the remote processor could be much slower to reply.
553ad62e1e6SAshwin Chaugule * So add an arbitrary amount of wait on top of Nominal.
554ad62e1e6SAshwin Chaugule */
5557b6da7feSSudeep Holla usecs_lat = NUM_RETRIES * pcc_chan->latency;
55658e1c035SPrakash, Prashanth pcc_data[pcc_ss_idx]->deadline_us = usecs_lat;
5577b6da7feSSudeep Holla pcc_data[pcc_ss_idx]->pcc_mrtt = pcc_chan->min_turnaround_time;
5587b6da7feSSudeep Holla pcc_data[pcc_ss_idx]->pcc_mpar = pcc_chan->max_access_rate;
5597b6da7feSSudeep Holla pcc_data[pcc_ss_idx]->pcc_nominal = pcc_chan->latency;
560337aadffSAshwin Chaugule
56185b1407bSGeorge Cherian pcc_data[pcc_ss_idx]->pcc_comm_addr =
5627b6da7feSSudeep Holla acpi_os_ioremap(pcc_chan->shmem_base_addr,
5637b6da7feSSudeep Holla pcc_chan->shmem_size);
56485b1407bSGeorge Cherian if (!pcc_data[pcc_ss_idx]->pcc_comm_addr) {
565d29abc83SGeorge Cherian pr_err("Failed to ioremap PCC comm region mem for %d\n",
566d29abc83SGeorge Cherian pcc_ss_idx);
567337aadffSAshwin Chaugule return -ENOMEM;
568337aadffSAshwin Chaugule }
569337aadffSAshwin Chaugule
570603fadf3SBjorn Helgaas /* Set flag so that we don't come here for each CPU. */
57185b1407bSGeorge Cherian pcc_data[pcc_ss_idx]->pcc_channel_acquired = true;
572337aadffSAshwin Chaugule }
573337aadffSAshwin Chaugule
574337aadffSAshwin Chaugule return 0;
575337aadffSAshwin Chaugule }
576337aadffSAshwin Chaugule
577a6cbcdd5SSrinivas Pandruvada /**
578a6cbcdd5SSrinivas Pandruvada * cpc_ffh_supported() - check if FFH reading supported
579a6cbcdd5SSrinivas Pandruvada *
580a6cbcdd5SSrinivas Pandruvada * Check if the architecture has support for functional fixed hardware
581a6cbcdd5SSrinivas Pandruvada * read/write capability.
582a6cbcdd5SSrinivas Pandruvada *
583a6cbcdd5SSrinivas Pandruvada * Return: true for supported, false for not supported
584a6cbcdd5SSrinivas Pandruvada */
cpc_ffh_supported(void)585a6cbcdd5SSrinivas Pandruvada bool __weak cpc_ffh_supported(void)
586a6cbcdd5SSrinivas Pandruvada {
587a6cbcdd5SSrinivas Pandruvada return false;
588a6cbcdd5SSrinivas Pandruvada }
589a6cbcdd5SSrinivas Pandruvada
59085b1407bSGeorge Cherian /**
5918b356e53SMario Limonciello * cpc_supported_by_cpu() - check if CPPC is supported by CPU
5928b356e53SMario Limonciello *
5938b356e53SMario Limonciello * Check if the architectural support for CPPC is present even
5948b356e53SMario Limonciello * if the _OSC hasn't prescribed it
5958b356e53SMario Limonciello *
5968b356e53SMario Limonciello * Return: true for supported, false for not supported
5978b356e53SMario Limonciello */
cpc_supported_by_cpu(void)5988b356e53SMario Limonciello bool __weak cpc_supported_by_cpu(void)
5998b356e53SMario Limonciello {
6008b356e53SMario Limonciello return false;
6018b356e53SMario Limonciello }
6028b356e53SMario Limonciello
6038b356e53SMario Limonciello /**
60485b1407bSGeorge Cherian * pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace
605fda7be20SYang Li * @pcc_ss_id: PCC Subspace index as in the PCC client ACPI package.
60685b1407bSGeorge Cherian *
60785b1407bSGeorge Cherian * Check and allocate the cppc_pcc_data memory.
60885b1407bSGeorge Cherian * In some processor configurations it is possible that same subspace
609603fadf3SBjorn Helgaas * is shared between multiple CPUs. This is seen especially in CPUs
61085b1407bSGeorge Cherian * with hardware multi-threading support.
61185b1407bSGeorge Cherian *
61285b1407bSGeorge Cherian * Return: 0 for success, errno for failure
61385b1407bSGeorge Cherian */
pcc_data_alloc(int pcc_ss_id)6145c447c18SZou Wei static int pcc_data_alloc(int pcc_ss_id)
61585b1407bSGeorge Cherian {
61685b1407bSGeorge Cherian if (pcc_ss_id < 0 || pcc_ss_id >= MAX_PCC_SUBSPACES)
61785b1407bSGeorge Cherian return -EINVAL;
61885b1407bSGeorge Cherian
61985b1407bSGeorge Cherian if (pcc_data[pcc_ss_id]) {
62085b1407bSGeorge Cherian pcc_data[pcc_ss_id]->refcount++;
62185b1407bSGeorge Cherian } else {
62285b1407bSGeorge Cherian pcc_data[pcc_ss_id] = kzalloc(sizeof(struct cppc_pcc_data),
62385b1407bSGeorge Cherian GFP_KERNEL);
62485b1407bSGeorge Cherian if (!pcc_data[pcc_ss_id])
62585b1407bSGeorge Cherian return -ENOMEM;
62685b1407bSGeorge Cherian pcc_data[pcc_ss_id]->refcount++;
62785b1407bSGeorge Cherian }
62885b1407bSGeorge Cherian
62985b1407bSGeorge Cherian return 0;
63085b1407bSGeorge Cherian }
6314773e77cSPrashanth Prakash
632337aadffSAshwin Chaugule /*
633337aadffSAshwin Chaugule * An example CPC table looks like the following.
634337aadffSAshwin Chaugule *
6351a901c91SAndy Shevchenko * Name (_CPC, Package() {
6361a901c91SAndy Shevchenko * 17, // NumEntries
6371a901c91SAndy Shevchenko * 1, // Revision
6381a901c91SAndy Shevchenko * ResourceTemplate() {Register(PCC, 32, 0, 0x120, 2)}, // Highest Performance
6391a901c91SAndy Shevchenko * ResourceTemplate() {Register(PCC, 32, 0, 0x124, 2)}, // Nominal Performance
6401a901c91SAndy Shevchenko * ResourceTemplate() {Register(PCC, 32, 0, 0x128, 2)}, // Lowest Nonlinear Performance
6411a901c91SAndy Shevchenko * ResourceTemplate() {Register(PCC, 32, 0, 0x12C, 2)}, // Lowest Performance
6421a901c91SAndy Shevchenko * ResourceTemplate() {Register(PCC, 32, 0, 0x130, 2)}, // Guaranteed Performance Register
6431a901c91SAndy Shevchenko * ResourceTemplate() {Register(PCC, 32, 0, 0x110, 2)}, // Desired Performance Register
644337aadffSAshwin Chaugule * ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)},
6451a901c91SAndy Shevchenko * ...
6461a901c91SAndy Shevchenko * ...
6471a901c91SAndy Shevchenko * ...
648337aadffSAshwin Chaugule * }
649337aadffSAshwin Chaugule * Each Register() encodes how to access that specific register.
650337aadffSAshwin Chaugule * e.g. a sample PCC entry has the following encoding:
651337aadffSAshwin Chaugule *
652337aadffSAshwin Chaugule * Register (
6531a901c91SAndy Shevchenko * PCC, // AddressSpaceKeyword
6541a901c91SAndy Shevchenko * 8, // RegisterBitWidth
6551a901c91SAndy Shevchenko * 8, // RegisterBitOffset
6561a901c91SAndy Shevchenko * 0x30, // RegisterAddress
6571a901c91SAndy Shevchenko * 9, // AccessSize (subspace ID)
658337aadffSAshwin Chaugule * )
659337aadffSAshwin Chaugule */
660337aadffSAshwin Chaugule
6611132e6deSIonela Voinescu #ifndef arch_init_invariance_cppc
arch_init_invariance_cppc(void)6621132e6deSIonela Voinescu static inline void arch_init_invariance_cppc(void) { }
66341ea6672SNathan Fontenot #endif
66441ea6672SNathan Fontenot
665337aadffSAshwin Chaugule /**
666337aadffSAshwin Chaugule * acpi_cppc_processor_probe - Search for per CPU _CPC objects.
667603fadf3SBjorn Helgaas * @pr: Ptr to acpi_processor containing this CPU's logical ID.
668337aadffSAshwin Chaugule *
669337aadffSAshwin Chaugule * Return: 0 for success or negative value for err.
670337aadffSAshwin Chaugule */
acpi_cppc_processor_probe(struct acpi_processor * pr)671337aadffSAshwin Chaugule int acpi_cppc_processor_probe(struct acpi_processor *pr)
672337aadffSAshwin Chaugule {
673337aadffSAshwin Chaugule struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL};
674337aadffSAshwin Chaugule union acpi_object *out_obj, *cpc_obj;
675337aadffSAshwin Chaugule struct cpc_desc *cpc_ptr;
676337aadffSAshwin Chaugule struct cpc_reg *gas_t;
677158c998eSAshwin Chaugule struct device *cpu_dev;
678337aadffSAshwin Chaugule acpi_handle handle = pr->handle;
679337aadffSAshwin Chaugule unsigned int num_ent, i, cpc_rev;
68085b1407bSGeorge Cherian int pcc_subspace_id = -1;
681337aadffSAshwin Chaugule acpi_status status;
682f21a3509SRafael J. Wysocki int ret = -ENODATA;
683337aadffSAshwin Chaugule
6847feec743SMario Limonciello if (!osc_sb_cppc2_support_acked) {
6857feec743SMario Limonciello pr_debug("CPPC v2 _OSC not acked\n");
6868b356e53SMario Limonciello if (!cpc_supported_by_cpu())
687c42fa24bSRafael J. Wysocki return -ENODEV;
6887feec743SMario Limonciello }
689c42fa24bSRafael J. Wysocki
690603fadf3SBjorn Helgaas /* Parse the ACPI _CPC table for this CPU. */
691337aadffSAshwin Chaugule status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output,
692337aadffSAshwin Chaugule ACPI_TYPE_PACKAGE);
693337aadffSAshwin Chaugule if (ACPI_FAILURE(status)) {
694337aadffSAshwin Chaugule ret = -ENODEV;
695337aadffSAshwin Chaugule goto out_buf_free;
696337aadffSAshwin Chaugule }
697337aadffSAshwin Chaugule
698337aadffSAshwin Chaugule out_obj = (union acpi_object *) output.pointer;
699337aadffSAshwin Chaugule
700337aadffSAshwin Chaugule cpc_ptr = kzalloc(sizeof(struct cpc_desc), GFP_KERNEL);
701337aadffSAshwin Chaugule if (!cpc_ptr) {
702337aadffSAshwin Chaugule ret = -ENOMEM;
703337aadffSAshwin Chaugule goto out_buf_free;
704337aadffSAshwin Chaugule }
705337aadffSAshwin Chaugule
706337aadffSAshwin Chaugule /* First entry is NumEntries. */
707337aadffSAshwin Chaugule cpc_obj = &out_obj->package.elements[0];
708337aadffSAshwin Chaugule if (cpc_obj->type == ACPI_TYPE_INTEGER) {
709337aadffSAshwin Chaugule num_ent = cpc_obj->integer.value;
71040d8abf3SRafael J. Wysocki if (num_ent <= 1) {
71140d8abf3SRafael J. Wysocki pr_debug("Unexpected _CPC NumEntries value (%d) for CPU:%d\n",
71240d8abf3SRafael J. Wysocki num_ent, pr->id);
71340d8abf3SRafael J. Wysocki goto out_free;
71440d8abf3SRafael J. Wysocki }
715337aadffSAshwin Chaugule } else {
716f21a3509SRafael J. Wysocki pr_debug("Unexpected _CPC NumEntries entry type (%d) for CPU:%d\n",
717f21a3509SRafael J. Wysocki cpc_obj->type, pr->id);
718337aadffSAshwin Chaugule goto out_free;
719337aadffSAshwin Chaugule }
7205bbb86aaSAshwin Chaugule
721337aadffSAshwin Chaugule /* Second entry should be revision. */
722337aadffSAshwin Chaugule cpc_obj = &out_obj->package.elements[1];
723337aadffSAshwin Chaugule if (cpc_obj->type == ACPI_TYPE_INTEGER) {
724337aadffSAshwin Chaugule cpc_rev = cpc_obj->integer.value;
725337aadffSAshwin Chaugule } else {
726f21a3509SRafael J. Wysocki pr_debug("Unexpected _CPC Revision entry type (%d) for CPU:%d\n",
727f21a3509SRafael J. Wysocki cpc_obj->type, pr->id);
728337aadffSAshwin Chaugule goto out_free;
729337aadffSAshwin Chaugule }
730337aadffSAshwin Chaugule
7314f4179fcSRafael J. Wysocki if (cpc_rev < CPPC_V2_REV) {
7324f4179fcSRafael J. Wysocki pr_debug("Unsupported _CPC Revision (%d) for CPU:%d\n", cpc_rev,
7334f4179fcSRafael J. Wysocki pr->id);
734337aadffSAshwin Chaugule goto out_free;
7354f4179fcSRafael J. Wysocki }
7364f4179fcSRafael J. Wysocki
7374f4179fcSRafael J. Wysocki /*
7384f4179fcSRafael J. Wysocki * Disregard _CPC if the number of entries in the return pachage is not
7394f4179fcSRafael J. Wysocki * as expected, but support future revisions being proper supersets of
7404f4179fcSRafael J. Wysocki * the v3 and only causing more entries to be returned by _CPC.
7414f4179fcSRafael J. Wysocki */
7424f4179fcSRafael J. Wysocki if ((cpc_rev == CPPC_V2_REV && num_ent != CPPC_V2_NUM_ENT) ||
7434f4179fcSRafael J. Wysocki (cpc_rev == CPPC_V3_REV && num_ent != CPPC_V3_NUM_ENT) ||
7444f4179fcSRafael J. Wysocki (cpc_rev > CPPC_V3_REV && num_ent <= CPPC_V3_NUM_ENT)) {
7454f4179fcSRafael J. Wysocki pr_debug("Unexpected number of _CPC return package entries (%d) for CPU:%d\n",
7464f4179fcSRafael J. Wysocki num_ent, pr->id);
7474f4179fcSRafael J. Wysocki goto out_free;
7484f4179fcSRafael J. Wysocki }
7494f4179fcSRafael J. Wysocki if (cpc_rev > CPPC_V3_REV) {
7504f4179fcSRafael J. Wysocki num_ent = CPPC_V3_NUM_ENT;
7514f4179fcSRafael J. Wysocki cpc_rev = CPPC_V3_REV;
7524f4179fcSRafael J. Wysocki }
7534f4179fcSRafael J. Wysocki
7544f4179fcSRafael J. Wysocki cpc_ptr->num_entries = num_ent;
7554f4179fcSRafael J. Wysocki cpc_ptr->version = cpc_rev;
756337aadffSAshwin Chaugule
757337aadffSAshwin Chaugule /* Iterate through remaining entries in _CPC */
758337aadffSAshwin Chaugule for (i = 2; i < num_ent; i++) {
759337aadffSAshwin Chaugule cpc_obj = &out_obj->package.elements[i];
760337aadffSAshwin Chaugule
761337aadffSAshwin Chaugule if (cpc_obj->type == ACPI_TYPE_INTEGER) {
762337aadffSAshwin Chaugule cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER;
763337aadffSAshwin Chaugule cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value;
764337aadffSAshwin Chaugule } else if (cpc_obj->type == ACPI_TYPE_BUFFER) {
765337aadffSAshwin Chaugule gas_t = (struct cpc_reg *)
766337aadffSAshwin Chaugule cpc_obj->buffer.pointer;
767337aadffSAshwin Chaugule
768337aadffSAshwin Chaugule /*
769337aadffSAshwin Chaugule * The PCC Subspace index is encoded inside
770337aadffSAshwin Chaugule * the CPC table entries. The same PCC index
771337aadffSAshwin Chaugule * will be used for all the PCC entries,
772337aadffSAshwin Chaugule * so extract it only once.
773337aadffSAshwin Chaugule */
774337aadffSAshwin Chaugule if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
77585b1407bSGeorge Cherian if (pcc_subspace_id < 0) {
77685b1407bSGeorge Cherian pcc_subspace_id = gas_t->access_width;
77785b1407bSGeorge Cherian if (pcc_data_alloc(pcc_subspace_id))
77885b1407bSGeorge Cherian goto out_free;
77985b1407bSGeorge Cherian } else if (pcc_subspace_id != gas_t->access_width) {
780f21a3509SRafael J. Wysocki pr_debug("Mismatched PCC ids in _CPC for CPU:%d\n",
781f21a3509SRafael J. Wysocki pr->id);
782337aadffSAshwin Chaugule goto out_free;
783337aadffSAshwin Chaugule }
7845bbb86aaSAshwin Chaugule } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
7855bbb86aaSAshwin Chaugule if (gas_t->address) {
7865bbb86aaSAshwin Chaugule void __iomem *addr;
7871b890ae4SJarred White size_t access_width;
7885bbb86aaSAshwin Chaugule
7890651ab90SPierre Gondois if (!osc_cpc_flexible_adr_space_confirmed) {
7900651ab90SPierre Gondois pr_debug("Flexible address space capability not supported\n");
79109073396SMario Limonciello if (!cpc_supported_by_cpu())
7920651ab90SPierre Gondois goto out_free;
7930651ab90SPierre Gondois }
7940651ab90SPierre Gondois
7951b890ae4SJarred White access_width = GET_BIT_WIDTH(gas_t) / 8;
7961b890ae4SJarred White addr = ioremap(gas_t->address, access_width);
7975bbb86aaSAshwin Chaugule if (!addr)
7985bbb86aaSAshwin Chaugule goto out_free;
7995bbb86aaSAshwin Chaugule cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr;
8005bbb86aaSAshwin Chaugule }
801a2c8f92bSSteven Noonan } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
802a2c8f92bSSteven Noonan if (gas_t->access_width < 1 || gas_t->access_width > 3) {
803a2c8f92bSSteven Noonan /*
804a2c8f92bSSteven Noonan * 1 = 8-bit, 2 = 16-bit, and 3 = 32-bit.
805a2c8f92bSSteven Noonan * SystemIO doesn't implement 64-bit
806a2c8f92bSSteven Noonan * registers.
807a2c8f92bSSteven Noonan */
808f21a3509SRafael J. Wysocki pr_debug("Invalid access width %d for SystemIO register in _CPC\n",
809a2c8f92bSSteven Noonan gas_t->access_width);
810a2c8f92bSSteven Noonan goto out_free;
811a2c8f92bSSteven Noonan }
812a2c8f92bSSteven Noonan if (gas_t->address & OVER_16BTS_MASK) {
813a2c8f92bSSteven Noonan /* SystemIO registers use 16-bit integer addresses */
814f21a3509SRafael J. Wysocki pr_debug("Invalid IO port %llu for SystemIO register in _CPC\n",
815a2c8f92bSSteven Noonan gas_t->address);
816a2c8f92bSSteven Noonan goto out_free;
817a2c8f92bSSteven Noonan }
8180651ab90SPierre Gondois if (!osc_cpc_flexible_adr_space_confirmed) {
8190651ab90SPierre Gondois pr_debug("Flexible address space capability not supported\n");
82009073396SMario Limonciello if (!cpc_supported_by_cpu())
8210651ab90SPierre Gondois goto out_free;
8220651ab90SPierre Gondois }
8235bbb86aaSAshwin Chaugule } else {
824a6cbcdd5SSrinivas Pandruvada if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) {
825a2c8f92bSSteven Noonan /* Support only PCC, SystemMemory, SystemIO, and FFH type regs. */
826f21a3509SRafael J. Wysocki pr_debug("Unsupported register type (%d) in _CPC\n",
827f21a3509SRafael J. Wysocki gas_t->space_id);
828337aadffSAshwin Chaugule goto out_free;
829337aadffSAshwin Chaugule }
830a6cbcdd5SSrinivas Pandruvada }
831337aadffSAshwin Chaugule
832337aadffSAshwin Chaugule cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER;
833337aadffSAshwin Chaugule memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t));
834337aadffSAshwin Chaugule } else {
835f21a3509SRafael J. Wysocki pr_debug("Invalid entry type (%d) in _CPC for CPU:%d\n",
836f21a3509SRafael J. Wysocki i, pr->id);
837337aadffSAshwin Chaugule goto out_free;
838337aadffSAshwin Chaugule }
839337aadffSAshwin Chaugule }
84085b1407bSGeorge Cherian per_cpu(cpu_pcc_subspace_idx, pr->id) = pcc_subspace_id;
8414773e77cSPrashanth Prakash
8424773e77cSPrashanth Prakash /*
8434773e77cSPrashanth Prakash * Initialize the remaining cpc_regs as unsupported.
8444773e77cSPrashanth Prakash * Example: In case FW exposes CPPC v2, the below loop will initialize
8454773e77cSPrashanth Prakash * LOWEST_FREQ and NOMINAL_FREQ regs as unsupported
8464773e77cSPrashanth Prakash */
8474773e77cSPrashanth Prakash for (i = num_ent - 2; i < MAX_CPC_REG_ENT; i++) {
8484773e77cSPrashanth Prakash cpc_ptr->cpc_regs[i].type = ACPI_TYPE_INTEGER;
8494773e77cSPrashanth Prakash cpc_ptr->cpc_regs[i].cpc_entry.int_value = 0;
8504773e77cSPrashanth Prakash }
8514773e77cSPrashanth Prakash
8524773e77cSPrashanth Prakash
853337aadffSAshwin Chaugule /* Store CPU Logical ID */
854337aadffSAshwin Chaugule cpc_ptr->cpu_id = pr->id;
855337aadffSAshwin Chaugule
856337aadffSAshwin Chaugule /* Parse PSD data for this CPU */
857337aadffSAshwin Chaugule ret = acpi_get_psd(cpc_ptr, handle);
858337aadffSAshwin Chaugule if (ret)
859337aadffSAshwin Chaugule goto out_free;
860337aadffSAshwin Chaugule
861603fadf3SBjorn Helgaas /* Register PCC channel once for all PCC subspace ID. */
86285b1407bSGeorge Cherian if (pcc_subspace_id >= 0 && !pcc_data[pcc_subspace_id]->pcc_channel_acquired) {
86385b1407bSGeorge Cherian ret = register_pcc_channel(pcc_subspace_id);
864337aadffSAshwin Chaugule if (ret)
865337aadffSAshwin Chaugule goto out_free;
8668482ef8cSPrakash, Prashanth
86785b1407bSGeorge Cherian init_rwsem(&pcc_data[pcc_subspace_id]->pcc_lock);
86885b1407bSGeorge Cherian init_waitqueue_head(&pcc_data[pcc_subspace_id]->pcc_write_wait_q);
869337aadffSAshwin Chaugule }
870337aadffSAshwin Chaugule
871337aadffSAshwin Chaugule /* Everything looks okay */
872337aadffSAshwin Chaugule pr_debug("Parsed CPC struct for CPU: %d\n", pr->id);
873337aadffSAshwin Chaugule
874158c998eSAshwin Chaugule /* Add per logical CPU nodes for reading its feedback counters. */
875158c998eSAshwin Chaugule cpu_dev = get_cpu_device(pr->id);
87650163475SDan Carpenter if (!cpu_dev) {
87750163475SDan Carpenter ret = -EINVAL;
878158c998eSAshwin Chaugule goto out_free;
87950163475SDan Carpenter }
880158c998eSAshwin Chaugule
881603fadf3SBjorn Helgaas /* Plug PSD data into this CPU's CPC descriptor. */
88228076483SRafael J. Wysocki per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr;
88328076483SRafael J. Wysocki
884158c998eSAshwin Chaugule ret = kobject_init_and_add(&cpc_ptr->kobj, &cppc_ktype, &cpu_dev->kobj,
885158c998eSAshwin Chaugule "acpi_cppc");
88628076483SRafael J. Wysocki if (ret) {
88728076483SRafael J. Wysocki per_cpu(cpc_desc_ptr, pr->id) = NULL;
8884d8be4bcSQiushi Wu kobject_put(&cpc_ptr->kobj);
889158c998eSAshwin Chaugule goto out_free;
89028076483SRafael J. Wysocki }
891158c998eSAshwin Chaugule
8921132e6deSIonela Voinescu arch_init_invariance_cppc();
89341ea6672SNathan Fontenot
894337aadffSAshwin Chaugule kfree(output.pointer);
895337aadffSAshwin Chaugule return 0;
896337aadffSAshwin Chaugule
897337aadffSAshwin Chaugule out_free:
8985bbb86aaSAshwin Chaugule /* Free all the mapped sys mem areas for this CPU */
8995bbb86aaSAshwin Chaugule for (i = 2; i < cpc_ptr->num_entries; i++) {
9005bbb86aaSAshwin Chaugule void __iomem *addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
9015bbb86aaSAshwin Chaugule
9025bbb86aaSAshwin Chaugule if (addr)
9035bbb86aaSAshwin Chaugule iounmap(addr);
9045bbb86aaSAshwin Chaugule }
905337aadffSAshwin Chaugule kfree(cpc_ptr);
906337aadffSAshwin Chaugule
907337aadffSAshwin Chaugule out_buf_free:
908337aadffSAshwin Chaugule kfree(output.pointer);
909337aadffSAshwin Chaugule return ret;
910337aadffSAshwin Chaugule }
911337aadffSAshwin Chaugule EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe);
912337aadffSAshwin Chaugule
913337aadffSAshwin Chaugule /**
914337aadffSAshwin Chaugule * acpi_cppc_processor_exit - Cleanup CPC structs.
915603fadf3SBjorn Helgaas * @pr: Ptr to acpi_processor containing this CPU's logical ID.
916337aadffSAshwin Chaugule *
917337aadffSAshwin Chaugule * Return: Void
918337aadffSAshwin Chaugule */
acpi_cppc_processor_exit(struct acpi_processor * pr)919337aadffSAshwin Chaugule void acpi_cppc_processor_exit(struct acpi_processor *pr)
920337aadffSAshwin Chaugule {
921337aadffSAshwin Chaugule struct cpc_desc *cpc_ptr;
9225bbb86aaSAshwin Chaugule unsigned int i;
9235bbb86aaSAshwin Chaugule void __iomem *addr;
92485b1407bSGeorge Cherian int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id);
92585b1407bSGeorge Cherian
92685b1407bSGeorge Cherian if (pcc_ss_id >= 0 && pcc_data[pcc_ss_id]) {
92785b1407bSGeorge Cherian if (pcc_data[pcc_ss_id]->pcc_channel_acquired) {
92885b1407bSGeorge Cherian pcc_data[pcc_ss_id]->refcount--;
92985b1407bSGeorge Cherian if (!pcc_data[pcc_ss_id]->refcount) {
93085b1407bSGeorge Cherian pcc_mbox_free_channel(pcc_data[pcc_ss_id]->pcc_channel);
93185b1407bSGeorge Cherian kfree(pcc_data[pcc_ss_id]);
93256a0b978SJohn Garry pcc_data[pcc_ss_id] = NULL;
93385b1407bSGeorge Cherian }
93485b1407bSGeorge Cherian }
93585b1407bSGeorge Cherian }
936158c998eSAshwin Chaugule
937337aadffSAshwin Chaugule cpc_ptr = per_cpu(cpc_desc_ptr, pr->id);
9389e9d68daSSebastian Andrzej Siewior if (!cpc_ptr)
9399e9d68daSSebastian Andrzej Siewior return;
9405bbb86aaSAshwin Chaugule
9415bbb86aaSAshwin Chaugule /* Free all the mapped sys mem areas for this CPU */
9425bbb86aaSAshwin Chaugule for (i = 2; i < cpc_ptr->num_entries; i++) {
9435bbb86aaSAshwin Chaugule addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
9445bbb86aaSAshwin Chaugule if (addr)
9455bbb86aaSAshwin Chaugule iounmap(addr);
9465bbb86aaSAshwin Chaugule }
9475bbb86aaSAshwin Chaugule
948158c998eSAshwin Chaugule kobject_put(&cpc_ptr->kobj);
949337aadffSAshwin Chaugule kfree(cpc_ptr);
950337aadffSAshwin Chaugule }
951337aadffSAshwin Chaugule EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit);
952337aadffSAshwin Chaugule
953a6cbcdd5SSrinivas Pandruvada /**
954a6cbcdd5SSrinivas Pandruvada * cpc_read_ffh() - Read FFH register
955603fadf3SBjorn Helgaas * @cpunum: CPU number to read
956a6cbcdd5SSrinivas Pandruvada * @reg: cppc register information
957a6cbcdd5SSrinivas Pandruvada * @val: place holder for return value
958a6cbcdd5SSrinivas Pandruvada *
959a6cbcdd5SSrinivas Pandruvada * Read bit_width bits from a specified address and bit_offset
960a6cbcdd5SSrinivas Pandruvada *
961a6cbcdd5SSrinivas Pandruvada * Return: 0 for success and error code
962a6cbcdd5SSrinivas Pandruvada */
cpc_read_ffh(int cpunum,struct cpc_reg * reg,u64 * val)963a6cbcdd5SSrinivas Pandruvada int __weak cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val)
964a6cbcdd5SSrinivas Pandruvada {
965a6cbcdd5SSrinivas Pandruvada return -ENOTSUPP;
966a6cbcdd5SSrinivas Pandruvada }
967a6cbcdd5SSrinivas Pandruvada
968a6cbcdd5SSrinivas Pandruvada /**
969a6cbcdd5SSrinivas Pandruvada * cpc_write_ffh() - Write FFH register
970603fadf3SBjorn Helgaas * @cpunum: CPU number to write
971a6cbcdd5SSrinivas Pandruvada * @reg: cppc register information
972a6cbcdd5SSrinivas Pandruvada * @val: value to write
973a6cbcdd5SSrinivas Pandruvada *
974a6cbcdd5SSrinivas Pandruvada * Write value of bit_width bits to a specified address and bit_offset
975a6cbcdd5SSrinivas Pandruvada *
976a6cbcdd5SSrinivas Pandruvada * Return: 0 for success and error code
977a6cbcdd5SSrinivas Pandruvada */
cpc_write_ffh(int cpunum,struct cpc_reg * reg,u64 val)978a6cbcdd5SSrinivas Pandruvada int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
979a6cbcdd5SSrinivas Pandruvada {
980a6cbcdd5SSrinivas Pandruvada return -ENOTSUPP;
981a6cbcdd5SSrinivas Pandruvada }
982a6cbcdd5SSrinivas Pandruvada
98377e3d86fSPrakash, Prashanth /*
98477e3d86fSPrakash, Prashanth * Since cpc_read and cpc_write are called while holding pcc_lock, it should be
98577e3d86fSPrakash, Prashanth * as fast as possible. We have already mapped the PCC subspace during init, so
98677e3d86fSPrakash, Prashanth * we can directly write to it.
98777e3d86fSPrakash, Prashanth */
98877e3d86fSPrakash, Prashanth
cpc_read(int cpu,struct cpc_register_resource * reg_res,u64 * val)989a6cbcdd5SSrinivas Pandruvada static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
990337aadffSAshwin Chaugule {
99126692cd9SIonela Voinescu void __iomem *vaddr = NULL;
9921b890ae4SJarred White int size;
99385b1407bSGeorge Cherian int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
9945bbb86aaSAshwin Chaugule struct cpc_reg *reg = ®_res->cpc_entry.reg;
9955bbb86aaSAshwin Chaugule
9965bbb86aaSAshwin Chaugule if (reg_res->type == ACPI_TYPE_INTEGER) {
9975bbb86aaSAshwin Chaugule *val = reg_res->cpc_entry.int_value;
998f684b107SRafael J. Wysocki return 0;
9995bbb86aaSAshwin Chaugule }
100077e3d86fSPrakash, Prashanth
100177e3d86fSPrakash, Prashanth *val = 0;
10023ecf2249SVanshidhar Konda size = GET_BIT_WIDTH(reg);
1003a2c8f92bSSteven Noonan
1004a2c8f92bSSteven Noonan if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
10055f51c7ceSRafael J. Wysocki u32 val_u32;
1006a2c8f92bSSteven Noonan acpi_status status;
1007a2c8f92bSSteven Noonan
1008a2c8f92bSSteven Noonan status = acpi_os_read_port((acpi_io_address)reg->address,
10093ecf2249SVanshidhar Konda &val_u32, size);
1010a2c8f92bSSteven Noonan if (ACPI_FAILURE(status)) {
1011a2c8f92bSSteven Noonan pr_debug("Error: Failed to read SystemIO port %llx\n",
1012a2c8f92bSSteven Noonan reg->address);
1013a2c8f92bSSteven Noonan return -EFAULT;
1014a2c8f92bSSteven Noonan }
1015a2c8f92bSSteven Noonan
10165f51c7ceSRafael J. Wysocki *val = val_u32;
1017a2c8f92bSSteven Noonan return 0;
10183ecf2249SVanshidhar Konda } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) {
10193ecf2249SVanshidhar Konda /*
10203ecf2249SVanshidhar Konda * For registers in PCC space, the register size is determined
10213ecf2249SVanshidhar Konda * by the bit width field; the access size is used to indicate
10223ecf2249SVanshidhar Konda * the PCC subspace id.
10233ecf2249SVanshidhar Konda */
10243ecf2249SVanshidhar Konda size = reg->bit_width;
102585b1407bSGeorge Cherian vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
10263ecf2249SVanshidhar Konda }
10275bbb86aaSAshwin Chaugule else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
10285bbb86aaSAshwin Chaugule vaddr = reg_res->sys_mem_vaddr;
1029a6cbcdd5SSrinivas Pandruvada else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
1030a6cbcdd5SSrinivas Pandruvada return cpc_read_ffh(cpu, reg, val);
10315bbb86aaSAshwin Chaugule else
10325bbb86aaSAshwin Chaugule return acpi_os_read_memory((acpi_physical_address)reg->address,
10333ecf2249SVanshidhar Konda val, size);
10341b890ae4SJarred White
10351b890ae4SJarred White switch (size) {
103677e3d86fSPrakash, Prashanth case 8:
1037beee23aeSPrakash, Prashanth *val = readb_relaxed(vaddr);
103877e3d86fSPrakash, Prashanth break;
103977e3d86fSPrakash, Prashanth case 16:
1040beee23aeSPrakash, Prashanth *val = readw_relaxed(vaddr);
104177e3d86fSPrakash, Prashanth break;
104277e3d86fSPrakash, Prashanth case 32:
1043beee23aeSPrakash, Prashanth *val = readl_relaxed(vaddr);
104477e3d86fSPrakash, Prashanth break;
104577e3d86fSPrakash, Prashanth case 64:
1046beee23aeSPrakash, Prashanth *val = readq_relaxed(vaddr);
104777e3d86fSPrakash, Prashanth break;
104877e3d86fSPrakash, Prashanth default:
10493ecf2249SVanshidhar Konda if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
10503ecf2249SVanshidhar Konda pr_debug("Error: Cannot read %u bit width from system memory: 0x%llx\n",
10513ecf2249SVanshidhar Konda size, reg->address);
10523ecf2249SVanshidhar Konda } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
1053d29abc83SGeorge Cherian pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n",
10543ecf2249SVanshidhar Konda size, pcc_ss_id);
10553ecf2249SVanshidhar Konda }
1056f684b107SRafael J. Wysocki return -EFAULT;
105777e3d86fSPrakash, Prashanth }
10585bbb86aaSAshwin Chaugule
10591b890ae4SJarred White if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
10601b890ae4SJarred White *val = MASK_VAL(reg, *val);
10611b890ae4SJarred White
1062f684b107SRafael J. Wysocki return 0;
1063337aadffSAshwin Chaugule }
1064337aadffSAshwin Chaugule
cpc_write(int cpu,struct cpc_register_resource * reg_res,u64 val)1065a6cbcdd5SSrinivas Pandruvada static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
1066337aadffSAshwin Chaugule {
106777e3d86fSPrakash, Prashanth int ret_val = 0;
10681b890ae4SJarred White int size;
106926692cd9SIonela Voinescu void __iomem *vaddr = NULL;
107085b1407bSGeorge Cherian int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
10715bbb86aaSAshwin Chaugule struct cpc_reg *reg = ®_res->cpc_entry.reg;
1072337aadffSAshwin Chaugule
10733ecf2249SVanshidhar Konda size = GET_BIT_WIDTH(reg);
10743ecf2249SVanshidhar Konda
1075a2c8f92bSSteven Noonan if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
1076a2c8f92bSSteven Noonan acpi_status status;
1077a2c8f92bSSteven Noonan
1078a2c8f92bSSteven Noonan status = acpi_os_write_port((acpi_io_address)reg->address,
10793ecf2249SVanshidhar Konda (u32)val, size);
1080a2c8f92bSSteven Noonan if (ACPI_FAILURE(status)) {
1081a2c8f92bSSteven Noonan pr_debug("Error: Failed to write SystemIO port %llx\n",
1082a2c8f92bSSteven Noonan reg->address);
1083a2c8f92bSSteven Noonan return -EFAULT;
1084a2c8f92bSSteven Noonan }
1085a2c8f92bSSteven Noonan
1086a2c8f92bSSteven Noonan return 0;
10873ecf2249SVanshidhar Konda } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) {
10883ecf2249SVanshidhar Konda /*
10893ecf2249SVanshidhar Konda * For registers in PCC space, the register size is determined
10903ecf2249SVanshidhar Konda * by the bit width field; the access size is used to indicate
10913ecf2249SVanshidhar Konda * the PCC subspace id.
10923ecf2249SVanshidhar Konda */
10933ecf2249SVanshidhar Konda size = reg->bit_width;
109485b1407bSGeorge Cherian vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
10953ecf2249SVanshidhar Konda }
10965bbb86aaSAshwin Chaugule else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
10975bbb86aaSAshwin Chaugule vaddr = reg_res->sys_mem_vaddr;
1098a6cbcdd5SSrinivas Pandruvada else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
1099a6cbcdd5SSrinivas Pandruvada return cpc_write_ffh(cpu, reg, val);
11005bbb86aaSAshwin Chaugule else
11015bbb86aaSAshwin Chaugule return acpi_os_write_memory((acpi_physical_address)reg->address,
11023ecf2249SVanshidhar Konda val, size);
11031b890ae4SJarred White
11041b890ae4SJarred White if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
11051b890ae4SJarred White val = MASK_VAL(reg, val);
11061b890ae4SJarred White
11071b890ae4SJarred White switch (size) {
110877e3d86fSPrakash, Prashanth case 8:
1109beee23aeSPrakash, Prashanth writeb_relaxed(val, vaddr);
111077e3d86fSPrakash, Prashanth break;
111177e3d86fSPrakash, Prashanth case 16:
1112beee23aeSPrakash, Prashanth writew_relaxed(val, vaddr);
111377e3d86fSPrakash, Prashanth break;
111477e3d86fSPrakash, Prashanth case 32:
1115beee23aeSPrakash, Prashanth writel_relaxed(val, vaddr);
111677e3d86fSPrakash, Prashanth break;
111777e3d86fSPrakash, Prashanth case 64:
1118beee23aeSPrakash, Prashanth writeq_relaxed(val, vaddr);
111977e3d86fSPrakash, Prashanth break;
112077e3d86fSPrakash, Prashanth default:
11213ecf2249SVanshidhar Konda if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
11223ecf2249SVanshidhar Konda pr_debug("Error: Cannot write %u bit width to system memory: 0x%llx\n",
11233ecf2249SVanshidhar Konda size, reg->address);
11243ecf2249SVanshidhar Konda } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
1125d29abc83SGeorge Cherian pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n",
11263ecf2249SVanshidhar Konda size, pcc_ss_id);
11273ecf2249SVanshidhar Konda }
112877e3d86fSPrakash, Prashanth ret_val = -EFAULT;
112977e3d86fSPrakash, Prashanth break;
1130337aadffSAshwin Chaugule }
11315bbb86aaSAshwin Chaugule
113277e3d86fSPrakash, Prashanth return ret_val;
1133337aadffSAshwin Chaugule }
1134337aadffSAshwin Chaugule
cppc_get_perf(int cpunum,enum cppc_regs reg_idx,u64 * perf)11350654cf05SRafael J. Wysocki static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf)
11361757d05fSXiongfeng Wang {
11371757d05fSXiongfeng Wang struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1138935dff30SRafael J. Wysocki struct cpc_register_resource *reg;
1139935dff30SRafael J. Wysocki
1140935dff30SRafael J. Wysocki if (!cpc_desc) {
1141935dff30SRafael J. Wysocki pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1142935dff30SRafael J. Wysocki return -ENODEV;
1143935dff30SRafael J. Wysocki }
1144935dff30SRafael J. Wysocki
1145935dff30SRafael J. Wysocki reg = &cpc_desc->cpc_regs[reg_idx];
11460654cf05SRafael J. Wysocki
11470654cf05SRafael J. Wysocki if (CPC_IN_PCC(reg)) {
11481757d05fSXiongfeng Wang int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
11491757d05fSXiongfeng Wang struct cppc_pcc_data *pcc_ss_data = NULL;
11501757d05fSXiongfeng Wang int ret = 0;
11511757d05fSXiongfeng Wang
11521757d05fSXiongfeng Wang if (pcc_ss_id < 0)
11531757d05fSXiongfeng Wang return -EIO;
11541757d05fSXiongfeng Wang
11551757d05fSXiongfeng Wang pcc_ss_data = pcc_data[pcc_ss_id];
11561757d05fSXiongfeng Wang
11571757d05fSXiongfeng Wang down_write(&pcc_ss_data->pcc_lock);
11581757d05fSXiongfeng Wang
11591757d05fSXiongfeng Wang if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0)
11600654cf05SRafael J. Wysocki cpc_read(cpunum, reg, perf);
11611757d05fSXiongfeng Wang else
11621757d05fSXiongfeng Wang ret = -EIO;
11631757d05fSXiongfeng Wang
11641757d05fSXiongfeng Wang up_write(&pcc_ss_data->pcc_lock);
11651757d05fSXiongfeng Wang
11661757d05fSXiongfeng Wang return ret;
11671757d05fSXiongfeng Wang }
11681757d05fSXiongfeng Wang
11690654cf05SRafael J. Wysocki cpc_read(cpunum, reg, perf);
11701757d05fSXiongfeng Wang
11711757d05fSXiongfeng Wang return 0;
11721757d05fSXiongfeng Wang }
11730654cf05SRafael J. Wysocki
11740654cf05SRafael J. Wysocki /**
11750654cf05SRafael J. Wysocki * cppc_get_desired_perf - Get the desired performance register value.
11760654cf05SRafael J. Wysocki * @cpunum: CPU from which to get desired performance.
11770654cf05SRafael J. Wysocki * @desired_perf: Return address.
11780654cf05SRafael J. Wysocki *
11790654cf05SRafael J. Wysocki * Return: 0 for success, -EIO otherwise.
11800654cf05SRafael J. Wysocki */
cppc_get_desired_perf(int cpunum,u64 * desired_perf)11810654cf05SRafael J. Wysocki int cppc_get_desired_perf(int cpunum, u64 *desired_perf)
11820654cf05SRafael J. Wysocki {
11830654cf05SRafael J. Wysocki return cppc_get_perf(cpunum, DESIRED_PERF, desired_perf);
11840654cf05SRafael J. Wysocki }
11851757d05fSXiongfeng Wang EXPORT_SYMBOL_GPL(cppc_get_desired_perf);
11861757d05fSXiongfeng Wang
11871757d05fSXiongfeng Wang /**
11880654cf05SRafael J. Wysocki * cppc_get_nominal_perf - Get the nominal performance register value.
11890654cf05SRafael J. Wysocki * @cpunum: CPU from which to get nominal performance.
11900654cf05SRafael J. Wysocki * @nominal_perf: Return address.
11910654cf05SRafael J. Wysocki *
11920654cf05SRafael J. Wysocki * Return: 0 for success, -EIO otherwise.
11930654cf05SRafael J. Wysocki */
cppc_get_nominal_perf(int cpunum,u64 * nominal_perf)11940654cf05SRafael J. Wysocki int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf)
11950654cf05SRafael J. Wysocki {
11960654cf05SRafael J. Wysocki return cppc_get_perf(cpunum, NOMINAL_PERF, nominal_perf);
11970654cf05SRafael J. Wysocki }
11980654cf05SRafael J. Wysocki
11990654cf05SRafael J. Wysocki /**
12007bc1fcd3SPerry Yuan * cppc_get_epp_perf - Get the epp register value.
12017bc1fcd3SPerry Yuan * @cpunum: CPU from which to get epp preference value.
12027bc1fcd3SPerry Yuan * @epp_perf: Return address.
12037bc1fcd3SPerry Yuan *
12047bc1fcd3SPerry Yuan * Return: 0 for success, -EIO otherwise.
12057bc1fcd3SPerry Yuan */
cppc_get_epp_perf(int cpunum,u64 * epp_perf)12067bc1fcd3SPerry Yuan int cppc_get_epp_perf(int cpunum, u64 *epp_perf)
12077bc1fcd3SPerry Yuan {
12087bc1fcd3SPerry Yuan return cppc_get_perf(cpunum, ENERGY_PERF, epp_perf);
12097bc1fcd3SPerry Yuan }
12107bc1fcd3SPerry Yuan EXPORT_SYMBOL_GPL(cppc_get_epp_perf);
12117bc1fcd3SPerry Yuan
12127bc1fcd3SPerry Yuan /**
1213603fadf3SBjorn Helgaas * cppc_get_perf_caps - Get a CPU's performance capabilities.
1214337aadffSAshwin Chaugule * @cpunum: CPU from which to get capabilities info.
1215337aadffSAshwin Chaugule * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h
1216337aadffSAshwin Chaugule *
1217337aadffSAshwin Chaugule * Return: 0 for success with perf_caps populated else -ERRNO.
1218337aadffSAshwin Chaugule */
cppc_get_perf_caps(int cpunum,struct cppc_perf_caps * perf_caps)1219337aadffSAshwin Chaugule int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
1220337aadffSAshwin Chaugule {
1221337aadffSAshwin Chaugule struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1222368520a6SPrakash, Prashanth struct cpc_register_resource *highest_reg, *lowest_reg,
122329523f09SSrinivas Pandruvada *lowest_non_linear_reg, *nominal_reg, *guaranteed_reg,
12244773e77cSPrashanth Prakash *low_freq_reg = NULL, *nom_freq_reg = NULL;
122529523f09SSrinivas Pandruvada u64 high, low, guaranteed, nom, min_nonlinear, low_f = 0, nom_f = 0;
122685b1407bSGeorge Cherian int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
12276fa12d58SPrashanth Prakash struct cppc_pcc_data *pcc_ss_data = NULL;
1228850d64a4SPrakash, Prashanth int ret = 0, regs_in_pcc = 0;
1229337aadffSAshwin Chaugule
12306fa12d58SPrashanth Prakash if (!cpc_desc) {
1231337aadffSAshwin Chaugule pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1232337aadffSAshwin Chaugule return -ENODEV;
1233337aadffSAshwin Chaugule }
1234337aadffSAshwin Chaugule
1235337aadffSAshwin Chaugule highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF];
1236337aadffSAshwin Chaugule lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF];
1237368520a6SPrakash, Prashanth lowest_non_linear_reg = &cpc_desc->cpc_regs[LOW_NON_LINEAR_PERF];
1238368520a6SPrakash, Prashanth nominal_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
12394773e77cSPrashanth Prakash low_freq_reg = &cpc_desc->cpc_regs[LOWEST_FREQ];
12404773e77cSPrashanth Prakash nom_freq_reg = &cpc_desc->cpc_regs[NOMINAL_FREQ];
124129523f09SSrinivas Pandruvada guaranteed_reg = &cpc_desc->cpc_regs[GUARANTEED_PERF];
1242337aadffSAshwin Chaugule
1243337aadffSAshwin Chaugule /* Are any of the regs PCC ?*/
124480b8286aSPrakash, Prashanth if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) ||
12454773e77cSPrashanth Prakash CPC_IN_PCC(lowest_non_linear_reg) || CPC_IN_PCC(nominal_reg) ||
12464773e77cSPrashanth Prakash CPC_IN_PCC(low_freq_reg) || CPC_IN_PCC(nom_freq_reg)) {
12476fa12d58SPrashanth Prakash if (pcc_ss_id < 0) {
12486fa12d58SPrashanth Prakash pr_debug("Invalid pcc_ss_id\n");
12496fa12d58SPrashanth Prakash return -ENODEV;
12506fa12d58SPrashanth Prakash }
12516fa12d58SPrashanth Prakash pcc_ss_data = pcc_data[pcc_ss_id];
1252850d64a4SPrakash, Prashanth regs_in_pcc = 1;
125385b1407bSGeorge Cherian down_write(&pcc_ss_data->pcc_lock);
1254337aadffSAshwin Chaugule /* Ring doorbell once to update PCC subspace */
125585b1407bSGeorge Cherian if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
1256337aadffSAshwin Chaugule ret = -EIO;
1257337aadffSAshwin Chaugule goto out_err;
1258337aadffSAshwin Chaugule }
1259337aadffSAshwin Chaugule }
1260337aadffSAshwin Chaugule
1261a6cbcdd5SSrinivas Pandruvada cpc_read(cpunum, highest_reg, &high);
1262337aadffSAshwin Chaugule perf_caps->highest_perf = high;
1263337aadffSAshwin Chaugule
1264a6cbcdd5SSrinivas Pandruvada cpc_read(cpunum, lowest_reg, &low);
1265337aadffSAshwin Chaugule perf_caps->lowest_perf = low;
1266337aadffSAshwin Chaugule
1267368520a6SPrakash, Prashanth cpc_read(cpunum, nominal_reg, &nom);
1268337aadffSAshwin Chaugule perf_caps->nominal_perf = nom;
1269337aadffSAshwin Chaugule
1270edef1ef1SSrinivas Pandruvada if (guaranteed_reg->type != ACPI_TYPE_BUFFER ||
1271edef1ef1SSrinivas Pandruvada IS_NULL_REG(&guaranteed_reg->cpc_entry.reg)) {
1272edef1ef1SSrinivas Pandruvada perf_caps->guaranteed_perf = 0;
1273edef1ef1SSrinivas Pandruvada } else {
127429523f09SSrinivas Pandruvada cpc_read(cpunum, guaranteed_reg, &guaranteed);
127529523f09SSrinivas Pandruvada perf_caps->guaranteed_perf = guaranteed;
1276edef1ef1SSrinivas Pandruvada }
127729523f09SSrinivas Pandruvada
1278368520a6SPrakash, Prashanth cpc_read(cpunum, lowest_non_linear_reg, &min_nonlinear);
1279368520a6SPrakash, Prashanth perf_caps->lowest_nonlinear_perf = min_nonlinear;
1280368520a6SPrakash, Prashanth
1281368520a6SPrakash, Prashanth if (!high || !low || !nom || !min_nonlinear)
1282337aadffSAshwin Chaugule ret = -EFAULT;
1283337aadffSAshwin Chaugule
12844773e77cSPrashanth Prakash /* Read optional lowest and nominal frequencies if present */
12854773e77cSPrashanth Prakash if (CPC_SUPPORTED(low_freq_reg))
12864773e77cSPrashanth Prakash cpc_read(cpunum, low_freq_reg, &low_f);
12874773e77cSPrashanth Prakash
12884773e77cSPrashanth Prakash if (CPC_SUPPORTED(nom_freq_reg))
12894773e77cSPrashanth Prakash cpc_read(cpunum, nom_freq_reg, &nom_f);
12904773e77cSPrashanth Prakash
12914773e77cSPrashanth Prakash perf_caps->lowest_freq = low_f;
12924773e77cSPrashanth Prakash perf_caps->nominal_freq = nom_f;
12934773e77cSPrashanth Prakash
12944773e77cSPrashanth Prakash
1295337aadffSAshwin Chaugule out_err:
1296850d64a4SPrakash, Prashanth if (regs_in_pcc)
129785b1407bSGeorge Cherian up_write(&pcc_ss_data->pcc_lock);
1298337aadffSAshwin Chaugule return ret;
1299337aadffSAshwin Chaugule }
1300337aadffSAshwin Chaugule EXPORT_SYMBOL_GPL(cppc_get_perf_caps);
1301337aadffSAshwin Chaugule
1302337aadffSAshwin Chaugule /**
1303ae2df912SJeremy Linton * cppc_perf_ctrs_in_pcc - Check if any perf counters are in a PCC region.
1304ae2df912SJeremy Linton *
1305ae2df912SJeremy Linton * CPPC has flexibility about how CPU performance counters are accessed.
1306ae2df912SJeremy Linton * One of the choices is PCC regions, which can have a high access latency. This
1307ae2df912SJeremy Linton * routine allows callers of cppc_get_perf_ctrs() to know this ahead of time.
1308ae2df912SJeremy Linton *
1309ae2df912SJeremy Linton * Return: true if any of the counters are in PCC regions, false otherwise
1310ae2df912SJeremy Linton */
cppc_perf_ctrs_in_pcc(void)1311ae2df912SJeremy Linton bool cppc_perf_ctrs_in_pcc(void)
1312ae2df912SJeremy Linton {
1313ae2df912SJeremy Linton int cpu;
1314ae2df912SJeremy Linton
1315ae2df912SJeremy Linton for_each_present_cpu(cpu) {
1316ae2df912SJeremy Linton struct cpc_register_resource *ref_perf_reg;
1317ae2df912SJeremy Linton struct cpc_desc *cpc_desc;
1318ae2df912SJeremy Linton
1319ae2df912SJeremy Linton cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1320ae2df912SJeremy Linton
1321ae2df912SJeremy Linton if (CPC_IN_PCC(&cpc_desc->cpc_regs[DELIVERED_CTR]) ||
1322ae2df912SJeremy Linton CPC_IN_PCC(&cpc_desc->cpc_regs[REFERENCE_CTR]) ||
1323ae2df912SJeremy Linton CPC_IN_PCC(&cpc_desc->cpc_regs[CTR_WRAP_TIME]))
1324ae2df912SJeremy Linton return true;
1325ae2df912SJeremy Linton
1326ae2df912SJeremy Linton
1327ae2df912SJeremy Linton ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF];
1328ae2df912SJeremy Linton
1329ae2df912SJeremy Linton /*
1330ae2df912SJeremy Linton * If reference perf register is not supported then we should
1331ae2df912SJeremy Linton * use the nominal perf value
1332ae2df912SJeremy Linton */
1333ae2df912SJeremy Linton if (!CPC_SUPPORTED(ref_perf_reg))
1334ae2df912SJeremy Linton ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1335ae2df912SJeremy Linton
1336ae2df912SJeremy Linton if (CPC_IN_PCC(ref_perf_reg))
1337ae2df912SJeremy Linton return true;
1338ae2df912SJeremy Linton }
1339ae2df912SJeremy Linton
1340ae2df912SJeremy Linton return false;
1341ae2df912SJeremy Linton }
1342ae2df912SJeremy Linton EXPORT_SYMBOL_GPL(cppc_perf_ctrs_in_pcc);
1343ae2df912SJeremy Linton
1344ae2df912SJeremy Linton /**
1345603fadf3SBjorn Helgaas * cppc_get_perf_ctrs - Read a CPU's performance feedback counters.
1346337aadffSAshwin Chaugule * @cpunum: CPU from which to read counters.
1347337aadffSAshwin Chaugule * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h
1348337aadffSAshwin Chaugule *
1349337aadffSAshwin Chaugule * Return: 0 for success with perf_fb_ctrs populated else -ERRNO.
1350337aadffSAshwin Chaugule */
cppc_get_perf_ctrs(int cpunum,struct cppc_perf_fb_ctrs * perf_fb_ctrs)1351337aadffSAshwin Chaugule int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
1352337aadffSAshwin Chaugule {
1353337aadffSAshwin Chaugule struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1354158c998eSAshwin Chaugule struct cpc_register_resource *delivered_reg, *reference_reg,
1355158c998eSAshwin Chaugule *ref_perf_reg, *ctr_wrap_reg;
135685b1407bSGeorge Cherian int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
13576fa12d58SPrashanth Prakash struct cppc_pcc_data *pcc_ss_data = NULL;
1358158c998eSAshwin Chaugule u64 delivered, reference, ref_perf, ctr_wrap_time;
1359850d64a4SPrakash, Prashanth int ret = 0, regs_in_pcc = 0;
1360337aadffSAshwin Chaugule
13616fa12d58SPrashanth Prakash if (!cpc_desc) {
1362337aadffSAshwin Chaugule pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1363337aadffSAshwin Chaugule return -ENODEV;
1364337aadffSAshwin Chaugule }
1365337aadffSAshwin Chaugule
1366337aadffSAshwin Chaugule delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR];
1367337aadffSAshwin Chaugule reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR];
1368158c998eSAshwin Chaugule ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF];
1369158c998eSAshwin Chaugule ctr_wrap_reg = &cpc_desc->cpc_regs[CTR_WRAP_TIME];
1370158c998eSAshwin Chaugule
1371158c998eSAshwin Chaugule /*
1372603fadf3SBjorn Helgaas * If reference perf register is not supported then we should
1373158c998eSAshwin Chaugule * use the nominal perf value
1374158c998eSAshwin Chaugule */
1375158c998eSAshwin Chaugule if (!CPC_SUPPORTED(ref_perf_reg))
1376158c998eSAshwin Chaugule ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1377337aadffSAshwin Chaugule
1378337aadffSAshwin Chaugule /* Are any of the regs PCC ?*/
1379158c998eSAshwin Chaugule if (CPC_IN_PCC(delivered_reg) || CPC_IN_PCC(reference_reg) ||
1380158c998eSAshwin Chaugule CPC_IN_PCC(ctr_wrap_reg) || CPC_IN_PCC(ref_perf_reg)) {
13816fa12d58SPrashanth Prakash if (pcc_ss_id < 0) {
13826fa12d58SPrashanth Prakash pr_debug("Invalid pcc_ss_id\n");
13836fa12d58SPrashanth Prakash return -ENODEV;
13846fa12d58SPrashanth Prakash }
13856fa12d58SPrashanth Prakash pcc_ss_data = pcc_data[pcc_ss_id];
138685b1407bSGeorge Cherian down_write(&pcc_ss_data->pcc_lock);
1387850d64a4SPrakash, Prashanth regs_in_pcc = 1;
1388337aadffSAshwin Chaugule /* Ring doorbell once to update PCC subspace */
138985b1407bSGeorge Cherian if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
1390337aadffSAshwin Chaugule ret = -EIO;
1391337aadffSAshwin Chaugule goto out_err;
1392337aadffSAshwin Chaugule }
1393337aadffSAshwin Chaugule }
1394337aadffSAshwin Chaugule
1395a6cbcdd5SSrinivas Pandruvada cpc_read(cpunum, delivered_reg, &delivered);
1396a6cbcdd5SSrinivas Pandruvada cpc_read(cpunum, reference_reg, &reference);
1397a6cbcdd5SSrinivas Pandruvada cpc_read(cpunum, ref_perf_reg, &ref_perf);
1398337aadffSAshwin Chaugule
1399158c998eSAshwin Chaugule /*
1400158c998eSAshwin Chaugule * Per spec, if ctr_wrap_time optional register is unsupported, then the
1401158c998eSAshwin Chaugule * performance counters are assumed to never wrap during the lifetime of
1402158c998eSAshwin Chaugule * platform
1403158c998eSAshwin Chaugule */
1404158c998eSAshwin Chaugule ctr_wrap_time = (u64)(~((u64)0));
1405158c998eSAshwin Chaugule if (CPC_SUPPORTED(ctr_wrap_reg))
1406a6cbcdd5SSrinivas Pandruvada cpc_read(cpunum, ctr_wrap_reg, &ctr_wrap_time);
1407158c998eSAshwin Chaugule
1408158c998eSAshwin Chaugule if (!delivered || !reference || !ref_perf) {
1409337aadffSAshwin Chaugule ret = -EFAULT;
1410337aadffSAshwin Chaugule goto out_err;
1411337aadffSAshwin Chaugule }
1412337aadffSAshwin Chaugule
1413337aadffSAshwin Chaugule perf_fb_ctrs->delivered = delivered;
1414337aadffSAshwin Chaugule perf_fb_ctrs->reference = reference;
1415158c998eSAshwin Chaugule perf_fb_ctrs->reference_perf = ref_perf;
14162c74d847SPrakash, Prashanth perf_fb_ctrs->wraparound_time = ctr_wrap_time;
1417337aadffSAshwin Chaugule out_err:
1418850d64a4SPrakash, Prashanth if (regs_in_pcc)
141985b1407bSGeorge Cherian up_write(&pcc_ss_data->pcc_lock);
1420337aadffSAshwin Chaugule return ret;
1421337aadffSAshwin Chaugule }
1422337aadffSAshwin Chaugule EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
1423337aadffSAshwin Chaugule
14247bc1fcd3SPerry Yuan /*
14257bc1fcd3SPerry Yuan * Set Energy Performance Preference Register value through
14267bc1fcd3SPerry Yuan * Performance Controls Interface
14277bc1fcd3SPerry Yuan */
cppc_set_epp_perf(int cpu,struct cppc_perf_ctrls * perf_ctrls,bool enable)14287bc1fcd3SPerry Yuan int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable)
14297bc1fcd3SPerry Yuan {
14307bc1fcd3SPerry Yuan int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
14317bc1fcd3SPerry Yuan struct cpc_register_resource *epp_set_reg;
14327bc1fcd3SPerry Yuan struct cpc_register_resource *auto_sel_reg;
14337bc1fcd3SPerry Yuan struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
14347bc1fcd3SPerry Yuan struct cppc_pcc_data *pcc_ss_data = NULL;
14357bc1fcd3SPerry Yuan int ret;
14367bc1fcd3SPerry Yuan
14377bc1fcd3SPerry Yuan if (!cpc_desc) {
14387bc1fcd3SPerry Yuan pr_debug("No CPC descriptor for CPU:%d\n", cpu);
14397bc1fcd3SPerry Yuan return -ENODEV;
14407bc1fcd3SPerry Yuan }
14417bc1fcd3SPerry Yuan
14427bc1fcd3SPerry Yuan auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
14437bc1fcd3SPerry Yuan epp_set_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
14447bc1fcd3SPerry Yuan
14457bc1fcd3SPerry Yuan if (CPC_IN_PCC(epp_set_reg) || CPC_IN_PCC(auto_sel_reg)) {
14467bc1fcd3SPerry Yuan if (pcc_ss_id < 0) {
14477bc1fcd3SPerry Yuan pr_debug("Invalid pcc_ss_id for CPU:%d\n", cpu);
14487bc1fcd3SPerry Yuan return -ENODEV;
14497bc1fcd3SPerry Yuan }
14507bc1fcd3SPerry Yuan
14517bc1fcd3SPerry Yuan if (CPC_SUPPORTED(auto_sel_reg)) {
14527bc1fcd3SPerry Yuan ret = cpc_write(cpu, auto_sel_reg, enable);
14537bc1fcd3SPerry Yuan if (ret)
14547bc1fcd3SPerry Yuan return ret;
14557bc1fcd3SPerry Yuan }
14567bc1fcd3SPerry Yuan
14577bc1fcd3SPerry Yuan if (CPC_SUPPORTED(epp_set_reg)) {
14587bc1fcd3SPerry Yuan ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf);
14597bc1fcd3SPerry Yuan if (ret)
14607bc1fcd3SPerry Yuan return ret;
14617bc1fcd3SPerry Yuan }
14627bc1fcd3SPerry Yuan
14637bc1fcd3SPerry Yuan pcc_ss_data = pcc_data[pcc_ss_id];
14647bc1fcd3SPerry Yuan
14657bc1fcd3SPerry Yuan down_write(&pcc_ss_data->pcc_lock);
14667bc1fcd3SPerry Yuan /* after writing CPC, transfer the ownership of PCC to platform */
14677bc1fcd3SPerry Yuan ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
14687bc1fcd3SPerry Yuan up_write(&pcc_ss_data->pcc_lock);
14697bc1fcd3SPerry Yuan } else {
14707bc1fcd3SPerry Yuan ret = -ENOTSUPP;
14717bc1fcd3SPerry Yuan pr_debug("_CPC in PCC is not supported\n");
14727bc1fcd3SPerry Yuan }
14737bc1fcd3SPerry Yuan
14747bc1fcd3SPerry Yuan return ret;
14757bc1fcd3SPerry Yuan }
14767bc1fcd3SPerry Yuan EXPORT_SYMBOL_GPL(cppc_set_epp_perf);
14777bc1fcd3SPerry Yuan
1478337aadffSAshwin Chaugule /**
1479c984f5d5SWyes Karny * cppc_get_auto_sel_caps - Read autonomous selection register.
1480c984f5d5SWyes Karny * @cpunum : CPU from which to read register.
1481c984f5d5SWyes Karny * @perf_caps : struct where autonomous selection register value is updated.
1482c984f5d5SWyes Karny */
cppc_get_auto_sel_caps(int cpunum,struct cppc_perf_caps * perf_caps)1483c984f5d5SWyes Karny int cppc_get_auto_sel_caps(int cpunum, struct cppc_perf_caps *perf_caps)
1484c984f5d5SWyes Karny {
1485c984f5d5SWyes Karny struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1486c984f5d5SWyes Karny struct cpc_register_resource *auto_sel_reg;
1487c984f5d5SWyes Karny u64 auto_sel;
1488c984f5d5SWyes Karny
1489c984f5d5SWyes Karny if (!cpc_desc) {
1490c984f5d5SWyes Karny pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1491c984f5d5SWyes Karny return -ENODEV;
1492c984f5d5SWyes Karny }
1493c984f5d5SWyes Karny
1494c984f5d5SWyes Karny auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
1495c984f5d5SWyes Karny
1496c984f5d5SWyes Karny if (!CPC_SUPPORTED(auto_sel_reg))
1497c984f5d5SWyes Karny pr_warn_once("Autonomous mode is not unsupported!\n");
1498c984f5d5SWyes Karny
1499c984f5d5SWyes Karny if (CPC_IN_PCC(auto_sel_reg)) {
1500c984f5d5SWyes Karny int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1501c984f5d5SWyes Karny struct cppc_pcc_data *pcc_ss_data = NULL;
1502c984f5d5SWyes Karny int ret = 0;
1503c984f5d5SWyes Karny
1504c984f5d5SWyes Karny if (pcc_ss_id < 0)
1505c984f5d5SWyes Karny return -ENODEV;
1506c984f5d5SWyes Karny
1507c984f5d5SWyes Karny pcc_ss_data = pcc_data[pcc_ss_id];
1508c984f5d5SWyes Karny
1509c984f5d5SWyes Karny down_write(&pcc_ss_data->pcc_lock);
1510c984f5d5SWyes Karny
1511c984f5d5SWyes Karny if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) {
1512c984f5d5SWyes Karny cpc_read(cpunum, auto_sel_reg, &auto_sel);
1513c984f5d5SWyes Karny perf_caps->auto_sel = (bool)auto_sel;
1514c984f5d5SWyes Karny } else {
1515c984f5d5SWyes Karny ret = -EIO;
1516c984f5d5SWyes Karny }
1517c984f5d5SWyes Karny
1518c984f5d5SWyes Karny up_write(&pcc_ss_data->pcc_lock);
1519c984f5d5SWyes Karny
1520c984f5d5SWyes Karny return ret;
1521c984f5d5SWyes Karny }
1522c984f5d5SWyes Karny
1523c984f5d5SWyes Karny return 0;
1524c984f5d5SWyes Karny }
1525c984f5d5SWyes Karny EXPORT_SYMBOL_GPL(cppc_get_auto_sel_caps);
1526c984f5d5SWyes Karny
1527c984f5d5SWyes Karny /**
1528c984f5d5SWyes Karny * cppc_set_auto_sel - Write autonomous selection register.
1529c984f5d5SWyes Karny * @cpu : CPU to which to write register.
1530c984f5d5SWyes Karny * @enable : the desired value of autonomous selection resiter to be updated.
1531c984f5d5SWyes Karny */
cppc_set_auto_sel(int cpu,bool enable)1532c984f5d5SWyes Karny int cppc_set_auto_sel(int cpu, bool enable)
1533c984f5d5SWyes Karny {
1534c984f5d5SWyes Karny int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1535c984f5d5SWyes Karny struct cpc_register_resource *auto_sel_reg;
1536c984f5d5SWyes Karny struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1537c984f5d5SWyes Karny struct cppc_pcc_data *pcc_ss_data = NULL;
1538c984f5d5SWyes Karny int ret = -EINVAL;
1539c984f5d5SWyes Karny
1540c984f5d5SWyes Karny if (!cpc_desc) {
1541c984f5d5SWyes Karny pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1542c984f5d5SWyes Karny return -ENODEV;
1543c984f5d5SWyes Karny }
1544c984f5d5SWyes Karny
1545c984f5d5SWyes Karny auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
1546c984f5d5SWyes Karny
1547c984f5d5SWyes Karny if (CPC_IN_PCC(auto_sel_reg)) {
1548c984f5d5SWyes Karny if (pcc_ss_id < 0) {
1549c984f5d5SWyes Karny pr_debug("Invalid pcc_ss_id\n");
1550c984f5d5SWyes Karny return -ENODEV;
1551c984f5d5SWyes Karny }
1552c984f5d5SWyes Karny
1553c984f5d5SWyes Karny if (CPC_SUPPORTED(auto_sel_reg)) {
1554c984f5d5SWyes Karny ret = cpc_write(cpu, auto_sel_reg, enable);
1555c984f5d5SWyes Karny if (ret)
1556c984f5d5SWyes Karny return ret;
1557c984f5d5SWyes Karny }
1558c984f5d5SWyes Karny
1559c984f5d5SWyes Karny pcc_ss_data = pcc_data[pcc_ss_id];
1560c984f5d5SWyes Karny
1561c984f5d5SWyes Karny down_write(&pcc_ss_data->pcc_lock);
1562c984f5d5SWyes Karny /* after writing CPC, transfer the ownership of PCC to platform */
1563c984f5d5SWyes Karny ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1564c984f5d5SWyes Karny up_write(&pcc_ss_data->pcc_lock);
1565c984f5d5SWyes Karny } else {
1566c984f5d5SWyes Karny ret = -ENOTSUPP;
1567c984f5d5SWyes Karny pr_debug("_CPC in PCC is not supported\n");
1568c984f5d5SWyes Karny }
1569c984f5d5SWyes Karny
1570c984f5d5SWyes Karny return ret;
1571c984f5d5SWyes Karny }
1572c984f5d5SWyes Karny EXPORT_SYMBOL_GPL(cppc_set_auto_sel);
1573c984f5d5SWyes Karny
1574c984f5d5SWyes Karny /**
1575fb0b00afSJinzhou Su * cppc_set_enable - Set to enable CPPC on the processor by writing the
1576fb0b00afSJinzhou Su * Continuous Performance Control package EnableRegister field.
1577fb0b00afSJinzhou Su * @cpu: CPU for which to enable CPPC register.
1578fb0b00afSJinzhou Su * @enable: 0 - disable, 1 - enable CPPC feature on the processor.
1579fb0b00afSJinzhou Su *
1580fb0b00afSJinzhou Su * Return: 0 for success, -ERRNO or -EIO otherwise.
1581fb0b00afSJinzhou Su */
cppc_set_enable(int cpu,bool enable)1582fb0b00afSJinzhou Su int cppc_set_enable(int cpu, bool enable)
1583fb0b00afSJinzhou Su {
1584fb0b00afSJinzhou Su int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1585fb0b00afSJinzhou Su struct cpc_register_resource *enable_reg;
1586fb0b00afSJinzhou Su struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1587fb0b00afSJinzhou Su struct cppc_pcc_data *pcc_ss_data = NULL;
1588fb0b00afSJinzhou Su int ret = -EINVAL;
1589fb0b00afSJinzhou Su
1590fb0b00afSJinzhou Su if (!cpc_desc) {
1591fb0b00afSJinzhou Su pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1592fb0b00afSJinzhou Su return -EINVAL;
1593fb0b00afSJinzhou Su }
1594fb0b00afSJinzhou Su
1595fb0b00afSJinzhou Su enable_reg = &cpc_desc->cpc_regs[ENABLE];
1596fb0b00afSJinzhou Su
1597fb0b00afSJinzhou Su if (CPC_IN_PCC(enable_reg)) {
1598fb0b00afSJinzhou Su
1599fb0b00afSJinzhou Su if (pcc_ss_id < 0)
1600fb0b00afSJinzhou Su return -EIO;
1601fb0b00afSJinzhou Su
1602fb0b00afSJinzhou Su ret = cpc_write(cpu, enable_reg, enable);
1603fb0b00afSJinzhou Su if (ret)
1604fb0b00afSJinzhou Su return ret;
1605fb0b00afSJinzhou Su
1606fb0b00afSJinzhou Su pcc_ss_data = pcc_data[pcc_ss_id];
1607fb0b00afSJinzhou Su
1608fb0b00afSJinzhou Su down_write(&pcc_ss_data->pcc_lock);
1609fb0b00afSJinzhou Su /* after writing CPC, transfer the ownership of PCC to platfrom */
1610fb0b00afSJinzhou Su ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1611fb0b00afSJinzhou Su up_write(&pcc_ss_data->pcc_lock);
1612fb0b00afSJinzhou Su return ret;
1613fb0b00afSJinzhou Su }
1614fb0b00afSJinzhou Su
1615fb0b00afSJinzhou Su return cpc_write(cpu, enable_reg, enable);
1616fb0b00afSJinzhou Su }
1617fb0b00afSJinzhou Su EXPORT_SYMBOL_GPL(cppc_set_enable);
1618fb0b00afSJinzhou Su
1619fb0b00afSJinzhou Su /**
1620603fadf3SBjorn Helgaas * cppc_set_perf - Set a CPU's performance controls.
1621337aadffSAshwin Chaugule * @cpu: CPU for which to set performance controls.
1622337aadffSAshwin Chaugule * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h
1623337aadffSAshwin Chaugule *
1624337aadffSAshwin Chaugule * Return: 0 for success, -ERRNO otherwise.
1625337aadffSAshwin Chaugule */
cppc_set_perf(int cpu,struct cppc_perf_ctrls * perf_ctrls)1626337aadffSAshwin Chaugule int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
1627337aadffSAshwin Chaugule {
1628337aadffSAshwin Chaugule struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
162976531df5SWyes Karny struct cpc_register_resource *desired_reg, *min_perf_reg, *max_perf_reg;
163085b1407bSGeorge Cherian int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
16316fa12d58SPrashanth Prakash struct cppc_pcc_data *pcc_ss_data = NULL;
1632337aadffSAshwin Chaugule int ret = 0;
1633337aadffSAshwin Chaugule
16346fa12d58SPrashanth Prakash if (!cpc_desc) {
1635337aadffSAshwin Chaugule pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1636337aadffSAshwin Chaugule return -ENODEV;
1637337aadffSAshwin Chaugule }
1638337aadffSAshwin Chaugule
1639337aadffSAshwin Chaugule desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
164076531df5SWyes Karny min_perf_reg = &cpc_desc->cpc_regs[MIN_PERF];
164176531df5SWyes Karny max_perf_reg = &cpc_desc->cpc_regs[MAX_PERF];
1642337aadffSAshwin Chaugule
164380b8286aSPrakash, Prashanth /*
164480b8286aSPrakash, Prashanth * This is Phase-I where we want to write to CPC registers
164580b8286aSPrakash, Prashanth * -> We want all CPUs to be able to execute this phase in parallel
164680b8286aSPrakash, Prashanth *
164780b8286aSPrakash, Prashanth * Since read_lock can be acquired by multiple CPUs simultaneously we
164880b8286aSPrakash, Prashanth * achieve that goal here
164980b8286aSPrakash, Prashanth */
165076531df5SWyes Karny if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg)) {
16516fa12d58SPrashanth Prakash if (pcc_ss_id < 0) {
16526fa12d58SPrashanth Prakash pr_debug("Invalid pcc_ss_id\n");
16536fa12d58SPrashanth Prakash return -ENODEV;
16546fa12d58SPrashanth Prakash }
16556fa12d58SPrashanth Prakash pcc_ss_data = pcc_data[pcc_ss_id];
165685b1407bSGeorge Cherian down_read(&pcc_ss_data->pcc_lock); /* BEGIN Phase-I */
165785b1407bSGeorge Cherian if (pcc_ss_data->platform_owns_pcc) {
165885b1407bSGeorge Cherian ret = check_pcc_chan(pcc_ss_id, false);
165980b8286aSPrakash, Prashanth if (ret) {
166085b1407bSGeorge Cherian up_read(&pcc_ss_data->pcc_lock);
166180b8286aSPrakash, Prashanth return ret;
166280b8286aSPrakash, Prashanth }
166380b8286aSPrakash, Prashanth }
1664139aee73SPrakash, Prashanth /*
1665139aee73SPrakash, Prashanth * Update the pending_write to make sure a PCC CMD_READ will not
1666139aee73SPrakash, Prashanth * arrive and steal the channel during the switch to write lock
1667139aee73SPrakash, Prashanth */
166885b1407bSGeorge Cherian pcc_ss_data->pending_pcc_write_cmd = true;
166985b1407bSGeorge Cherian cpc_desc->write_cmd_id = pcc_ss_data->pcc_write_cnt;
167080b8286aSPrakash, Prashanth cpc_desc->write_cmd_status = 0;
1671ad62e1e6SAshwin Chaugule }
1672ad62e1e6SAshwin Chaugule
1673a6cbcdd5SSrinivas Pandruvada cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
1674337aadffSAshwin Chaugule
167576531df5SWyes Karny /*
167676531df5SWyes Karny * Only write if min_perf and max_perf not zero. Some drivers pass zero
167776531df5SWyes Karny * value to min and max perf, but they don't mean to set the zero value,
167876531df5SWyes Karny * they just don't want to write to those registers.
167976531df5SWyes Karny */
168076531df5SWyes Karny if (perf_ctrls->min_perf)
168176531df5SWyes Karny cpc_write(cpu, min_perf_reg, perf_ctrls->min_perf);
168276531df5SWyes Karny if (perf_ctrls->max_perf)
168376531df5SWyes Karny cpc_write(cpu, max_perf_reg, perf_ctrls->max_perf);
168476531df5SWyes Karny
168576531df5SWyes Karny if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg))
168685b1407bSGeorge Cherian up_read(&pcc_ss_data->pcc_lock); /* END Phase-I */
168780b8286aSPrakash, Prashanth /*
168880b8286aSPrakash, Prashanth * This is Phase-II where we transfer the ownership of PCC to Platform
168980b8286aSPrakash, Prashanth *
169080b8286aSPrakash, Prashanth * Short Summary: Basically if we think of a group of cppc_set_perf
169180b8286aSPrakash, Prashanth * requests that happened in short overlapping interval. The last CPU to
169280b8286aSPrakash, Prashanth * come out of Phase-I will enter Phase-II and ring the doorbell.
169380b8286aSPrakash, Prashanth *
169480b8286aSPrakash, Prashanth * We have the following requirements for Phase-II:
169580b8286aSPrakash, Prashanth * 1. We want to execute Phase-II only when there are no CPUs
169680b8286aSPrakash, Prashanth * currently executing in Phase-I
169780b8286aSPrakash, Prashanth * 2. Once we start Phase-II we want to avoid all other CPUs from
169880b8286aSPrakash, Prashanth * entering Phase-I.
169980b8286aSPrakash, Prashanth * 3. We want only one CPU among all those who went through Phase-I
170080b8286aSPrakash, Prashanth * to run phase-II
170180b8286aSPrakash, Prashanth *
170280b8286aSPrakash, Prashanth * If write_trylock fails to get the lock and doesn't transfer the
170380b8286aSPrakash, Prashanth * PCC ownership to the platform, then one of the following will be TRUE
170480b8286aSPrakash, Prashanth * 1. There is at-least one CPU in Phase-I which will later execute
170580b8286aSPrakash, Prashanth * write_trylock, so the CPUs in Phase-I will be responsible for
170680b8286aSPrakash, Prashanth * executing the Phase-II.
170780b8286aSPrakash, Prashanth * 2. Some other CPU has beaten this CPU to successfully execute the
170880b8286aSPrakash, Prashanth * write_trylock and has already acquired the write_lock. We know for a
170980b8286aSPrakash, Prashanth * fact it (other CPU acquiring the write_lock) couldn't have happened
171080b8286aSPrakash, Prashanth * before this CPU's Phase-I as we held the read_lock.
171180b8286aSPrakash, Prashanth * 3. Some other CPU executing pcc CMD_READ has stolen the
171280b8286aSPrakash, Prashanth * down_write, in which case, send_pcc_cmd will check for pending
171380b8286aSPrakash, Prashanth * CMD_WRITE commands by checking the pending_pcc_write_cmd.
171480b8286aSPrakash, Prashanth * So this CPU can be certain that its request will be delivered
171580b8286aSPrakash, Prashanth * So in all cases, this CPU knows that its request will be delivered
171680b8286aSPrakash, Prashanth * by another CPU and can return
171780b8286aSPrakash, Prashanth *
171880b8286aSPrakash, Prashanth * After getting the down_write we still need to check for
171980b8286aSPrakash, Prashanth * pending_pcc_write_cmd to take care of the following scenario
172080b8286aSPrakash, Prashanth * The thread running this code could be scheduled out between
172180b8286aSPrakash, Prashanth * Phase-I and Phase-II. Before it is scheduled back on, another CPU
172280b8286aSPrakash, Prashanth * could have delivered the request to Platform by triggering the
172380b8286aSPrakash, Prashanth * doorbell and transferred the ownership of PCC to platform. So this
172480b8286aSPrakash, Prashanth * avoids triggering an unnecessary doorbell and more importantly before
172580b8286aSPrakash, Prashanth * triggering the doorbell it makes sure that the PCC channel ownership
172680b8286aSPrakash, Prashanth * is still with OSPM.
172780b8286aSPrakash, Prashanth * pending_pcc_write_cmd can also be cleared by a different CPU, if
172880b8286aSPrakash, Prashanth * there was a pcc CMD_READ waiting on down_write and it steals the lock
1729935ab850STom Saeger * before the pcc CMD_WRITE is completed. send_pcc_cmd checks for this
173080b8286aSPrakash, Prashanth * case during a CMD_READ and if there are pending writes it delivers
173180b8286aSPrakash, Prashanth * the write command before servicing the read command
173280b8286aSPrakash, Prashanth */
173376531df5SWyes Karny if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg)) {
173485b1407bSGeorge Cherian if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */
173580b8286aSPrakash, Prashanth /* Update only if there are pending write commands */
173685b1407bSGeorge Cherian if (pcc_ss_data->pending_pcc_write_cmd)
173785b1407bSGeorge Cherian send_pcc_cmd(pcc_ss_id, CMD_WRITE);
173885b1407bSGeorge Cherian up_write(&pcc_ss_data->pcc_lock); /* END Phase-II */
173980b8286aSPrakash, Prashanth } else
174080b8286aSPrakash, Prashanth /* Wait until pcc_write_cnt is updated by send_pcc_cmd */
174185b1407bSGeorge Cherian wait_event(pcc_ss_data->pcc_write_wait_q,
174285b1407bSGeorge Cherian cpc_desc->write_cmd_id != pcc_ss_data->pcc_write_cnt);
174380b8286aSPrakash, Prashanth
174480b8286aSPrakash, Prashanth /* send_pcc_cmd updates the status in case of failure */
174580b8286aSPrakash, Prashanth ret = cpc_desc->write_cmd_status;
1746337aadffSAshwin Chaugule }
1747337aadffSAshwin Chaugule return ret;
1748337aadffSAshwin Chaugule }
1749337aadffSAshwin Chaugule EXPORT_SYMBOL_GPL(cppc_set_perf);
1750be8b88d7SPrakash, Prashanth
1751be8b88d7SPrakash, Prashanth /**
1752be8b88d7SPrakash, Prashanth * cppc_get_transition_latency - returns frequency transition latency in ns
1753fda7be20SYang Li * @cpu_num: CPU number for per_cpu().
1754be8b88d7SPrakash, Prashanth *
1755935ab850STom Saeger * ACPI CPPC does not explicitly specify how a platform can specify the
1756935ab850STom Saeger * transition latency for performance change requests. The closest we have
1757be8b88d7SPrakash, Prashanth * is the timing information from the PCCT tables which provides the info
1758be8b88d7SPrakash, Prashanth * on the number and frequency of PCC commands the platform can handle.
17596380b7b2SPierre Gondois *
17606380b7b2SPierre Gondois * If desired_reg is in the SystemMemory or SystemIo ACPI address space,
17616380b7b2SPierre Gondois * then assume there is no latency.
1762be8b88d7SPrakash, Prashanth */
cppc_get_transition_latency(int cpu_num)1763be8b88d7SPrakash, Prashanth unsigned int cppc_get_transition_latency(int cpu_num)
1764be8b88d7SPrakash, Prashanth {
1765be8b88d7SPrakash, Prashanth /*
1766be8b88d7SPrakash, Prashanth * Expected transition latency is based on the PCCT timing values
1767be8b88d7SPrakash, Prashanth * Below are definition from ACPI spec:
1768be8b88d7SPrakash, Prashanth * pcc_nominal- Expected latency to process a command, in microseconds
1769be8b88d7SPrakash, Prashanth * pcc_mpar - The maximum number of periodic requests that the subspace
1770be8b88d7SPrakash, Prashanth * channel can support, reported in commands per minute. 0
1771be8b88d7SPrakash, Prashanth * indicates no limitation.
1772be8b88d7SPrakash, Prashanth * pcc_mrtt - The minimum amount of time that OSPM must wait after the
1773be8b88d7SPrakash, Prashanth * completion of a command before issuing the next command,
1774be8b88d7SPrakash, Prashanth * in microseconds.
1775be8b88d7SPrakash, Prashanth */
1776be8b88d7SPrakash, Prashanth unsigned int latency_ns = 0;
1777be8b88d7SPrakash, Prashanth struct cpc_desc *cpc_desc;
1778be8b88d7SPrakash, Prashanth struct cpc_register_resource *desired_reg;
177985b1407bSGeorge Cherian int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu_num);
17801ecbd717SGeorge Cherian struct cppc_pcc_data *pcc_ss_data;
1781be8b88d7SPrakash, Prashanth
1782be8b88d7SPrakash, Prashanth cpc_desc = per_cpu(cpc_desc_ptr, cpu_num);
1783be8b88d7SPrakash, Prashanth if (!cpc_desc)
1784be8b88d7SPrakash, Prashanth return CPUFREQ_ETERNAL;
1785be8b88d7SPrakash, Prashanth
1786be8b88d7SPrakash, Prashanth desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
17876380b7b2SPierre Gondois if (CPC_IN_SYSTEM_MEMORY(desired_reg) || CPC_IN_SYSTEM_IO(desired_reg))
17886380b7b2SPierre Gondois return 0;
17896380b7b2SPierre Gondois else if (!CPC_IN_PCC(desired_reg))
1790be8b88d7SPrakash, Prashanth return CPUFREQ_ETERNAL;
1791be8b88d7SPrakash, Prashanth
17921ecbd717SGeorge Cherian if (pcc_ss_id < 0)
17931ecbd717SGeorge Cherian return CPUFREQ_ETERNAL;
17941ecbd717SGeorge Cherian
17951ecbd717SGeorge Cherian pcc_ss_data = pcc_data[pcc_ss_id];
179685b1407bSGeorge Cherian if (pcc_ss_data->pcc_mpar)
179785b1407bSGeorge Cherian latency_ns = 60 * (1000 * 1000 * 1000 / pcc_ss_data->pcc_mpar);
1798be8b88d7SPrakash, Prashanth
179985b1407bSGeorge Cherian latency_ns = max(latency_ns, pcc_ss_data->pcc_nominal * 1000);
180085b1407bSGeorge Cherian latency_ns = max(latency_ns, pcc_ss_data->pcc_mrtt * 1000);
1801be8b88d7SPrakash, Prashanth
1802be8b88d7SPrakash, Prashanth return latency_ns;
1803be8b88d7SPrakash, Prashanth }
1804be8b88d7SPrakash, Prashanth EXPORT_SYMBOL_GPL(cppc_get_transition_latency);
1805