1 /******************************************************************************* 2 * 3 * Module Name: hwregs - Read/write access functions for the various ACPI 4 * control and status registers. 5 * 6 ******************************************************************************/ 7 8 /* 9 * Copyright (C) 2000 - 2016, Intel Corp. 10 * All rights reserved. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions, and the following disclaimer, 17 * without modification. 18 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 19 * substantially similar to the "NO WARRANTY" disclaimer below 20 * ("Disclaimer") and any redistribution must be conditioned upon 21 * including a substantially similar Disclaimer requirement for further 22 * binary redistribution. 23 * 3. Neither the names of the above-listed copyright holders nor the names 24 * of any contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * Alternatively, this software may be distributed under the terms of the 28 * GNU General Public License ("GPL") version 2 as published by the Free 29 * Software Foundation. 30 * 31 * NO WARRANTY 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 35 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 36 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 40 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 41 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 42 * POSSIBILITY OF SUCH DAMAGES. 43 */ 44 45 #include <acpi/acpi.h> 46 #include "accommon.h" 47 #include "acevents.h" 48 49 #define _COMPONENT ACPI_HARDWARE 50 ACPI_MODULE_NAME("hwregs") 51 52 #if (!ACPI_REDUCED_HARDWARE) 53 /* Local Prototypes */ 54 static u8 55 acpi_hw_get_access_bit_width(struct acpi_generic_address *reg, 56 u8 max_bit_width); 57 58 static acpi_status 59 acpi_hw_read_multiple(u32 *value, 60 struct acpi_generic_address *register_a, 61 struct acpi_generic_address *register_b); 62 63 static acpi_status 64 acpi_hw_write_multiple(u32 value, 65 struct acpi_generic_address *register_a, 66 struct acpi_generic_address *register_b); 67 68 #endif /* !ACPI_REDUCED_HARDWARE */ 69 70 /****************************************************************************** 71 * 72 * FUNCTION: acpi_hw_get_access_bit_width 73 * 74 * PARAMETERS: reg - GAS register structure 75 * max_bit_width - Max bit_width supported (32 or 64) 76 * 77 * RETURN: Status 78 * 79 * DESCRIPTION: Obtain optimal access bit width 80 * 81 ******************************************************************************/ 82 83 static u8 84 acpi_hw_get_access_bit_width(struct acpi_generic_address *reg, u8 max_bit_width) 85 { 86 if (!reg->access_width) { 87 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) { 88 max_bit_width = 32; 89 } 90 91 /* 92 * Detect old register descriptors where only the bit_width field 93 * makes senses. 94 */ 95 if (reg->bit_width < max_bit_width && 96 !reg->bit_offset && reg->bit_width && 97 ACPI_IS_POWER_OF_TWO(reg->bit_width) && 98 ACPI_IS_ALIGNED(reg->bit_width, 8)) { 99 return (reg->bit_width); 100 } 101 return (max_bit_width); 102 } else { 103 return (1 << (reg->access_width + 2)); 104 } 105 } 106 107 /****************************************************************************** 108 * 109 * FUNCTION: acpi_hw_validate_register 110 * 111 * PARAMETERS: reg - GAS register structure 112 * max_bit_width - Max bit_width supported (32 or 64) 113 * address - Pointer to where the gas->address 114 * is returned 115 * 116 * RETURN: Status 117 * 118 * DESCRIPTION: Validate the contents of a GAS register. Checks the GAS 119 * pointer, Address, space_id, bit_width, and bit_offset. 120 * 121 ******************************************************************************/ 122 123 acpi_status 124 acpi_hw_validate_register(struct acpi_generic_address *reg, 125 u8 max_bit_width, u64 *address) 126 { 127 u8 bit_width; 128 u8 access_width; 129 130 /* Must have a valid pointer to a GAS structure */ 131 132 if (!reg) { 133 return (AE_BAD_PARAMETER); 134 } 135 136 /* 137 * Copy the target address. This handles possible alignment issues. 138 * Address must not be null. A null address also indicates an optional 139 * ACPI register that is not supported, so no error message. 140 */ 141 ACPI_MOVE_64_TO_64(address, ®->address); 142 if (!(*address)) { 143 return (AE_BAD_ADDRESS); 144 } 145 146 /* Validate the space_ID */ 147 148 if ((reg->space_id != ACPI_ADR_SPACE_SYSTEM_MEMORY) && 149 (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO)) { 150 ACPI_ERROR((AE_INFO, 151 "Unsupported address space: 0x%X", reg->space_id)); 152 return (AE_SUPPORT); 153 } 154 155 /* Validate the access_width */ 156 157 if (reg->access_width > 4) { 158 ACPI_ERROR((AE_INFO, 159 "Unsupported register access width: 0x%X", 160 reg->access_width)); 161 return (AE_SUPPORT); 162 } 163 164 /* Validate the bit_width, convert access_width into number of bits */ 165 166 access_width = acpi_hw_get_access_bit_width(reg, max_bit_width); 167 bit_width = 168 ACPI_ROUND_UP(reg->bit_offset + reg->bit_width, access_width); 169 if (max_bit_width < bit_width) { 170 ACPI_WARNING((AE_INFO, 171 "Requested bit width 0x%X is smaller than register bit width 0x%X", 172 max_bit_width, bit_width)); 173 return (AE_SUPPORT); 174 } 175 176 return (AE_OK); 177 } 178 179 /****************************************************************************** 180 * 181 * FUNCTION: acpi_hw_read 182 * 183 * PARAMETERS: value - Where the value is returned 184 * reg - GAS register structure 185 * 186 * RETURN: Status 187 * 188 * DESCRIPTION: Read from either memory or IO space. This is a 32-bit max 189 * version of acpi_read, used internally since the overhead of 190 * 64-bit values is not needed. 191 * 192 * LIMITATIONS: <These limitations also apply to acpi_hw_write> 193 * space_ID must be system_memory or system_IO. 194 * 195 ******************************************************************************/ 196 197 acpi_status acpi_hw_read(u32 *value, struct acpi_generic_address *reg) 198 { 199 u64 address; 200 u8 access_width; 201 u32 bit_width; 202 u8 bit_offset; 203 u64 value64; 204 u32 value32; 205 u8 index; 206 acpi_status status; 207 208 ACPI_FUNCTION_NAME(hw_read); 209 210 /* Validate contents of the GAS register */ 211 212 status = acpi_hw_validate_register(reg, 32, &address); 213 if (ACPI_FAILURE(status)) { 214 return (status); 215 } 216 217 /* 218 * Initialize entire 32-bit return value to zero, convert access_width 219 * into number of bits based 220 */ 221 *value = 0; 222 access_width = acpi_hw_get_access_bit_width(reg, 32); 223 bit_width = reg->bit_offset + reg->bit_width; 224 bit_offset = reg->bit_offset; 225 226 /* 227 * Two address spaces supported: Memory or IO. PCI_Config is 228 * not supported here because the GAS structure is insufficient 229 */ 230 index = 0; 231 while (bit_width) { 232 if (bit_offset >= access_width) { 233 value32 = 0; 234 bit_offset -= access_width; 235 } else { 236 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) { 237 status = 238 acpi_os_read_memory((acpi_physical_address) 239 address + 240 index * 241 ACPI_DIV_8 242 (access_width), 243 &value64, access_width); 244 value32 = (u32)value64; 245 } else { /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */ 246 247 status = acpi_hw_read_port((acpi_io_address) 248 address + 249 index * 250 ACPI_DIV_8 251 (access_width), 252 &value32, 253 access_width); 254 } 255 256 /* 257 * Use offset style bit masks because: 258 * bit_offset < access_width/bit_width < access_width, and 259 * access_width is ensured to be less than 32-bits by 260 * acpi_hw_validate_register(). 261 */ 262 if (bit_offset) { 263 value32 &= ACPI_MASK_BITS_BELOW(bit_offset); 264 bit_offset = 0; 265 } 266 if (bit_width < access_width) { 267 value32 &= ACPI_MASK_BITS_ABOVE(bit_width); 268 } 269 } 270 271 /* 272 * Use offset style bit writes because "Index * AccessWidth" is 273 * ensured to be less than 32-bits by acpi_hw_validate_register(). 274 */ 275 ACPI_SET_BITS(value, index * access_width, 276 ACPI_MASK_BITS_ABOVE_32(access_width), value32); 277 278 bit_width -= 279 bit_width > access_width ? access_width : bit_width; 280 index++; 281 } 282 283 ACPI_DEBUG_PRINT((ACPI_DB_IO, 284 "Read: %8.8X width %2d from %8.8X%8.8X (%s)\n", 285 *value, access_width, ACPI_FORMAT_UINT64(address), 286 acpi_ut_get_region_name(reg->space_id))); 287 288 return (status); 289 } 290 291 /****************************************************************************** 292 * 293 * FUNCTION: acpi_hw_write 294 * 295 * PARAMETERS: value - Value to be written 296 * reg - GAS register structure 297 * 298 * RETURN: Status 299 * 300 * DESCRIPTION: Write to either memory or IO space. This is a 32-bit max 301 * version of acpi_write, used internally since the overhead of 302 * 64-bit values is not needed. 303 * 304 ******************************************************************************/ 305 306 acpi_status acpi_hw_write(u32 value, struct acpi_generic_address *reg) 307 { 308 u64 address; 309 u8 access_width; 310 u32 bit_width; 311 u8 bit_offset; 312 u64 value64; 313 u32 new_value32, old_value32; 314 u8 index; 315 acpi_status status; 316 317 ACPI_FUNCTION_NAME(hw_write); 318 319 /* Validate contents of the GAS register */ 320 321 status = acpi_hw_validate_register(reg, 32, &address); 322 if (ACPI_FAILURE(status)) { 323 return (status); 324 } 325 326 /* Convert access_width into number of bits based */ 327 328 access_width = acpi_hw_get_access_bit_width(reg, 32); 329 bit_width = reg->bit_offset + reg->bit_width; 330 bit_offset = reg->bit_offset; 331 332 /* 333 * Two address spaces supported: Memory or IO. PCI_Config is 334 * not supported here because the GAS structure is insufficient 335 */ 336 index = 0; 337 while (bit_width) { 338 /* 339 * Use offset style bit reads because "Index * AccessWidth" is 340 * ensured to be less than 32-bits by acpi_hw_validate_register(). 341 */ 342 new_value32 = ACPI_GET_BITS(&value, index * access_width, 343 ACPI_MASK_BITS_ABOVE_32 344 (access_width)); 345 346 if (bit_offset >= access_width) { 347 bit_offset -= access_width; 348 } else { 349 /* 350 * Use offset style bit masks because access_width is ensured 351 * to be less than 32-bits by acpi_hw_validate_register() and 352 * bit_offset/bit_width is less than access_width here. 353 */ 354 if (bit_offset) { 355 new_value32 &= ACPI_MASK_BITS_BELOW(bit_offset); 356 } 357 if (bit_width < access_width) { 358 new_value32 &= ACPI_MASK_BITS_ABOVE(bit_width); 359 } 360 361 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) { 362 if (bit_offset || bit_width < access_width) { 363 /* 364 * Read old values in order not to modify the bits that 365 * are beyond the register bit_width/bit_offset setting. 366 */ 367 status = 368 acpi_os_read_memory((acpi_physical_address) 369 address + 370 index * 371 ACPI_DIV_8 372 (access_width), 373 &value64, 374 access_width); 375 old_value32 = (u32)value64; 376 377 /* 378 * Use offset style bit masks because access_width is 379 * ensured to be less than 32-bits by 380 * acpi_hw_validate_register() and bit_offset/bit_width is 381 * less than access_width here. 382 */ 383 if (bit_offset) { 384 old_value32 &= 385 ACPI_MASK_BITS_ABOVE 386 (bit_offset); 387 bit_offset = 0; 388 } 389 if (bit_width < access_width) { 390 old_value32 &= 391 ACPI_MASK_BITS_BELOW 392 (bit_width); 393 } 394 395 new_value32 |= old_value32; 396 } 397 398 value64 = (u64)new_value32; 399 status = 400 acpi_os_write_memory((acpi_physical_address) 401 address + 402 index * 403 ACPI_DIV_8 404 (access_width), 405 value64, access_width); 406 } else { /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */ 407 408 if (bit_offset || bit_width < access_width) { 409 /* 410 * Read old values in order not to modify the bits that 411 * are beyond the register bit_width/bit_offset setting. 412 */ 413 status = 414 acpi_hw_read_port((acpi_io_address) 415 address + 416 index * 417 ACPI_DIV_8 418 (access_width), 419 &old_value32, 420 access_width); 421 422 /* 423 * Use offset style bit masks because access_width is 424 * ensured to be less than 32-bits by 425 * acpi_hw_validate_register() and bit_offset/bit_width is 426 * less than access_width here. 427 */ 428 if (bit_offset) { 429 old_value32 &= 430 ACPI_MASK_BITS_ABOVE 431 (bit_offset); 432 bit_offset = 0; 433 } 434 if (bit_width < access_width) { 435 old_value32 &= 436 ACPI_MASK_BITS_BELOW 437 (bit_width); 438 } 439 440 new_value32 |= old_value32; 441 } 442 443 status = acpi_hw_write_port((acpi_io_address) 444 address + 445 index * 446 ACPI_DIV_8 447 (access_width), 448 new_value32, 449 access_width); 450 } 451 } 452 453 /* 454 * Index * access_width is ensured to be less than 32-bits by 455 * acpi_hw_validate_register(). 456 */ 457 bit_width -= 458 bit_width > access_width ? access_width : bit_width; 459 index++; 460 } 461 462 ACPI_DEBUG_PRINT((ACPI_DB_IO, 463 "Wrote: %8.8X width %2d to %8.8X%8.8X (%s)\n", 464 value, access_width, ACPI_FORMAT_UINT64(address), 465 acpi_ut_get_region_name(reg->space_id))); 466 467 return (status); 468 } 469 470 #if (!ACPI_REDUCED_HARDWARE) 471 /******************************************************************************* 472 * 473 * FUNCTION: acpi_hw_clear_acpi_status 474 * 475 * PARAMETERS: None 476 * 477 * RETURN: Status 478 * 479 * DESCRIPTION: Clears all fixed and general purpose status bits 480 * 481 ******************************************************************************/ 482 483 acpi_status acpi_hw_clear_acpi_status(void) 484 { 485 acpi_status status; 486 acpi_cpu_flags lock_flags = 0; 487 488 ACPI_FUNCTION_TRACE(hw_clear_acpi_status); 489 490 ACPI_DEBUG_PRINT((ACPI_DB_IO, "About to write %04X to %8.8X%8.8X\n", 491 ACPI_BITMASK_ALL_FIXED_STATUS, 492 ACPI_FORMAT_UINT64(acpi_gbl_xpm1a_status.address))); 493 494 lock_flags = acpi_os_acquire_lock(acpi_gbl_hardware_lock); 495 496 /* Clear the fixed events in PM1 A/B */ 497 498 status = acpi_hw_register_write(ACPI_REGISTER_PM1_STATUS, 499 ACPI_BITMASK_ALL_FIXED_STATUS); 500 501 acpi_os_release_lock(acpi_gbl_hardware_lock, lock_flags); 502 503 if (ACPI_FAILURE(status)) { 504 goto exit; 505 } 506 507 /* Clear the GPE Bits in all GPE registers in all GPE blocks */ 508 509 status = acpi_ev_walk_gpe_list(acpi_hw_clear_gpe_block, NULL); 510 511 exit: 512 return_ACPI_STATUS(status); 513 } 514 515 /******************************************************************************* 516 * 517 * FUNCTION: acpi_hw_get_bit_register_info 518 * 519 * PARAMETERS: register_id - Index of ACPI Register to access 520 * 521 * RETURN: The bitmask to be used when accessing the register 522 * 523 * DESCRIPTION: Map register_id into a register bitmask. 524 * 525 ******************************************************************************/ 526 527 struct acpi_bit_register_info *acpi_hw_get_bit_register_info(u32 register_id) 528 { 529 ACPI_FUNCTION_ENTRY(); 530 531 if (register_id > ACPI_BITREG_MAX) { 532 ACPI_ERROR((AE_INFO, "Invalid BitRegister ID: 0x%X", 533 register_id)); 534 return (NULL); 535 } 536 537 return (&acpi_gbl_bit_register_info[register_id]); 538 } 539 540 /****************************************************************************** 541 * 542 * FUNCTION: acpi_hw_write_pm1_control 543 * 544 * PARAMETERS: pm1a_control - Value to be written to PM1A control 545 * pm1b_control - Value to be written to PM1B control 546 * 547 * RETURN: Status 548 * 549 * DESCRIPTION: Write the PM1 A/B control registers. These registers are 550 * different than than the PM1 A/B status and enable registers 551 * in that different values can be written to the A/B registers. 552 * Most notably, the SLP_TYP bits can be different, as per the 553 * values returned from the _Sx predefined methods. 554 * 555 ******************************************************************************/ 556 557 acpi_status acpi_hw_write_pm1_control(u32 pm1a_control, u32 pm1b_control) 558 { 559 acpi_status status; 560 561 ACPI_FUNCTION_TRACE(hw_write_pm1_control); 562 563 status = 564 acpi_hw_write(pm1a_control, &acpi_gbl_FADT.xpm1a_control_block); 565 if (ACPI_FAILURE(status)) { 566 return_ACPI_STATUS(status); 567 } 568 569 if (acpi_gbl_FADT.xpm1b_control_block.address) { 570 status = 571 acpi_hw_write(pm1b_control, 572 &acpi_gbl_FADT.xpm1b_control_block); 573 } 574 return_ACPI_STATUS(status); 575 } 576 577 /****************************************************************************** 578 * 579 * FUNCTION: acpi_hw_register_read 580 * 581 * PARAMETERS: register_id - ACPI Register ID 582 * return_value - Where the register value is returned 583 * 584 * RETURN: Status and the value read. 585 * 586 * DESCRIPTION: Read from the specified ACPI register 587 * 588 ******************************************************************************/ 589 acpi_status acpi_hw_register_read(u32 register_id, u32 *return_value) 590 { 591 u32 value = 0; 592 acpi_status status; 593 594 ACPI_FUNCTION_TRACE(hw_register_read); 595 596 switch (register_id) { 597 case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */ 598 599 status = acpi_hw_read_multiple(&value, 600 &acpi_gbl_xpm1a_status, 601 &acpi_gbl_xpm1b_status); 602 break; 603 604 case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access each */ 605 606 status = acpi_hw_read_multiple(&value, 607 &acpi_gbl_xpm1a_enable, 608 &acpi_gbl_xpm1b_enable); 609 break; 610 611 case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */ 612 613 status = acpi_hw_read_multiple(&value, 614 &acpi_gbl_FADT. 615 xpm1a_control_block, 616 &acpi_gbl_FADT. 617 xpm1b_control_block); 618 619 /* 620 * Zero the write-only bits. From the ACPI specification, "Hardware 621 * Write-Only Bits": "Upon reads to registers with write-only bits, 622 * software masks out all write-only bits." 623 */ 624 value &= ~ACPI_PM1_CONTROL_WRITEONLY_BITS; 625 break; 626 627 case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */ 628 629 status = 630 acpi_hw_read(&value, &acpi_gbl_FADT.xpm2_control_block); 631 break; 632 633 case ACPI_REGISTER_PM_TIMER: /* 32-bit access */ 634 635 status = acpi_hw_read(&value, &acpi_gbl_FADT.xpm_timer_block); 636 break; 637 638 case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */ 639 640 status = 641 acpi_hw_read_port(acpi_gbl_FADT.smi_command, &value, 8); 642 break; 643 644 default: 645 646 ACPI_ERROR((AE_INFO, "Unknown Register ID: 0x%X", register_id)); 647 status = AE_BAD_PARAMETER; 648 break; 649 } 650 651 if (ACPI_SUCCESS(status)) { 652 *return_value = value; 653 } 654 655 return_ACPI_STATUS(status); 656 } 657 658 /****************************************************************************** 659 * 660 * FUNCTION: acpi_hw_register_write 661 * 662 * PARAMETERS: register_id - ACPI Register ID 663 * value - The value to write 664 * 665 * RETURN: Status 666 * 667 * DESCRIPTION: Write to the specified ACPI register 668 * 669 * NOTE: In accordance with the ACPI specification, this function automatically 670 * preserves the value of the following bits, meaning that these bits cannot be 671 * changed via this interface: 672 * 673 * PM1_CONTROL[0] = SCI_EN 674 * PM1_CONTROL[9] 675 * PM1_STATUS[11] 676 * 677 * ACPI References: 678 * 1) Hardware Ignored Bits: When software writes to a register with ignored 679 * bit fields, it preserves the ignored bit fields 680 * 2) SCI_EN: OSPM always preserves this bit position 681 * 682 ******************************************************************************/ 683 684 acpi_status acpi_hw_register_write(u32 register_id, u32 value) 685 { 686 acpi_status status; 687 u32 read_value; 688 689 ACPI_FUNCTION_TRACE(hw_register_write); 690 691 switch (register_id) { 692 case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */ 693 /* 694 * Handle the "ignored" bit in PM1 Status. According to the ACPI 695 * specification, ignored bits are to be preserved when writing. 696 * Normally, this would mean a read/modify/write sequence. However, 697 * preserving a bit in the status register is different. Writing a 698 * one clears the status, and writing a zero preserves the status. 699 * Therefore, we must always write zero to the ignored bit. 700 * 701 * This behavior is clarified in the ACPI 4.0 specification. 702 */ 703 value &= ~ACPI_PM1_STATUS_PRESERVED_BITS; 704 705 status = acpi_hw_write_multiple(value, 706 &acpi_gbl_xpm1a_status, 707 &acpi_gbl_xpm1b_status); 708 break; 709 710 case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access each */ 711 712 status = acpi_hw_write_multiple(value, 713 &acpi_gbl_xpm1a_enable, 714 &acpi_gbl_xpm1b_enable); 715 break; 716 717 case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */ 718 /* 719 * Perform a read first to preserve certain bits (per ACPI spec) 720 * Note: This includes SCI_EN, we never want to change this bit 721 */ 722 status = acpi_hw_read_multiple(&read_value, 723 &acpi_gbl_FADT. 724 xpm1a_control_block, 725 &acpi_gbl_FADT. 726 xpm1b_control_block); 727 if (ACPI_FAILURE(status)) { 728 goto exit; 729 } 730 731 /* Insert the bits to be preserved */ 732 733 ACPI_INSERT_BITS(value, ACPI_PM1_CONTROL_PRESERVED_BITS, 734 read_value); 735 736 /* Now we can write the data */ 737 738 status = acpi_hw_write_multiple(value, 739 &acpi_gbl_FADT. 740 xpm1a_control_block, 741 &acpi_gbl_FADT. 742 xpm1b_control_block); 743 break; 744 745 case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */ 746 /* 747 * For control registers, all reserved bits must be preserved, 748 * as per the ACPI spec. 749 */ 750 status = 751 acpi_hw_read(&read_value, 752 &acpi_gbl_FADT.xpm2_control_block); 753 if (ACPI_FAILURE(status)) { 754 goto exit; 755 } 756 757 /* Insert the bits to be preserved */ 758 759 ACPI_INSERT_BITS(value, ACPI_PM2_CONTROL_PRESERVED_BITS, 760 read_value); 761 762 status = 763 acpi_hw_write(value, &acpi_gbl_FADT.xpm2_control_block); 764 break; 765 766 case ACPI_REGISTER_PM_TIMER: /* 32-bit access */ 767 768 status = acpi_hw_write(value, &acpi_gbl_FADT.xpm_timer_block); 769 break; 770 771 case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */ 772 773 /* SMI_CMD is currently always in IO space */ 774 775 status = 776 acpi_hw_write_port(acpi_gbl_FADT.smi_command, value, 8); 777 break; 778 779 default: 780 781 ACPI_ERROR((AE_INFO, "Unknown Register ID: 0x%X", register_id)); 782 status = AE_BAD_PARAMETER; 783 break; 784 } 785 786 exit: 787 return_ACPI_STATUS(status); 788 } 789 790 /****************************************************************************** 791 * 792 * FUNCTION: acpi_hw_read_multiple 793 * 794 * PARAMETERS: value - Where the register value is returned 795 * register_a - First ACPI register (required) 796 * register_b - Second ACPI register (optional) 797 * 798 * RETURN: Status 799 * 800 * DESCRIPTION: Read from the specified two-part ACPI register (such as PM1 A/B) 801 * 802 ******************************************************************************/ 803 804 static acpi_status 805 acpi_hw_read_multiple(u32 *value, 806 struct acpi_generic_address *register_a, 807 struct acpi_generic_address *register_b) 808 { 809 u32 value_a = 0; 810 u32 value_b = 0; 811 acpi_status status; 812 813 /* The first register is always required */ 814 815 status = acpi_hw_read(&value_a, register_a); 816 if (ACPI_FAILURE(status)) { 817 return (status); 818 } 819 820 /* Second register is optional */ 821 822 if (register_b->address) { 823 status = acpi_hw_read(&value_b, register_b); 824 if (ACPI_FAILURE(status)) { 825 return (status); 826 } 827 } 828 829 /* 830 * OR the two return values together. No shifting or masking is necessary, 831 * because of how the PM1 registers are defined in the ACPI specification: 832 * 833 * "Although the bits can be split between the two register blocks (each 834 * register block has a unique pointer within the FADT), the bit positions 835 * are maintained. The register block with unimplemented bits (that is, 836 * those implemented in the other register block) always returns zeros, 837 * and writes have no side effects" 838 */ 839 *value = (value_a | value_b); 840 return (AE_OK); 841 } 842 843 /****************************************************************************** 844 * 845 * FUNCTION: acpi_hw_write_multiple 846 * 847 * PARAMETERS: value - The value to write 848 * register_a - First ACPI register (required) 849 * register_b - Second ACPI register (optional) 850 * 851 * RETURN: Status 852 * 853 * DESCRIPTION: Write to the specified two-part ACPI register (such as PM1 A/B) 854 * 855 ******************************************************************************/ 856 857 static acpi_status 858 acpi_hw_write_multiple(u32 value, 859 struct acpi_generic_address *register_a, 860 struct acpi_generic_address *register_b) 861 { 862 acpi_status status; 863 864 /* The first register is always required */ 865 866 status = acpi_hw_write(value, register_a); 867 if (ACPI_FAILURE(status)) { 868 return (status); 869 } 870 871 /* 872 * Second register is optional 873 * 874 * No bit shifting or clearing is necessary, because of how the PM1 875 * registers are defined in the ACPI specification: 876 * 877 * "Although the bits can be split between the two register blocks (each 878 * register block has a unique pointer within the FADT), the bit positions 879 * are maintained. The register block with unimplemented bits (that is, 880 * those implemented in the other register block) always returns zeros, 881 * and writes have no side effects" 882 */ 883 if (register_b->address) { 884 status = acpi_hw_write(value, register_b); 885 } 886 887 return (status); 888 } 889 890 #endif /* !ACPI_REDUCED_HARDWARE */ 891