1 /* 2 * ACPI support for Intel Lynxpoint LPSS. 3 * 4 * Copyright (C) 2013, Intel Corporation 5 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> 6 * Rafael J. Wysocki <rafael.j.wysocki@intel.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/acpi.h> 14 #include <linux/clk.h> 15 #include <linux/clkdev.h> 16 #include <linux/clk-provider.h> 17 #include <linux/err.h> 18 #include <linux/io.h> 19 #include <linux/platform_device.h> 20 #include <linux/platform_data/clk-lpss.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/delay.h> 23 24 #include "internal.h" 25 26 ACPI_MODULE_NAME("acpi_lpss"); 27 28 #ifdef CONFIG_X86_INTEL_LPSS 29 30 #define LPSS_ADDR(desc) ((unsigned long)&desc) 31 32 #define LPSS_CLK_SIZE 0x04 33 #define LPSS_LTR_SIZE 0x18 34 35 /* Offsets relative to LPSS_PRIVATE_OFFSET */ 36 #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16)) 37 #define LPSS_RESETS 0x04 38 #define LPSS_RESETS_RESET_FUNC BIT(0) 39 #define LPSS_RESETS_RESET_APB BIT(1) 40 #define LPSS_GENERAL 0x08 41 #define LPSS_GENERAL_LTR_MODE_SW BIT(2) 42 #define LPSS_GENERAL_UART_RTS_OVRD BIT(3) 43 #define LPSS_SW_LTR 0x10 44 #define LPSS_AUTO_LTR 0x14 45 #define LPSS_LTR_SNOOP_REQ BIT(15) 46 #define LPSS_LTR_SNOOP_MASK 0x0000FFFF 47 #define LPSS_LTR_SNOOP_LAT_1US 0x800 48 #define LPSS_LTR_SNOOP_LAT_32US 0xC00 49 #define LPSS_LTR_SNOOP_LAT_SHIFT 5 50 #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000 51 #define LPSS_LTR_MAX_VAL 0x3FF 52 #define LPSS_TX_INT 0x20 53 #define LPSS_TX_INT_MASK BIT(1) 54 55 #define LPSS_PRV_REG_COUNT 9 56 57 /* LPSS Flags */ 58 #define LPSS_CLK BIT(0) 59 #define LPSS_CLK_GATE BIT(1) 60 #define LPSS_CLK_DIVIDER BIT(2) 61 #define LPSS_LTR BIT(3) 62 #define LPSS_SAVE_CTX BIT(4) 63 64 struct lpss_private_data; 65 66 struct lpss_device_desc { 67 unsigned int flags; 68 const char *clk_con_id; 69 unsigned int prv_offset; 70 size_t prv_size_override; 71 void (*setup)(struct lpss_private_data *pdata); 72 }; 73 74 static struct lpss_device_desc lpss_dma_desc = { 75 .flags = LPSS_CLK, 76 }; 77 78 struct lpss_private_data { 79 void __iomem *mmio_base; 80 resource_size_t mmio_size; 81 unsigned int fixed_clk_rate; 82 struct clk *clk; 83 const struct lpss_device_desc *dev_desc; 84 u32 prv_reg_ctx[LPSS_PRV_REG_COUNT]; 85 }; 86 87 /* UART Component Parameter Register */ 88 #define LPSS_UART_CPR 0xF4 89 #define LPSS_UART_CPR_AFCE BIT(4) 90 91 static void lpss_uart_setup(struct lpss_private_data *pdata) 92 { 93 unsigned int offset; 94 u32 val; 95 96 offset = pdata->dev_desc->prv_offset + LPSS_TX_INT; 97 val = readl(pdata->mmio_base + offset); 98 writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset); 99 100 val = readl(pdata->mmio_base + LPSS_UART_CPR); 101 if (!(val & LPSS_UART_CPR_AFCE)) { 102 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL; 103 val = readl(pdata->mmio_base + offset); 104 val |= LPSS_GENERAL_UART_RTS_OVRD; 105 writel(val, pdata->mmio_base + offset); 106 } 107 } 108 109 static void lpss_deassert_reset(struct lpss_private_data *pdata) 110 { 111 unsigned int offset; 112 u32 val; 113 114 offset = pdata->dev_desc->prv_offset + LPSS_RESETS; 115 val = readl(pdata->mmio_base + offset); 116 val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC; 117 writel(val, pdata->mmio_base + offset); 118 } 119 120 #define LPSS_I2C_ENABLE 0x6c 121 122 static void byt_i2c_setup(struct lpss_private_data *pdata) 123 { 124 lpss_deassert_reset(pdata); 125 126 if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset)) 127 pdata->fixed_clk_rate = 133000000; 128 129 writel(0, pdata->mmio_base + LPSS_I2C_ENABLE); 130 } 131 132 static const struct lpss_device_desc lpt_dev_desc = { 133 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR, 134 .prv_offset = 0x800, 135 }; 136 137 static const struct lpss_device_desc lpt_i2c_dev_desc = { 138 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR, 139 .prv_offset = 0x800, 140 }; 141 142 static const struct lpss_device_desc lpt_uart_dev_desc = { 143 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR, 144 .clk_con_id = "baudclk", 145 .prv_offset = 0x800, 146 .setup = lpss_uart_setup, 147 }; 148 149 static const struct lpss_device_desc lpt_sdio_dev_desc = { 150 .flags = LPSS_LTR, 151 .prv_offset = 0x1000, 152 .prv_size_override = 0x1018, 153 }; 154 155 static const struct lpss_device_desc byt_pwm_dev_desc = { 156 .flags = LPSS_SAVE_CTX, 157 }; 158 159 static const struct lpss_device_desc byt_uart_dev_desc = { 160 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, 161 .clk_con_id = "baudclk", 162 .prv_offset = 0x800, 163 .setup = lpss_uart_setup, 164 }; 165 166 static const struct lpss_device_desc byt_spi_dev_desc = { 167 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, 168 .prv_offset = 0x400, 169 }; 170 171 static const struct lpss_device_desc byt_sdio_dev_desc = { 172 .flags = LPSS_CLK, 173 }; 174 175 static const struct lpss_device_desc byt_i2c_dev_desc = { 176 .flags = LPSS_CLK | LPSS_SAVE_CTX, 177 .prv_offset = 0x800, 178 .setup = byt_i2c_setup, 179 }; 180 181 static struct lpss_device_desc bsw_spi_dev_desc = { 182 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, 183 .prv_offset = 0x400, 184 .setup = lpss_deassert_reset, 185 }; 186 187 #else 188 189 #define LPSS_ADDR(desc) (0UL) 190 191 #endif /* CONFIG_X86_INTEL_LPSS */ 192 193 static const struct acpi_device_id acpi_lpss_device_ids[] = { 194 /* Generic LPSS devices */ 195 { "INTL9C60", LPSS_ADDR(lpss_dma_desc) }, 196 197 /* Lynxpoint LPSS devices */ 198 { "INT33C0", LPSS_ADDR(lpt_dev_desc) }, 199 { "INT33C1", LPSS_ADDR(lpt_dev_desc) }, 200 { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) }, 201 { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) }, 202 { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) }, 203 { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) }, 204 { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) }, 205 { "INT33C7", }, 206 207 /* BayTrail LPSS devices */ 208 { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) }, 209 { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) }, 210 { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) }, 211 { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) }, 212 { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) }, 213 { "INT33B2", }, 214 { "INT33FC", }, 215 216 /* Braswell LPSS devices */ 217 { "80862288", LPSS_ADDR(byt_pwm_dev_desc) }, 218 { "8086228A", LPSS_ADDR(byt_uart_dev_desc) }, 219 { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) }, 220 { "808622C1", LPSS_ADDR(byt_i2c_dev_desc) }, 221 222 { "INT3430", LPSS_ADDR(lpt_dev_desc) }, 223 { "INT3431", LPSS_ADDR(lpt_dev_desc) }, 224 { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) }, 225 { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) }, 226 { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) }, 227 { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) }, 228 { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) }, 229 { "INT3437", }, 230 231 /* Wildcat Point LPSS devices */ 232 { "INT3438", LPSS_ADDR(lpt_dev_desc) }, 233 234 { } 235 }; 236 237 #ifdef CONFIG_X86_INTEL_LPSS 238 239 static int is_memory(struct acpi_resource *res, void *not_used) 240 { 241 struct resource r; 242 return !acpi_dev_resource_memory(res, &r); 243 } 244 245 /* LPSS main clock device. */ 246 static struct platform_device *lpss_clk_dev; 247 248 static inline void lpt_register_clock_device(void) 249 { 250 lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0); 251 } 252 253 static int register_device_clock(struct acpi_device *adev, 254 struct lpss_private_data *pdata) 255 { 256 const struct lpss_device_desc *dev_desc = pdata->dev_desc; 257 const char *devname = dev_name(&adev->dev); 258 struct clk *clk = ERR_PTR(-ENODEV); 259 struct lpss_clk_data *clk_data; 260 const char *parent, *clk_name; 261 void __iomem *prv_base; 262 263 if (!lpss_clk_dev) 264 lpt_register_clock_device(); 265 266 clk_data = platform_get_drvdata(lpss_clk_dev); 267 if (!clk_data) 268 return -ENODEV; 269 clk = clk_data->clk; 270 271 if (!pdata->mmio_base 272 || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE) 273 return -ENODATA; 274 275 parent = clk_data->name; 276 prv_base = pdata->mmio_base + dev_desc->prv_offset; 277 278 if (pdata->fixed_clk_rate) { 279 clk = clk_register_fixed_rate(NULL, devname, parent, 0, 280 pdata->fixed_clk_rate); 281 goto out; 282 } 283 284 if (dev_desc->flags & LPSS_CLK_GATE) { 285 clk = clk_register_gate(NULL, devname, parent, 0, 286 prv_base, 0, 0, NULL); 287 parent = devname; 288 } 289 290 if (dev_desc->flags & LPSS_CLK_DIVIDER) { 291 /* Prevent division by zero */ 292 if (!readl(prv_base)) 293 writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base); 294 295 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname); 296 if (!clk_name) 297 return -ENOMEM; 298 clk = clk_register_fractional_divider(NULL, clk_name, parent, 299 0, prv_base, 300 1, 15, 16, 15, 0, NULL); 301 parent = clk_name; 302 303 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname); 304 if (!clk_name) { 305 kfree(parent); 306 return -ENOMEM; 307 } 308 clk = clk_register_gate(NULL, clk_name, parent, 309 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, 310 prv_base, 31, 0, NULL); 311 kfree(parent); 312 kfree(clk_name); 313 } 314 out: 315 if (IS_ERR(clk)) 316 return PTR_ERR(clk); 317 318 pdata->clk = clk; 319 clk_register_clkdev(clk, dev_desc->clk_con_id, devname); 320 return 0; 321 } 322 323 static int acpi_lpss_create_device(struct acpi_device *adev, 324 const struct acpi_device_id *id) 325 { 326 const struct lpss_device_desc *dev_desc; 327 struct lpss_private_data *pdata; 328 struct resource_entry *rentry; 329 struct list_head resource_list; 330 struct platform_device *pdev; 331 int ret; 332 333 dev_desc = (const struct lpss_device_desc *)id->driver_data; 334 if (!dev_desc) { 335 pdev = acpi_create_platform_device(adev); 336 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1; 337 } 338 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); 339 if (!pdata) 340 return -ENOMEM; 341 342 INIT_LIST_HEAD(&resource_list); 343 ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL); 344 if (ret < 0) 345 goto err_out; 346 347 list_for_each_entry(rentry, &resource_list, node) 348 if (resource_type(rentry->res) == IORESOURCE_MEM) { 349 if (dev_desc->prv_size_override) 350 pdata->mmio_size = dev_desc->prv_size_override; 351 else 352 pdata->mmio_size = resource_size(rentry->res); 353 pdata->mmio_base = ioremap(rentry->res->start, 354 pdata->mmio_size); 355 break; 356 } 357 358 acpi_dev_free_resource_list(&resource_list); 359 360 if (!pdata->mmio_base) { 361 ret = -ENOMEM; 362 goto err_out; 363 } 364 365 pdata->dev_desc = dev_desc; 366 367 if (dev_desc->setup) 368 dev_desc->setup(pdata); 369 370 if (dev_desc->flags & LPSS_CLK) { 371 ret = register_device_clock(adev, pdata); 372 if (ret) { 373 /* Skip the device, but continue the namespace scan. */ 374 ret = 0; 375 goto err_out; 376 } 377 } 378 379 /* 380 * This works around a known issue in ACPI tables where LPSS devices 381 * have _PS0 and _PS3 without _PSC (and no power resources), so 382 * acpi_bus_init_power() will assume that the BIOS has put them into D0. 383 */ 384 ret = acpi_device_fix_up_power(adev); 385 if (ret) { 386 /* Skip the device, but continue the namespace scan. */ 387 ret = 0; 388 goto err_out; 389 } 390 391 adev->driver_data = pdata; 392 pdev = acpi_create_platform_device(adev); 393 if (!IS_ERR_OR_NULL(pdev)) { 394 return 1; 395 } 396 397 ret = PTR_ERR(pdev); 398 adev->driver_data = NULL; 399 400 err_out: 401 kfree(pdata); 402 return ret; 403 } 404 405 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg) 406 { 407 return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg); 408 } 409 410 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata, 411 unsigned int reg) 412 { 413 writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg); 414 } 415 416 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val) 417 { 418 struct acpi_device *adev; 419 struct lpss_private_data *pdata; 420 unsigned long flags; 421 int ret; 422 423 ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev); 424 if (WARN_ON(ret)) 425 return ret; 426 427 spin_lock_irqsave(&dev->power.lock, flags); 428 if (pm_runtime_suspended(dev)) { 429 ret = -EAGAIN; 430 goto out; 431 } 432 pdata = acpi_driver_data(adev); 433 if (WARN_ON(!pdata || !pdata->mmio_base)) { 434 ret = -ENODEV; 435 goto out; 436 } 437 *val = __lpss_reg_read(pdata, reg); 438 439 out: 440 spin_unlock_irqrestore(&dev->power.lock, flags); 441 return ret; 442 } 443 444 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr, 445 char *buf) 446 { 447 u32 ltr_value = 0; 448 unsigned int reg; 449 int ret; 450 451 reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR; 452 ret = lpss_reg_read(dev, reg, <r_value); 453 if (ret) 454 return ret; 455 456 return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value); 457 } 458 459 static ssize_t lpss_ltr_mode_show(struct device *dev, 460 struct device_attribute *attr, char *buf) 461 { 462 u32 ltr_mode = 0; 463 char *outstr; 464 int ret; 465 466 ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode); 467 if (ret) 468 return ret; 469 470 outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto"; 471 return sprintf(buf, "%s\n", outstr); 472 } 473 474 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL); 475 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL); 476 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL); 477 478 static struct attribute *lpss_attrs[] = { 479 &dev_attr_auto_ltr.attr, 480 &dev_attr_sw_ltr.attr, 481 &dev_attr_ltr_mode.attr, 482 NULL, 483 }; 484 485 static struct attribute_group lpss_attr_group = { 486 .attrs = lpss_attrs, 487 .name = "lpss_ltr", 488 }; 489 490 static void acpi_lpss_set_ltr(struct device *dev, s32 val) 491 { 492 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 493 u32 ltr_mode, ltr_val; 494 495 ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL); 496 if (val < 0) { 497 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) { 498 ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW; 499 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); 500 } 501 return; 502 } 503 ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK; 504 if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) { 505 ltr_val |= LPSS_LTR_SNOOP_LAT_32US; 506 val = LPSS_LTR_MAX_VAL; 507 } else if (val > LPSS_LTR_MAX_VAL) { 508 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ; 509 val >>= LPSS_LTR_SNOOP_LAT_SHIFT; 510 } else { 511 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ; 512 } 513 ltr_val |= val; 514 __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR); 515 if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) { 516 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW; 517 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); 518 } 519 } 520 521 #ifdef CONFIG_PM 522 /** 523 * acpi_lpss_save_ctx() - Save the private registers of LPSS device 524 * @dev: LPSS device 525 * @pdata: pointer to the private data of the LPSS device 526 * 527 * Most LPSS devices have private registers which may loose their context when 528 * the device is powered down. acpi_lpss_save_ctx() saves those registers into 529 * prv_reg_ctx array. 530 */ 531 static void acpi_lpss_save_ctx(struct device *dev, 532 struct lpss_private_data *pdata) 533 { 534 unsigned int i; 535 536 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { 537 unsigned long offset = i * sizeof(u32); 538 539 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset); 540 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n", 541 pdata->prv_reg_ctx[i], offset); 542 } 543 } 544 545 /** 546 * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device 547 * @dev: LPSS device 548 * @pdata: pointer to the private data of the LPSS device 549 * 550 * Restores the registers that were previously stored with acpi_lpss_save_ctx(). 551 */ 552 static void acpi_lpss_restore_ctx(struct device *dev, 553 struct lpss_private_data *pdata) 554 { 555 unsigned int i; 556 557 /* 558 * The following delay is needed or the subsequent write operations may 559 * fail. The LPSS devices are actually PCI devices and the PCI spec 560 * expects 10ms delay before the device can be accessed after D3 to D0 561 * transition. 562 */ 563 msleep(10); 564 565 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { 566 unsigned long offset = i * sizeof(u32); 567 568 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset); 569 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n", 570 pdata->prv_reg_ctx[i], offset); 571 } 572 } 573 574 #ifdef CONFIG_PM_SLEEP 575 static int acpi_lpss_suspend_late(struct device *dev) 576 { 577 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 578 int ret; 579 580 ret = pm_generic_suspend_late(dev); 581 if (ret) 582 return ret; 583 584 if (pdata->dev_desc->flags & LPSS_SAVE_CTX) 585 acpi_lpss_save_ctx(dev, pdata); 586 587 return acpi_dev_suspend_late(dev); 588 } 589 590 static int acpi_lpss_resume_early(struct device *dev) 591 { 592 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 593 int ret; 594 595 ret = acpi_dev_resume_early(dev); 596 if (ret) 597 return ret; 598 599 if (pdata->dev_desc->flags & LPSS_SAVE_CTX) 600 acpi_lpss_restore_ctx(dev, pdata); 601 602 return pm_generic_resume_early(dev); 603 } 604 #endif /* CONFIG_PM_SLEEP */ 605 606 static int acpi_lpss_runtime_suspend(struct device *dev) 607 { 608 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 609 int ret; 610 611 ret = pm_generic_runtime_suspend(dev); 612 if (ret) 613 return ret; 614 615 if (pdata->dev_desc->flags & LPSS_SAVE_CTX) 616 acpi_lpss_save_ctx(dev, pdata); 617 618 return acpi_dev_runtime_suspend(dev); 619 } 620 621 static int acpi_lpss_runtime_resume(struct device *dev) 622 { 623 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 624 int ret; 625 626 ret = acpi_dev_runtime_resume(dev); 627 if (ret) 628 return ret; 629 630 if (pdata->dev_desc->flags & LPSS_SAVE_CTX) 631 acpi_lpss_restore_ctx(dev, pdata); 632 633 return pm_generic_runtime_resume(dev); 634 } 635 #endif /* CONFIG_PM */ 636 637 static struct dev_pm_domain acpi_lpss_pm_domain = { 638 .ops = { 639 #ifdef CONFIG_PM 640 #ifdef CONFIG_PM_SLEEP 641 .prepare = acpi_subsys_prepare, 642 .complete = acpi_subsys_complete, 643 .suspend = acpi_subsys_suspend, 644 .suspend_late = acpi_lpss_suspend_late, 645 .resume_early = acpi_lpss_resume_early, 646 .freeze = acpi_subsys_freeze, 647 .poweroff = acpi_subsys_suspend, 648 .poweroff_late = acpi_lpss_suspend_late, 649 .restore_early = acpi_lpss_resume_early, 650 #endif 651 .runtime_suspend = acpi_lpss_runtime_suspend, 652 .runtime_resume = acpi_lpss_runtime_resume, 653 #endif 654 }, 655 }; 656 657 static int acpi_lpss_platform_notify(struct notifier_block *nb, 658 unsigned long action, void *data) 659 { 660 struct platform_device *pdev = to_platform_device(data); 661 struct lpss_private_data *pdata; 662 struct acpi_device *adev; 663 const struct acpi_device_id *id; 664 665 id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev); 666 if (!id || !id->driver_data) 667 return 0; 668 669 if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) 670 return 0; 671 672 pdata = acpi_driver_data(adev); 673 if (!pdata) 674 return 0; 675 676 if (pdata->mmio_base && 677 pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) { 678 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n"); 679 return 0; 680 } 681 682 switch (action) { 683 case BUS_NOTIFY_ADD_DEVICE: 684 pdev->dev.pm_domain = &acpi_lpss_pm_domain; 685 if (pdata->dev_desc->flags & LPSS_LTR) 686 return sysfs_create_group(&pdev->dev.kobj, 687 &lpss_attr_group); 688 break; 689 case BUS_NOTIFY_DEL_DEVICE: 690 if (pdata->dev_desc->flags & LPSS_LTR) 691 sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group); 692 pdev->dev.pm_domain = NULL; 693 break; 694 default: 695 break; 696 } 697 698 return 0; 699 } 700 701 static struct notifier_block acpi_lpss_nb = { 702 .notifier_call = acpi_lpss_platform_notify, 703 }; 704 705 static void acpi_lpss_bind(struct device *dev) 706 { 707 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 708 709 if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR)) 710 return; 711 712 if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) 713 dev->power.set_latency_tolerance = acpi_lpss_set_ltr; 714 else 715 dev_err(dev, "MMIO size insufficient to access LTR\n"); 716 } 717 718 static void acpi_lpss_unbind(struct device *dev) 719 { 720 dev->power.set_latency_tolerance = NULL; 721 } 722 723 static struct acpi_scan_handler lpss_handler = { 724 .ids = acpi_lpss_device_ids, 725 .attach = acpi_lpss_create_device, 726 .bind = acpi_lpss_bind, 727 .unbind = acpi_lpss_unbind, 728 }; 729 730 void __init acpi_lpss_init(void) 731 { 732 if (!lpt_clk_init()) { 733 bus_register_notifier(&platform_bus_type, &acpi_lpss_nb); 734 acpi_scan_add_handler(&lpss_handler); 735 } 736 } 737 738 #else 739 740 static struct acpi_scan_handler lpss_handler = { 741 .ids = acpi_lpss_device_ids, 742 }; 743 744 void __init acpi_lpss_init(void) 745 { 746 acpi_scan_add_handler(&lpss_handler); 747 } 748 749 #endif /* CONFIG_X86_INTEL_LPSS */ 750