1 /* 2 * ACPI support for Intel Lynxpoint LPSS. 3 * 4 * Copyright (C) 2013, Intel Corporation 5 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> 6 * Rafael J. Wysocki <rafael.j.wysocki@intel.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/acpi.h> 14 #include <linux/clk.h> 15 #include <linux/clkdev.h> 16 #include <linux/clk-provider.h> 17 #include <linux/err.h> 18 #include <linux/io.h> 19 #include <linux/platform_device.h> 20 #include <linux/platform_data/clk-lpss.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/delay.h> 23 24 #include "internal.h" 25 26 ACPI_MODULE_NAME("acpi_lpss"); 27 28 #ifdef CONFIG_X86_INTEL_LPSS 29 30 #define LPSS_ADDR(desc) ((unsigned long)&desc) 31 32 #define LPSS_CLK_SIZE 0x04 33 #define LPSS_LTR_SIZE 0x18 34 35 /* Offsets relative to LPSS_PRIVATE_OFFSET */ 36 #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16)) 37 #define LPSS_RESETS 0x04 38 #define LPSS_RESETS_RESET_FUNC BIT(0) 39 #define LPSS_RESETS_RESET_APB BIT(1) 40 #define LPSS_GENERAL 0x08 41 #define LPSS_GENERAL_LTR_MODE_SW BIT(2) 42 #define LPSS_GENERAL_UART_RTS_OVRD BIT(3) 43 #define LPSS_SW_LTR 0x10 44 #define LPSS_AUTO_LTR 0x14 45 #define LPSS_LTR_SNOOP_REQ BIT(15) 46 #define LPSS_LTR_SNOOP_MASK 0x0000FFFF 47 #define LPSS_LTR_SNOOP_LAT_1US 0x800 48 #define LPSS_LTR_SNOOP_LAT_32US 0xC00 49 #define LPSS_LTR_SNOOP_LAT_SHIFT 5 50 #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000 51 #define LPSS_LTR_MAX_VAL 0x3FF 52 #define LPSS_TX_INT 0x20 53 #define LPSS_TX_INT_MASK BIT(1) 54 55 #define LPSS_PRV_REG_COUNT 9 56 57 struct lpss_shared_clock { 58 const char *name; 59 unsigned long rate; 60 struct clk *clk; 61 }; 62 63 struct lpss_private_data; 64 65 struct lpss_device_desc { 66 bool clk_required; 67 const char *clkdev_name; 68 bool ltr_required; 69 unsigned int prv_offset; 70 size_t prv_size_override; 71 bool clk_divider; 72 bool clk_gate; 73 bool save_ctx; 74 struct lpss_shared_clock *shared_clock; 75 void (*setup)(struct lpss_private_data *pdata); 76 }; 77 78 static struct lpss_device_desc lpss_dma_desc = { 79 .clk_required = true, 80 .clkdev_name = "hclk", 81 }; 82 83 struct lpss_private_data { 84 void __iomem *mmio_base; 85 resource_size_t mmio_size; 86 struct clk *clk; 87 const struct lpss_device_desc *dev_desc; 88 u32 prv_reg_ctx[LPSS_PRV_REG_COUNT]; 89 }; 90 91 static void lpss_uart_setup(struct lpss_private_data *pdata) 92 { 93 unsigned int offset; 94 u32 reg; 95 96 offset = pdata->dev_desc->prv_offset + LPSS_TX_INT; 97 reg = readl(pdata->mmio_base + offset); 98 writel(reg | LPSS_TX_INT_MASK, pdata->mmio_base + offset); 99 100 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL; 101 reg = readl(pdata->mmio_base + offset); 102 writel(reg | LPSS_GENERAL_UART_RTS_OVRD, pdata->mmio_base + offset); 103 } 104 105 static void lpss_i2c_setup(struct lpss_private_data *pdata) 106 { 107 unsigned int offset; 108 u32 val; 109 110 offset = pdata->dev_desc->prv_offset + LPSS_RESETS; 111 val = readl(pdata->mmio_base + offset); 112 val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC; 113 writel(val, pdata->mmio_base + offset); 114 } 115 116 static struct lpss_device_desc lpt_dev_desc = { 117 .clk_required = true, 118 .prv_offset = 0x800, 119 .ltr_required = true, 120 .clk_divider = true, 121 .clk_gate = true, 122 }; 123 124 static struct lpss_device_desc lpt_i2c_dev_desc = { 125 .clk_required = true, 126 .prv_offset = 0x800, 127 .ltr_required = true, 128 .clk_gate = true, 129 }; 130 131 static struct lpss_device_desc lpt_uart_dev_desc = { 132 .clk_required = true, 133 .prv_offset = 0x800, 134 .ltr_required = true, 135 .clk_divider = true, 136 .clk_gate = true, 137 .setup = lpss_uart_setup, 138 }; 139 140 static struct lpss_device_desc lpt_sdio_dev_desc = { 141 .prv_offset = 0x1000, 142 .prv_size_override = 0x1018, 143 .ltr_required = true, 144 }; 145 146 static struct lpss_shared_clock pwm_clock = { 147 .name = "pwm_clk", 148 .rate = 25000000, 149 }; 150 151 static struct lpss_device_desc byt_pwm_dev_desc = { 152 .clk_required = true, 153 .save_ctx = true, 154 .shared_clock = &pwm_clock, 155 }; 156 157 static struct lpss_device_desc byt_uart_dev_desc = { 158 .clk_required = true, 159 .prv_offset = 0x800, 160 .clk_divider = true, 161 .clk_gate = true, 162 .save_ctx = true, 163 .setup = lpss_uart_setup, 164 }; 165 166 static struct lpss_device_desc byt_spi_dev_desc = { 167 .clk_required = true, 168 .prv_offset = 0x400, 169 .clk_divider = true, 170 .clk_gate = true, 171 .save_ctx = true, 172 }; 173 174 static struct lpss_device_desc byt_sdio_dev_desc = { 175 .clk_required = true, 176 }; 177 178 static struct lpss_shared_clock i2c_clock = { 179 .name = "i2c_clk", 180 .rate = 100000000, 181 }; 182 183 static struct lpss_device_desc byt_i2c_dev_desc = { 184 .clk_required = true, 185 .prv_offset = 0x800, 186 .save_ctx = true, 187 .shared_clock = &i2c_clock, 188 .setup = lpss_i2c_setup, 189 }; 190 191 #else 192 193 #define LPSS_ADDR(desc) (0UL) 194 195 #endif /* CONFIG_X86_INTEL_LPSS */ 196 197 static const struct acpi_device_id acpi_lpss_device_ids[] = { 198 /* Generic LPSS devices */ 199 { "INTL9C60", LPSS_ADDR(lpss_dma_desc) }, 200 201 /* Lynxpoint LPSS devices */ 202 { "INT33C0", LPSS_ADDR(lpt_dev_desc) }, 203 { "INT33C1", LPSS_ADDR(lpt_dev_desc) }, 204 { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) }, 205 { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) }, 206 { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) }, 207 { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) }, 208 { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) }, 209 { "INT33C7", }, 210 211 /* BayTrail LPSS devices */ 212 { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) }, 213 { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) }, 214 { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) }, 215 { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) }, 216 { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) }, 217 { "INT33B2", }, 218 { "INT33FC", }, 219 220 { "INT3430", LPSS_ADDR(lpt_dev_desc) }, 221 { "INT3431", LPSS_ADDR(lpt_dev_desc) }, 222 { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) }, 223 { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) }, 224 { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) }, 225 { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) }, 226 { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) }, 227 { "INT3437", }, 228 229 { } 230 }; 231 232 #ifdef CONFIG_X86_INTEL_LPSS 233 234 static int is_memory(struct acpi_resource *res, void *not_used) 235 { 236 struct resource r; 237 return !acpi_dev_resource_memory(res, &r); 238 } 239 240 /* LPSS main clock device. */ 241 static struct platform_device *lpss_clk_dev; 242 243 static inline void lpt_register_clock_device(void) 244 { 245 lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0); 246 } 247 248 static int register_device_clock(struct acpi_device *adev, 249 struct lpss_private_data *pdata) 250 { 251 const struct lpss_device_desc *dev_desc = pdata->dev_desc; 252 struct lpss_shared_clock *shared_clock = dev_desc->shared_clock; 253 const char *devname = dev_name(&adev->dev); 254 struct clk *clk = ERR_PTR(-ENODEV); 255 struct lpss_clk_data *clk_data; 256 const char *parent, *clk_name; 257 void __iomem *prv_base; 258 259 if (!lpss_clk_dev) 260 lpt_register_clock_device(); 261 262 clk_data = platform_get_drvdata(lpss_clk_dev); 263 if (!clk_data) 264 return -ENODEV; 265 266 if (dev_desc->clkdev_name) { 267 clk_register_clkdev(clk_data->clk, dev_desc->clkdev_name, 268 devname); 269 return 0; 270 } 271 272 if (!pdata->mmio_base 273 || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE) 274 return -ENODATA; 275 276 parent = clk_data->name; 277 prv_base = pdata->mmio_base + dev_desc->prv_offset; 278 279 if (shared_clock) { 280 clk = shared_clock->clk; 281 if (!clk) { 282 clk = clk_register_fixed_rate(NULL, shared_clock->name, 283 "lpss_clk", 0, 284 shared_clock->rate); 285 shared_clock->clk = clk; 286 } 287 parent = shared_clock->name; 288 } 289 290 if (dev_desc->clk_gate) { 291 clk = clk_register_gate(NULL, devname, parent, 0, 292 prv_base, 0, 0, NULL); 293 parent = devname; 294 } 295 296 if (dev_desc->clk_divider) { 297 /* Prevent division by zero */ 298 if (!readl(prv_base)) 299 writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base); 300 301 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname); 302 if (!clk_name) 303 return -ENOMEM; 304 clk = clk_register_fractional_divider(NULL, clk_name, parent, 305 0, prv_base, 306 1, 15, 16, 15, 0, NULL); 307 parent = clk_name; 308 309 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname); 310 if (!clk_name) { 311 kfree(parent); 312 return -ENOMEM; 313 } 314 clk = clk_register_gate(NULL, clk_name, parent, 315 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, 316 prv_base, 31, 0, NULL); 317 kfree(parent); 318 kfree(clk_name); 319 } 320 321 if (IS_ERR(clk)) 322 return PTR_ERR(clk); 323 324 pdata->clk = clk; 325 clk_register_clkdev(clk, NULL, devname); 326 return 0; 327 } 328 329 static int acpi_lpss_create_device(struct acpi_device *adev, 330 const struct acpi_device_id *id) 331 { 332 struct lpss_device_desc *dev_desc; 333 struct lpss_private_data *pdata; 334 struct resource_list_entry *rentry; 335 struct list_head resource_list; 336 struct platform_device *pdev; 337 int ret; 338 339 dev_desc = (struct lpss_device_desc *)id->driver_data; 340 if (!dev_desc) { 341 pdev = acpi_create_platform_device(adev); 342 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1; 343 } 344 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); 345 if (!pdata) 346 return -ENOMEM; 347 348 INIT_LIST_HEAD(&resource_list); 349 ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL); 350 if (ret < 0) 351 goto err_out; 352 353 list_for_each_entry(rentry, &resource_list, node) 354 if (resource_type(&rentry->res) == IORESOURCE_MEM) { 355 if (dev_desc->prv_size_override) 356 pdata->mmio_size = dev_desc->prv_size_override; 357 else 358 pdata->mmio_size = resource_size(&rentry->res); 359 pdata->mmio_base = ioremap(rentry->res.start, 360 pdata->mmio_size); 361 break; 362 } 363 364 acpi_dev_free_resource_list(&resource_list); 365 366 pdata->dev_desc = dev_desc; 367 368 if (dev_desc->clk_required) { 369 ret = register_device_clock(adev, pdata); 370 if (ret) { 371 /* Skip the device, but continue the namespace scan. */ 372 ret = 0; 373 goto err_out; 374 } 375 } 376 377 /* 378 * This works around a known issue in ACPI tables where LPSS devices 379 * have _PS0 and _PS3 without _PSC (and no power resources), so 380 * acpi_bus_init_power() will assume that the BIOS has put them into D0. 381 */ 382 ret = acpi_device_fix_up_power(adev); 383 if (ret) { 384 /* Skip the device, but continue the namespace scan. */ 385 ret = 0; 386 goto err_out; 387 } 388 389 if (dev_desc->setup) 390 dev_desc->setup(pdata); 391 392 adev->driver_data = pdata; 393 pdev = acpi_create_platform_device(adev); 394 if (!IS_ERR_OR_NULL(pdev)) { 395 device_enable_async_suspend(&pdev->dev); 396 return 1; 397 } 398 399 ret = PTR_ERR(pdev); 400 adev->driver_data = NULL; 401 402 err_out: 403 kfree(pdata); 404 return ret; 405 } 406 407 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg) 408 { 409 return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg); 410 } 411 412 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata, 413 unsigned int reg) 414 { 415 writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg); 416 } 417 418 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val) 419 { 420 struct acpi_device *adev; 421 struct lpss_private_data *pdata; 422 unsigned long flags; 423 int ret; 424 425 ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev); 426 if (WARN_ON(ret)) 427 return ret; 428 429 spin_lock_irqsave(&dev->power.lock, flags); 430 if (pm_runtime_suspended(dev)) { 431 ret = -EAGAIN; 432 goto out; 433 } 434 pdata = acpi_driver_data(adev); 435 if (WARN_ON(!pdata || !pdata->mmio_base)) { 436 ret = -ENODEV; 437 goto out; 438 } 439 *val = __lpss_reg_read(pdata, reg); 440 441 out: 442 spin_unlock_irqrestore(&dev->power.lock, flags); 443 return ret; 444 } 445 446 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr, 447 char *buf) 448 { 449 u32 ltr_value = 0; 450 unsigned int reg; 451 int ret; 452 453 reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR; 454 ret = lpss_reg_read(dev, reg, <r_value); 455 if (ret) 456 return ret; 457 458 return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value); 459 } 460 461 static ssize_t lpss_ltr_mode_show(struct device *dev, 462 struct device_attribute *attr, char *buf) 463 { 464 u32 ltr_mode = 0; 465 char *outstr; 466 int ret; 467 468 ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode); 469 if (ret) 470 return ret; 471 472 outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto"; 473 return sprintf(buf, "%s\n", outstr); 474 } 475 476 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL); 477 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL); 478 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL); 479 480 static struct attribute *lpss_attrs[] = { 481 &dev_attr_auto_ltr.attr, 482 &dev_attr_sw_ltr.attr, 483 &dev_attr_ltr_mode.attr, 484 NULL, 485 }; 486 487 static struct attribute_group lpss_attr_group = { 488 .attrs = lpss_attrs, 489 .name = "lpss_ltr", 490 }; 491 492 static void acpi_lpss_set_ltr(struct device *dev, s32 val) 493 { 494 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 495 u32 ltr_mode, ltr_val; 496 497 ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL); 498 if (val < 0) { 499 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) { 500 ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW; 501 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); 502 } 503 return; 504 } 505 ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK; 506 if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) { 507 ltr_val |= LPSS_LTR_SNOOP_LAT_32US; 508 val = LPSS_LTR_MAX_VAL; 509 } else if (val > LPSS_LTR_MAX_VAL) { 510 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ; 511 val >>= LPSS_LTR_SNOOP_LAT_SHIFT; 512 } else { 513 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ; 514 } 515 ltr_val |= val; 516 __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR); 517 if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) { 518 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW; 519 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); 520 } 521 } 522 523 #ifdef CONFIG_PM 524 /** 525 * acpi_lpss_save_ctx() - Save the private registers of LPSS device 526 * @dev: LPSS device 527 * 528 * Most LPSS devices have private registers which may loose their context when 529 * the device is powered down. acpi_lpss_save_ctx() saves those registers into 530 * prv_reg_ctx array. 531 */ 532 static void acpi_lpss_save_ctx(struct device *dev) 533 { 534 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 535 unsigned int i; 536 537 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { 538 unsigned long offset = i * sizeof(u32); 539 540 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset); 541 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n", 542 pdata->prv_reg_ctx[i], offset); 543 } 544 } 545 546 /** 547 * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device 548 * @dev: LPSS device 549 * 550 * Restores the registers that were previously stored with acpi_lpss_save_ctx(). 551 */ 552 static void acpi_lpss_restore_ctx(struct device *dev) 553 { 554 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 555 unsigned int i; 556 557 /* 558 * The following delay is needed or the subsequent write operations may 559 * fail. The LPSS devices are actually PCI devices and the PCI spec 560 * expects 10ms delay before the device can be accessed after D3 to D0 561 * transition. 562 */ 563 msleep(10); 564 565 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { 566 unsigned long offset = i * sizeof(u32); 567 568 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset); 569 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n", 570 pdata->prv_reg_ctx[i], offset); 571 } 572 } 573 574 #ifdef CONFIG_PM_SLEEP 575 static int acpi_lpss_suspend_late(struct device *dev) 576 { 577 int ret = pm_generic_suspend_late(dev); 578 579 if (ret) 580 return ret; 581 582 acpi_lpss_save_ctx(dev); 583 return acpi_dev_suspend_late(dev); 584 } 585 586 static int acpi_lpss_restore_early(struct device *dev) 587 { 588 int ret = acpi_dev_resume_early(dev); 589 590 if (ret) 591 return ret; 592 593 acpi_lpss_restore_ctx(dev); 594 return pm_generic_resume_early(dev); 595 } 596 #endif /* CONFIG_PM_SLEEP */ 597 598 #ifdef CONFIG_PM_RUNTIME 599 static int acpi_lpss_runtime_suspend(struct device *dev) 600 { 601 int ret = pm_generic_runtime_suspend(dev); 602 603 if (ret) 604 return ret; 605 606 acpi_lpss_save_ctx(dev); 607 return acpi_dev_runtime_suspend(dev); 608 } 609 610 static int acpi_lpss_runtime_resume(struct device *dev) 611 { 612 int ret = acpi_dev_runtime_resume(dev); 613 614 if (ret) 615 return ret; 616 617 acpi_lpss_restore_ctx(dev); 618 return pm_generic_runtime_resume(dev); 619 } 620 #endif /* CONFIG_PM_RUNTIME */ 621 #endif /* CONFIG_PM */ 622 623 static struct dev_pm_domain acpi_lpss_pm_domain = { 624 .ops = { 625 #ifdef CONFIG_PM_SLEEP 626 .suspend_late = acpi_lpss_suspend_late, 627 .restore_early = acpi_lpss_restore_early, 628 .prepare = acpi_subsys_prepare, 629 .complete = acpi_subsys_complete, 630 .suspend = acpi_subsys_suspend, 631 .resume_early = acpi_subsys_resume_early, 632 .freeze = acpi_subsys_freeze, 633 .poweroff = acpi_subsys_suspend, 634 .poweroff_late = acpi_subsys_suspend_late, 635 #endif 636 #ifdef CONFIG_PM_RUNTIME 637 .runtime_suspend = acpi_lpss_runtime_suspend, 638 .runtime_resume = acpi_lpss_runtime_resume, 639 #endif 640 }, 641 }; 642 643 static int acpi_lpss_platform_notify(struct notifier_block *nb, 644 unsigned long action, void *data) 645 { 646 struct platform_device *pdev = to_platform_device(data); 647 struct lpss_private_data *pdata; 648 struct acpi_device *adev; 649 const struct acpi_device_id *id; 650 651 id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev); 652 if (!id || !id->driver_data) 653 return 0; 654 655 if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) 656 return 0; 657 658 pdata = acpi_driver_data(adev); 659 if (!pdata || !pdata->mmio_base) 660 return 0; 661 662 if (pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) { 663 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n"); 664 return 0; 665 } 666 667 switch (action) { 668 case BUS_NOTIFY_BOUND_DRIVER: 669 if (pdata->dev_desc->save_ctx) 670 pdev->dev.pm_domain = &acpi_lpss_pm_domain; 671 break; 672 case BUS_NOTIFY_UNBOUND_DRIVER: 673 if (pdata->dev_desc->save_ctx) 674 pdev->dev.pm_domain = NULL; 675 break; 676 case BUS_NOTIFY_ADD_DEVICE: 677 if (pdata->dev_desc->ltr_required) 678 return sysfs_create_group(&pdev->dev.kobj, 679 &lpss_attr_group); 680 case BUS_NOTIFY_DEL_DEVICE: 681 if (pdata->dev_desc->ltr_required) 682 sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group); 683 default: 684 break; 685 } 686 687 return 0; 688 } 689 690 static struct notifier_block acpi_lpss_nb = { 691 .notifier_call = acpi_lpss_platform_notify, 692 }; 693 694 static void acpi_lpss_bind(struct device *dev) 695 { 696 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 697 698 if (!pdata || !pdata->mmio_base || !pdata->dev_desc->ltr_required) 699 return; 700 701 if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) 702 dev->power.set_latency_tolerance = acpi_lpss_set_ltr; 703 else 704 dev_err(dev, "MMIO size insufficient to access LTR\n"); 705 } 706 707 static void acpi_lpss_unbind(struct device *dev) 708 { 709 dev->power.set_latency_tolerance = NULL; 710 } 711 712 static struct acpi_scan_handler lpss_handler = { 713 .ids = acpi_lpss_device_ids, 714 .attach = acpi_lpss_create_device, 715 .bind = acpi_lpss_bind, 716 .unbind = acpi_lpss_unbind, 717 }; 718 719 void __init acpi_lpss_init(void) 720 { 721 if (!lpt_clk_init()) { 722 bus_register_notifier(&platform_bus_type, &acpi_lpss_nb); 723 acpi_scan_add_handler(&lpss_handler); 724 } 725 } 726 727 #else 728 729 static struct acpi_scan_handler lpss_handler = { 730 .ids = acpi_lpss_device_ids, 731 }; 732 733 void __init acpi_lpss_init(void) 734 { 735 acpi_scan_add_handler(&lpss_handler); 736 } 737 738 #endif /* CONFIG_X86_INTEL_LPSS */ 739