1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ACPI support for Intel Lynxpoint LPSS. 4 * 5 * Copyright (C) 2013, Intel Corporation 6 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> 7 * Rafael J. Wysocki <rafael.j.wysocki@intel.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/clkdev.h> 12 #include <linux/clk-provider.h> 13 #include <linux/dmi.h> 14 #include <linux/err.h> 15 #include <linux/io.h> 16 #include <linux/mutex.h> 17 #include <linux/pci.h> 18 #include <linux/platform_device.h> 19 #include <linux/platform_data/x86/clk-lpss.h> 20 #include <linux/platform_data/x86/pmc_atom.h> 21 #include <linux/pm_domain.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/pwm.h> 24 #include <linux/pxa2xx_ssp.h> 25 #include <linux/suspend.h> 26 #include <linux/delay.h> 27 28 #include "internal.h" 29 30 #ifdef CONFIG_X86_INTEL_LPSS 31 32 #include <asm/cpu_device_id.h> 33 #include <asm/intel-family.h> 34 #include <asm/iosf_mbi.h> 35 36 #define LPSS_ADDR(desc) ((unsigned long)&desc) 37 38 #define LPSS_CLK_SIZE 0x04 39 #define LPSS_LTR_SIZE 0x18 40 41 /* Offsets relative to LPSS_PRIVATE_OFFSET */ 42 #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16)) 43 #define LPSS_RESETS 0x04 44 #define LPSS_RESETS_RESET_FUNC BIT(0) 45 #define LPSS_RESETS_RESET_APB BIT(1) 46 #define LPSS_GENERAL 0x08 47 #define LPSS_GENERAL_LTR_MODE_SW BIT(2) 48 #define LPSS_GENERAL_UART_RTS_OVRD BIT(3) 49 #define LPSS_SW_LTR 0x10 50 #define LPSS_AUTO_LTR 0x14 51 #define LPSS_LTR_SNOOP_REQ BIT(15) 52 #define LPSS_LTR_SNOOP_MASK 0x0000FFFF 53 #define LPSS_LTR_SNOOP_LAT_1US 0x800 54 #define LPSS_LTR_SNOOP_LAT_32US 0xC00 55 #define LPSS_LTR_SNOOP_LAT_SHIFT 5 56 #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000 57 #define LPSS_LTR_MAX_VAL 0x3FF 58 #define LPSS_TX_INT 0x20 59 #define LPSS_TX_INT_MASK BIT(1) 60 61 #define LPSS_PRV_REG_COUNT 9 62 63 /* LPSS Flags */ 64 #define LPSS_CLK BIT(0) 65 #define LPSS_CLK_GATE BIT(1) 66 #define LPSS_CLK_DIVIDER BIT(2) 67 #define LPSS_LTR BIT(3) 68 #define LPSS_SAVE_CTX BIT(4) 69 /* 70 * For some devices the DSDT AML code for another device turns off the device 71 * before our suspend handler runs, causing us to read/save all 1-s (0xffffffff) 72 * as ctx register values. 73 * Luckily these devices always use the same ctx register values, so we can 74 * work around this by saving the ctx registers once on activation. 75 */ 76 #define LPSS_SAVE_CTX_ONCE BIT(5) 77 #define LPSS_NO_D3_DELAY BIT(6) 78 79 struct lpss_private_data; 80 81 struct lpss_device_desc { 82 unsigned int flags; 83 const char *clk_con_id; 84 unsigned int prv_offset; 85 size_t prv_size_override; 86 const struct property_entry *properties; 87 void (*setup)(struct lpss_private_data *pdata); 88 bool resume_from_noirq; 89 }; 90 91 static const struct lpss_device_desc lpss_dma_desc = { 92 .flags = LPSS_CLK, 93 }; 94 95 struct lpss_private_data { 96 struct acpi_device *adev; 97 void __iomem *mmio_base; 98 resource_size_t mmio_size; 99 unsigned int fixed_clk_rate; 100 struct clk *clk; 101 const struct lpss_device_desc *dev_desc; 102 u32 prv_reg_ctx[LPSS_PRV_REG_COUNT]; 103 }; 104 105 /* Devices which need to be in D3 before lpss_iosf_enter_d3_state() proceeds */ 106 static u32 pmc_atom_d3_mask = 0xfe000ffe; 107 108 /* LPSS run time quirks */ 109 static unsigned int lpss_quirks; 110 111 /* 112 * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device. 113 * 114 * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover 115 * it can be powered off automatically whenever the last LPSS device goes down. 116 * In case of no power any access to the DMA controller will hang the system. 117 * The behaviour is reproduced on some HP laptops based on Intel BayTrail as 118 * well as on ASuS T100TA transformer. 119 * 120 * This quirk overrides power state of entire LPSS island to keep DMA powered 121 * on whenever we have at least one other device in use. 122 */ 123 #define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0) 124 125 /* UART Component Parameter Register */ 126 #define LPSS_UART_CPR 0xF4 127 #define LPSS_UART_CPR_AFCE BIT(4) 128 129 static void lpss_uart_setup(struct lpss_private_data *pdata) 130 { 131 unsigned int offset; 132 u32 val; 133 134 offset = pdata->dev_desc->prv_offset + LPSS_TX_INT; 135 val = readl(pdata->mmio_base + offset); 136 writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset); 137 138 val = readl(pdata->mmio_base + LPSS_UART_CPR); 139 if (!(val & LPSS_UART_CPR_AFCE)) { 140 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL; 141 val = readl(pdata->mmio_base + offset); 142 val |= LPSS_GENERAL_UART_RTS_OVRD; 143 writel(val, pdata->mmio_base + offset); 144 } 145 } 146 147 static void lpss_deassert_reset(struct lpss_private_data *pdata) 148 { 149 unsigned int offset; 150 u32 val; 151 152 offset = pdata->dev_desc->prv_offset + LPSS_RESETS; 153 val = readl(pdata->mmio_base + offset); 154 val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC; 155 writel(val, pdata->mmio_base + offset); 156 } 157 158 /* 159 * BYT PWM used for backlight control by the i915 driver on systems without 160 * the Crystal Cove PMIC. 161 */ 162 static struct pwm_lookup byt_pwm_lookup[] = { 163 PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0", 164 "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL, 165 "pwm-lpss-platform"), 166 }; 167 168 static void byt_pwm_setup(struct lpss_private_data *pdata) 169 { 170 struct acpi_device *adev = pdata->adev; 171 172 /* Only call pwm_add_table for the first PWM controller */ 173 if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1")) 174 return; 175 176 pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup)); 177 } 178 179 #define LPSS_I2C_ENABLE 0x6c 180 181 static void byt_i2c_setup(struct lpss_private_data *pdata) 182 { 183 const char *uid_str = acpi_device_uid(pdata->adev); 184 acpi_handle handle = pdata->adev->handle; 185 unsigned long long shared_host = 0; 186 acpi_status status; 187 long uid = 0; 188 189 /* Expected to always be true, but better safe then sorry */ 190 if (uid_str && !kstrtol(uid_str, 10, &uid) && uid) { 191 /* Detect I2C bus shared with PUNIT and ignore its d3 status */ 192 status = acpi_evaluate_integer(handle, "_SEM", NULL, &shared_host); 193 if (ACPI_SUCCESS(status) && shared_host) 194 pmc_atom_d3_mask &= ~(BIT_LPSS2_F1_I2C1 << (uid - 1)); 195 } 196 197 lpss_deassert_reset(pdata); 198 199 if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset)) 200 pdata->fixed_clk_rate = 133000000; 201 202 writel(0, pdata->mmio_base + LPSS_I2C_ENABLE); 203 } 204 205 /* BSW PWM used for backlight control by the i915 driver */ 206 static struct pwm_lookup bsw_pwm_lookup[] = { 207 PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0", 208 "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL, 209 "pwm-lpss-platform"), 210 }; 211 212 static void bsw_pwm_setup(struct lpss_private_data *pdata) 213 { 214 struct acpi_device *adev = pdata->adev; 215 216 /* Only call pwm_add_table for the first PWM controller */ 217 if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1")) 218 return; 219 220 pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup)); 221 } 222 223 static const struct property_entry lpt_spi_properties[] = { 224 PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_LPT_SSP), 225 { } 226 }; 227 228 static const struct lpss_device_desc lpt_spi_dev_desc = { 229 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR 230 | LPSS_SAVE_CTX, 231 .prv_offset = 0x800, 232 .properties = lpt_spi_properties, 233 }; 234 235 static const struct lpss_device_desc lpt_i2c_dev_desc = { 236 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR | LPSS_SAVE_CTX, 237 .prv_offset = 0x800, 238 }; 239 240 static struct property_entry uart_properties[] = { 241 PROPERTY_ENTRY_U32("reg-io-width", 4), 242 PROPERTY_ENTRY_U32("reg-shift", 2), 243 PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"), 244 { }, 245 }; 246 247 static const struct lpss_device_desc lpt_uart_dev_desc = { 248 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR 249 | LPSS_SAVE_CTX, 250 .clk_con_id = "baudclk", 251 .prv_offset = 0x800, 252 .setup = lpss_uart_setup, 253 .properties = uart_properties, 254 }; 255 256 static const struct lpss_device_desc lpt_sdio_dev_desc = { 257 .flags = LPSS_LTR, 258 .prv_offset = 0x1000, 259 .prv_size_override = 0x1018, 260 }; 261 262 static const struct lpss_device_desc byt_pwm_dev_desc = { 263 .flags = LPSS_SAVE_CTX, 264 .prv_offset = 0x800, 265 .setup = byt_pwm_setup, 266 }; 267 268 static const struct lpss_device_desc bsw_pwm_dev_desc = { 269 .flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY, 270 .prv_offset = 0x800, 271 .setup = bsw_pwm_setup, 272 .resume_from_noirq = true, 273 }; 274 275 static const struct lpss_device_desc byt_uart_dev_desc = { 276 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, 277 .clk_con_id = "baudclk", 278 .prv_offset = 0x800, 279 .setup = lpss_uart_setup, 280 .properties = uart_properties, 281 }; 282 283 static const struct lpss_device_desc bsw_uart_dev_desc = { 284 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX 285 | LPSS_NO_D3_DELAY, 286 .clk_con_id = "baudclk", 287 .prv_offset = 0x800, 288 .setup = lpss_uart_setup, 289 .properties = uart_properties, 290 }; 291 292 static const struct property_entry byt_spi_properties[] = { 293 PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_BYT_SSP), 294 { } 295 }; 296 297 static const struct lpss_device_desc byt_spi_dev_desc = { 298 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, 299 .prv_offset = 0x400, 300 .properties = byt_spi_properties, 301 }; 302 303 static const struct lpss_device_desc byt_sdio_dev_desc = { 304 .flags = LPSS_CLK, 305 }; 306 307 static const struct lpss_device_desc byt_i2c_dev_desc = { 308 .flags = LPSS_CLK | LPSS_SAVE_CTX, 309 .prv_offset = 0x800, 310 .setup = byt_i2c_setup, 311 .resume_from_noirq = true, 312 }; 313 314 static const struct lpss_device_desc bsw_i2c_dev_desc = { 315 .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, 316 .prv_offset = 0x800, 317 .setup = byt_i2c_setup, 318 .resume_from_noirq = true, 319 }; 320 321 static const struct property_entry bsw_spi_properties[] = { 322 PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_BSW_SSP), 323 { } 324 }; 325 326 static const struct lpss_device_desc bsw_spi_dev_desc = { 327 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX 328 | LPSS_NO_D3_DELAY, 329 .prv_offset = 0x400, 330 .setup = lpss_deassert_reset, 331 .properties = bsw_spi_properties, 332 }; 333 334 static const struct x86_cpu_id lpss_cpu_ids[] = { 335 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, NULL), 336 X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, NULL), 337 {} 338 }; 339 340 #else 341 342 #define LPSS_ADDR(desc) (0UL) 343 344 #endif /* CONFIG_X86_INTEL_LPSS */ 345 346 static const struct acpi_device_id acpi_lpss_device_ids[] = { 347 /* Generic LPSS devices */ 348 { "INTL9C60", LPSS_ADDR(lpss_dma_desc) }, 349 350 /* Lynxpoint LPSS devices */ 351 { "INT33C0", LPSS_ADDR(lpt_spi_dev_desc) }, 352 { "INT33C1", LPSS_ADDR(lpt_spi_dev_desc) }, 353 { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) }, 354 { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) }, 355 { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) }, 356 { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) }, 357 { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) }, 358 { "INT33C7", }, 359 360 /* BayTrail LPSS devices */ 361 { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) }, 362 { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) }, 363 { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) }, 364 { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) }, 365 { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) }, 366 { "INT33B2", }, 367 { "INT33FC", }, 368 369 /* Braswell LPSS devices */ 370 { "80862286", LPSS_ADDR(lpss_dma_desc) }, 371 { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) }, 372 { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) }, 373 { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) }, 374 { "808622C0", LPSS_ADDR(lpss_dma_desc) }, 375 { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) }, 376 377 /* Broadwell LPSS devices */ 378 { "INT3430", LPSS_ADDR(lpt_spi_dev_desc) }, 379 { "INT3431", LPSS_ADDR(lpt_spi_dev_desc) }, 380 { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) }, 381 { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) }, 382 { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) }, 383 { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) }, 384 { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) }, 385 { "INT3437", }, 386 387 /* Wildcat Point LPSS devices */ 388 { "INT3438", LPSS_ADDR(lpt_spi_dev_desc) }, 389 390 { } 391 }; 392 393 #ifdef CONFIG_X86_INTEL_LPSS 394 395 static int is_memory(struct acpi_resource *res, void *not_used) 396 { 397 struct resource r; 398 399 return !acpi_dev_resource_memory(res, &r); 400 } 401 402 /* LPSS main clock device. */ 403 static struct platform_device *lpss_clk_dev; 404 405 static inline void lpt_register_clock_device(void) 406 { 407 lpss_clk_dev = platform_device_register_simple("clk-lpss-atom", 408 PLATFORM_DEVID_NONE, 409 NULL, 0); 410 } 411 412 static int register_device_clock(struct acpi_device *adev, 413 struct lpss_private_data *pdata) 414 { 415 const struct lpss_device_desc *dev_desc = pdata->dev_desc; 416 const char *devname = dev_name(&adev->dev); 417 struct clk *clk; 418 struct lpss_clk_data *clk_data; 419 const char *parent, *clk_name; 420 void __iomem *prv_base; 421 422 if (!lpss_clk_dev) 423 lpt_register_clock_device(); 424 425 if (IS_ERR(lpss_clk_dev)) 426 return PTR_ERR(lpss_clk_dev); 427 428 clk_data = platform_get_drvdata(lpss_clk_dev); 429 if (!clk_data) 430 return -ENODEV; 431 clk = clk_data->clk; 432 433 if (!pdata->mmio_base 434 || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE) 435 return -ENODATA; 436 437 parent = clk_data->name; 438 prv_base = pdata->mmio_base + dev_desc->prv_offset; 439 440 if (pdata->fixed_clk_rate) { 441 clk = clk_register_fixed_rate(NULL, devname, parent, 0, 442 pdata->fixed_clk_rate); 443 goto out; 444 } 445 446 if (dev_desc->flags & LPSS_CLK_GATE) { 447 clk = clk_register_gate(NULL, devname, parent, 0, 448 prv_base, 0, 0, NULL); 449 parent = devname; 450 } 451 452 if (dev_desc->flags & LPSS_CLK_DIVIDER) { 453 /* Prevent division by zero */ 454 if (!readl(prv_base)) 455 writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base); 456 457 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname); 458 if (!clk_name) 459 return -ENOMEM; 460 clk = clk_register_fractional_divider(NULL, clk_name, parent, 461 CLK_FRAC_DIVIDER_POWER_OF_TWO_PS, 462 prv_base, 1, 15, 16, 15, 0, NULL); 463 parent = clk_name; 464 465 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname); 466 if (!clk_name) { 467 kfree(parent); 468 return -ENOMEM; 469 } 470 clk = clk_register_gate(NULL, clk_name, parent, 471 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, 472 prv_base, 31, 0, NULL); 473 kfree(parent); 474 kfree(clk_name); 475 } 476 out: 477 if (IS_ERR(clk)) 478 return PTR_ERR(clk); 479 480 pdata->clk = clk; 481 clk_register_clkdev(clk, dev_desc->clk_con_id, devname); 482 return 0; 483 } 484 485 struct lpss_device_links { 486 const char *supplier_hid; 487 const char *supplier_uid; 488 const char *consumer_hid; 489 const char *consumer_uid; 490 u32 flags; 491 const struct dmi_system_id *dep_missing_ids; 492 }; 493 494 /* Please keep this list sorted alphabetically by vendor and model */ 495 static const struct dmi_system_id i2c1_dep_missing_dmi_ids[] = { 496 { 497 .matches = { 498 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), 499 DMI_MATCH(DMI_PRODUCT_NAME, "T200TA"), 500 }, 501 }, 502 {} 503 }; 504 505 /* 506 * The _DEP method is used to identify dependencies but instead of creating 507 * device links for every handle in _DEP, only links in the following list are 508 * created. That is necessary because, in the general case, _DEP can refer to 509 * devices that might not have drivers, or that are on different buses, or where 510 * the supplier is not enumerated until after the consumer is probed. 511 */ 512 static const struct lpss_device_links lpss_device_links[] = { 513 /* CHT External sdcard slot controller depends on PMIC I2C ctrl */ 514 {"808622C1", "7", "80860F14", "3", DL_FLAG_PM_RUNTIME}, 515 /* CHT iGPU depends on PMIC I2C controller */ 516 {"808622C1", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, 517 /* BYT iGPU depends on the Embedded Controller I2C controller (UID 1) */ 518 {"80860F41", "1", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME, 519 i2c1_dep_missing_dmi_ids}, 520 /* BYT CR iGPU depends on PMIC I2C controller (UID 5 on CR) */ 521 {"80860F41", "5", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, 522 /* BYT iGPU depends on PMIC I2C controller (UID 7 on non CR) */ 523 {"80860F41", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, 524 }; 525 526 static bool acpi_lpss_is_supplier(struct acpi_device *adev, 527 const struct lpss_device_links *link) 528 { 529 return acpi_dev_hid_uid_match(adev, link->supplier_hid, link->supplier_uid); 530 } 531 532 static bool acpi_lpss_is_consumer(struct acpi_device *adev, 533 const struct lpss_device_links *link) 534 { 535 return acpi_dev_hid_uid_match(adev, link->consumer_hid, link->consumer_uid); 536 } 537 538 struct hid_uid { 539 const char *hid; 540 const char *uid; 541 }; 542 543 static int match_hid_uid(struct device *dev, const void *data) 544 { 545 struct acpi_device *adev = ACPI_COMPANION(dev); 546 const struct hid_uid *id = data; 547 548 if (!adev) 549 return 0; 550 551 return acpi_dev_hid_uid_match(adev, id->hid, id->uid); 552 } 553 554 static struct device *acpi_lpss_find_device(const char *hid, const char *uid) 555 { 556 struct device *dev; 557 558 struct hid_uid data = { 559 .hid = hid, 560 .uid = uid, 561 }; 562 563 dev = bus_find_device(&platform_bus_type, NULL, &data, match_hid_uid); 564 if (dev) 565 return dev; 566 567 return bus_find_device(&pci_bus_type, NULL, &data, match_hid_uid); 568 } 569 570 static bool acpi_lpss_dep(struct acpi_device *adev, acpi_handle handle) 571 { 572 struct acpi_handle_list dep_devices; 573 acpi_status status; 574 int i; 575 576 if (!acpi_has_method(adev->handle, "_DEP")) 577 return false; 578 579 status = acpi_evaluate_reference(adev->handle, "_DEP", NULL, 580 &dep_devices); 581 if (ACPI_FAILURE(status)) { 582 dev_dbg(&adev->dev, "Failed to evaluate _DEP.\n"); 583 return false; 584 } 585 586 for (i = 0; i < dep_devices.count; i++) { 587 if (dep_devices.handles[i] == handle) 588 return true; 589 } 590 591 return false; 592 } 593 594 static void acpi_lpss_link_consumer(struct device *dev1, 595 const struct lpss_device_links *link) 596 { 597 struct device *dev2; 598 599 dev2 = acpi_lpss_find_device(link->consumer_hid, link->consumer_uid); 600 if (!dev2) 601 return; 602 603 if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids)) 604 || acpi_lpss_dep(ACPI_COMPANION(dev2), ACPI_HANDLE(dev1))) 605 device_link_add(dev2, dev1, link->flags); 606 607 put_device(dev2); 608 } 609 610 static void acpi_lpss_link_supplier(struct device *dev1, 611 const struct lpss_device_links *link) 612 { 613 struct device *dev2; 614 615 dev2 = acpi_lpss_find_device(link->supplier_hid, link->supplier_uid); 616 if (!dev2) 617 return; 618 619 if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids)) 620 || acpi_lpss_dep(ACPI_COMPANION(dev1), ACPI_HANDLE(dev2))) 621 device_link_add(dev1, dev2, link->flags); 622 623 put_device(dev2); 624 } 625 626 static void acpi_lpss_create_device_links(struct acpi_device *adev, 627 struct platform_device *pdev) 628 { 629 int i; 630 631 for (i = 0; i < ARRAY_SIZE(lpss_device_links); i++) { 632 const struct lpss_device_links *link = &lpss_device_links[i]; 633 634 if (acpi_lpss_is_supplier(adev, link)) 635 acpi_lpss_link_consumer(&pdev->dev, link); 636 637 if (acpi_lpss_is_consumer(adev, link)) 638 acpi_lpss_link_supplier(&pdev->dev, link); 639 } 640 } 641 642 static int acpi_lpss_create_device(struct acpi_device *adev, 643 const struct acpi_device_id *id) 644 { 645 const struct lpss_device_desc *dev_desc; 646 struct lpss_private_data *pdata; 647 struct resource_entry *rentry; 648 struct list_head resource_list; 649 struct platform_device *pdev; 650 int ret; 651 652 dev_desc = (const struct lpss_device_desc *)id->driver_data; 653 if (!dev_desc) { 654 pdev = acpi_create_platform_device(adev, NULL); 655 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1; 656 } 657 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); 658 if (!pdata) 659 return -ENOMEM; 660 661 INIT_LIST_HEAD(&resource_list); 662 ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL); 663 if (ret < 0) 664 goto err_out; 665 666 list_for_each_entry(rentry, &resource_list, node) 667 if (resource_type(rentry->res) == IORESOURCE_MEM) { 668 if (dev_desc->prv_size_override) 669 pdata->mmio_size = dev_desc->prv_size_override; 670 else 671 pdata->mmio_size = resource_size(rentry->res); 672 pdata->mmio_base = ioremap(rentry->res->start, 673 pdata->mmio_size); 674 break; 675 } 676 677 acpi_dev_free_resource_list(&resource_list); 678 679 if (!pdata->mmio_base) { 680 /* Avoid acpi_bus_attach() instantiating a pdev for this dev. */ 681 adev->pnp.type.platform_id = 0; 682 /* Skip the device, but continue the namespace scan. */ 683 ret = 0; 684 goto err_out; 685 } 686 687 pdata->adev = adev; 688 pdata->dev_desc = dev_desc; 689 690 if (dev_desc->setup) 691 dev_desc->setup(pdata); 692 693 if (dev_desc->flags & LPSS_CLK) { 694 ret = register_device_clock(adev, pdata); 695 if (ret) { 696 /* Skip the device, but continue the namespace scan. */ 697 ret = 0; 698 goto err_out; 699 } 700 } 701 702 /* 703 * This works around a known issue in ACPI tables where LPSS devices 704 * have _PS0 and _PS3 without _PSC (and no power resources), so 705 * acpi_bus_init_power() will assume that the BIOS has put them into D0. 706 */ 707 acpi_device_fix_up_power(adev); 708 709 adev->driver_data = pdata; 710 pdev = acpi_create_platform_device(adev, dev_desc->properties); 711 if (!IS_ERR_OR_NULL(pdev)) { 712 acpi_lpss_create_device_links(adev, pdev); 713 return 1; 714 } 715 716 ret = PTR_ERR(pdev); 717 adev->driver_data = NULL; 718 719 err_out: 720 kfree(pdata); 721 return ret; 722 } 723 724 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg) 725 { 726 return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg); 727 } 728 729 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata, 730 unsigned int reg) 731 { 732 writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg); 733 } 734 735 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val) 736 { 737 struct acpi_device *adev = ACPI_COMPANION(dev); 738 struct lpss_private_data *pdata; 739 unsigned long flags; 740 int ret; 741 742 if (WARN_ON(!adev)) 743 return -ENODEV; 744 745 spin_lock_irqsave(&dev->power.lock, flags); 746 if (pm_runtime_suspended(dev)) { 747 ret = -EAGAIN; 748 goto out; 749 } 750 pdata = acpi_driver_data(adev); 751 if (WARN_ON(!pdata || !pdata->mmio_base)) { 752 ret = -ENODEV; 753 goto out; 754 } 755 *val = __lpss_reg_read(pdata, reg); 756 ret = 0; 757 758 out: 759 spin_unlock_irqrestore(&dev->power.lock, flags); 760 return ret; 761 } 762 763 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr, 764 char *buf) 765 { 766 u32 ltr_value = 0; 767 unsigned int reg; 768 int ret; 769 770 reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR; 771 ret = lpss_reg_read(dev, reg, <r_value); 772 if (ret) 773 return ret; 774 775 return sysfs_emit(buf, "%08x\n", ltr_value); 776 } 777 778 static ssize_t lpss_ltr_mode_show(struct device *dev, 779 struct device_attribute *attr, char *buf) 780 { 781 u32 ltr_mode = 0; 782 char *outstr; 783 int ret; 784 785 ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode); 786 if (ret) 787 return ret; 788 789 outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto"; 790 return sprintf(buf, "%s\n", outstr); 791 } 792 793 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL); 794 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL); 795 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL); 796 797 static struct attribute *lpss_attrs[] = { 798 &dev_attr_auto_ltr.attr, 799 &dev_attr_sw_ltr.attr, 800 &dev_attr_ltr_mode.attr, 801 NULL, 802 }; 803 804 static const struct attribute_group lpss_attr_group = { 805 .attrs = lpss_attrs, 806 .name = "lpss_ltr", 807 }; 808 809 static void acpi_lpss_set_ltr(struct device *dev, s32 val) 810 { 811 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 812 u32 ltr_mode, ltr_val; 813 814 ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL); 815 if (val < 0) { 816 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) { 817 ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW; 818 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); 819 } 820 return; 821 } 822 ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK; 823 if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) { 824 ltr_val |= LPSS_LTR_SNOOP_LAT_32US; 825 val = LPSS_LTR_MAX_VAL; 826 } else if (val > LPSS_LTR_MAX_VAL) { 827 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ; 828 val >>= LPSS_LTR_SNOOP_LAT_SHIFT; 829 } else { 830 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ; 831 } 832 ltr_val |= val; 833 __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR); 834 if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) { 835 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW; 836 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); 837 } 838 } 839 840 #ifdef CONFIG_PM 841 /** 842 * acpi_lpss_save_ctx() - Save the private registers of LPSS device 843 * @dev: LPSS device 844 * @pdata: pointer to the private data of the LPSS device 845 * 846 * Most LPSS devices have private registers which may loose their context when 847 * the device is powered down. acpi_lpss_save_ctx() saves those registers into 848 * prv_reg_ctx array. 849 */ 850 static void acpi_lpss_save_ctx(struct device *dev, 851 struct lpss_private_data *pdata) 852 { 853 unsigned int i; 854 855 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { 856 unsigned long offset = i * sizeof(u32); 857 858 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset); 859 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n", 860 pdata->prv_reg_ctx[i], offset); 861 } 862 } 863 864 /** 865 * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device 866 * @dev: LPSS device 867 * @pdata: pointer to the private data of the LPSS device 868 * 869 * Restores the registers that were previously stored with acpi_lpss_save_ctx(). 870 */ 871 static void acpi_lpss_restore_ctx(struct device *dev, 872 struct lpss_private_data *pdata) 873 { 874 unsigned int i; 875 876 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { 877 unsigned long offset = i * sizeof(u32); 878 879 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset); 880 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n", 881 pdata->prv_reg_ctx[i], offset); 882 } 883 } 884 885 static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata) 886 { 887 /* 888 * The following delay is needed or the subsequent write operations may 889 * fail. The LPSS devices are actually PCI devices and the PCI spec 890 * expects 10ms delay before the device can be accessed after D3 to D0 891 * transition. However some platforms like BSW does not need this delay. 892 */ 893 unsigned int delay = 10; /* default 10ms delay */ 894 895 if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY) 896 delay = 0; 897 898 msleep(delay); 899 } 900 901 static int acpi_lpss_activate(struct device *dev) 902 { 903 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 904 int ret; 905 906 ret = acpi_dev_resume(dev); 907 if (ret) 908 return ret; 909 910 acpi_lpss_d3_to_d0_delay(pdata); 911 912 /* 913 * This is called only on ->probe() stage where a device is either in 914 * known state defined by BIOS or most likely powered off. Due to this 915 * we have to deassert reset line to be sure that ->probe() will 916 * recognize the device. 917 */ 918 if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE)) 919 lpss_deassert_reset(pdata); 920 921 #ifdef CONFIG_PM 922 if (pdata->dev_desc->flags & LPSS_SAVE_CTX_ONCE) 923 acpi_lpss_save_ctx(dev, pdata); 924 #endif 925 926 return 0; 927 } 928 929 static void acpi_lpss_dismiss(struct device *dev) 930 { 931 acpi_dev_suspend(dev, false); 932 } 933 934 /* IOSF SB for LPSS island */ 935 #define LPSS_IOSF_UNIT_LPIOEP 0xA0 936 #define LPSS_IOSF_UNIT_LPIO1 0xAB 937 #define LPSS_IOSF_UNIT_LPIO2 0xAC 938 939 #define LPSS_IOSF_PMCSR 0x84 940 #define LPSS_PMCSR_D0 0 941 #define LPSS_PMCSR_D3hot 3 942 #define LPSS_PMCSR_Dx_MASK GENMASK(1, 0) 943 944 #define LPSS_IOSF_GPIODEF0 0x154 945 #define LPSS_GPIODEF0_DMA1_D3 BIT(2) 946 #define LPSS_GPIODEF0_DMA2_D3 BIT(3) 947 #define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2) 948 #define LPSS_GPIODEF0_DMA_LLP BIT(13) 949 950 static DEFINE_MUTEX(lpss_iosf_mutex); 951 static bool lpss_iosf_d3_entered = true; 952 953 static void lpss_iosf_enter_d3_state(void) 954 { 955 u32 value1 = 0; 956 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; 957 u32 value2 = LPSS_PMCSR_D3hot; 958 u32 mask2 = LPSS_PMCSR_Dx_MASK; 959 /* 960 * PMC provides an information about actual status of the LPSS devices. 961 * Here we read the values related to LPSS power island, i.e. LPSS 962 * devices, excluding both LPSS DMA controllers, along with SCC domain. 963 */ 964 u32 func_dis, d3_sts_0, pmc_status; 965 int ret; 966 967 ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis); 968 if (ret) 969 return; 970 971 mutex_lock(&lpss_iosf_mutex); 972 973 ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0); 974 if (ret) 975 goto exit; 976 977 /* 978 * Get the status of entire LPSS power island per device basis. 979 * Shutdown both LPSS DMA controllers if and only if all other devices 980 * are already in D3hot. 981 */ 982 pmc_status = (~(d3_sts_0 | func_dis)) & pmc_atom_d3_mask; 983 if (pmc_status) 984 goto exit; 985 986 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, 987 LPSS_IOSF_PMCSR, value2, mask2); 988 989 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, 990 LPSS_IOSF_PMCSR, value2, mask2); 991 992 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, 993 LPSS_IOSF_GPIODEF0, value1, mask1); 994 995 lpss_iosf_d3_entered = true; 996 997 exit: 998 mutex_unlock(&lpss_iosf_mutex); 999 } 1000 1001 static void lpss_iosf_exit_d3_state(void) 1002 { 1003 u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 | 1004 LPSS_GPIODEF0_DMA_LLP; 1005 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; 1006 u32 value2 = LPSS_PMCSR_D0; 1007 u32 mask2 = LPSS_PMCSR_Dx_MASK; 1008 1009 mutex_lock(&lpss_iosf_mutex); 1010 1011 if (!lpss_iosf_d3_entered) 1012 goto exit; 1013 1014 lpss_iosf_d3_entered = false; 1015 1016 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, 1017 LPSS_IOSF_GPIODEF0, value1, mask1); 1018 1019 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, 1020 LPSS_IOSF_PMCSR, value2, mask2); 1021 1022 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, 1023 LPSS_IOSF_PMCSR, value2, mask2); 1024 1025 exit: 1026 mutex_unlock(&lpss_iosf_mutex); 1027 } 1028 1029 static int acpi_lpss_suspend(struct device *dev, bool wakeup) 1030 { 1031 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1032 int ret; 1033 1034 if (pdata->dev_desc->flags & LPSS_SAVE_CTX) 1035 acpi_lpss_save_ctx(dev, pdata); 1036 1037 ret = acpi_dev_suspend(dev, wakeup); 1038 1039 /* 1040 * This call must be last in the sequence, otherwise PMC will return 1041 * wrong status for devices being about to be powered off. See 1042 * lpss_iosf_enter_d3_state() for further information. 1043 */ 1044 if (acpi_target_system_state() == ACPI_STATE_S0 && 1045 lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) 1046 lpss_iosf_enter_d3_state(); 1047 1048 return ret; 1049 } 1050 1051 static int acpi_lpss_resume(struct device *dev) 1052 { 1053 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1054 int ret; 1055 1056 /* 1057 * This call is kept first to be in symmetry with 1058 * acpi_lpss_runtime_suspend() one. 1059 */ 1060 if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) 1061 lpss_iosf_exit_d3_state(); 1062 1063 ret = acpi_dev_resume(dev); 1064 if (ret) 1065 return ret; 1066 1067 acpi_lpss_d3_to_d0_delay(pdata); 1068 1069 if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE)) 1070 acpi_lpss_restore_ctx(dev, pdata); 1071 1072 return 0; 1073 } 1074 1075 #ifdef CONFIG_PM_SLEEP 1076 static int acpi_lpss_do_suspend_late(struct device *dev) 1077 { 1078 int ret; 1079 1080 if (dev_pm_skip_suspend(dev)) 1081 return 0; 1082 1083 ret = pm_generic_suspend_late(dev); 1084 return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev)); 1085 } 1086 1087 static int acpi_lpss_suspend_late(struct device *dev) 1088 { 1089 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1090 1091 if (pdata->dev_desc->resume_from_noirq) 1092 return 0; 1093 1094 return acpi_lpss_do_suspend_late(dev); 1095 } 1096 1097 static int acpi_lpss_suspend_noirq(struct device *dev) 1098 { 1099 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1100 int ret; 1101 1102 if (pdata->dev_desc->resume_from_noirq) { 1103 /* 1104 * The driver's ->suspend_late callback will be invoked by 1105 * acpi_lpss_do_suspend_late(), with the assumption that the 1106 * driver really wanted to run that code in ->suspend_noirq, but 1107 * it could not run after acpi_dev_suspend() and the driver 1108 * expected the latter to be called in the "late" phase. 1109 */ 1110 ret = acpi_lpss_do_suspend_late(dev); 1111 if (ret) 1112 return ret; 1113 } 1114 1115 return acpi_subsys_suspend_noirq(dev); 1116 } 1117 1118 static int acpi_lpss_do_resume_early(struct device *dev) 1119 { 1120 int ret = acpi_lpss_resume(dev); 1121 1122 return ret ? ret : pm_generic_resume_early(dev); 1123 } 1124 1125 static int acpi_lpss_resume_early(struct device *dev) 1126 { 1127 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1128 1129 if (pdata->dev_desc->resume_from_noirq) 1130 return 0; 1131 1132 if (dev_pm_skip_resume(dev)) 1133 return 0; 1134 1135 return acpi_lpss_do_resume_early(dev); 1136 } 1137 1138 static int acpi_lpss_resume_noirq(struct device *dev) 1139 { 1140 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1141 int ret; 1142 1143 /* Follow acpi_subsys_resume_noirq(). */ 1144 if (dev_pm_skip_resume(dev)) 1145 return 0; 1146 1147 ret = pm_generic_resume_noirq(dev); 1148 if (ret) 1149 return ret; 1150 1151 if (!pdata->dev_desc->resume_from_noirq) 1152 return 0; 1153 1154 /* 1155 * The driver's ->resume_early callback will be invoked by 1156 * acpi_lpss_do_resume_early(), with the assumption that the driver 1157 * really wanted to run that code in ->resume_noirq, but it could not 1158 * run before acpi_dev_resume() and the driver expected the latter to be 1159 * called in the "early" phase. 1160 */ 1161 return acpi_lpss_do_resume_early(dev); 1162 } 1163 1164 static int acpi_lpss_do_restore_early(struct device *dev) 1165 { 1166 int ret = acpi_lpss_resume(dev); 1167 1168 return ret ? ret : pm_generic_restore_early(dev); 1169 } 1170 1171 static int acpi_lpss_restore_early(struct device *dev) 1172 { 1173 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1174 1175 if (pdata->dev_desc->resume_from_noirq) 1176 return 0; 1177 1178 return acpi_lpss_do_restore_early(dev); 1179 } 1180 1181 static int acpi_lpss_restore_noirq(struct device *dev) 1182 { 1183 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1184 int ret; 1185 1186 ret = pm_generic_restore_noirq(dev); 1187 if (ret) 1188 return ret; 1189 1190 if (!pdata->dev_desc->resume_from_noirq) 1191 return 0; 1192 1193 /* This is analogous to what happens in acpi_lpss_resume_noirq(). */ 1194 return acpi_lpss_do_restore_early(dev); 1195 } 1196 1197 static int acpi_lpss_do_poweroff_late(struct device *dev) 1198 { 1199 int ret = pm_generic_poweroff_late(dev); 1200 1201 return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev)); 1202 } 1203 1204 static int acpi_lpss_poweroff_late(struct device *dev) 1205 { 1206 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1207 1208 if (dev_pm_skip_suspend(dev)) 1209 return 0; 1210 1211 if (pdata->dev_desc->resume_from_noirq) 1212 return 0; 1213 1214 return acpi_lpss_do_poweroff_late(dev); 1215 } 1216 1217 static int acpi_lpss_poweroff_noirq(struct device *dev) 1218 { 1219 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1220 1221 if (dev_pm_skip_suspend(dev)) 1222 return 0; 1223 1224 if (pdata->dev_desc->resume_from_noirq) { 1225 /* This is analogous to the acpi_lpss_suspend_noirq() case. */ 1226 int ret = acpi_lpss_do_poweroff_late(dev); 1227 1228 if (ret) 1229 return ret; 1230 } 1231 1232 return pm_generic_poweroff_noirq(dev); 1233 } 1234 #endif /* CONFIG_PM_SLEEP */ 1235 1236 static int acpi_lpss_runtime_suspend(struct device *dev) 1237 { 1238 int ret = pm_generic_runtime_suspend(dev); 1239 1240 return ret ? ret : acpi_lpss_suspend(dev, true); 1241 } 1242 1243 static int acpi_lpss_runtime_resume(struct device *dev) 1244 { 1245 int ret = acpi_lpss_resume(dev); 1246 1247 return ret ? ret : pm_generic_runtime_resume(dev); 1248 } 1249 #endif /* CONFIG_PM */ 1250 1251 static struct dev_pm_domain acpi_lpss_pm_domain = { 1252 #ifdef CONFIG_PM 1253 .activate = acpi_lpss_activate, 1254 .dismiss = acpi_lpss_dismiss, 1255 #endif 1256 .ops = { 1257 #ifdef CONFIG_PM 1258 #ifdef CONFIG_PM_SLEEP 1259 .prepare = acpi_subsys_prepare, 1260 .complete = acpi_subsys_complete, 1261 .suspend = acpi_subsys_suspend, 1262 .suspend_late = acpi_lpss_suspend_late, 1263 .suspend_noirq = acpi_lpss_suspend_noirq, 1264 .resume_noirq = acpi_lpss_resume_noirq, 1265 .resume_early = acpi_lpss_resume_early, 1266 .freeze = acpi_subsys_freeze, 1267 .poweroff = acpi_subsys_poweroff, 1268 .poweroff_late = acpi_lpss_poweroff_late, 1269 .poweroff_noirq = acpi_lpss_poweroff_noirq, 1270 .restore_noirq = acpi_lpss_restore_noirq, 1271 .restore_early = acpi_lpss_restore_early, 1272 #endif 1273 .runtime_suspend = acpi_lpss_runtime_suspend, 1274 .runtime_resume = acpi_lpss_runtime_resume, 1275 #endif 1276 }, 1277 }; 1278 1279 static int acpi_lpss_platform_notify(struct notifier_block *nb, 1280 unsigned long action, void *data) 1281 { 1282 struct platform_device *pdev = to_platform_device(data); 1283 struct lpss_private_data *pdata; 1284 struct acpi_device *adev; 1285 const struct acpi_device_id *id; 1286 1287 id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev); 1288 if (!id || !id->driver_data) 1289 return 0; 1290 1291 adev = ACPI_COMPANION(&pdev->dev); 1292 if (!adev) 1293 return 0; 1294 1295 pdata = acpi_driver_data(adev); 1296 if (!pdata) 1297 return 0; 1298 1299 if (pdata->mmio_base && 1300 pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) { 1301 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n"); 1302 return 0; 1303 } 1304 1305 switch (action) { 1306 case BUS_NOTIFY_BIND_DRIVER: 1307 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); 1308 break; 1309 case BUS_NOTIFY_DRIVER_NOT_BOUND: 1310 case BUS_NOTIFY_UNBOUND_DRIVER: 1311 dev_pm_domain_set(&pdev->dev, NULL); 1312 break; 1313 case BUS_NOTIFY_ADD_DEVICE: 1314 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); 1315 if (pdata->dev_desc->flags & LPSS_LTR) 1316 return sysfs_create_group(&pdev->dev.kobj, 1317 &lpss_attr_group); 1318 break; 1319 case BUS_NOTIFY_DEL_DEVICE: 1320 if (pdata->dev_desc->flags & LPSS_LTR) 1321 sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group); 1322 dev_pm_domain_set(&pdev->dev, NULL); 1323 break; 1324 default: 1325 break; 1326 } 1327 1328 return 0; 1329 } 1330 1331 static struct notifier_block acpi_lpss_nb = { 1332 .notifier_call = acpi_lpss_platform_notify, 1333 }; 1334 1335 static void acpi_lpss_bind(struct device *dev) 1336 { 1337 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1338 1339 if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR)) 1340 return; 1341 1342 if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) 1343 dev->power.set_latency_tolerance = acpi_lpss_set_ltr; 1344 else 1345 dev_err(dev, "MMIO size insufficient to access LTR\n"); 1346 } 1347 1348 static void acpi_lpss_unbind(struct device *dev) 1349 { 1350 dev->power.set_latency_tolerance = NULL; 1351 } 1352 1353 static struct acpi_scan_handler lpss_handler = { 1354 .ids = acpi_lpss_device_ids, 1355 .attach = acpi_lpss_create_device, 1356 .bind = acpi_lpss_bind, 1357 .unbind = acpi_lpss_unbind, 1358 }; 1359 1360 void __init acpi_lpss_init(void) 1361 { 1362 const struct x86_cpu_id *id; 1363 int ret; 1364 1365 ret = lpss_atom_clk_init(); 1366 if (ret) 1367 return; 1368 1369 id = x86_match_cpu(lpss_cpu_ids); 1370 if (id) 1371 lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON; 1372 1373 bus_register_notifier(&platform_bus_type, &acpi_lpss_nb); 1374 acpi_scan_add_handler(&lpss_handler); 1375 } 1376 1377 #else 1378 1379 static struct acpi_scan_handler lpss_handler = { 1380 .ids = acpi_lpss_device_ids, 1381 }; 1382 1383 void __init acpi_lpss_init(void) 1384 { 1385 acpi_scan_add_handler(&lpss_handler); 1386 } 1387 1388 #endif /* CONFIG_X86_INTEL_LPSS */ 1389