1 /* 2 * ACPI support for Intel Lynxpoint LPSS. 3 * 4 * Copyright (C) 2013, Intel Corporation 5 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> 6 * Rafael J. Wysocki <rafael.j.wysocki@intel.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/acpi.h> 14 #include <linux/clkdev.h> 15 #include <linux/clk-provider.h> 16 #include <linux/err.h> 17 #include <linux/io.h> 18 #include <linux/mutex.h> 19 #include <linux/platform_device.h> 20 #include <linux/platform_data/clk-lpss.h> 21 #include <linux/platform_data/x86/pmc_atom.h> 22 #include <linux/pm_domain.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/pwm.h> 25 #include <linux/delay.h> 26 27 #include "internal.h" 28 29 ACPI_MODULE_NAME("acpi_lpss"); 30 31 #ifdef CONFIG_X86_INTEL_LPSS 32 33 #include <asm/cpu_device_id.h> 34 #include <asm/intel-family.h> 35 #include <asm/iosf_mbi.h> 36 37 #define LPSS_ADDR(desc) ((unsigned long)&desc) 38 39 #define LPSS_CLK_SIZE 0x04 40 #define LPSS_LTR_SIZE 0x18 41 42 /* Offsets relative to LPSS_PRIVATE_OFFSET */ 43 #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16)) 44 #define LPSS_RESETS 0x04 45 #define LPSS_RESETS_RESET_FUNC BIT(0) 46 #define LPSS_RESETS_RESET_APB BIT(1) 47 #define LPSS_GENERAL 0x08 48 #define LPSS_GENERAL_LTR_MODE_SW BIT(2) 49 #define LPSS_GENERAL_UART_RTS_OVRD BIT(3) 50 #define LPSS_SW_LTR 0x10 51 #define LPSS_AUTO_LTR 0x14 52 #define LPSS_LTR_SNOOP_REQ BIT(15) 53 #define LPSS_LTR_SNOOP_MASK 0x0000FFFF 54 #define LPSS_LTR_SNOOP_LAT_1US 0x800 55 #define LPSS_LTR_SNOOP_LAT_32US 0xC00 56 #define LPSS_LTR_SNOOP_LAT_SHIFT 5 57 #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000 58 #define LPSS_LTR_MAX_VAL 0x3FF 59 #define LPSS_TX_INT 0x20 60 #define LPSS_TX_INT_MASK BIT(1) 61 62 #define LPSS_PRV_REG_COUNT 9 63 64 /* LPSS Flags */ 65 #define LPSS_CLK BIT(0) 66 #define LPSS_CLK_GATE BIT(1) 67 #define LPSS_CLK_DIVIDER BIT(2) 68 #define LPSS_LTR BIT(3) 69 #define LPSS_SAVE_CTX BIT(4) 70 #define LPSS_NO_D3_DELAY BIT(5) 71 72 struct lpss_private_data; 73 74 struct lpss_device_desc { 75 unsigned int flags; 76 const char *clk_con_id; 77 unsigned int prv_offset; 78 size_t prv_size_override; 79 struct property_entry *properties; 80 void (*setup)(struct lpss_private_data *pdata); 81 }; 82 83 static const struct lpss_device_desc lpss_dma_desc = { 84 .flags = LPSS_CLK, 85 }; 86 87 struct lpss_private_data { 88 struct acpi_device *adev; 89 void __iomem *mmio_base; 90 resource_size_t mmio_size; 91 unsigned int fixed_clk_rate; 92 struct clk *clk; 93 const struct lpss_device_desc *dev_desc; 94 u32 prv_reg_ctx[LPSS_PRV_REG_COUNT]; 95 }; 96 97 /* LPSS run time quirks */ 98 static unsigned int lpss_quirks; 99 100 /* 101 * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device. 102 * 103 * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover 104 * it can be powered off automatically whenever the last LPSS device goes down. 105 * In case of no power any access to the DMA controller will hang the system. 106 * The behaviour is reproduced on some HP laptops based on Intel BayTrail as 107 * well as on ASuS T100TA transformer. 108 * 109 * This quirk overrides power state of entire LPSS island to keep DMA powered 110 * on whenever we have at least one other device in use. 111 */ 112 #define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0) 113 114 /* UART Component Parameter Register */ 115 #define LPSS_UART_CPR 0xF4 116 #define LPSS_UART_CPR_AFCE BIT(4) 117 118 static void lpss_uart_setup(struct lpss_private_data *pdata) 119 { 120 unsigned int offset; 121 u32 val; 122 123 offset = pdata->dev_desc->prv_offset + LPSS_TX_INT; 124 val = readl(pdata->mmio_base + offset); 125 writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset); 126 127 val = readl(pdata->mmio_base + LPSS_UART_CPR); 128 if (!(val & LPSS_UART_CPR_AFCE)) { 129 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL; 130 val = readl(pdata->mmio_base + offset); 131 val |= LPSS_GENERAL_UART_RTS_OVRD; 132 writel(val, pdata->mmio_base + offset); 133 } 134 } 135 136 static void lpss_deassert_reset(struct lpss_private_data *pdata) 137 { 138 unsigned int offset; 139 u32 val; 140 141 offset = pdata->dev_desc->prv_offset + LPSS_RESETS; 142 val = readl(pdata->mmio_base + offset); 143 val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC; 144 writel(val, pdata->mmio_base + offset); 145 } 146 147 /* 148 * BYT PWM used for backlight control by the i915 driver on systems without 149 * the Crystal Cove PMIC. 150 */ 151 static struct pwm_lookup byt_pwm_lookup[] = { 152 PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0", 153 "pwm_backlight", 0, PWM_POLARITY_NORMAL, 154 "pwm-lpss-platform"), 155 }; 156 157 static void byt_pwm_setup(struct lpss_private_data *pdata) 158 { 159 struct acpi_device *adev = pdata->adev; 160 161 /* Only call pwm_add_table for the first PWM controller */ 162 if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1")) 163 return; 164 165 if (!acpi_dev_present("INT33FD", NULL, -1)) 166 pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup)); 167 } 168 169 #define LPSS_I2C_ENABLE 0x6c 170 171 static void byt_i2c_setup(struct lpss_private_data *pdata) 172 { 173 lpss_deassert_reset(pdata); 174 175 if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset)) 176 pdata->fixed_clk_rate = 133000000; 177 178 writel(0, pdata->mmio_base + LPSS_I2C_ENABLE); 179 } 180 181 /* BSW PWM used for backlight control by the i915 driver */ 182 static struct pwm_lookup bsw_pwm_lookup[] = { 183 PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0", 184 "pwm_backlight", 0, PWM_POLARITY_NORMAL, 185 "pwm-lpss-platform"), 186 }; 187 188 static void bsw_pwm_setup(struct lpss_private_data *pdata) 189 { 190 struct acpi_device *adev = pdata->adev; 191 192 /* Only call pwm_add_table for the first PWM controller */ 193 if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1")) 194 return; 195 196 pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup)); 197 } 198 199 static const struct lpss_device_desc lpt_dev_desc = { 200 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR, 201 .prv_offset = 0x800, 202 }; 203 204 static const struct lpss_device_desc lpt_i2c_dev_desc = { 205 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR, 206 .prv_offset = 0x800, 207 }; 208 209 static struct property_entry uart_properties[] = { 210 PROPERTY_ENTRY_U32("reg-io-width", 4), 211 PROPERTY_ENTRY_U32("reg-shift", 2), 212 PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"), 213 { }, 214 }; 215 216 static const struct lpss_device_desc lpt_uart_dev_desc = { 217 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR, 218 .clk_con_id = "baudclk", 219 .prv_offset = 0x800, 220 .setup = lpss_uart_setup, 221 .properties = uart_properties, 222 }; 223 224 static const struct lpss_device_desc lpt_sdio_dev_desc = { 225 .flags = LPSS_LTR, 226 .prv_offset = 0x1000, 227 .prv_size_override = 0x1018, 228 }; 229 230 static const struct lpss_device_desc byt_pwm_dev_desc = { 231 .flags = LPSS_SAVE_CTX, 232 .setup = byt_pwm_setup, 233 }; 234 235 static const struct lpss_device_desc bsw_pwm_dev_desc = { 236 .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, 237 .setup = bsw_pwm_setup, 238 }; 239 240 static const struct lpss_device_desc byt_uart_dev_desc = { 241 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, 242 .clk_con_id = "baudclk", 243 .prv_offset = 0x800, 244 .setup = lpss_uart_setup, 245 .properties = uart_properties, 246 }; 247 248 static const struct lpss_device_desc bsw_uart_dev_desc = { 249 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX 250 | LPSS_NO_D3_DELAY, 251 .clk_con_id = "baudclk", 252 .prv_offset = 0x800, 253 .setup = lpss_uart_setup, 254 .properties = uart_properties, 255 }; 256 257 static const struct lpss_device_desc byt_spi_dev_desc = { 258 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, 259 .prv_offset = 0x400, 260 }; 261 262 static const struct lpss_device_desc byt_sdio_dev_desc = { 263 .flags = LPSS_CLK, 264 }; 265 266 static const struct lpss_device_desc byt_i2c_dev_desc = { 267 .flags = LPSS_CLK | LPSS_SAVE_CTX, 268 .prv_offset = 0x800, 269 .setup = byt_i2c_setup, 270 }; 271 272 static const struct lpss_device_desc bsw_i2c_dev_desc = { 273 .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, 274 .prv_offset = 0x800, 275 .setup = byt_i2c_setup, 276 }; 277 278 static const struct lpss_device_desc bsw_spi_dev_desc = { 279 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX 280 | LPSS_NO_D3_DELAY, 281 .prv_offset = 0x400, 282 .setup = lpss_deassert_reset, 283 }; 284 285 #define ICPU(model) { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, } 286 287 static const struct x86_cpu_id lpss_cpu_ids[] = { 288 ICPU(INTEL_FAM6_ATOM_SILVERMONT1), /* Valleyview, Bay Trail */ 289 ICPU(INTEL_FAM6_ATOM_AIRMONT), /* Braswell, Cherry Trail */ 290 {} 291 }; 292 293 #else 294 295 #define LPSS_ADDR(desc) (0UL) 296 297 #endif /* CONFIG_X86_INTEL_LPSS */ 298 299 static const struct acpi_device_id acpi_lpss_device_ids[] = { 300 /* Generic LPSS devices */ 301 { "INTL9C60", LPSS_ADDR(lpss_dma_desc) }, 302 303 /* Lynxpoint LPSS devices */ 304 { "INT33C0", LPSS_ADDR(lpt_dev_desc) }, 305 { "INT33C1", LPSS_ADDR(lpt_dev_desc) }, 306 { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) }, 307 { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) }, 308 { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) }, 309 { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) }, 310 { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) }, 311 { "INT33C7", }, 312 313 /* BayTrail LPSS devices */ 314 { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) }, 315 { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) }, 316 { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) }, 317 { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) }, 318 { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) }, 319 { "INT33B2", }, 320 { "INT33FC", }, 321 322 /* Braswell LPSS devices */ 323 { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) }, 324 { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) }, 325 { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) }, 326 { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) }, 327 328 /* Broadwell LPSS devices */ 329 { "INT3430", LPSS_ADDR(lpt_dev_desc) }, 330 { "INT3431", LPSS_ADDR(lpt_dev_desc) }, 331 { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) }, 332 { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) }, 333 { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) }, 334 { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) }, 335 { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) }, 336 { "INT3437", }, 337 338 /* Wildcat Point LPSS devices */ 339 { "INT3438", LPSS_ADDR(lpt_dev_desc) }, 340 341 { } 342 }; 343 344 #ifdef CONFIG_X86_INTEL_LPSS 345 346 static int is_memory(struct acpi_resource *res, void *not_used) 347 { 348 struct resource r; 349 return !acpi_dev_resource_memory(res, &r); 350 } 351 352 /* LPSS main clock device. */ 353 static struct platform_device *lpss_clk_dev; 354 355 static inline void lpt_register_clock_device(void) 356 { 357 lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0); 358 } 359 360 static int register_device_clock(struct acpi_device *adev, 361 struct lpss_private_data *pdata) 362 { 363 const struct lpss_device_desc *dev_desc = pdata->dev_desc; 364 const char *devname = dev_name(&adev->dev); 365 struct clk *clk; 366 struct lpss_clk_data *clk_data; 367 const char *parent, *clk_name; 368 void __iomem *prv_base; 369 370 if (!lpss_clk_dev) 371 lpt_register_clock_device(); 372 373 clk_data = platform_get_drvdata(lpss_clk_dev); 374 if (!clk_data) 375 return -ENODEV; 376 clk = clk_data->clk; 377 378 if (!pdata->mmio_base 379 || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE) 380 return -ENODATA; 381 382 parent = clk_data->name; 383 prv_base = pdata->mmio_base + dev_desc->prv_offset; 384 385 if (pdata->fixed_clk_rate) { 386 clk = clk_register_fixed_rate(NULL, devname, parent, 0, 387 pdata->fixed_clk_rate); 388 goto out; 389 } 390 391 if (dev_desc->flags & LPSS_CLK_GATE) { 392 clk = clk_register_gate(NULL, devname, parent, 0, 393 prv_base, 0, 0, NULL); 394 parent = devname; 395 } 396 397 if (dev_desc->flags & LPSS_CLK_DIVIDER) { 398 /* Prevent division by zero */ 399 if (!readl(prv_base)) 400 writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base); 401 402 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname); 403 if (!clk_name) 404 return -ENOMEM; 405 clk = clk_register_fractional_divider(NULL, clk_name, parent, 406 0, prv_base, 407 1, 15, 16, 15, 0, NULL); 408 parent = clk_name; 409 410 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname); 411 if (!clk_name) { 412 kfree(parent); 413 return -ENOMEM; 414 } 415 clk = clk_register_gate(NULL, clk_name, parent, 416 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, 417 prv_base, 31, 0, NULL); 418 kfree(parent); 419 kfree(clk_name); 420 } 421 out: 422 if (IS_ERR(clk)) 423 return PTR_ERR(clk); 424 425 pdata->clk = clk; 426 clk_register_clkdev(clk, dev_desc->clk_con_id, devname); 427 return 0; 428 } 429 430 struct lpss_device_links { 431 const char *supplier_hid; 432 const char *supplier_uid; 433 const char *consumer_hid; 434 const char *consumer_uid; 435 u32 flags; 436 }; 437 438 /* 439 * The _DEP method is used to identify dependencies but instead of creating 440 * device links for every handle in _DEP, only links in the following list are 441 * created. That is necessary because, in the general case, _DEP can refer to 442 * devices that might not have drivers, or that are on different buses, or where 443 * the supplier is not enumerated until after the consumer is probed. 444 */ 445 static const struct lpss_device_links lpss_device_links[] = { 446 {"808622C1", "7", "80860F14", "3", DL_FLAG_PM_RUNTIME}, 447 }; 448 449 static bool hid_uid_match(const char *hid1, const char *uid1, 450 const char *hid2, const char *uid2) 451 { 452 return !strcmp(hid1, hid2) && uid1 && uid2 && !strcmp(uid1, uid2); 453 } 454 455 static bool acpi_lpss_is_supplier(struct acpi_device *adev, 456 const struct lpss_device_links *link) 457 { 458 return hid_uid_match(acpi_device_hid(adev), acpi_device_uid(adev), 459 link->supplier_hid, link->supplier_uid); 460 } 461 462 static bool acpi_lpss_is_consumer(struct acpi_device *adev, 463 const struct lpss_device_links *link) 464 { 465 return hid_uid_match(acpi_device_hid(adev), acpi_device_uid(adev), 466 link->consumer_hid, link->consumer_uid); 467 } 468 469 struct hid_uid { 470 const char *hid; 471 const char *uid; 472 }; 473 474 static int match_hid_uid(struct device *dev, void *data) 475 { 476 struct acpi_device *adev = ACPI_COMPANION(dev); 477 struct hid_uid *id = data; 478 479 if (!adev) 480 return 0; 481 482 return hid_uid_match(acpi_device_hid(adev), acpi_device_uid(adev), 483 id->hid, id->uid); 484 } 485 486 static struct device *acpi_lpss_find_device(const char *hid, const char *uid) 487 { 488 struct hid_uid data = { 489 .hid = hid, 490 .uid = uid, 491 }; 492 493 return bus_find_device(&platform_bus_type, NULL, &data, match_hid_uid); 494 } 495 496 static bool acpi_lpss_dep(struct acpi_device *adev, acpi_handle handle) 497 { 498 struct acpi_handle_list dep_devices; 499 acpi_status status; 500 int i; 501 502 if (!acpi_has_method(adev->handle, "_DEP")) 503 return false; 504 505 status = acpi_evaluate_reference(adev->handle, "_DEP", NULL, 506 &dep_devices); 507 if (ACPI_FAILURE(status)) { 508 dev_dbg(&adev->dev, "Failed to evaluate _DEP.\n"); 509 return false; 510 } 511 512 for (i = 0; i < dep_devices.count; i++) { 513 if (dep_devices.handles[i] == handle) 514 return true; 515 } 516 517 return false; 518 } 519 520 static void acpi_lpss_link_consumer(struct device *dev1, 521 const struct lpss_device_links *link) 522 { 523 struct device *dev2; 524 525 dev2 = acpi_lpss_find_device(link->consumer_hid, link->consumer_uid); 526 if (!dev2) 527 return; 528 529 if (acpi_lpss_dep(ACPI_COMPANION(dev2), ACPI_HANDLE(dev1))) 530 device_link_add(dev2, dev1, link->flags); 531 532 put_device(dev2); 533 } 534 535 static void acpi_lpss_link_supplier(struct device *dev1, 536 const struct lpss_device_links *link) 537 { 538 struct device *dev2; 539 540 dev2 = acpi_lpss_find_device(link->supplier_hid, link->supplier_uid); 541 if (!dev2) 542 return; 543 544 if (acpi_lpss_dep(ACPI_COMPANION(dev1), ACPI_HANDLE(dev2))) 545 device_link_add(dev1, dev2, link->flags); 546 547 put_device(dev2); 548 } 549 550 static void acpi_lpss_create_device_links(struct acpi_device *adev, 551 struct platform_device *pdev) 552 { 553 int i; 554 555 for (i = 0; i < ARRAY_SIZE(lpss_device_links); i++) { 556 const struct lpss_device_links *link = &lpss_device_links[i]; 557 558 if (acpi_lpss_is_supplier(adev, link)) 559 acpi_lpss_link_consumer(&pdev->dev, link); 560 561 if (acpi_lpss_is_consumer(adev, link)) 562 acpi_lpss_link_supplier(&pdev->dev, link); 563 } 564 } 565 566 static int acpi_lpss_create_device(struct acpi_device *adev, 567 const struct acpi_device_id *id) 568 { 569 const struct lpss_device_desc *dev_desc; 570 struct lpss_private_data *pdata; 571 struct resource_entry *rentry; 572 struct list_head resource_list; 573 struct platform_device *pdev; 574 int ret; 575 576 dev_desc = (const struct lpss_device_desc *)id->driver_data; 577 if (!dev_desc) { 578 pdev = acpi_create_platform_device(adev, NULL); 579 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1; 580 } 581 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); 582 if (!pdata) 583 return -ENOMEM; 584 585 INIT_LIST_HEAD(&resource_list); 586 ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL); 587 if (ret < 0) 588 goto err_out; 589 590 list_for_each_entry(rentry, &resource_list, node) 591 if (resource_type(rentry->res) == IORESOURCE_MEM) { 592 if (dev_desc->prv_size_override) 593 pdata->mmio_size = dev_desc->prv_size_override; 594 else 595 pdata->mmio_size = resource_size(rentry->res); 596 pdata->mmio_base = ioremap(rentry->res->start, 597 pdata->mmio_size); 598 break; 599 } 600 601 acpi_dev_free_resource_list(&resource_list); 602 603 if (!pdata->mmio_base) { 604 /* Avoid acpi_bus_attach() instantiating a pdev for this dev. */ 605 adev->pnp.type.platform_id = 0; 606 /* Skip the device, but continue the namespace scan. */ 607 ret = 0; 608 goto err_out; 609 } 610 611 pdata->adev = adev; 612 pdata->dev_desc = dev_desc; 613 614 if (dev_desc->setup) 615 dev_desc->setup(pdata); 616 617 if (dev_desc->flags & LPSS_CLK) { 618 ret = register_device_clock(adev, pdata); 619 if (ret) { 620 /* Skip the device, but continue the namespace scan. */ 621 ret = 0; 622 goto err_out; 623 } 624 } 625 626 /* 627 * This works around a known issue in ACPI tables where LPSS devices 628 * have _PS0 and _PS3 without _PSC (and no power resources), so 629 * acpi_bus_init_power() will assume that the BIOS has put them into D0. 630 */ 631 ret = acpi_device_fix_up_power(adev); 632 if (ret) { 633 /* Skip the device, but continue the namespace scan. */ 634 ret = 0; 635 goto err_out; 636 } 637 638 adev->driver_data = pdata; 639 pdev = acpi_create_platform_device(adev, dev_desc->properties); 640 if (!IS_ERR_OR_NULL(pdev)) { 641 acpi_lpss_create_device_links(adev, pdev); 642 return 1; 643 } 644 645 ret = PTR_ERR(pdev); 646 adev->driver_data = NULL; 647 648 err_out: 649 kfree(pdata); 650 return ret; 651 } 652 653 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg) 654 { 655 return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg); 656 } 657 658 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata, 659 unsigned int reg) 660 { 661 writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg); 662 } 663 664 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val) 665 { 666 struct acpi_device *adev; 667 struct lpss_private_data *pdata; 668 unsigned long flags; 669 int ret; 670 671 ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev); 672 if (WARN_ON(ret)) 673 return ret; 674 675 spin_lock_irqsave(&dev->power.lock, flags); 676 if (pm_runtime_suspended(dev)) { 677 ret = -EAGAIN; 678 goto out; 679 } 680 pdata = acpi_driver_data(adev); 681 if (WARN_ON(!pdata || !pdata->mmio_base)) { 682 ret = -ENODEV; 683 goto out; 684 } 685 *val = __lpss_reg_read(pdata, reg); 686 687 out: 688 spin_unlock_irqrestore(&dev->power.lock, flags); 689 return ret; 690 } 691 692 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr, 693 char *buf) 694 { 695 u32 ltr_value = 0; 696 unsigned int reg; 697 int ret; 698 699 reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR; 700 ret = lpss_reg_read(dev, reg, <r_value); 701 if (ret) 702 return ret; 703 704 return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value); 705 } 706 707 static ssize_t lpss_ltr_mode_show(struct device *dev, 708 struct device_attribute *attr, char *buf) 709 { 710 u32 ltr_mode = 0; 711 char *outstr; 712 int ret; 713 714 ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode); 715 if (ret) 716 return ret; 717 718 outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto"; 719 return sprintf(buf, "%s\n", outstr); 720 } 721 722 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL); 723 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL); 724 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL); 725 726 static struct attribute *lpss_attrs[] = { 727 &dev_attr_auto_ltr.attr, 728 &dev_attr_sw_ltr.attr, 729 &dev_attr_ltr_mode.attr, 730 NULL, 731 }; 732 733 static const struct attribute_group lpss_attr_group = { 734 .attrs = lpss_attrs, 735 .name = "lpss_ltr", 736 }; 737 738 static void acpi_lpss_set_ltr(struct device *dev, s32 val) 739 { 740 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 741 u32 ltr_mode, ltr_val; 742 743 ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL); 744 if (val < 0) { 745 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) { 746 ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW; 747 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); 748 } 749 return; 750 } 751 ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK; 752 if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) { 753 ltr_val |= LPSS_LTR_SNOOP_LAT_32US; 754 val = LPSS_LTR_MAX_VAL; 755 } else if (val > LPSS_LTR_MAX_VAL) { 756 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ; 757 val >>= LPSS_LTR_SNOOP_LAT_SHIFT; 758 } else { 759 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ; 760 } 761 ltr_val |= val; 762 __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR); 763 if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) { 764 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW; 765 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); 766 } 767 } 768 769 #ifdef CONFIG_PM 770 /** 771 * acpi_lpss_save_ctx() - Save the private registers of LPSS device 772 * @dev: LPSS device 773 * @pdata: pointer to the private data of the LPSS device 774 * 775 * Most LPSS devices have private registers which may loose their context when 776 * the device is powered down. acpi_lpss_save_ctx() saves those registers into 777 * prv_reg_ctx array. 778 */ 779 static void acpi_lpss_save_ctx(struct device *dev, 780 struct lpss_private_data *pdata) 781 { 782 unsigned int i; 783 784 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { 785 unsigned long offset = i * sizeof(u32); 786 787 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset); 788 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n", 789 pdata->prv_reg_ctx[i], offset); 790 } 791 } 792 793 /** 794 * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device 795 * @dev: LPSS device 796 * @pdata: pointer to the private data of the LPSS device 797 * 798 * Restores the registers that were previously stored with acpi_lpss_save_ctx(). 799 */ 800 static void acpi_lpss_restore_ctx(struct device *dev, 801 struct lpss_private_data *pdata) 802 { 803 unsigned int i; 804 805 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { 806 unsigned long offset = i * sizeof(u32); 807 808 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset); 809 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n", 810 pdata->prv_reg_ctx[i], offset); 811 } 812 } 813 814 static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata) 815 { 816 /* 817 * The following delay is needed or the subsequent write operations may 818 * fail. The LPSS devices are actually PCI devices and the PCI spec 819 * expects 10ms delay before the device can be accessed after D3 to D0 820 * transition. However some platforms like BSW does not need this delay. 821 */ 822 unsigned int delay = 10; /* default 10ms delay */ 823 824 if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY) 825 delay = 0; 826 827 msleep(delay); 828 } 829 830 static int acpi_lpss_activate(struct device *dev) 831 { 832 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 833 int ret; 834 835 ret = acpi_dev_resume(dev); 836 if (ret) 837 return ret; 838 839 acpi_lpss_d3_to_d0_delay(pdata); 840 841 /* 842 * This is called only on ->probe() stage where a device is either in 843 * known state defined by BIOS or most likely powered off. Due to this 844 * we have to deassert reset line to be sure that ->probe() will 845 * recognize the device. 846 */ 847 if (pdata->dev_desc->flags & LPSS_SAVE_CTX) 848 lpss_deassert_reset(pdata); 849 850 return 0; 851 } 852 853 static void acpi_lpss_dismiss(struct device *dev) 854 { 855 acpi_dev_suspend(dev, false); 856 } 857 858 /* IOSF SB for LPSS island */ 859 #define LPSS_IOSF_UNIT_LPIOEP 0xA0 860 #define LPSS_IOSF_UNIT_LPIO1 0xAB 861 #define LPSS_IOSF_UNIT_LPIO2 0xAC 862 863 #define LPSS_IOSF_PMCSR 0x84 864 #define LPSS_PMCSR_D0 0 865 #define LPSS_PMCSR_D3hot 3 866 #define LPSS_PMCSR_Dx_MASK GENMASK(1, 0) 867 868 #define LPSS_IOSF_GPIODEF0 0x154 869 #define LPSS_GPIODEF0_DMA1_D3 BIT(2) 870 #define LPSS_GPIODEF0_DMA2_D3 BIT(3) 871 #define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2) 872 #define LPSS_GPIODEF0_DMA_LLP BIT(13) 873 874 static DEFINE_MUTEX(lpss_iosf_mutex); 875 876 static void lpss_iosf_enter_d3_state(void) 877 { 878 u32 value1 = 0; 879 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; 880 u32 value2 = LPSS_PMCSR_D3hot; 881 u32 mask2 = LPSS_PMCSR_Dx_MASK; 882 /* 883 * PMC provides an information about actual status of the LPSS devices. 884 * Here we read the values related to LPSS power island, i.e. LPSS 885 * devices, excluding both LPSS DMA controllers, along with SCC domain. 886 */ 887 u32 func_dis, d3_sts_0, pmc_status, pmc_mask = 0xfe000ffe; 888 int ret; 889 890 ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis); 891 if (ret) 892 return; 893 894 mutex_lock(&lpss_iosf_mutex); 895 896 ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0); 897 if (ret) 898 goto exit; 899 900 /* 901 * Get the status of entire LPSS power island per device basis. 902 * Shutdown both LPSS DMA controllers if and only if all other devices 903 * are already in D3hot. 904 */ 905 pmc_status = (~(d3_sts_0 | func_dis)) & pmc_mask; 906 if (pmc_status) 907 goto exit; 908 909 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, 910 LPSS_IOSF_PMCSR, value2, mask2); 911 912 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, 913 LPSS_IOSF_PMCSR, value2, mask2); 914 915 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, 916 LPSS_IOSF_GPIODEF0, value1, mask1); 917 exit: 918 mutex_unlock(&lpss_iosf_mutex); 919 } 920 921 static void lpss_iosf_exit_d3_state(void) 922 { 923 u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 | 924 LPSS_GPIODEF0_DMA_LLP; 925 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; 926 u32 value2 = LPSS_PMCSR_D0; 927 u32 mask2 = LPSS_PMCSR_Dx_MASK; 928 929 mutex_lock(&lpss_iosf_mutex); 930 931 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, 932 LPSS_IOSF_GPIODEF0, value1, mask1); 933 934 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, 935 LPSS_IOSF_PMCSR, value2, mask2); 936 937 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, 938 LPSS_IOSF_PMCSR, value2, mask2); 939 940 mutex_unlock(&lpss_iosf_mutex); 941 } 942 943 static int acpi_lpss_suspend(struct device *dev, bool wakeup) 944 { 945 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 946 int ret; 947 948 if (pdata->dev_desc->flags & LPSS_SAVE_CTX) 949 acpi_lpss_save_ctx(dev, pdata); 950 951 ret = acpi_dev_suspend(dev, wakeup); 952 953 /* 954 * This call must be last in the sequence, otherwise PMC will return 955 * wrong status for devices being about to be powered off. See 956 * lpss_iosf_enter_d3_state() for further information. 957 */ 958 if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) 959 lpss_iosf_enter_d3_state(); 960 961 return ret; 962 } 963 964 static int acpi_lpss_resume(struct device *dev) 965 { 966 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 967 int ret; 968 969 /* 970 * This call is kept first to be in symmetry with 971 * acpi_lpss_runtime_suspend() one. 972 */ 973 if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) 974 lpss_iosf_exit_d3_state(); 975 976 ret = acpi_dev_resume(dev); 977 if (ret) 978 return ret; 979 980 acpi_lpss_d3_to_d0_delay(pdata); 981 982 if (pdata->dev_desc->flags & LPSS_SAVE_CTX) 983 acpi_lpss_restore_ctx(dev, pdata); 984 985 return 0; 986 } 987 988 #ifdef CONFIG_PM_SLEEP 989 static int acpi_lpss_suspend_late(struct device *dev) 990 { 991 int ret; 992 993 if (dev_pm_smart_suspend_and_suspended(dev)) 994 return 0; 995 996 ret = pm_generic_suspend_late(dev); 997 return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev)); 998 } 999 1000 static int acpi_lpss_resume_early(struct device *dev) 1001 { 1002 int ret = acpi_lpss_resume(dev); 1003 1004 return ret ? ret : pm_generic_resume_early(dev); 1005 } 1006 #endif /* CONFIG_PM_SLEEP */ 1007 1008 static int acpi_lpss_runtime_suspend(struct device *dev) 1009 { 1010 int ret = pm_generic_runtime_suspend(dev); 1011 1012 return ret ? ret : acpi_lpss_suspend(dev, true); 1013 } 1014 1015 static int acpi_lpss_runtime_resume(struct device *dev) 1016 { 1017 int ret = acpi_lpss_resume(dev); 1018 1019 return ret ? ret : pm_generic_runtime_resume(dev); 1020 } 1021 #endif /* CONFIG_PM */ 1022 1023 static struct dev_pm_domain acpi_lpss_pm_domain = { 1024 #ifdef CONFIG_PM 1025 .activate = acpi_lpss_activate, 1026 .dismiss = acpi_lpss_dismiss, 1027 #endif 1028 .ops = { 1029 #ifdef CONFIG_PM 1030 #ifdef CONFIG_PM_SLEEP 1031 .prepare = acpi_subsys_prepare, 1032 .complete = acpi_subsys_complete, 1033 .suspend = acpi_subsys_suspend, 1034 .suspend_late = acpi_lpss_suspend_late, 1035 .suspend_noirq = acpi_subsys_suspend_noirq, 1036 .resume_noirq = acpi_subsys_resume_noirq, 1037 .resume_early = acpi_lpss_resume_early, 1038 .freeze = acpi_subsys_freeze, 1039 .freeze_late = acpi_subsys_freeze_late, 1040 .freeze_noirq = acpi_subsys_freeze_noirq, 1041 .thaw_noirq = acpi_subsys_thaw_noirq, 1042 .poweroff = acpi_subsys_suspend, 1043 .poweroff_late = acpi_lpss_suspend_late, 1044 .poweroff_noirq = acpi_subsys_suspend_noirq, 1045 .restore_noirq = acpi_subsys_resume_noirq, 1046 .restore_early = acpi_lpss_resume_early, 1047 #endif 1048 .runtime_suspend = acpi_lpss_runtime_suspend, 1049 .runtime_resume = acpi_lpss_runtime_resume, 1050 #endif 1051 }, 1052 }; 1053 1054 static int acpi_lpss_platform_notify(struct notifier_block *nb, 1055 unsigned long action, void *data) 1056 { 1057 struct platform_device *pdev = to_platform_device(data); 1058 struct lpss_private_data *pdata; 1059 struct acpi_device *adev; 1060 const struct acpi_device_id *id; 1061 1062 id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev); 1063 if (!id || !id->driver_data) 1064 return 0; 1065 1066 if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) 1067 return 0; 1068 1069 pdata = acpi_driver_data(adev); 1070 if (!pdata) 1071 return 0; 1072 1073 if (pdata->mmio_base && 1074 pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) { 1075 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n"); 1076 return 0; 1077 } 1078 1079 switch (action) { 1080 case BUS_NOTIFY_BIND_DRIVER: 1081 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); 1082 break; 1083 case BUS_NOTIFY_DRIVER_NOT_BOUND: 1084 case BUS_NOTIFY_UNBOUND_DRIVER: 1085 dev_pm_domain_set(&pdev->dev, NULL); 1086 break; 1087 case BUS_NOTIFY_ADD_DEVICE: 1088 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); 1089 if (pdata->dev_desc->flags & LPSS_LTR) 1090 return sysfs_create_group(&pdev->dev.kobj, 1091 &lpss_attr_group); 1092 break; 1093 case BUS_NOTIFY_DEL_DEVICE: 1094 if (pdata->dev_desc->flags & LPSS_LTR) 1095 sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group); 1096 dev_pm_domain_set(&pdev->dev, NULL); 1097 break; 1098 default: 1099 break; 1100 } 1101 1102 return 0; 1103 } 1104 1105 static struct notifier_block acpi_lpss_nb = { 1106 .notifier_call = acpi_lpss_platform_notify, 1107 }; 1108 1109 static void acpi_lpss_bind(struct device *dev) 1110 { 1111 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1112 1113 if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR)) 1114 return; 1115 1116 if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) 1117 dev->power.set_latency_tolerance = acpi_lpss_set_ltr; 1118 else 1119 dev_err(dev, "MMIO size insufficient to access LTR\n"); 1120 } 1121 1122 static void acpi_lpss_unbind(struct device *dev) 1123 { 1124 dev->power.set_latency_tolerance = NULL; 1125 } 1126 1127 static struct acpi_scan_handler lpss_handler = { 1128 .ids = acpi_lpss_device_ids, 1129 .attach = acpi_lpss_create_device, 1130 .bind = acpi_lpss_bind, 1131 .unbind = acpi_lpss_unbind, 1132 }; 1133 1134 void __init acpi_lpss_init(void) 1135 { 1136 const struct x86_cpu_id *id; 1137 int ret; 1138 1139 ret = lpt_clk_init(); 1140 if (ret) 1141 return; 1142 1143 id = x86_match_cpu(lpss_cpu_ids); 1144 if (id) 1145 lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON; 1146 1147 bus_register_notifier(&platform_bus_type, &acpi_lpss_nb); 1148 acpi_scan_add_handler(&lpss_handler); 1149 } 1150 1151 #else 1152 1153 static struct acpi_scan_handler lpss_handler = { 1154 .ids = acpi_lpss_device_ids, 1155 }; 1156 1157 void __init acpi_lpss_init(void) 1158 { 1159 acpi_scan_add_handler(&lpss_handler); 1160 } 1161 1162 #endif /* CONFIG_X86_INTEL_LPSS */ 1163